Analogous to AVX2, these need to be implemented as macros to properly
propagate the immediate index operand.
Part of <rdar://problem/
17688758>
git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@226496
91177308-0d34-0410-b5e6-
96231b3b80d8
BUILTIN(__builtin_ia32_vpermt2varpd512_mask, "V8dV8LLiV8dV8dUc", "")
BUILTIN(__builtin_ia32_alignq512_mask, "V8LLiV8LLiV8LLiUcV8LLiUc", "")
BUILTIN(__builtin_ia32_alignd512_mask, "V16iV16iV16iUcV16iUc", "")
+BUILTIN(__builtin_ia32_extractf64x4_mask, "V4dV8dIcV4dUc", "")
+BUILTIN(__builtin_ia32_extractf32x4_mask, "V4fV16fIcV4fUc", "")
BUILTIN(__builtin_ia32_gathersiv8df, "V8dV8dvC*V8iUciC", "")
BUILTIN(__builtin_ia32_gathersiv16sf, "V16fV16fvC*UsiC", "")
BUILTIN(__builtin_ia32_gatherdiv8df, "V8dV8dvC*V8LLiUciC", "")
(__mmask16) -1);
}
+/* Vector Extract */
+
+#define _mm512_extractf64x4_pd(A, I) __extension__ ({ \
+ __m512d __A = (A); \
+ (__m256d) \
+ __builtin_ia32_extractf64x4_mask((__v8df)__A, \
+ (I), \
+ (__v4df)_mm256_setzero_si256(), \
+ (__mmask8) -1); })
+
+#define _mm512_extractf32x4_ps(A, I) __extension__ ({ \
+ __m512 __A = (A); \
+ (__m128) \
+ __builtin_ia32_extractf32x4_mask((__v16sf)__A, \
+ (I), \
+ (__v4sf)_mm_setzero_ps(), \
+ (__mmask8) -1); })
+
/* Vector Blend */
static __inline __m512d __attribute__ ((__always_inline__, __nodebug__))
// CHECK: @llvm.x86.avx512.mask.cmp.pd.512
return _mm512_cmp_pd_mask(__a, __b, 0);
}
+
+__m256d test_mm512_extractf64x4_pd(__m512d a)
+{
+ // CHECK-LABEL: @test_mm512_extractf64x4_pd
+ // CHECK: @llvm.x86.avx512.mask.vextractf64x4.512
+ return _mm512_extractf64x4_pd(a, 1);
+}
+
+__m128 test_mm512_extractf32x4_ps(__m512 a)
+{
+ // CHECK-LABEL: @test_mm512_extractf32x4_ps
+ // CHECK: @llvm.x86.avx512.mask.vextractf32x4.512
+ return _mm512_extractf32x4_ps(a, 1);
+}