-// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD\r
-//\r
-// Licensed under the Apache License, Version 2.0 (the "License");\r
-// you may not use this file except in compliance with the License.\r
-// You may obtain a copy of the License at\r
-\r
-// http://www.apache.org/licenses/LICENSE-2.0\r
-//\r
-// Unless required by applicable law or agreed to in writing, software\r
-// distributed under the License is distributed on an "AS IS" BASIS,\r
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
-// See the License for the specific language governing permissions and\r
-// limitations under the License.\r
-#ifndef _SOC_I2C_REG_H_\r
-#define _SOC_I2C_REG_H_\r
-\r
-\r
-#include "soc.h"\r
-\r
-#define REG_I2C_BASE(i) (DR_REG_I2C_EXT_BASE + (i) * 0x14000 )\r
-\r
-#define I2C_SCL_LOW_PERIOD_REG(i) (REG_I2C_BASE(i) + 0x0000)\r
-/* I2C_SCL_LOW_PERIOD : R/W ;bitpos:[13:0] ;default: 14'b0 ; */\r
-/*description: This register is used to configure the low level width of SCL clock.*/\r
-#define I2C_SCL_LOW_PERIOD 0x00003FFF\r
-#define I2C_SCL_LOW_PERIOD_M ((I2C_SCL_LOW_PERIOD_V)<<(I2C_SCL_LOW_PERIOD_S))\r
-#define I2C_SCL_LOW_PERIOD_V 0x3FFF\r
-#define I2C_SCL_LOW_PERIOD_S 0\r
-\r
-#define I2C_CTR_REG(i) (REG_I2C_BASE(i) + 0x0004)\r
-/* I2C_CLK_EN : R/W ;bitpos:[8] ;default: 1'b0 ; */\r
-/*description: This is the clock gating control bit for reading or writing registers.*/\r
-#define I2C_CLK_EN (BIT(8))\r
-#define I2C_CLK_EN_M (BIT(8))\r
-#define I2C_CLK_EN_V 0x1\r
-#define I2C_CLK_EN_S 8\r
-/* I2C_RX_LSB_FIRST : R/W ;bitpos:[7] ;default: 1'h0 ; */\r
-/*description: This bit is used to control the storage mode for received datas.\r
- 1: receive data from most significant bit 0: receive data from least significant bit*/\r
-#define I2C_RX_LSB_FIRST (BIT(7))\r
-#define I2C_RX_LSB_FIRST_M (BIT(7))\r
-#define I2C_RX_LSB_FIRST_V 0x1\r
-#define I2C_RX_LSB_FIRST_S 7\r
-/* I2C_TX_LSB_FIRST : R/W ;bitpos:[6] ;default: 1'b0 ; */\r
-/*description: This bit is used to control the sending mode for data need to\r
- be send. 1: receive data from most significant bit 0: receive data from least significant bit*/\r
-#define I2C_TX_LSB_FIRST (BIT(6))\r
-#define I2C_TX_LSB_FIRST_M (BIT(6))\r
-#define I2C_TX_LSB_FIRST_V 0x1\r
-#define I2C_TX_LSB_FIRST_S 6\r
-/* I2C_TRANS_START : R/W ;bitpos:[5] ;default: 1'b0 ; */\r
-/*description: Set this bit to start sending data in txfifo.*/\r
-#define I2C_TRANS_START (BIT(5))\r
-#define I2C_TRANS_START_M (BIT(5))\r
-#define I2C_TRANS_START_V 0x1\r
-#define I2C_TRANS_START_S 5\r
-/* I2C_MS_MODE : R/W ;bitpos:[4] ;default: 1'b0 ; */\r
-/*description: Set this bit to configure the module as i2c master clear this\r
- bit to configure the module as i2c slave.*/\r
-#define I2C_MS_MODE (BIT(4))\r
-#define I2C_MS_MODE_M (BIT(4))\r
-#define I2C_MS_MODE_V 0x1\r
-#define I2C_MS_MODE_S 4\r
-/* I2C_SAMPLE_SCL_LEVEL : R/W ;bitpos:[2] ;default: 1'b0 ; */\r
-/*description: Set this bit to sample data in SCL low level. clear this bit\r
- to sample data in SCL high level.*/\r
-#define I2C_SAMPLE_SCL_LEVEL (BIT(2))\r
-#define I2C_SAMPLE_SCL_LEVEL_M (BIT(2))\r
-#define I2C_SAMPLE_SCL_LEVEL_V 0x1\r
-#define I2C_SAMPLE_SCL_LEVEL_S 2\r
-/* I2C_SCL_FORCE_OUT : R/W ;bitpos:[1] ;default: 1'b1 ; */\r
-/*description: 1: normally ouput scl clock 0: exchange the function of scl_o\r
- and scl_oe (scl_o is the original internal output scl signal scl_oe is the enable bit for the internal output scl signal)*/\r
-#define I2C_SCL_FORCE_OUT (BIT(1))\r
-#define I2C_SCL_FORCE_OUT_M (BIT(1))\r
-#define I2C_SCL_FORCE_OUT_V 0x1\r
-#define I2C_SCL_FORCE_OUT_S 1\r
-/* I2C_SDA_FORCE_OUT : R/W ;bitpos:[0] ;default: 1'b1 ; */\r
-/*description: 1: normally ouput sda data 0: exchange the function of sda_o\r
- and sda_oe (sda_o is the original internal output sda signal sda_oe is the enable bit for the internal output sda signal)*/\r
-#define I2C_SDA_FORCE_OUT (BIT(0))\r
-#define I2C_SDA_FORCE_OUT_M (BIT(0))\r
-#define I2C_SDA_FORCE_OUT_V 0x1\r
-#define I2C_SDA_FORCE_OUT_S 0\r
-\r
-#define I2C_SR_REG(i) (REG_I2C_BASE(i) + 0x0008)\r
-/* I2C_SCL_STATE_LAST : RO ;bitpos:[30:28] ;default: 3'b0 ; */\r
-/*description: This register stores the value of state machine to produce SCL.\r
- 3'h0: SCL_IDLE 3'h1:SCL_START 3'h2:SCL_LOW_EDGE 3'h3: SCL_LOW 3'h4:SCL_HIGH_EDGE 3'h5:SCL_HIGH 3'h6:SCL_STOP*/\r
-#define I2C_SCL_STATE_LAST 0x00000007\r
-#define I2C_SCL_STATE_LAST_M ((I2C_SCL_STATE_LAST_V)<<(I2C_SCL_STATE_LAST_S))\r
-#define I2C_SCL_STATE_LAST_V 0x7\r
-#define I2C_SCL_STATE_LAST_S 28\r
-/* I2C_SCL_MAIN_STATE_LAST : RO ;bitpos:[26:24] ;default: 3'b0 ; */\r
-/*description: This register stores the value of state machine for i2c module.\r
- 3'h0: SCL_MAIN_IDLE 3'h1: SCL_ADDRESS_SHIFT 3'h2: SCL_ACK_ADDRESS 3'h3: SCL_RX_DATA 3'h4 SCL_TX_DATA 3'h5:SCL_SEND_ACK 3'h6:SCL_WAIT_ACK*/\r
-#define I2C_SCL_MAIN_STATE_LAST 0x00000007\r
-#define I2C_SCL_MAIN_STATE_LAST_M ((I2C_SCL_MAIN_STATE_LAST_V)<<(I2C_SCL_MAIN_STATE_LAST_S))\r
-#define I2C_SCL_MAIN_STATE_LAST_V 0x7\r
-#define I2C_SCL_MAIN_STATE_LAST_S 24\r
-/* I2C_TXFIFO_CNT : RO ;bitpos:[23:18] ;default: 6'b0 ; */\r
-/*description: This register stores the amount of received data in ram.*/\r
-#define I2C_TXFIFO_CNT 0x0000003F\r
-#define I2C_TXFIFO_CNT_M ((I2C_TXFIFO_CNT_V)<<(I2C_TXFIFO_CNT_S))\r
-#define I2C_TXFIFO_CNT_V 0x3F\r
-#define I2C_TXFIFO_CNT_S 18\r
-/* I2C_RXFIFO_CNT : RO ;bitpos:[13:8] ;default: 6'b0 ; */\r
-/*description: This register represent the amount of data need to send.*/\r
-#define I2C_RXFIFO_CNT 0x0000003F\r
-#define I2C_RXFIFO_CNT_M ((I2C_RXFIFO_CNT_V)<<(I2C_RXFIFO_CNT_S))\r
-#define I2C_RXFIFO_CNT_V 0x3F\r
-#define I2C_RXFIFO_CNT_S 8\r
-/* I2C_BYTE_TRANS : RO ;bitpos:[6] ;default: 1'b0 ; */\r
-/*description: This register changes to high level when one byte is transferred.*/\r
-#define I2C_BYTE_TRANS (BIT(6))\r
-#define I2C_BYTE_TRANS_M (BIT(6))\r
-#define I2C_BYTE_TRANS_V 0x1\r
-#define I2C_BYTE_TRANS_S 6\r
-/* I2C_SLAVE_ADDRESSED : RO ;bitpos:[5] ;default: 1'b0 ; */\r
-/*description: when configured as i2c slave and the address send by master\r
- is equal to slave's address then this bit will be high level.*/\r
-#define I2C_SLAVE_ADDRESSED (BIT(5))\r
-#define I2C_SLAVE_ADDRESSED_M (BIT(5))\r
-#define I2C_SLAVE_ADDRESSED_V 0x1\r
-#define I2C_SLAVE_ADDRESSED_S 5\r
-/* I2C_BUS_BUSY : RO ;bitpos:[4] ;default: 1'b0 ; */\r
-/*description: 1:I2C bus is busy transferring data. 0:I2C bus is in idle state.*/\r
-#define I2C_BUS_BUSY (BIT(4))\r
-#define I2C_BUS_BUSY_M (BIT(4))\r
-#define I2C_BUS_BUSY_V 0x1\r
-#define I2C_BUS_BUSY_S 4\r
-/* I2C_ARB_LOST : RO ;bitpos:[3] ;default: 1'b0 ; */\r
-/*description: when I2C lost control of SDA line this register changes to high level.*/\r
-#define I2C_ARB_LOST (BIT(3))\r
-#define I2C_ARB_LOST_M (BIT(3))\r
-#define I2C_ARB_LOST_V 0x1\r
-#define I2C_ARB_LOST_S 3\r
-/* I2C_TIME_OUT : RO ;bitpos:[2] ;default: 1'b0 ; */\r
-/*description: when I2C takes more than time_out_reg clocks to receive a data\r
- then this register changes to high level.*/\r
-#define I2C_TIME_OUT (BIT(2))\r
-#define I2C_TIME_OUT_M (BIT(2))\r
-#define I2C_TIME_OUT_V 0x1\r
-#define I2C_TIME_OUT_S 2\r
-/* I2C_SLAVE_RW : RO ;bitpos:[1] ;default: 1'b0 ; */\r
-/*description: when in slave mode 1: master read slave 0: master write slave.*/\r
-#define I2C_SLAVE_RW (BIT(1))\r
-#define I2C_SLAVE_RW_M (BIT(1))\r
-#define I2C_SLAVE_RW_V 0x1\r
-#define I2C_SLAVE_RW_S 1\r
-/* I2C_ACK_REC : RO ;bitpos:[0] ;default: 1'b0 ; */\r
-/*description: This register stores the value of ACK bit.*/\r
-#define I2C_ACK_REC (BIT(0))\r
-#define I2C_ACK_REC_M (BIT(0))\r
-#define I2C_ACK_REC_V 0x1\r
-#define I2C_ACK_REC_S 0\r
-\r
-#define I2C_TO_REG(i) (REG_I2C_BASE(i) + 0x000c)\r
-/* I2C_TIME_OUT_REG : R/W ;bitpos:[19:0] ;default: 20'b0 ; */\r
-/*description: This register is used to configure the max clock number of receiving a data.*/\r
-#define I2C_TIME_OUT_REG 0x000FFFFF\r
-#define I2C_TIME_OUT_REG_M ((I2C_TIME_OUT_REG_V)<<(I2C_TIME_OUT_REG_S))\r
-#define I2C_TIME_OUT_REG_V 0xFFFFF\r
-#define I2C_TIME_OUT_REG_S 0\r
-\r
-#define I2C_SLAVE_ADDR_REG(i) (REG_I2C_BASE(i) + 0x0010)\r
-/* I2C_ADDR_10BIT_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */\r
-/*description: This register is used to enable slave 10bit address mode.*/\r
-#define I2C_ADDR_10BIT_EN (BIT(31))\r
-#define I2C_ADDR_10BIT_EN_M (BIT(31))\r
-#define I2C_ADDR_10BIT_EN_V 0x1\r
-#define I2C_ADDR_10BIT_EN_S 31\r
-/* I2C_SLAVE_ADDR : R/W ;bitpos:[14:0] ;default: 15'b0 ; */\r
-/*description: when configured as i2c slave this register is used to configure\r
- slave's address.*/\r
-#define I2C_SLAVE_ADDR 0x00007FFF\r
-#define I2C_SLAVE_ADDR_M ((I2C_SLAVE_ADDR_V)<<(I2C_SLAVE_ADDR_S))\r
-#define I2C_SLAVE_ADDR_V 0x7FFF\r
-#define I2C_SLAVE_ADDR_S 0\r
-\r
-#define I2C_RXFIFO_ST_REG(i) (REG_I2C_BASE(i) + 0x0014)\r
-/* I2C_TXFIFO_END_ADDR : RO ;bitpos:[19:15] ;default: 5'b0 ; */\r
-/*description: This is the offset address of the last sending data as described\r
- in nonfifo_tx_thres register.*/\r
-#define I2C_TXFIFO_END_ADDR 0x0000001F\r
-#define I2C_TXFIFO_END_ADDR_M ((I2C_TXFIFO_END_ADDR_V)<<(I2C_TXFIFO_END_ADDR_S))\r
-#define I2C_TXFIFO_END_ADDR_V 0x1F\r
-#define I2C_TXFIFO_END_ADDR_S 15\r
-/* I2C_TXFIFO_START_ADDR : RO ;bitpos:[14:10] ;default: 5'b0 ; */\r
-/*description: This is the offset address of the first sending data as described\r
- in nonfifo_tx_thres register.*/\r
-#define I2C_TXFIFO_START_ADDR 0x0000001F\r
-#define I2C_TXFIFO_START_ADDR_M ((I2C_TXFIFO_START_ADDR_V)<<(I2C_TXFIFO_START_ADDR_S))\r
-#define I2C_TXFIFO_START_ADDR_V 0x1F\r
-#define I2C_TXFIFO_START_ADDR_S 10\r
-/* I2C_RXFIFO_END_ADDR : RO ;bitpos:[9:5] ;default: 5'b0 ; */\r
-/*description: This is the offset address of the first receiving data as described\r
- in nonfifo_rx_thres_register.*/\r
-#define I2C_RXFIFO_END_ADDR 0x0000001F\r
-#define I2C_RXFIFO_END_ADDR_M ((I2C_RXFIFO_END_ADDR_V)<<(I2C_RXFIFO_END_ADDR_S))\r
-#define I2C_RXFIFO_END_ADDR_V 0x1F\r
-#define I2C_RXFIFO_END_ADDR_S 5\r
-/* I2C_RXFIFO_START_ADDR : RO ;bitpos:[4:0] ;default: 5'b0 ; */\r
-/*description: This is the offset address of the last receiving data as described\r
- in nonfifo_rx_thres_register.*/\r
-#define I2C_RXFIFO_START_ADDR 0x0000001F\r
-#define I2C_RXFIFO_START_ADDR_M ((I2C_RXFIFO_START_ADDR_V)<<(I2C_RXFIFO_START_ADDR_S))\r
-#define I2C_RXFIFO_START_ADDR_V 0x1F\r
-#define I2C_RXFIFO_START_ADDR_S 0\r
-\r
-#define I2C_FIFO_CONF_REG(i) (REG_I2C_BASE(i) + 0x0018)\r
-/* I2C_NONFIFO_TX_THRES : R/W ;bitpos:[25:20] ;default: 6'h15 ; */\r
-/*description: when I2C sends more than nonfifo_tx_thres data it will produce\r
- tx_send_empty_int_raw interrupt and update the current offset address of the sending data.*/\r
-#define I2C_NONFIFO_TX_THRES 0x0000003F\r
-#define I2C_NONFIFO_TX_THRES_M ((I2C_NONFIFO_TX_THRES_V)<<(I2C_NONFIFO_TX_THRES_S))\r
-#define I2C_NONFIFO_TX_THRES_V 0x3F\r
-#define I2C_NONFIFO_TX_THRES_S 20\r
-/* I2C_NONFIFO_RX_THRES : R/W ;bitpos:[19:14] ;default: 6'h15 ; */\r
-/*description: when I2C receives more than nonfifo_rx_thres data it will produce\r
- rx_send_full_int_raw interrupt and update the current offset address of the receiving data.*/\r
-#define I2C_NONFIFO_RX_THRES 0x0000003F\r
-#define I2C_NONFIFO_RX_THRES_M ((I2C_NONFIFO_RX_THRES_V)<<(I2C_NONFIFO_RX_THRES_S))\r
-#define I2C_NONFIFO_RX_THRES_V 0x3F\r
-#define I2C_NONFIFO_RX_THRES_S 14\r
-/* I2C_TX_FIFO_RST : R/W ;bitpos:[13] ;default: 1'b0 ; */\r
-/*description: Set this bit to reset tx fifo when using apb fifo access.*/\r
-#define I2C_TX_FIFO_RST (BIT(13))\r
-#define I2C_TX_FIFO_RST_M (BIT(13))\r
-#define I2C_TX_FIFO_RST_V 0x1\r
-#define I2C_TX_FIFO_RST_S 13\r
-/* I2C_RX_FIFO_RST : R/W ;bitpos:[12] ;default: 1'b0 ; */\r
-/*description: Set this bit to reset rx fifo when using apb fifo access.*/\r
-#define I2C_RX_FIFO_RST (BIT(12))\r
-#define I2C_RX_FIFO_RST_M (BIT(12))\r
-#define I2C_RX_FIFO_RST_V 0x1\r
-#define I2C_RX_FIFO_RST_S 12\r
-/* I2C_FIFO_ADDR_CFG_EN : R/W ;bitpos:[11] ;default: 1'b0 ; */\r
-/*description: When this bit is set to 1 then the byte after address represent\r
- the offset address of I2C Slave's ram.*/\r
-#define I2C_FIFO_ADDR_CFG_EN (BIT(11))\r
-#define I2C_FIFO_ADDR_CFG_EN_M (BIT(11))\r
-#define I2C_FIFO_ADDR_CFG_EN_V 0x1\r
-#define I2C_FIFO_ADDR_CFG_EN_S 11\r
-/* I2C_NONFIFO_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */\r
-/*description: Set this bit to enble apb nonfifo access.*/\r
-#define I2C_NONFIFO_EN (BIT(10))\r
-#define I2C_NONFIFO_EN_M (BIT(10))\r
-#define I2C_NONFIFO_EN_V 0x1\r
-#define I2C_NONFIFO_EN_S 10\r
-/* I2C_TXFIFO_EMPTY_THRHD : R/W ;bitpos:[9:5] ;default: 5'h4 ; */\r
-/*description: Config txfifo empty threhd value when using apb fifo access*/\r
-#define I2C_TXFIFO_EMPTY_THRHD 0x0000001F\r
-#define I2C_TXFIFO_EMPTY_THRHD_M ((I2C_TXFIFO_EMPTY_THRHD_V)<<(I2C_TXFIFO_EMPTY_THRHD_S))\r
-#define I2C_TXFIFO_EMPTY_THRHD_V 0x1F\r
-#define I2C_TXFIFO_EMPTY_THRHD_S 5\r
-/* I2C_RXFIFO_FULL_THRHD : R/W ;bitpos:[4:0] ;default: 5'hb ; */\r
-/*description: */\r
-#define I2C_RXFIFO_FULL_THRHD 0x0000001F\r
-#define I2C_RXFIFO_FULL_THRHD_M ((I2C_RXFIFO_FULL_THRHD_V)<<(I2C_RXFIFO_FULL_THRHD_S))\r
-#define I2C_RXFIFO_FULL_THRHD_V 0x1F\r
-#define I2C_RXFIFO_FULL_THRHD_S 0\r
-\r
-#define I2C_DATA_APB_REG(i) (0x60013000 + (i) * 0x14000 + 0x001c)\r
-\r
-#define I2C_DATA_REG(i) (REG_I2C_BASE(i) + 0x001c)\r
-/* I2C_FIFO_RDATA : RO ;bitpos:[7:0] ;default: 8'b0 ; */\r
-/*description: The register represent the byte data read from rxfifo when use apb fifo access*/\r
-#define I2C_FIFO_RDATA 0x000000FF\r
-#define I2C_FIFO_RDATA_M ((I2C_FIFO_RDATA_V)<<(I2C_FIFO_RDATA_S))\r
-#define I2C_FIFO_RDATA_V 0xFF\r
-#define I2C_FIFO_RDATA_S 0\r
-\r
-#define I2C_INT_RAW_REG(i) (REG_I2C_BASE(i) + 0x0020)\r
-/* I2C_TX_SEND_EMPTY_INT_RAW : RO ;bitpos:[12] ;default: 1'b0 ; */\r
-/*description: The raw interrupt status bit for tx_send_empty_int interrupt.when\r
- I2C sends more data than nonfifo_tx_thres it will produce tx_send_empty_int interrupt..*/\r
-#define I2C_TX_SEND_EMPTY_INT_RAW (BIT(12))\r
-#define I2C_TX_SEND_EMPTY_INT_RAW_M (BIT(12))\r
-#define I2C_TX_SEND_EMPTY_INT_RAW_V 0x1\r
-#define I2C_TX_SEND_EMPTY_INT_RAW_S 12\r
-/* I2C_RX_REC_FULL_INT_RAW : RO ;bitpos:[11] ;default: 1'b0 ; */\r
-/*description: The raw interrupt status bit for rx_rec_full_int interrupt. when\r
- I2C receives more data than nonfifo_rx_thres it will produce rx_rec_full_int interrupt.*/\r
-#define I2C_RX_REC_FULL_INT_RAW (BIT(11))\r
-#define I2C_RX_REC_FULL_INT_RAW_M (BIT(11))\r
-#define I2C_RX_REC_FULL_INT_RAW_V 0x1\r
-#define I2C_RX_REC_FULL_INT_RAW_S 11\r
-/* I2C_ACK_ERR_INT_RAW : RO ;bitpos:[10] ;default: 1'b0 ; */\r
-/*description: The raw interrupt status bit for ack_err_int interrupt. when\r
- I2C receives a wrong ACK bit it will produce ack_err_int interrupt..*/\r
-#define I2C_ACK_ERR_INT_RAW (BIT(10))\r
-#define I2C_ACK_ERR_INT_RAW_M (BIT(10))\r
-#define I2C_ACK_ERR_INT_RAW_V 0x1\r
-#define I2C_ACK_ERR_INT_RAW_S 10\r
-/* I2C_TRANS_START_INT_RAW : RO ;bitpos:[9] ;default: 1'b0 ; */\r
-/*description: The raw interrupt status bit for trans_start_int interrupt. when\r
- I2C sends the START bit it will produce trans_start_int interrupt.*/\r
-#define I2C_TRANS_START_INT_RAW (BIT(9))\r
-#define I2C_TRANS_START_INT_RAW_M (BIT(9))\r
-#define I2C_TRANS_START_INT_RAW_V 0x1\r
-#define I2C_TRANS_START_INT_RAW_S 9\r
-/* I2C_TIME_OUT_INT_RAW : RO ;bitpos:[8] ;default: 1'b0 ; */\r
-/*description: The raw interrupt status bit for time_out_int interrupt. when\r
- I2C takes a lot of time to receive a data it will produce time_out_int interrupt.*/\r
-#define I2C_TIME_OUT_INT_RAW (BIT(8))\r
-#define I2C_TIME_OUT_INT_RAW_M (BIT(8))\r
-#define I2C_TIME_OUT_INT_RAW_V 0x1\r
-#define I2C_TIME_OUT_INT_RAW_S 8\r
-/* I2C_TRANS_COMPLETE_INT_RAW : RO ;bitpos:[7] ;default: 1'b0 ; */\r
-/*description: The raw interrupt status bit for trans_complete_int interrupt.\r
- when I2C Master finished STOP command it will produce trans_complete_int interrupt.*/\r
-#define I2C_TRANS_COMPLETE_INT_RAW (BIT(7))\r
-#define I2C_TRANS_COMPLETE_INT_RAW_M (BIT(7))\r
-#define I2C_TRANS_COMPLETE_INT_RAW_V 0x1\r
-#define I2C_TRANS_COMPLETE_INT_RAW_S 7\r
-/* I2C_MASTER_TRAN_COMP_INT_RAW : RO ;bitpos:[6] ;default: 1'b0 ; */\r
-/*description: The raw interrupt status bit for master_tra_comp_int interrupt.\r
- when I2C Master sends or receives a byte it will produce master_tran_comp_int interrupt.*/\r
-#define I2C_MASTER_TRAN_COMP_INT_RAW (BIT(6))\r
-#define I2C_MASTER_TRAN_COMP_INT_RAW_M (BIT(6))\r
-#define I2C_MASTER_TRAN_COMP_INT_RAW_V 0x1\r
-#define I2C_MASTER_TRAN_COMP_INT_RAW_S 6\r
-/* I2C_ARBITRATION_LOST_INT_RAW : RO ;bitpos:[5] ;default: 1'b0 ; */\r
-/*description: The raw interrupt status bit for arbitration_lost_int interrupt.when\r
- I2C lost the usage right of I2C BUS it will produce arbitration_lost_int interrupt.*/\r
-#define I2C_ARBITRATION_LOST_INT_RAW (BIT(5))\r
-#define I2C_ARBITRATION_LOST_INT_RAW_M (BIT(5))\r
-#define I2C_ARBITRATION_LOST_INT_RAW_V 0x1\r
-#define I2C_ARBITRATION_LOST_INT_RAW_S 5\r
-/* I2C_SLAVE_TRAN_COMP_INT_RAW : RO ;bitpos:[4] ;default: 1'b0 ; */\r
-/*description: The raw interrupt status bit for slave_tran_comp_int interrupt.\r
- when I2C Slave detectsthe STOP bit it will produce slave_tran_comp_int interrupt.*/\r
-#define I2C_SLAVE_TRAN_COMP_INT_RAW (BIT(4))\r
-#define I2C_SLAVE_TRAN_COMP_INT_RAW_M (BIT(4))\r
-#define I2C_SLAVE_TRAN_COMP_INT_RAW_V 0x1\r
-#define I2C_SLAVE_TRAN_COMP_INT_RAW_S 4\r
-/* I2C_END_DETECT_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */\r
-/*description: The raw interrupt status bit for end_detect_int interrupt. when\r
- I2C deals with the END command it will produce end_detect_int interrupt.*/\r
-#define I2C_END_DETECT_INT_RAW (BIT(3))\r
-#define I2C_END_DETECT_INT_RAW_M (BIT(3))\r
-#define I2C_END_DETECT_INT_RAW_V 0x1\r
-#define I2C_END_DETECT_INT_RAW_S 3\r
-/* I2C_RXFIFO_OVF_INT_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */\r
-/*description: The raw interrupt status bit for receiving data overflow when\r
- use apb fifo access.*/\r
-#define I2C_RXFIFO_OVF_INT_RAW (BIT(2))\r
-#define I2C_RXFIFO_OVF_INT_RAW_M (BIT(2))\r
-#define I2C_RXFIFO_OVF_INT_RAW_V 0x1\r
-#define I2C_RXFIFO_OVF_INT_RAW_S 2\r
-/* I2C_TXFIFO_EMPTY_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */\r
-/*description: The raw interrupt status bit for txfifo empty when use apb fifo access.*/\r
-#define I2C_TXFIFO_EMPTY_INT_RAW (BIT(1))\r
-#define I2C_TXFIFO_EMPTY_INT_RAW_M (BIT(1))\r
-#define I2C_TXFIFO_EMPTY_INT_RAW_V 0x1\r
-#define I2C_TXFIFO_EMPTY_INT_RAW_S 1\r
-/* I2C_RXFIFO_FULL_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */\r
-/*description: The raw interrupt status bit for rxfifo full when use apb fifo access.*/\r
-#define I2C_RXFIFO_FULL_INT_RAW (BIT(0))\r
-#define I2C_RXFIFO_FULL_INT_RAW_M (BIT(0))\r
-#define I2C_RXFIFO_FULL_INT_RAW_V 0x1\r
-#define I2C_RXFIFO_FULL_INT_RAW_S 0\r
-\r
-#define I2C_INT_CLR_REG(i) (REG_I2C_BASE(i) + 0x0024)\r
-/* I2C_TX_SEND_EMPTY_INT_CLR : WO ;bitpos:[12] ;default: 1'b0 ; */\r
-/*description: Set this bit to clear the tx_send_empty_int interrupt.*/\r
-#define I2C_TX_SEND_EMPTY_INT_CLR (BIT(12))\r
-#define I2C_TX_SEND_EMPTY_INT_CLR_M (BIT(12))\r
-#define I2C_TX_SEND_EMPTY_INT_CLR_V 0x1\r
-#define I2C_TX_SEND_EMPTY_INT_CLR_S 12\r
-/* I2C_RX_REC_FULL_INT_CLR : WO ;bitpos:[11] ;default: 1'b0 ; */\r
-/*description: Set this bit to clear the rx_rec_full_int interrupt.*/\r
-#define I2C_RX_REC_FULL_INT_CLR (BIT(11))\r
-#define I2C_RX_REC_FULL_INT_CLR_M (BIT(11))\r
-#define I2C_RX_REC_FULL_INT_CLR_V 0x1\r
-#define I2C_RX_REC_FULL_INT_CLR_S 11\r
-/* I2C_ACK_ERR_INT_CLR : WO ;bitpos:[10] ;default: 1'b0 ; */\r
-/*description: Set this bit to clear the ack_err_int interrupt.*/\r
-#define I2C_ACK_ERR_INT_CLR (BIT(10))\r
-#define I2C_ACK_ERR_INT_CLR_M (BIT(10))\r
-#define I2C_ACK_ERR_INT_CLR_V 0x1\r
-#define I2C_ACK_ERR_INT_CLR_S 10\r
-/* I2C_TRANS_START_INT_CLR : WO ;bitpos:[9] ;default: 1'b0 ; */\r
-/*description: Set this bit to clear the trans_start_int interrupt.*/\r
-#define I2C_TRANS_START_INT_CLR (BIT(9))\r
-#define I2C_TRANS_START_INT_CLR_M (BIT(9))\r
-#define I2C_TRANS_START_INT_CLR_V 0x1\r
-#define I2C_TRANS_START_INT_CLR_S 9\r
-/* I2C_TIME_OUT_INT_CLR : WO ;bitpos:[8] ;default: 1'b0 ; */\r
-/*description: Set this bit to clear the time_out_int interrupt.*/\r
-#define I2C_TIME_OUT_INT_CLR (BIT(8))\r
-#define I2C_TIME_OUT_INT_CLR_M (BIT(8))\r
-#define I2C_TIME_OUT_INT_CLR_V 0x1\r
-#define I2C_TIME_OUT_INT_CLR_S 8\r
-/* I2C_TRANS_COMPLETE_INT_CLR : WO ;bitpos:[7] ;default: 1'b0 ; */\r
-/*description: Set this bit to clear the trans_complete_int interrupt.*/\r
-#define I2C_TRANS_COMPLETE_INT_CLR (BIT(7))\r
-#define I2C_TRANS_COMPLETE_INT_CLR_M (BIT(7))\r
-#define I2C_TRANS_COMPLETE_INT_CLR_V 0x1\r
-#define I2C_TRANS_COMPLETE_INT_CLR_S 7\r
-/* I2C_MASTER_TRAN_COMP_INT_CLR : WO ;bitpos:[6] ;default: 1'b0 ; */\r
-/*description: Set this bit to clear the master_tran_comp interrupt.*/\r
-#define I2C_MASTER_TRAN_COMP_INT_CLR (BIT(6))\r
-#define I2C_MASTER_TRAN_COMP_INT_CLR_M (BIT(6))\r
-#define I2C_MASTER_TRAN_COMP_INT_CLR_V 0x1\r
-#define I2C_MASTER_TRAN_COMP_INT_CLR_S 6\r
-/* I2C_ARBITRATION_LOST_INT_CLR : WO ;bitpos:[5] ;default: 1'b0 ; */\r
-/*description: Set this bit to clear the arbitration_lost_int interrupt.*/\r
-#define I2C_ARBITRATION_LOST_INT_CLR (BIT(5))\r
-#define I2C_ARBITRATION_LOST_INT_CLR_M (BIT(5))\r
-#define I2C_ARBITRATION_LOST_INT_CLR_V 0x1\r
-#define I2C_ARBITRATION_LOST_INT_CLR_S 5\r
-/* I2C_SLAVE_TRAN_COMP_INT_CLR : WO ;bitpos:[4] ;default: 1'b0 ; */\r
-/*description: Set this bit to clear the slave_tran_comp_int interrupt.*/\r
-#define I2C_SLAVE_TRAN_COMP_INT_CLR (BIT(4))\r
-#define I2C_SLAVE_TRAN_COMP_INT_CLR_M (BIT(4))\r
-#define I2C_SLAVE_TRAN_COMP_INT_CLR_V 0x1\r
-#define I2C_SLAVE_TRAN_COMP_INT_CLR_S 4\r
-/* I2C_END_DETECT_INT_CLR : WO ;bitpos:[3] ;default: 1'b0 ; */\r
-/*description: Set this bit to clear the end_detect_int interrupt.*/\r
-#define I2C_END_DETECT_INT_CLR (BIT(3))\r
-#define I2C_END_DETECT_INT_CLR_M (BIT(3))\r
-#define I2C_END_DETECT_INT_CLR_V 0x1\r
-#define I2C_END_DETECT_INT_CLR_S 3\r
-/* I2C_RXFIFO_OVF_INT_CLR : WO ;bitpos:[2] ;default: 1'b0 ; */\r
-/*description: Set this bit to clear the rxfifo_ovf_int interrupt.*/\r
-#define I2C_RXFIFO_OVF_INT_CLR (BIT(2))\r
-#define I2C_RXFIFO_OVF_INT_CLR_M (BIT(2))\r
-#define I2C_RXFIFO_OVF_INT_CLR_V 0x1\r
-#define I2C_RXFIFO_OVF_INT_CLR_S 2\r
-/* I2C_TXFIFO_EMPTY_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */\r
-/*description: Set this bit to clear the txfifo_empty_int interrupt.*/\r
-#define I2C_TXFIFO_EMPTY_INT_CLR (BIT(1))\r
-#define I2C_TXFIFO_EMPTY_INT_CLR_M (BIT(1))\r
-#define I2C_TXFIFO_EMPTY_INT_CLR_V 0x1\r
-#define I2C_TXFIFO_EMPTY_INT_CLR_S 1\r
-/* I2C_RXFIFO_FULL_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */\r
-/*description: Set this bit to clear the rxfifo_full_int interrupt.*/\r
-#define I2C_RXFIFO_FULL_INT_CLR (BIT(0))\r
-#define I2C_RXFIFO_FULL_INT_CLR_M (BIT(0))\r
-#define I2C_RXFIFO_FULL_INT_CLR_V 0x1\r
-#define I2C_RXFIFO_FULL_INT_CLR_S 0\r
-\r
-#define I2C_INT_ENA_REG(i) (REG_I2C_BASE(i) + 0x0028)\r
-/* I2C_TX_SEND_EMPTY_INT_ENA : R/W ;bitpos:[12] ;default: 1'b0 ; */\r
-/*description: The enable bit for tx_send_empty_int interrupt.*/\r
-#define I2C_TX_SEND_EMPTY_INT_ENA (BIT(12))\r
-#define I2C_TX_SEND_EMPTY_INT_ENA_M (BIT(12))\r
-#define I2C_TX_SEND_EMPTY_INT_ENA_V 0x1\r
-#define I2C_TX_SEND_EMPTY_INT_ENA_S 12\r
-/* I2C_RX_REC_FULL_INT_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */\r
-/*description: The enable bit for rx_rec_full_int interrupt.*/\r
-#define I2C_RX_REC_FULL_INT_ENA (BIT(11))\r
-#define I2C_RX_REC_FULL_INT_ENA_M (BIT(11))\r
-#define I2C_RX_REC_FULL_INT_ENA_V 0x1\r
-#define I2C_RX_REC_FULL_INT_ENA_S 11\r
-/* I2C_ACK_ERR_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */\r
-/*description: The enable bit for ack_err_int interrupt.*/\r
-#define I2C_ACK_ERR_INT_ENA (BIT(10))\r
-#define I2C_ACK_ERR_INT_ENA_M (BIT(10))\r
-#define I2C_ACK_ERR_INT_ENA_V 0x1\r
-#define I2C_ACK_ERR_INT_ENA_S 10\r
-/* I2C_TRANS_START_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */\r
-/*description: The enable bit for trans_start_int interrupt.*/\r
-#define I2C_TRANS_START_INT_ENA (BIT(9))\r
-#define I2C_TRANS_START_INT_ENA_M (BIT(9))\r
-#define I2C_TRANS_START_INT_ENA_V 0x1\r
-#define I2C_TRANS_START_INT_ENA_S 9\r
-/* I2C_TIME_OUT_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */\r
-/*description: The enable bit for time_out_int interrupt.*/\r
-#define I2C_TIME_OUT_INT_ENA (BIT(8))\r
-#define I2C_TIME_OUT_INT_ENA_M (BIT(8))\r
-#define I2C_TIME_OUT_INT_ENA_V 0x1\r
-#define I2C_TIME_OUT_INT_ENA_S 8\r
-/* I2C_TRANS_COMPLETE_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */\r
-/*description: The enable bit for trans_complete_int interrupt.*/\r
-#define I2C_TRANS_COMPLETE_INT_ENA (BIT(7))\r
-#define I2C_TRANS_COMPLETE_INT_ENA_M (BIT(7))\r
-#define I2C_TRANS_COMPLETE_INT_ENA_V 0x1\r
-#define I2C_TRANS_COMPLETE_INT_ENA_S 7\r
-/* I2C_MASTER_TRAN_COMP_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */\r
-/*description: The enable bit for master_tran_comp_int interrupt.*/\r
-#define I2C_MASTER_TRAN_COMP_INT_ENA (BIT(6))\r
-#define I2C_MASTER_TRAN_COMP_INT_ENA_M (BIT(6))\r
-#define I2C_MASTER_TRAN_COMP_INT_ENA_V 0x1\r
-#define I2C_MASTER_TRAN_COMP_INT_ENA_S 6\r
-/* I2C_ARBITRATION_LOST_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */\r
-/*description: The enable bit for arbitration_lost_int interrupt.*/\r
-#define I2C_ARBITRATION_LOST_INT_ENA (BIT(5))\r
-#define I2C_ARBITRATION_LOST_INT_ENA_M (BIT(5))\r
-#define I2C_ARBITRATION_LOST_INT_ENA_V 0x1\r
-#define I2C_ARBITRATION_LOST_INT_ENA_S 5\r
-/* I2C_SLAVE_TRAN_COMP_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */\r
-/*description: The enable bit for slave_tran_comp_int interrupt.*/\r
-#define I2C_SLAVE_TRAN_COMP_INT_ENA (BIT(4))\r
-#define I2C_SLAVE_TRAN_COMP_INT_ENA_M (BIT(4))\r
-#define I2C_SLAVE_TRAN_COMP_INT_ENA_V 0x1\r
-#define I2C_SLAVE_TRAN_COMP_INT_ENA_S 4\r
-/* I2C_END_DETECT_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */\r
-/*description: The enable bit for end_detect_int interrupt.*/\r
-#define I2C_END_DETECT_INT_ENA (BIT(3))\r
-#define I2C_END_DETECT_INT_ENA_M (BIT(3))\r
-#define I2C_END_DETECT_INT_ENA_V 0x1\r
-#define I2C_END_DETECT_INT_ENA_S 3\r
-/* I2C_RXFIFO_OVF_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */\r
-/*description: The enable bit for rxfifo_ovf_int interrupt.*/\r
-#define I2C_RXFIFO_OVF_INT_ENA (BIT(2))\r
-#define I2C_RXFIFO_OVF_INT_ENA_M (BIT(2))\r
-#define I2C_RXFIFO_OVF_INT_ENA_V 0x1\r
-#define I2C_RXFIFO_OVF_INT_ENA_S 2\r
-/* I2C_TXFIFO_EMPTY_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */\r
-/*description: The enable bit for txfifo_empty_int interrupt.*/\r
-#define I2C_TXFIFO_EMPTY_INT_ENA (BIT(1))\r
-#define I2C_TXFIFO_EMPTY_INT_ENA_M (BIT(1))\r
-#define I2C_TXFIFO_EMPTY_INT_ENA_V 0x1\r
-#define I2C_TXFIFO_EMPTY_INT_ENA_S 1\r
-/* I2C_RXFIFO_FULL_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */\r
-/*description: The enable bit for rxfifo_full_int interrupt.*/\r
-#define I2C_RXFIFO_FULL_INT_ENA (BIT(0))\r
-#define I2C_RXFIFO_FULL_INT_ENA_M (BIT(0))\r
-#define I2C_RXFIFO_FULL_INT_ENA_V 0x1\r
-#define I2C_RXFIFO_FULL_INT_ENA_S 0\r
-\r
-#define I2C_INT_STATUS_REG(i) (REG_I2C_BASE(i) + 0x002c)\r
-/* I2C_TX_SEND_EMPTY_INT_ST : RO ;bitpos:[12] ;default: 1'b0 ; */\r
-/*description: The masked interrupt status for tx_send_empty_int interrupt.*/\r
-#define I2C_TX_SEND_EMPTY_INT_ST (BIT(12))\r
-#define I2C_TX_SEND_EMPTY_INT_ST_M (BIT(12))\r
-#define I2C_TX_SEND_EMPTY_INT_ST_V 0x1\r
-#define I2C_TX_SEND_EMPTY_INT_ST_S 12\r
-/* I2C_RX_REC_FULL_INT_ST : RO ;bitpos:[11] ;default: 1'b0 ; */\r
-/*description: The masked interrupt status for rx_rec_full_int interrupt.*/\r
-#define I2C_RX_REC_FULL_INT_ST (BIT(11))\r
-#define I2C_RX_REC_FULL_INT_ST_M (BIT(11))\r
-#define I2C_RX_REC_FULL_INT_ST_V 0x1\r
-#define I2C_RX_REC_FULL_INT_ST_S 11\r
-/* I2C_ACK_ERR_INT_ST : RO ;bitpos:[10] ;default: 1'b0 ; */\r
-/*description: The masked interrupt status for ack_err_int interrupt.*/\r
-#define I2C_ACK_ERR_INT_ST (BIT(10))\r
-#define I2C_ACK_ERR_INT_ST_M (BIT(10))\r
-#define I2C_ACK_ERR_INT_ST_V 0x1\r
-#define I2C_ACK_ERR_INT_ST_S 10\r
-/* I2C_TRANS_START_INT_ST : RO ;bitpos:[9] ;default: 1'b0 ; */\r
-/*description: The masked interrupt status for trans_start_int interrupt.*/\r
-#define I2C_TRANS_START_INT_ST (BIT(9))\r
-#define I2C_TRANS_START_INT_ST_M (BIT(9))\r
-#define I2C_TRANS_START_INT_ST_V 0x1\r
-#define I2C_TRANS_START_INT_ST_S 9\r
-/* I2C_TIME_OUT_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */\r
-/*description: The masked interrupt status for time_out_int interrupt.*/\r
-#define I2C_TIME_OUT_INT_ST (BIT(8))\r
-#define I2C_TIME_OUT_INT_ST_M (BIT(8))\r
-#define I2C_TIME_OUT_INT_ST_V 0x1\r
-#define I2C_TIME_OUT_INT_ST_S 8\r
-/* I2C_TRANS_COMPLETE_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */\r
-/*description: The masked interrupt status for trans_complete_int interrupt.*/\r
-#define I2C_TRANS_COMPLETE_INT_ST (BIT(7))\r
-#define I2C_TRANS_COMPLETE_INT_ST_M (BIT(7))\r
-#define I2C_TRANS_COMPLETE_INT_ST_V 0x1\r
-#define I2C_TRANS_COMPLETE_INT_ST_S 7\r
-/* I2C_MASTER_TRAN_COMP_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */\r
-/*description: The masked interrupt status for master_tran_comp_int interrupt.*/\r
-#define I2C_MASTER_TRAN_COMP_INT_ST (BIT(6))\r
-#define I2C_MASTER_TRAN_COMP_INT_ST_M (BIT(6))\r
-#define I2C_MASTER_TRAN_COMP_INT_ST_V 0x1\r
-#define I2C_MASTER_TRAN_COMP_INT_ST_S 6\r
-/* I2C_ARBITRATION_LOST_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */\r
-/*description: The masked interrupt status for arbitration_lost_int interrupt.*/\r
-#define I2C_ARBITRATION_LOST_INT_ST (BIT(5))\r
-#define I2C_ARBITRATION_LOST_INT_ST_M (BIT(5))\r
-#define I2C_ARBITRATION_LOST_INT_ST_V 0x1\r
-#define I2C_ARBITRATION_LOST_INT_ST_S 5\r
-/* I2C_SLAVE_TRAN_COMP_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */\r
-/*description: The masked interrupt status for slave_tran_comp_int interrupt.*/\r
-#define I2C_SLAVE_TRAN_COMP_INT_ST (BIT(4))\r
-#define I2C_SLAVE_TRAN_COMP_INT_ST_M (BIT(4))\r
-#define I2C_SLAVE_TRAN_COMP_INT_ST_V 0x1\r
-#define I2C_SLAVE_TRAN_COMP_INT_ST_S 4\r
-/* I2C_END_DETECT_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */\r
-/*description: The masked interrupt status for end_detect_int interrupt.*/\r
-#define I2C_END_DETECT_INT_ST (BIT(3))\r
-#define I2C_END_DETECT_INT_ST_M (BIT(3))\r
-#define I2C_END_DETECT_INT_ST_V 0x1\r
-#define I2C_END_DETECT_INT_ST_S 3\r
-/* I2C_RXFIFO_OVF_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */\r
-/*description: The masked interrupt status for rxfifo_ovf_int interrupt.*/\r
-#define I2C_RXFIFO_OVF_INT_ST (BIT(2))\r
-#define I2C_RXFIFO_OVF_INT_ST_M (BIT(2))\r
-#define I2C_RXFIFO_OVF_INT_ST_V 0x1\r
-#define I2C_RXFIFO_OVF_INT_ST_S 2\r
-/* I2C_TXFIFO_EMPTY_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */\r
-/*description: The masked interrupt status for txfifo_empty_int interrupt.*/\r
-#define I2C_TXFIFO_EMPTY_INT_ST (BIT(1))\r
-#define I2C_TXFIFO_EMPTY_INT_ST_M (BIT(1))\r
-#define I2C_TXFIFO_EMPTY_INT_ST_V 0x1\r
-#define I2C_TXFIFO_EMPTY_INT_ST_S 1\r
-/* I2C_RXFIFO_FULL_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */\r
-/*description: The masked interrupt status for rxfifo_full_int interrupt.*/\r
-#define I2C_RXFIFO_FULL_INT_ST (BIT(0))\r
-#define I2C_RXFIFO_FULL_INT_ST_M (BIT(0))\r
-#define I2C_RXFIFO_FULL_INT_ST_V 0x1\r
-#define I2C_RXFIFO_FULL_INT_ST_S 0\r
-\r
-#define I2C_SDA_HOLD_REG(i) (REG_I2C_BASE(i) + 0x0030)\r
-/* I2C_SDA_HOLD_TIME : R/W ;bitpos:[9:0] ;default: 10'b0 ; */\r
-/*description: This register is used to configure the clock num I2C used to\r
- hold the data after the negedge of SCL.*/\r
-#define I2C_SDA_HOLD_TIME 0x000003FF\r
-#define I2C_SDA_HOLD_TIME_M ((I2C_SDA_HOLD_TIME_V)<<(I2C_SDA_HOLD_TIME_S))\r
-#define I2C_SDA_HOLD_TIME_V 0x3FF\r
-#define I2C_SDA_HOLD_TIME_S 0\r
-\r
-#define I2C_SDA_SAMPLE_REG(i) (REG_I2C_BASE(i) + 0x0034)\r
-/* I2C_SDA_SAMPLE_TIME : R/W ;bitpos:[9:0] ;default: 10'b0 ; */\r
-/*description: This register is used to configure the clock num I2C used to\r
- sample data on SDA after the posedge of SCL*/\r
-#define I2C_SDA_SAMPLE_TIME 0x000003FF\r
-#define I2C_SDA_SAMPLE_TIME_M ((I2C_SDA_SAMPLE_TIME_V)<<(I2C_SDA_SAMPLE_TIME_S))\r
-#define I2C_SDA_SAMPLE_TIME_V 0x3FF\r
-#define I2C_SDA_SAMPLE_TIME_S 0\r
-\r
-#define I2C_SCL_HIGH_PERIOD_REG(i) (REG_I2C_BASE(i) + 0x0038)\r
-/* I2C_SCL_HIGH_PERIOD : R/W ;bitpos:[13:0] ;default: 14'b0 ; */\r
-/*description: This register is used to configure the clock num during SCL is low level.*/\r
-#define I2C_SCL_HIGH_PERIOD 0x00003FFF\r
-#define I2C_SCL_HIGH_PERIOD_M ((I2C_SCL_HIGH_PERIOD_V)<<(I2C_SCL_HIGH_PERIOD_S))\r
-#define I2C_SCL_HIGH_PERIOD_V 0x3FFF\r
-#define I2C_SCL_HIGH_PERIOD_S 0\r
-\r
-#define I2C_SCL_START_HOLD_REG(i) (REG_I2C_BASE(i) + 0x0040)\r
-/* I2C_SCL_START_HOLD_TIME : R/W ;bitpos:[9:0] ;default: 10'b1000 ; */\r
-/*description: This register is used to configure the clock num between the\r
- negedge of SDA and negedge of SCL for start mark.*/\r
-#define I2C_SCL_START_HOLD_TIME 0x000003FF\r
-#define I2C_SCL_START_HOLD_TIME_M ((I2C_SCL_START_HOLD_TIME_V)<<(I2C_SCL_START_HOLD_TIME_S))\r
-#define I2C_SCL_START_HOLD_TIME_V 0x3FF\r
-#define I2C_SCL_START_HOLD_TIME_S 0\r
-\r
-#define I2C_SCL_RSTART_SETUP_REG(i) (REG_I2C_BASE(i) + 0x0044)\r
-/* I2C_SCL_RSTART_SETUP_TIME : R/W ;bitpos:[9:0] ;default: 10'b1000 ; */\r
-/*description: This register is used to configure the clock num between the\r
- posedge of SCL and the negedge of SDA for restart mark.*/\r
-#define I2C_SCL_RSTART_SETUP_TIME 0x000003FF\r
-#define I2C_SCL_RSTART_SETUP_TIME_M ((I2C_SCL_RSTART_SETUP_TIME_V)<<(I2C_SCL_RSTART_SETUP_TIME_S))\r
-#define I2C_SCL_RSTART_SETUP_TIME_V 0x3FF\r
-#define I2C_SCL_RSTART_SETUP_TIME_S 0\r
-\r
-#define I2C_SCL_STOP_HOLD_REG(i) (REG_I2C_BASE(i) + 0x0048)\r
-/* I2C_SCL_STOP_HOLD_TIME : R/W ;bitpos:[13:0] ;default: 14'b0 ; */\r
-/*description: This register is used to configure the clock num after the STOP bit's posedge.*/\r
-#define I2C_SCL_STOP_HOLD_TIME 0x00003FFF\r
-#define I2C_SCL_STOP_HOLD_TIME_M ((I2C_SCL_STOP_HOLD_TIME_V)<<(I2C_SCL_STOP_HOLD_TIME_S))\r
-#define I2C_SCL_STOP_HOLD_TIME_V 0x3FFF\r
-#define I2C_SCL_STOP_HOLD_TIME_S 0\r
-\r
-#define I2C_SCL_STOP_SETUP_REG(i) (REG_I2C_BASE(i) + 0x004C)\r
-/* I2C_SCL_STOP_SETUP_TIME : R/W ;bitpos:[9:0] ;default: 10'b0 ; */\r
-/*description: This register is used to configure the clock num between the\r
- posedge of SCL and the posedge of SDA.*/\r
-#define I2C_SCL_STOP_SETUP_TIME 0x000003FF\r
-#define I2C_SCL_STOP_SETUP_TIME_M ((I2C_SCL_STOP_SETUP_TIME_V)<<(I2C_SCL_STOP_SETUP_TIME_S))\r
-#define I2C_SCL_STOP_SETUP_TIME_V 0x3FF\r
-#define I2C_SCL_STOP_SETUP_TIME_S 0\r
-\r
-#define I2C_SCL_FILTER_CFG_REG(i) (REG_I2C_BASE(i) + 0x0050)\r
-/* I2C_SCL_FILTER_EN : R/W ;bitpos:[3] ;default: 1'b1 ; */\r
-/*description: This is the filter enable bit for SCL.*/\r
-#define I2C_SCL_FILTER_EN (BIT(3))\r
-#define I2C_SCL_FILTER_EN_M (BIT(3))\r
-#define I2C_SCL_FILTER_EN_V 0x1\r
-#define I2C_SCL_FILTER_EN_S 3\r
-/* I2C_SCL_FILTER_THRES : R/W ;bitpos:[2:0] ;default: 3'b0 ; */\r
-/*description: When input SCL's pulse width is smaller than this register value\r
- I2C ignores this pulse.*/\r
-#define I2C_SCL_FILTER_THRES 0x00000007\r
-#define I2C_SCL_FILTER_THRES_M ((I2C_SCL_FILTER_THRES_V)<<(I2C_SCL_FILTER_THRES_S))\r
-#define I2C_SCL_FILTER_THRES_V 0x7\r
-#define I2C_SCL_FILTER_THRES_S 0\r
-\r
-#define I2C_SDA_FILTER_CFG_REG(i) (REG_I2C_BASE(i) + 0x0054)\r
-/* I2C_SDA_FILTER_EN : R/W ;bitpos:[3] ;default: 1'b1 ; */\r
-/*description: This is the filter enable bit for SDA.*/\r
-#define I2C_SDA_FILTER_EN (BIT(3))\r
-#define I2C_SDA_FILTER_EN_M (BIT(3))\r
-#define I2C_SDA_FILTER_EN_V 0x1\r
-#define I2C_SDA_FILTER_EN_S 3\r
-/* I2C_SDA_FILTER_THRES : R/W ;bitpos:[2:0] ;default: 3'b0 ; */\r
-/*description: When input SCL's pulse width is smaller than this register value\r
- I2C ignores this pulse.*/\r
-#define I2C_SDA_FILTER_THRES 0x00000007\r
-#define I2C_SDA_FILTER_THRES_M ((I2C_SDA_FILTER_THRES_V)<<(I2C_SDA_FILTER_THRES_S))\r
-#define I2C_SDA_FILTER_THRES_V 0x7\r
-#define I2C_SDA_FILTER_THRES_S 0\r
-\r
-#define I2C_COMD0_REG(i) (REG_I2C_BASE(i) + 0x0058)\r
-/* I2C_COMMAND0_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */\r
-/*description: When command0 is done in I2C Master mode this bit changes to high level.*/\r
-#define I2C_COMMAND0_DONE (BIT(31))\r
-#define I2C_COMMAND0_DONE_M (BIT(31))\r
-#define I2C_COMMAND0_DONE_V 0x1\r
-#define I2C_COMMAND0_DONE_S 31\r
-/* I2C_COMMAND0 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */\r
-/*description: This is the content of command0. It consists of three part. op_code\r
- is the command 0: RSTART 1: WRITE 2: READ 3: STOP . 4:END. Byte_num represent the number of data need to be send or data need to be received. ack_check_en ack_exp and ack value are used to control the ack bit.*/\r
-#define I2C_COMMAND0 0x00003FFF\r
-#define I2C_COMMAND0_M ((I2C_COMMAND0_V)<<(I2C_COMMAND0_S))\r
-#define I2C_COMMAND0_V 0x3FFF\r
-#define I2C_COMMAND0_S 0\r
-\r
-#define I2C_COMD1_REG(i) (REG_I2C_BASE(i) + 0x005C)\r
-/* I2C_COMMAND1_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */\r
-/*description: When command1 is done in I2C Master mode this bit changes to high level.*/\r
-#define I2C_COMMAND1_DONE (BIT(31))\r
-#define I2C_COMMAND1_DONE_M (BIT(31))\r
-#define I2C_COMMAND1_DONE_V 0x1\r
-#define I2C_COMMAND1_DONE_S 31\r
-/* I2C_COMMAND1 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */\r
-/*description: This is the content of command1. It consists of three part. op_code\r
- is the command 0: RSTART 1: WRITE 2: READ 3: STOP . 4:END. Byte_num represent the number of data need to be send or data need to be received. ack_check_en ack_exp and ack value are used to control the ack bit.*/\r
-#define I2C_COMMAND1 0x00003FFF\r
-#define I2C_COMMAND1_M ((I2C_COMMAND1_V)<<(I2C_COMMAND1_S))\r
-#define I2C_COMMAND1_V 0x3FFF\r
-#define I2C_COMMAND1_S 0\r
-\r
-#define I2C_COMD2_REG(i) (REG_I2C_BASE(i) + 0x0060)\r
-/* I2C_COMMAND2_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */\r
-/*description: When command2 is done in I2C Master mode this bit changes to high level.*/\r
-#define I2C_COMMAND2_DONE (BIT(31))\r
-#define I2C_COMMAND2_DONE_M (BIT(31))\r
-#define I2C_COMMAND2_DONE_V 0x1\r
-#define I2C_COMMAND2_DONE_S 31\r
-/* I2C_COMMAND2 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */\r
-/*description: This is the content of command2. It consists of three part. op_code\r
- is the command 0: RSTART 1: WRITE 2: READ 3: STOP . 4:END. Byte_num represent the number of data need to be send or data need to be received. ack_check_en ack_exp and ack value are used to control the ack bit.*/\r
-#define I2C_COMMAND2 0x00003FFF\r
-#define I2C_COMMAND2_M ((I2C_COMMAND2_V)<<(I2C_COMMAND2_S))\r
-#define I2C_COMMAND2_V 0x3FFF\r
-#define I2C_COMMAND2_S 0\r
-\r
-#define I2C_COMD3_REG(i) (REG_I2C_BASE(i) + 0x0064)\r
-/* I2C_COMMAND3_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */\r
-/*description: When command3 is done in I2C Master mode this bit changes to high level.*/\r
-#define I2C_COMMAND3_DONE (BIT(31))\r
-#define I2C_COMMAND3_DONE_M (BIT(31))\r
-#define I2C_COMMAND3_DONE_V 0x1\r
-#define I2C_COMMAND3_DONE_S 31\r
-/* I2C_COMMAND3 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */\r
-/*description: This is the content of command3. It consists of three part. op_code\r
- is the command 0: RSTART 1: WRITE 2: READ 3: STOP . 4:END. Byte_num represent the number of data need to be send or data need to be received. ack_check_en ack_exp and ack value are used to control the ack bit.*/\r
-#define I2C_COMMAND3 0x00003FFF\r
-#define I2C_COMMAND3_M ((I2C_COMMAND3_V)<<(I2C_COMMAND3_S))\r
-#define I2C_COMMAND3_V 0x3FFF\r
-#define I2C_COMMAND3_S 0\r
-\r
-#define I2C_COMD4_REG(i) (REG_I2C_BASE(i) + 0x0068)\r
-/* I2C_COMMAND4_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */\r
-/*description: When command4 is done in I2C Master mode this bit changes to high level.*/\r
-#define I2C_COMMAND4_DONE (BIT(31))\r
-#define I2C_COMMAND4_DONE_M (BIT(31))\r
-#define I2C_COMMAND4_DONE_V 0x1\r
-#define I2C_COMMAND4_DONE_S 31\r
-/* I2C_COMMAND4 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */\r
-/*description: This is the content of command4. It consists of three part. op_code\r
- is the command 0: RSTART 1: WRITE 2: READ 3: STOP . 4:END. Byte_num represent the number of data need to be send or data need to be received. ack_check_en ack_exp and ack value are used to control the ack bit.*/\r
-#define I2C_COMMAND4 0x00003FFF\r
-#define I2C_COMMAND4_M ((I2C_COMMAND4_V)<<(I2C_COMMAND4_S))\r
-#define I2C_COMMAND4_V 0x3FFF\r
-#define I2C_COMMAND4_S 0\r
-\r
-#define I2C_COMD5_REG(i) (REG_I2C_BASE(i) + 0x006C)\r
-/* I2C_COMMAND5_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */\r
-/*description: When command5 is done in I2C Master mode this bit changes to high level.*/\r
-#define I2C_COMMAND5_DONE (BIT(31))\r
-#define I2C_COMMAND5_DONE_M (BIT(31))\r
-#define I2C_COMMAND5_DONE_V 0x1\r
-#define I2C_COMMAND5_DONE_S 31\r
-/* I2C_COMMAND5 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */\r
-/*description: This is the content of command5. It consists of three part. op_code\r
- is the command 0: RSTART 1: WRITE 2: READ 3: STOP . 4:END. Byte_num represent the number of data need to be send or data need to be received. ack_check_en ack_exp and ack value are used to control the ack bit.*/\r
-#define I2C_COMMAND5 0x00003FFF\r
-#define I2C_COMMAND5_M ((I2C_COMMAND5_V)<<(I2C_COMMAND5_S))\r
-#define I2C_COMMAND5_V 0x3FFF\r
-#define I2C_COMMAND5_S 0\r
-\r
-#define I2C_COMD6_REG(i) (REG_I2C_BASE(i) + 0x0070)\r
-/* I2C_COMMAND6_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */\r
-/*description: When command6 is done in I2C Master mode this bit changes to high level.*/\r
-#define I2C_COMMAND6_DONE (BIT(31))\r
-#define I2C_COMMAND6_DONE_M (BIT(31))\r
-#define I2C_COMMAND6_DONE_V 0x1\r
-#define I2C_COMMAND6_DONE_S 31\r
-/* I2C_COMMAND6 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */\r
-/*description: This is the content of command6. It consists of three part. op_code\r
- is the command 0: RSTART 1: WRITE 2: READ 3: STOP . 4:END. Byte_num represent the number of data need to be send or data need to be received. ack_check_en ack_exp and ack value are used to control the ack bit.*/\r
-#define I2C_COMMAND6 0x00003FFF\r
-#define I2C_COMMAND6_M ((I2C_COMMAND6_V)<<(I2C_COMMAND6_S))\r
-#define I2C_COMMAND6_V 0x3FFF\r
-#define I2C_COMMAND6_S 0\r
-\r
-#define I2C_COMD7_REG(i) (REG_I2C_BASE(i) + 0x0074)\r
-/* I2C_COMMAND7_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */\r
-/*description: When command7 is done in I2C Master mode this bit changes to high level.*/\r
-#define I2C_COMMAND7_DONE (BIT(31))\r
-#define I2C_COMMAND7_DONE_M (BIT(31))\r
-#define I2C_COMMAND7_DONE_V 0x1\r
-#define I2C_COMMAND7_DONE_S 31\r
-/* I2C_COMMAND7 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */\r
-/*description: This is the content of command7. It consists of three part. op_code\r
- is the command 0: RSTART 1: WRITE 2: READ 3: STOP . 4:END. Byte_num represent the number of data need to be send or data need to be received. ack_check_en ack_exp and ack value are used to control the ack bit.*/\r
-#define I2C_COMMAND7 0x00003FFF\r
-#define I2C_COMMAND7_M ((I2C_COMMAND7_V)<<(I2C_COMMAND7_S))\r
-#define I2C_COMMAND7_V 0x3FFF\r
-#define I2C_COMMAND7_S 0\r
-\r
-#define I2C_COMD8_REG(i) (REG_I2C_BASE(i) + 0x0078)\r
-/* I2C_COMMAND8_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */\r
-/*description: When command8 is done in I2C Master mode this bit changes to high level.*/\r
-#define I2C_COMMAND8_DONE (BIT(31))\r
-#define I2C_COMMAND8_DONE_M (BIT(31))\r
-#define I2C_COMMAND8_DONE_V 0x1\r
-#define I2C_COMMAND8_DONE_S 31\r
-/* I2C_COMMAND8 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */\r
-/*description: This is the content of command8. It consists of three part. op_code\r
- is the command 0: RSTART 1: WRITE 2: READ 3: STOP . 4:END. Byte_num represent the number of data need to be send or data need to be received. ack_check_en ack_exp and ack value are used to control the ack bit.*/\r
-#define I2C_COMMAND8 0x00003FFF\r
-#define I2C_COMMAND8_M ((I2C_COMMAND8_V)<<(I2C_COMMAND8_S))\r
-#define I2C_COMMAND8_V 0x3FFF\r
-#define I2C_COMMAND8_S 0\r
-\r
-#define I2C_COMD9_REG(i) (REG_I2C_BASE(i) + 0x007C)\r
-/* I2C_COMMAND9_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */\r
-/*description: When command9 is done in I2C Master mode this bit changes to high level.*/\r
-#define I2C_COMMAND9_DONE (BIT(31))\r
-#define I2C_COMMAND9_DONE_M (BIT(31))\r
-#define I2C_COMMAND9_DONE_V 0x1\r
-#define I2C_COMMAND9_DONE_S 31\r
-/* I2C_COMMAND9 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */\r
-/*description: This is the content of command9. It consists of three part. op_code\r
- is the command 0: RSTART 1: WRITE 2: READ 3: STOP . 4:END. Byte_num represent the number of data need to be send or data need to be received. ack_check_en ack_exp and ack value are used to control the ack bit.*/\r
-#define I2C_COMMAND9 0x00003FFF\r
-#define I2C_COMMAND9_M ((I2C_COMMAND9_V)<<(I2C_COMMAND9_S))\r
-#define I2C_COMMAND9_V 0x3FFF\r
-#define I2C_COMMAND9_S 0\r
-\r
-#define I2C_COMD10_REG(i) (REG_I2C_BASE(i) + 0x0080)\r
-/* I2C_COMMAND10_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */\r
-/*description: When command10 is done in I2C Master mode this bit changes to high level.*/\r
-#define I2C_COMMAND10_DONE (BIT(31))\r
-#define I2C_COMMAND10_DONE_M (BIT(31))\r
-#define I2C_COMMAND10_DONE_V 0x1\r
-#define I2C_COMMAND10_DONE_S 31\r
-/* I2C_COMMAND10 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */\r
-/*description: This is the content of command10. It consists of three part.\r
- op_code is the command 0: RSTART 1: WRITE 2: READ 3: STOP . 4:END. Byte_num represent the number of data need to be send or data need to be received. ack_check_en ack_exp and ack value are used to control the ack bit.*/\r
-#define I2C_COMMAND10 0x00003FFF\r
-#define I2C_COMMAND10_M ((I2C_COMMAND10_V)<<(I2C_COMMAND10_S))\r
-#define I2C_COMMAND10_V 0x3FFF\r
-#define I2C_COMMAND10_S 0\r
-\r
-#define I2C_COMD11_REG(i) (REG_I2C_BASE(i) + 0x0084)\r
-/* I2C_COMMAND11_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */\r
-/*description: When command11 is done in I2C Master mode this bit changes to high level.*/\r
-#define I2C_COMMAND11_DONE (BIT(31))\r
-#define I2C_COMMAND11_DONE_M (BIT(31))\r
-#define I2C_COMMAND11_DONE_V 0x1\r
-#define I2C_COMMAND11_DONE_S 31\r
-/* I2C_COMMAND11 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */\r
-/*description: This is the content of command11. It consists of three part.\r
- op_code is the command 0: RSTART 1: WRITE 2: READ 3: STOP . 4:END. Byte_num represent the number of data need to be send or data need to be received. ack_check_en ack_exp and ack value are used to control the ack bit.*/\r
-#define I2C_COMMAND11 0x00003FFF\r
-#define I2C_COMMAND11_M ((I2C_COMMAND11_V)<<(I2C_COMMAND11_S))\r
-#define I2C_COMMAND11_V 0x3FFF\r
-#define I2C_COMMAND11_S 0\r
-\r
-#define I2C_COMD12_REG(i) (REG_I2C_BASE(i) + 0x0088)\r
-/* I2C_COMMAND12_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */\r
-/*description: When command12 is done in I2C Master mode this bit changes to high level.*/\r
-#define I2C_COMMAND12_DONE (BIT(31))\r
-#define I2C_COMMAND12_DONE_M (BIT(31))\r
-#define I2C_COMMAND12_DONE_V 0x1\r
-#define I2C_COMMAND12_DONE_S 31\r
-/* I2C_COMMAND12 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */\r
-/*description: This is the content of command12. It consists of three part.\r
- op_code is the command 0: RSTART 1: WRITE 2: READ 3: STOP . 4:END. Byte_num represent the number of data need to be send or data need to be received. ack_check_en ack_exp and ack value are used to control the ack bit.*/\r
-#define I2C_COMMAND12 0x00003FFF\r
-#define I2C_COMMAND12_M ((I2C_COMMAND12_V)<<(I2C_COMMAND12_S))\r
-#define I2C_COMMAND12_V 0x3FFF\r
-#define I2C_COMMAND12_S 0\r
-\r
-#define I2C_COMD13_REG(i) (REG_I2C_BASE(i) + 0x008C)\r
-/* I2C_COMMAND13_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */\r
-/*description: When command13 is done in I2C Master mode this bit changes to high level.*/\r
-#define I2C_COMMAND13_DONE (BIT(31))\r
-#define I2C_COMMAND13_DONE_M (BIT(31))\r
-#define I2C_COMMAND13_DONE_V 0x1\r
-#define I2C_COMMAND13_DONE_S 31\r
-/* I2C_COMMAND13 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */\r
-/*description: This is the content of command13. It consists of three part.\r
- op_code is the command 0: RSTART 1: WRITE 2: READ 3: STOP . 4:END. Byte_num represent the number of data need to be send or data need to be received. ack_check_en ack_exp and ack value are used to control the ack bit.*/\r
-#define I2C_COMMAND13 0x00003FFF\r
-#define I2C_COMMAND13_M ((I2C_COMMAND13_V)<<(I2C_COMMAND13_S))\r
-#define I2C_COMMAND13_V 0x3FFF\r
-#define I2C_COMMAND13_S 0\r
-\r
-#define I2C_COMD14_REG(i) (REG_I2C_BASE(i) + 0x0090)\r
-/* I2C_COMMAND14_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */\r
-/*description: When command14 is done in I2C Master mode this bit changes to high level.*/\r
-#define I2C_COMMAND14_DONE (BIT(31))\r
-#define I2C_COMMAND14_DONE_M (BIT(31))\r
-#define I2C_COMMAND14_DONE_V 0x1\r
-#define I2C_COMMAND14_DONE_S 31\r
-/* I2C_COMMAND14 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */\r
-/*description: This is the content of command14. It consists of three part.\r
- op_code is the command 0: RSTART 1: WRITE 2: READ 3: STOP . 4:END. Byte_num represent the number of data need to be send or data need to be received. ack_check_en ack_exp and ack value are used to control the ack bit.*/\r
-#define I2C_COMMAND14 0x00003FFF\r
-#define I2C_COMMAND14_M ((I2C_COMMAND14_V)<<(I2C_COMMAND14_S))\r
-#define I2C_COMMAND14_V 0x3FFF\r
-#define I2C_COMMAND14_S 0\r
-\r
-#define I2C_COMD15_REG(i) (REG_I2C_BASE(i) + 0x0094)\r
-/* I2C_COMMAND15_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */\r
-/*description: When command15 is done in I2C Master mode this bit changes to high level.*/\r
-#define I2C_COMMAND15_DONE (BIT(31))\r
-#define I2C_COMMAND15_DONE_M (BIT(31))\r
-#define I2C_COMMAND15_DONE_V 0x1\r
-#define I2C_COMMAND15_DONE_S 31\r
-/* I2C_COMMAND15 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */\r
-/*description: This is the content of command15. It consists of three part.\r
- op_code is the command 0: RSTART 1: WRITE 2: READ 3: STOP . 4:END. Byte_num represent the number of data need to be send or data need to be received. ack_check_en ack_exp and ack value are used to control the ack bit.*/\r
-#define I2C_COMMAND15 0x00003FFF\r
-#define I2C_COMMAND15_M ((I2C_COMMAND15_V)<<(I2C_COMMAND15_S))\r
-#define I2C_COMMAND15_V 0x3FFF\r
-#define I2C_COMMAND15_S 0\r
-\r
-#define I2C_DATE_REG(i) (REG_I2C_BASE(i) + 0x00F8)\r
-/* I2C_DATE : R/W ;bitpos:[31:0] ;default: 32'h16042000 ; */\r
-/*description: */\r
-#define I2C_DATE 0xFFFFFFFF\r
-#define I2C_DATE_M ((I2C_DATE_V)<<(I2C_DATE_S))\r
-#define I2C_DATE_V 0xFFFFFFFF\r
-#define I2C_DATE_S 0\r
-\r
-#define I2C_FIFO_START_ADDR_REG(i) (REG_I2C_BASE(i) + 0x0100)\r
-\r
-\r
-\r
-\r
-#endif /*_SOC_I2C_REG_H_ */\r
-\r
-\r
+// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+#ifndef _SOC_I2C_REG_H_
+#define _SOC_I2C_REG_H_
+
+
+#include "soc.h"
+
+#define REG_I2C_BASE(i) (DR_REG_I2C_EXT_BASE + (i) * 0x14000 )
+
+#define I2C_SCL_LOW_PERIOD_REG(i) (REG_I2C_BASE(i) + 0x0000)
+/* I2C_SCL_LOW_PERIOD : R/W ;bitpos:[13:0] ;default: 14'b0 ; */
+/*description: This register is used to configure the low level width of SCL clock.*/
+#define I2C_SCL_LOW_PERIOD 0x00003FFF
+#define I2C_SCL_LOW_PERIOD_M ((I2C_SCL_LOW_PERIOD_V)<<(I2C_SCL_LOW_PERIOD_S))
+#define I2C_SCL_LOW_PERIOD_V 0x3FFF
+#define I2C_SCL_LOW_PERIOD_S 0
+
+#define I2C_CTR_REG(i) (REG_I2C_BASE(i) + 0x0004)
+/* I2C_CLK_EN : R/W ;bitpos:[8] ;default: 1'b0 ; */
+/*description: This is the clock gating control bit for reading or writing registers.*/
+#define I2C_CLK_EN (BIT(8))
+#define I2C_CLK_EN_M (BIT(8))
+#define I2C_CLK_EN_V 0x1
+#define I2C_CLK_EN_S 8
+/* I2C_RX_LSB_FIRST : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: This bit is used to control the storage mode for received datas.
+ 1: receive data from most significant bit 0: receive data from least significant bit*/
+#define I2C_RX_LSB_FIRST (BIT(7))
+#define I2C_RX_LSB_FIRST_M (BIT(7))
+#define I2C_RX_LSB_FIRST_V 0x1
+#define I2C_RX_LSB_FIRST_S 7
+/* I2C_TX_LSB_FIRST : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: This bit is used to control the sending mode for data need to
+ be send. 1: receive data from most significant bit 0: receive data from least significant bit*/
+#define I2C_TX_LSB_FIRST (BIT(6))
+#define I2C_TX_LSB_FIRST_M (BIT(6))
+#define I2C_TX_LSB_FIRST_V 0x1
+#define I2C_TX_LSB_FIRST_S 6
+/* I2C_TRANS_START : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: Set this bit to start sending data in txfifo.*/
+#define I2C_TRANS_START (BIT(5))
+#define I2C_TRANS_START_M (BIT(5))
+#define I2C_TRANS_START_V 0x1
+#define I2C_TRANS_START_S 5
+/* I2C_MS_MODE : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: Set this bit to configure the module as i2c master clear this
+ bit to configure the module as i2c slave.*/
+#define I2C_MS_MODE (BIT(4))
+#define I2C_MS_MODE_M (BIT(4))
+#define I2C_MS_MODE_V 0x1
+#define I2C_MS_MODE_S 4
+/* I2C_SAMPLE_SCL_LEVEL : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: Set this bit to sample data in SCL low level. clear this bit
+ to sample data in SCL high level.*/
+#define I2C_SAMPLE_SCL_LEVEL (BIT(2))
+#define I2C_SAMPLE_SCL_LEVEL_M (BIT(2))
+#define I2C_SAMPLE_SCL_LEVEL_V 0x1
+#define I2C_SAMPLE_SCL_LEVEL_S 2
+/* I2C_SCL_FORCE_OUT : R/W ;bitpos:[1] ;default: 1'b1 ; */
+/*description: 1: normally ouput scl clock 0: exchange the function of scl_o
+ and scl_oe (scl_o is the original internal output scl signal scl_oe is the enable bit for the internal output scl signal)*/
+#define I2C_SCL_FORCE_OUT (BIT(1))
+#define I2C_SCL_FORCE_OUT_M (BIT(1))
+#define I2C_SCL_FORCE_OUT_V 0x1
+#define I2C_SCL_FORCE_OUT_S 1
+/* I2C_SDA_FORCE_OUT : R/W ;bitpos:[0] ;default: 1'b1 ; */
+/*description: 1: normally ouput sda data 0: exchange the function of sda_o
+ and sda_oe (sda_o is the original internal output sda signal sda_oe is the enable bit for the internal output sda signal)*/
+#define I2C_SDA_FORCE_OUT (BIT(0))
+#define I2C_SDA_FORCE_OUT_M (BIT(0))
+#define I2C_SDA_FORCE_OUT_V 0x1
+#define I2C_SDA_FORCE_OUT_S 0
+
+#define I2C_SR_REG(i) (REG_I2C_BASE(i) + 0x0008)
+/* I2C_SCL_STATE_LAST : RO ;bitpos:[30:28] ;default: 3'b0 ; */
+/*description: This register stores the value of state machine to produce SCL.
+ 3'h0: SCL_IDLE 3'h1:SCL_START 3'h2:SCL_LOW_EDGE 3'h3: SCL_LOW 3'h4:SCL_HIGH_EDGE 3'h5:SCL_HIGH 3'h6:SCL_STOP*/
+#define I2C_SCL_STATE_LAST 0x00000007
+#define I2C_SCL_STATE_LAST_M ((I2C_SCL_STATE_LAST_V)<<(I2C_SCL_STATE_LAST_S))
+#define I2C_SCL_STATE_LAST_V 0x7
+#define I2C_SCL_STATE_LAST_S 28
+/* I2C_SCL_MAIN_STATE_LAST : RO ;bitpos:[26:24] ;default: 3'b0 ; */
+/*description: This register stores the value of state machine for i2c module.
+ 3'h0: SCL_MAIN_IDLE 3'h1: SCL_ADDRESS_SHIFT 3'h2: SCL_ACK_ADDRESS 3'h3: SCL_RX_DATA 3'h4 SCL_TX_DATA 3'h5:SCL_SEND_ACK 3'h6:SCL_WAIT_ACK*/
+#define I2C_SCL_MAIN_STATE_LAST 0x00000007
+#define I2C_SCL_MAIN_STATE_LAST_M ((I2C_SCL_MAIN_STATE_LAST_V)<<(I2C_SCL_MAIN_STATE_LAST_S))
+#define I2C_SCL_MAIN_STATE_LAST_V 0x7
+#define I2C_SCL_MAIN_STATE_LAST_S 24
+/* I2C_TXFIFO_CNT : RO ;bitpos:[23:18] ;default: 6'b0 ; */
+/*description: This register stores the amount of received data in ram.*/
+#define I2C_TXFIFO_CNT 0x0000003F
+#define I2C_TXFIFO_CNT_M ((I2C_TXFIFO_CNT_V)<<(I2C_TXFIFO_CNT_S))
+#define I2C_TXFIFO_CNT_V 0x3F
+#define I2C_TXFIFO_CNT_S 18
+/* I2C_RXFIFO_CNT : RO ;bitpos:[13:8] ;default: 6'b0 ; */
+/*description: This register represent the amount of data need to send.*/
+#define I2C_RXFIFO_CNT 0x0000003F
+#define I2C_RXFIFO_CNT_M ((I2C_RXFIFO_CNT_V)<<(I2C_RXFIFO_CNT_S))
+#define I2C_RXFIFO_CNT_V 0x3F
+#define I2C_RXFIFO_CNT_S 8
+/* I2C_BYTE_TRANS : RO ;bitpos:[6] ;default: 1'b0 ; */
+/*description: This register changes to high level when one byte is transferred.*/
+#define I2C_BYTE_TRANS (BIT(6))
+#define I2C_BYTE_TRANS_M (BIT(6))
+#define I2C_BYTE_TRANS_V 0x1
+#define I2C_BYTE_TRANS_S 6
+/* I2C_SLAVE_ADDRESSED : RO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: when configured as i2c slave and the address send by master
+ is equal to slave's address then this bit will be high level.*/
+#define I2C_SLAVE_ADDRESSED (BIT(5))
+#define I2C_SLAVE_ADDRESSED_M (BIT(5))
+#define I2C_SLAVE_ADDRESSED_V 0x1
+#define I2C_SLAVE_ADDRESSED_S 5
+/* I2C_BUS_BUSY : RO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: 1:I2C bus is busy transferring data. 0:I2C bus is in idle state.*/
+#define I2C_BUS_BUSY (BIT(4))
+#define I2C_BUS_BUSY_M (BIT(4))
+#define I2C_BUS_BUSY_V 0x1
+#define I2C_BUS_BUSY_S 4
+/* I2C_ARB_LOST : RO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: when I2C lost control of SDA line this register changes to high level.*/
+#define I2C_ARB_LOST (BIT(3))
+#define I2C_ARB_LOST_M (BIT(3))
+#define I2C_ARB_LOST_V 0x1
+#define I2C_ARB_LOST_S 3
+/* I2C_TIME_OUT : RO ;bitpos:[2] ;default: 1'b0 ; */
+/*description: when I2C takes more than time_out_reg clocks to receive a data
+ then this register changes to high level.*/
+#define I2C_TIME_OUT (BIT(2))
+#define I2C_TIME_OUT_M (BIT(2))
+#define I2C_TIME_OUT_V 0x1
+#define I2C_TIME_OUT_S 2
+/* I2C_SLAVE_RW : RO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: when in slave mode 1: master read slave 0: master write slave.*/
+#define I2C_SLAVE_RW (BIT(1))
+#define I2C_SLAVE_RW_M (BIT(1))
+#define I2C_SLAVE_RW_V 0x1
+#define I2C_SLAVE_RW_S 1
+/* I2C_ACK_REC : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: This register stores the value of ACK bit.*/
+#define I2C_ACK_REC (BIT(0))
+#define I2C_ACK_REC_M (BIT(0))
+#define I2C_ACK_REC_V 0x1
+#define I2C_ACK_REC_S 0
+
+#define I2C_TO_REG(i) (REG_I2C_BASE(i) + 0x000c)
+/* I2C_TIME_OUT_REG : R/W ;bitpos:[19:0] ;default: 20'b0 ; */
+/*description: This register is used to configure the max clock number of receiving a data.*/
+#define I2C_TIME_OUT_REG 0x000FFFFF
+#define I2C_TIME_OUT_REG_M ((I2C_TIME_OUT_REG_V)<<(I2C_TIME_OUT_REG_S))
+#define I2C_TIME_OUT_REG_V 0xFFFFF
+#define I2C_TIME_OUT_REG_S 0
+
+#define I2C_SLAVE_ADDR_REG(i) (REG_I2C_BASE(i) + 0x0010)
+/* I2C_ADDR_10BIT_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */
+/*description: This register is used to enable slave 10bit address mode.*/
+#define I2C_ADDR_10BIT_EN (BIT(31))
+#define I2C_ADDR_10BIT_EN_M (BIT(31))
+#define I2C_ADDR_10BIT_EN_V 0x1
+#define I2C_ADDR_10BIT_EN_S 31
+/* I2C_SLAVE_ADDR : R/W ;bitpos:[14:0] ;default: 15'b0 ; */
+/*description: when configured as i2c slave this register is used to configure
+ slave's address.*/
+#define I2C_SLAVE_ADDR 0x00007FFF
+#define I2C_SLAVE_ADDR_M ((I2C_SLAVE_ADDR_V)<<(I2C_SLAVE_ADDR_S))
+#define I2C_SLAVE_ADDR_V 0x7FFF
+#define I2C_SLAVE_ADDR_S 0
+
+#define I2C_RXFIFO_ST_REG(i) (REG_I2C_BASE(i) + 0x0014)
+/* I2C_TXFIFO_END_ADDR : RO ;bitpos:[19:15] ;default: 5'b0 ; */
+/*description: This is the offset address of the last sending data as described
+ in nonfifo_tx_thres register.*/
+#define I2C_TXFIFO_END_ADDR 0x0000001F
+#define I2C_TXFIFO_END_ADDR_M ((I2C_TXFIFO_END_ADDR_V)<<(I2C_TXFIFO_END_ADDR_S))
+#define I2C_TXFIFO_END_ADDR_V 0x1F
+#define I2C_TXFIFO_END_ADDR_S 15
+/* I2C_TXFIFO_START_ADDR : RO ;bitpos:[14:10] ;default: 5'b0 ; */
+/*description: This is the offset address of the first sending data as described
+ in nonfifo_tx_thres register.*/
+#define I2C_TXFIFO_START_ADDR 0x0000001F
+#define I2C_TXFIFO_START_ADDR_M ((I2C_TXFIFO_START_ADDR_V)<<(I2C_TXFIFO_START_ADDR_S))
+#define I2C_TXFIFO_START_ADDR_V 0x1F
+#define I2C_TXFIFO_START_ADDR_S 10
+/* I2C_RXFIFO_END_ADDR : RO ;bitpos:[9:5] ;default: 5'b0 ; */
+/*description: This is the offset address of the first receiving data as described
+ in nonfifo_rx_thres_register.*/
+#define I2C_RXFIFO_END_ADDR 0x0000001F
+#define I2C_RXFIFO_END_ADDR_M ((I2C_RXFIFO_END_ADDR_V)<<(I2C_RXFIFO_END_ADDR_S))
+#define I2C_RXFIFO_END_ADDR_V 0x1F
+#define I2C_RXFIFO_END_ADDR_S 5
+/* I2C_RXFIFO_START_ADDR : RO ;bitpos:[4:0] ;default: 5'b0 ; */
+/*description: This is the offset address of the last receiving data as described
+ in nonfifo_rx_thres_register.*/
+#define I2C_RXFIFO_START_ADDR 0x0000001F
+#define I2C_RXFIFO_START_ADDR_M ((I2C_RXFIFO_START_ADDR_V)<<(I2C_RXFIFO_START_ADDR_S))
+#define I2C_RXFIFO_START_ADDR_V 0x1F
+#define I2C_RXFIFO_START_ADDR_S 0
+
+#define I2C_FIFO_CONF_REG(i) (REG_I2C_BASE(i) + 0x0018)
+/* I2C_NONFIFO_TX_THRES : R/W ;bitpos:[25:20] ;default: 6'h15 ; */
+/*description: when I2C sends more than nonfifo_tx_thres data it will produce
+ tx_send_empty_int_raw interrupt and update the current offset address of the sending data.*/
+#define I2C_NONFIFO_TX_THRES 0x0000003F
+#define I2C_NONFIFO_TX_THRES_M ((I2C_NONFIFO_TX_THRES_V)<<(I2C_NONFIFO_TX_THRES_S))
+#define I2C_NONFIFO_TX_THRES_V 0x3F
+#define I2C_NONFIFO_TX_THRES_S 20
+/* I2C_NONFIFO_RX_THRES : R/W ;bitpos:[19:14] ;default: 6'h15 ; */
+/*description: when I2C receives more than nonfifo_rx_thres data it will produce
+ rx_send_full_int_raw interrupt and update the current offset address of the receiving data.*/
+#define I2C_NONFIFO_RX_THRES 0x0000003F
+#define I2C_NONFIFO_RX_THRES_M ((I2C_NONFIFO_RX_THRES_V)<<(I2C_NONFIFO_RX_THRES_S))
+#define I2C_NONFIFO_RX_THRES_V 0x3F
+#define I2C_NONFIFO_RX_THRES_S 14
+/* I2C_TX_FIFO_RST : R/W ;bitpos:[13] ;default: 1'b0 ; */
+/*description: Set this bit to reset tx fifo when using apb fifo access.*/
+#define I2C_TX_FIFO_RST (BIT(13))
+#define I2C_TX_FIFO_RST_M (BIT(13))
+#define I2C_TX_FIFO_RST_V 0x1
+#define I2C_TX_FIFO_RST_S 13
+/* I2C_RX_FIFO_RST : R/W ;bitpos:[12] ;default: 1'b0 ; */
+/*description: Set this bit to reset rx fifo when using apb fifo access.*/
+#define I2C_RX_FIFO_RST (BIT(12))
+#define I2C_RX_FIFO_RST_M (BIT(12))
+#define I2C_RX_FIFO_RST_V 0x1
+#define I2C_RX_FIFO_RST_S 12
+/* I2C_FIFO_ADDR_CFG_EN : R/W ;bitpos:[11] ;default: 1'b0 ; */
+/*description: When this bit is set to 1 then the byte after address represent
+ the offset address of I2C Slave's ram.*/
+#define I2C_FIFO_ADDR_CFG_EN (BIT(11))
+#define I2C_FIFO_ADDR_CFG_EN_M (BIT(11))
+#define I2C_FIFO_ADDR_CFG_EN_V 0x1
+#define I2C_FIFO_ADDR_CFG_EN_S 11
+/* I2C_NONFIFO_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */
+/*description: Set this bit to enble apb nonfifo access.*/
+#define I2C_NONFIFO_EN (BIT(10))
+#define I2C_NONFIFO_EN_M (BIT(10))
+#define I2C_NONFIFO_EN_V 0x1
+#define I2C_NONFIFO_EN_S 10
+/* I2C_TXFIFO_EMPTY_THRHD : R/W ;bitpos:[9:5] ;default: 5'h4 ; */
+/*description: Config txfifo empty threhd value when using apb fifo access*/
+#define I2C_TXFIFO_EMPTY_THRHD 0x0000001F
+#define I2C_TXFIFO_EMPTY_THRHD_M ((I2C_TXFIFO_EMPTY_THRHD_V)<<(I2C_TXFIFO_EMPTY_THRHD_S))
+#define I2C_TXFIFO_EMPTY_THRHD_V 0x1F
+#define I2C_TXFIFO_EMPTY_THRHD_S 5
+/* I2C_RXFIFO_FULL_THRHD : R/W ;bitpos:[4:0] ;default: 5'hb ; */
+/*description: */
+#define I2C_RXFIFO_FULL_THRHD 0x0000001F
+#define I2C_RXFIFO_FULL_THRHD_M ((I2C_RXFIFO_FULL_THRHD_V)<<(I2C_RXFIFO_FULL_THRHD_S))
+#define I2C_RXFIFO_FULL_THRHD_V 0x1F
+#define I2C_RXFIFO_FULL_THRHD_S 0
+
+#define I2C_DATA_APB_REG(i) (0x60013000 + (i) * 0x14000 + 0x001c)
+
+#define I2C_DATA_REG(i) (REG_I2C_BASE(i) + 0x001c)
+/* I2C_FIFO_RDATA : RO ;bitpos:[7:0] ;default: 8'b0 ; */
+/*description: The register represent the byte data read from rxfifo when use apb fifo access*/
+#define I2C_FIFO_RDATA 0x000000FF
+#define I2C_FIFO_RDATA_M ((I2C_FIFO_RDATA_V)<<(I2C_FIFO_RDATA_S))
+#define I2C_FIFO_RDATA_V 0xFF
+#define I2C_FIFO_RDATA_S 0
+
+#define I2C_INT_RAW_REG(i) (REG_I2C_BASE(i) + 0x0020)
+/* I2C_TX_SEND_EMPTY_INT_RAW : RO ;bitpos:[12] ;default: 1'b0 ; */
+/*description: The raw interrupt status bit for tx_send_empty_int interrupt.when
+ I2C sends more data than nonfifo_tx_thres it will produce tx_send_empty_int interrupt..*/
+#define I2C_TX_SEND_EMPTY_INT_RAW (BIT(12))
+#define I2C_TX_SEND_EMPTY_INT_RAW_M (BIT(12))
+#define I2C_TX_SEND_EMPTY_INT_RAW_V 0x1
+#define I2C_TX_SEND_EMPTY_INT_RAW_S 12
+/* I2C_RX_REC_FULL_INT_RAW : RO ;bitpos:[11] ;default: 1'b0 ; */
+/*description: The raw interrupt status bit for rx_rec_full_int interrupt. when
+ I2C receives more data than nonfifo_rx_thres it will produce rx_rec_full_int interrupt.*/
+#define I2C_RX_REC_FULL_INT_RAW (BIT(11))
+#define I2C_RX_REC_FULL_INT_RAW_M (BIT(11))
+#define I2C_RX_REC_FULL_INT_RAW_V 0x1
+#define I2C_RX_REC_FULL_INT_RAW_S 11
+/* I2C_ACK_ERR_INT_RAW : RO ;bitpos:[10] ;default: 1'b0 ; */
+/*description: The raw interrupt status bit for ack_err_int interrupt. when
+ I2C receives a wrong ACK bit it will produce ack_err_int interrupt..*/
+#define I2C_ACK_ERR_INT_RAW (BIT(10))
+#define I2C_ACK_ERR_INT_RAW_M (BIT(10))
+#define I2C_ACK_ERR_INT_RAW_V 0x1
+#define I2C_ACK_ERR_INT_RAW_S 10
+/* I2C_TRANS_START_INT_RAW : RO ;bitpos:[9] ;default: 1'b0 ; */
+/*description: The raw interrupt status bit for trans_start_int interrupt. when
+ I2C sends the START bit it will produce trans_start_int interrupt.*/
+#define I2C_TRANS_START_INT_RAW (BIT(9))
+#define I2C_TRANS_START_INT_RAW_M (BIT(9))
+#define I2C_TRANS_START_INT_RAW_V 0x1
+#define I2C_TRANS_START_INT_RAW_S 9
+/* I2C_TIME_OUT_INT_RAW : RO ;bitpos:[8] ;default: 1'b0 ; */
+/*description: The raw interrupt status bit for time_out_int interrupt. when
+ I2C takes a lot of time to receive a data it will produce time_out_int interrupt.*/
+#define I2C_TIME_OUT_INT_RAW (BIT(8))
+#define I2C_TIME_OUT_INT_RAW_M (BIT(8))
+#define I2C_TIME_OUT_INT_RAW_V 0x1
+#define I2C_TIME_OUT_INT_RAW_S 8
+/* I2C_TRANS_COMPLETE_INT_RAW : RO ;bitpos:[7] ;default: 1'b0 ; */
+/*description: The raw interrupt status bit for trans_complete_int interrupt.
+ when I2C Master finished STOP command it will produce trans_complete_int interrupt.*/
+#define I2C_TRANS_COMPLETE_INT_RAW (BIT(7))
+#define I2C_TRANS_COMPLETE_INT_RAW_M (BIT(7))
+#define I2C_TRANS_COMPLETE_INT_RAW_V 0x1
+#define I2C_TRANS_COMPLETE_INT_RAW_S 7
+/* I2C_MASTER_TRAN_COMP_INT_RAW : RO ;bitpos:[6] ;default: 1'b0 ; */
+/*description: The raw interrupt status bit for master_tra_comp_int interrupt.
+ when I2C Master sends or receives a byte it will produce master_tran_comp_int interrupt.*/
+#define I2C_MASTER_TRAN_COMP_INT_RAW (BIT(6))
+#define I2C_MASTER_TRAN_COMP_INT_RAW_M (BIT(6))
+#define I2C_MASTER_TRAN_COMP_INT_RAW_V 0x1
+#define I2C_MASTER_TRAN_COMP_INT_RAW_S 6
+/* I2C_ARBITRATION_LOST_INT_RAW : RO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: The raw interrupt status bit for arbitration_lost_int interrupt.when
+ I2C lost the usage right of I2C BUS it will produce arbitration_lost_int interrupt.*/
+#define I2C_ARBITRATION_LOST_INT_RAW (BIT(5))
+#define I2C_ARBITRATION_LOST_INT_RAW_M (BIT(5))
+#define I2C_ARBITRATION_LOST_INT_RAW_V 0x1
+#define I2C_ARBITRATION_LOST_INT_RAW_S 5
+/* I2C_SLAVE_TRAN_COMP_INT_RAW : RO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: The raw interrupt status bit for slave_tran_comp_int interrupt.
+ when I2C Slave detectsthe STOP bit it will produce slave_tran_comp_int interrupt.*/
+#define I2C_SLAVE_TRAN_COMP_INT_RAW (BIT(4))
+#define I2C_SLAVE_TRAN_COMP_INT_RAW_M (BIT(4))
+#define I2C_SLAVE_TRAN_COMP_INT_RAW_V 0x1
+#define I2C_SLAVE_TRAN_COMP_INT_RAW_S 4
+/* I2C_END_DETECT_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: The raw interrupt status bit for end_detect_int interrupt. when
+ I2C deals with the END command it will produce end_detect_int interrupt.*/
+#define I2C_END_DETECT_INT_RAW (BIT(3))
+#define I2C_END_DETECT_INT_RAW_M (BIT(3))
+#define I2C_END_DETECT_INT_RAW_V 0x1
+#define I2C_END_DETECT_INT_RAW_S 3
+/* I2C_RXFIFO_OVF_INT_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */
+/*description: The raw interrupt status bit for receiving data overflow when
+ use apb fifo access.*/
+#define I2C_RXFIFO_OVF_INT_RAW (BIT(2))
+#define I2C_RXFIFO_OVF_INT_RAW_M (BIT(2))
+#define I2C_RXFIFO_OVF_INT_RAW_V 0x1
+#define I2C_RXFIFO_OVF_INT_RAW_S 2
+/* I2C_TXFIFO_EMPTY_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: The raw interrupt status bit for txfifo empty when use apb fifo access.*/
+#define I2C_TXFIFO_EMPTY_INT_RAW (BIT(1))
+#define I2C_TXFIFO_EMPTY_INT_RAW_M (BIT(1))
+#define I2C_TXFIFO_EMPTY_INT_RAW_V 0x1
+#define I2C_TXFIFO_EMPTY_INT_RAW_S 1
+/* I2C_RXFIFO_FULL_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: The raw interrupt status bit for rxfifo full when use apb fifo access.*/
+#define I2C_RXFIFO_FULL_INT_RAW (BIT(0))
+#define I2C_RXFIFO_FULL_INT_RAW_M (BIT(0))
+#define I2C_RXFIFO_FULL_INT_RAW_V 0x1
+#define I2C_RXFIFO_FULL_INT_RAW_S 0
+
+#define I2C_INT_CLR_REG(i) (REG_I2C_BASE(i) + 0x0024)
+/* I2C_TX_SEND_EMPTY_INT_CLR : WO ;bitpos:[12] ;default: 1'b0 ; */
+/*description: Set this bit to clear the tx_send_empty_int interrupt.*/
+#define I2C_TX_SEND_EMPTY_INT_CLR (BIT(12))
+#define I2C_TX_SEND_EMPTY_INT_CLR_M (BIT(12))
+#define I2C_TX_SEND_EMPTY_INT_CLR_V 0x1
+#define I2C_TX_SEND_EMPTY_INT_CLR_S 12
+/* I2C_RX_REC_FULL_INT_CLR : WO ;bitpos:[11] ;default: 1'b0 ; */
+/*description: Set this bit to clear the rx_rec_full_int interrupt.*/
+#define I2C_RX_REC_FULL_INT_CLR (BIT(11))
+#define I2C_RX_REC_FULL_INT_CLR_M (BIT(11))
+#define I2C_RX_REC_FULL_INT_CLR_V 0x1
+#define I2C_RX_REC_FULL_INT_CLR_S 11
+/* I2C_ACK_ERR_INT_CLR : WO ;bitpos:[10] ;default: 1'b0 ; */
+/*description: Set this bit to clear the ack_err_int interrupt.*/
+#define I2C_ACK_ERR_INT_CLR (BIT(10))
+#define I2C_ACK_ERR_INT_CLR_M (BIT(10))
+#define I2C_ACK_ERR_INT_CLR_V 0x1
+#define I2C_ACK_ERR_INT_CLR_S 10
+/* I2C_TRANS_START_INT_CLR : WO ;bitpos:[9] ;default: 1'b0 ; */
+/*description: Set this bit to clear the trans_start_int interrupt.*/
+#define I2C_TRANS_START_INT_CLR (BIT(9))
+#define I2C_TRANS_START_INT_CLR_M (BIT(9))
+#define I2C_TRANS_START_INT_CLR_V 0x1
+#define I2C_TRANS_START_INT_CLR_S 9
+/* I2C_TIME_OUT_INT_CLR : WO ;bitpos:[8] ;default: 1'b0 ; */
+/*description: Set this bit to clear the time_out_int interrupt.*/
+#define I2C_TIME_OUT_INT_CLR (BIT(8))
+#define I2C_TIME_OUT_INT_CLR_M (BIT(8))
+#define I2C_TIME_OUT_INT_CLR_V 0x1
+#define I2C_TIME_OUT_INT_CLR_S 8
+/* I2C_TRANS_COMPLETE_INT_CLR : WO ;bitpos:[7] ;default: 1'b0 ; */
+/*description: Set this bit to clear the trans_complete_int interrupt.*/
+#define I2C_TRANS_COMPLETE_INT_CLR (BIT(7))
+#define I2C_TRANS_COMPLETE_INT_CLR_M (BIT(7))
+#define I2C_TRANS_COMPLETE_INT_CLR_V 0x1
+#define I2C_TRANS_COMPLETE_INT_CLR_S 7
+/* I2C_MASTER_TRAN_COMP_INT_CLR : WO ;bitpos:[6] ;default: 1'b0 ; */
+/*description: Set this bit to clear the master_tran_comp interrupt.*/
+#define I2C_MASTER_TRAN_COMP_INT_CLR (BIT(6))
+#define I2C_MASTER_TRAN_COMP_INT_CLR_M (BIT(6))
+#define I2C_MASTER_TRAN_COMP_INT_CLR_V 0x1
+#define I2C_MASTER_TRAN_COMP_INT_CLR_S 6
+/* I2C_ARBITRATION_LOST_INT_CLR : WO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: Set this bit to clear the arbitration_lost_int interrupt.*/
+#define I2C_ARBITRATION_LOST_INT_CLR (BIT(5))
+#define I2C_ARBITRATION_LOST_INT_CLR_M (BIT(5))
+#define I2C_ARBITRATION_LOST_INT_CLR_V 0x1
+#define I2C_ARBITRATION_LOST_INT_CLR_S 5
+/* I2C_SLAVE_TRAN_COMP_INT_CLR : WO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: Set this bit to clear the slave_tran_comp_int interrupt.*/
+#define I2C_SLAVE_TRAN_COMP_INT_CLR (BIT(4))
+#define I2C_SLAVE_TRAN_COMP_INT_CLR_M (BIT(4))
+#define I2C_SLAVE_TRAN_COMP_INT_CLR_V 0x1
+#define I2C_SLAVE_TRAN_COMP_INT_CLR_S 4
+/* I2C_END_DETECT_INT_CLR : WO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: Set this bit to clear the end_detect_int interrupt.*/
+#define I2C_END_DETECT_INT_CLR (BIT(3))
+#define I2C_END_DETECT_INT_CLR_M (BIT(3))
+#define I2C_END_DETECT_INT_CLR_V 0x1
+#define I2C_END_DETECT_INT_CLR_S 3
+/* I2C_RXFIFO_OVF_INT_CLR : WO ;bitpos:[2] ;default: 1'b0 ; */
+/*description: Set this bit to clear the rxfifo_ovf_int interrupt.*/
+#define I2C_RXFIFO_OVF_INT_CLR (BIT(2))
+#define I2C_RXFIFO_OVF_INT_CLR_M (BIT(2))
+#define I2C_RXFIFO_OVF_INT_CLR_V 0x1
+#define I2C_RXFIFO_OVF_INT_CLR_S 2
+/* I2C_TXFIFO_EMPTY_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: Set this bit to clear the txfifo_empty_int interrupt.*/
+#define I2C_TXFIFO_EMPTY_INT_CLR (BIT(1))
+#define I2C_TXFIFO_EMPTY_INT_CLR_M (BIT(1))
+#define I2C_TXFIFO_EMPTY_INT_CLR_V 0x1
+#define I2C_TXFIFO_EMPTY_INT_CLR_S 1
+/* I2C_RXFIFO_FULL_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: Set this bit to clear the rxfifo_full_int interrupt.*/
+#define I2C_RXFIFO_FULL_INT_CLR (BIT(0))
+#define I2C_RXFIFO_FULL_INT_CLR_M (BIT(0))
+#define I2C_RXFIFO_FULL_INT_CLR_V 0x1
+#define I2C_RXFIFO_FULL_INT_CLR_S 0
+
+#define I2C_INT_ENA_REG(i) (REG_I2C_BASE(i) + 0x0028)
+/* I2C_TX_SEND_EMPTY_INT_ENA : R/W ;bitpos:[12] ;default: 1'b0 ; */
+/*description: The enable bit for tx_send_empty_int interrupt.*/
+#define I2C_TX_SEND_EMPTY_INT_ENA (BIT(12))
+#define I2C_TX_SEND_EMPTY_INT_ENA_M (BIT(12))
+#define I2C_TX_SEND_EMPTY_INT_ENA_V 0x1
+#define I2C_TX_SEND_EMPTY_INT_ENA_S 12
+/* I2C_RX_REC_FULL_INT_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */
+/*description: The enable bit for rx_rec_full_int interrupt.*/
+#define I2C_RX_REC_FULL_INT_ENA (BIT(11))
+#define I2C_RX_REC_FULL_INT_ENA_M (BIT(11))
+#define I2C_RX_REC_FULL_INT_ENA_V 0x1
+#define I2C_RX_REC_FULL_INT_ENA_S 11
+/* I2C_ACK_ERR_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */
+/*description: The enable bit for ack_err_int interrupt.*/
+#define I2C_ACK_ERR_INT_ENA (BIT(10))
+#define I2C_ACK_ERR_INT_ENA_M (BIT(10))
+#define I2C_ACK_ERR_INT_ENA_V 0x1
+#define I2C_ACK_ERR_INT_ENA_S 10
+/* I2C_TRANS_START_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */
+/*description: The enable bit for trans_start_int interrupt.*/
+#define I2C_TRANS_START_INT_ENA (BIT(9))
+#define I2C_TRANS_START_INT_ENA_M (BIT(9))
+#define I2C_TRANS_START_INT_ENA_V 0x1
+#define I2C_TRANS_START_INT_ENA_S 9
+/* I2C_TIME_OUT_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */
+/*description: The enable bit for time_out_int interrupt.*/
+#define I2C_TIME_OUT_INT_ENA (BIT(8))
+#define I2C_TIME_OUT_INT_ENA_M (BIT(8))
+#define I2C_TIME_OUT_INT_ENA_V 0x1
+#define I2C_TIME_OUT_INT_ENA_S 8
+/* I2C_TRANS_COMPLETE_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: The enable bit for trans_complete_int interrupt.*/
+#define I2C_TRANS_COMPLETE_INT_ENA (BIT(7))
+#define I2C_TRANS_COMPLETE_INT_ENA_M (BIT(7))
+#define I2C_TRANS_COMPLETE_INT_ENA_V 0x1
+#define I2C_TRANS_COMPLETE_INT_ENA_S 7
+/* I2C_MASTER_TRAN_COMP_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: The enable bit for master_tran_comp_int interrupt.*/
+#define I2C_MASTER_TRAN_COMP_INT_ENA (BIT(6))
+#define I2C_MASTER_TRAN_COMP_INT_ENA_M (BIT(6))
+#define I2C_MASTER_TRAN_COMP_INT_ENA_V 0x1
+#define I2C_MASTER_TRAN_COMP_INT_ENA_S 6
+/* I2C_ARBITRATION_LOST_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: The enable bit for arbitration_lost_int interrupt.*/
+#define I2C_ARBITRATION_LOST_INT_ENA (BIT(5))
+#define I2C_ARBITRATION_LOST_INT_ENA_M (BIT(5))
+#define I2C_ARBITRATION_LOST_INT_ENA_V 0x1
+#define I2C_ARBITRATION_LOST_INT_ENA_S 5
+/* I2C_SLAVE_TRAN_COMP_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: The enable bit for slave_tran_comp_int interrupt.*/
+#define I2C_SLAVE_TRAN_COMP_INT_ENA (BIT(4))
+#define I2C_SLAVE_TRAN_COMP_INT_ENA_M (BIT(4))
+#define I2C_SLAVE_TRAN_COMP_INT_ENA_V 0x1
+#define I2C_SLAVE_TRAN_COMP_INT_ENA_S 4
+/* I2C_END_DETECT_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: The enable bit for end_detect_int interrupt.*/
+#define I2C_END_DETECT_INT_ENA (BIT(3))
+#define I2C_END_DETECT_INT_ENA_M (BIT(3))
+#define I2C_END_DETECT_INT_ENA_V 0x1
+#define I2C_END_DETECT_INT_ENA_S 3
+/* I2C_RXFIFO_OVF_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: The enable bit for rxfifo_ovf_int interrupt.*/
+#define I2C_RXFIFO_OVF_INT_ENA (BIT(2))
+#define I2C_RXFIFO_OVF_INT_ENA_M (BIT(2))
+#define I2C_RXFIFO_OVF_INT_ENA_V 0x1
+#define I2C_RXFIFO_OVF_INT_ENA_S 2
+/* I2C_TXFIFO_EMPTY_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: The enable bit for txfifo_empty_int interrupt.*/
+#define I2C_TXFIFO_EMPTY_INT_ENA (BIT(1))
+#define I2C_TXFIFO_EMPTY_INT_ENA_M (BIT(1))
+#define I2C_TXFIFO_EMPTY_INT_ENA_V 0x1
+#define I2C_TXFIFO_EMPTY_INT_ENA_S 1
+/* I2C_RXFIFO_FULL_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: The enable bit for rxfifo_full_int interrupt.*/
+#define I2C_RXFIFO_FULL_INT_ENA (BIT(0))
+#define I2C_RXFIFO_FULL_INT_ENA_M (BIT(0))
+#define I2C_RXFIFO_FULL_INT_ENA_V 0x1
+#define I2C_RXFIFO_FULL_INT_ENA_S 0
+
+#define I2C_INT_STATUS_REG(i) (REG_I2C_BASE(i) + 0x002c)
+/* I2C_TX_SEND_EMPTY_INT_ST : RO ;bitpos:[12] ;default: 1'b0 ; */
+/*description: The masked interrupt status for tx_send_empty_int interrupt.*/
+#define I2C_TX_SEND_EMPTY_INT_ST (BIT(12))
+#define I2C_TX_SEND_EMPTY_INT_ST_M (BIT(12))
+#define I2C_TX_SEND_EMPTY_INT_ST_V 0x1
+#define I2C_TX_SEND_EMPTY_INT_ST_S 12
+/* I2C_RX_REC_FULL_INT_ST : RO ;bitpos:[11] ;default: 1'b0 ; */
+/*description: The masked interrupt status for rx_rec_full_int interrupt.*/
+#define I2C_RX_REC_FULL_INT_ST (BIT(11))
+#define I2C_RX_REC_FULL_INT_ST_M (BIT(11))
+#define I2C_RX_REC_FULL_INT_ST_V 0x1
+#define I2C_RX_REC_FULL_INT_ST_S 11
+/* I2C_ACK_ERR_INT_ST : RO ;bitpos:[10] ;default: 1'b0 ; */
+/*description: The masked interrupt status for ack_err_int interrupt.*/
+#define I2C_ACK_ERR_INT_ST (BIT(10))
+#define I2C_ACK_ERR_INT_ST_M (BIT(10))
+#define I2C_ACK_ERR_INT_ST_V 0x1
+#define I2C_ACK_ERR_INT_ST_S 10
+/* I2C_TRANS_START_INT_ST : RO ;bitpos:[9] ;default: 1'b0 ; */
+/*description: The masked interrupt status for trans_start_int interrupt.*/
+#define I2C_TRANS_START_INT_ST (BIT(9))
+#define I2C_TRANS_START_INT_ST_M (BIT(9))
+#define I2C_TRANS_START_INT_ST_V 0x1
+#define I2C_TRANS_START_INT_ST_S 9
+/* I2C_TIME_OUT_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */
+/*description: The masked interrupt status for time_out_int interrupt.*/
+#define I2C_TIME_OUT_INT_ST (BIT(8))
+#define I2C_TIME_OUT_INT_ST_M (BIT(8))
+#define I2C_TIME_OUT_INT_ST_V 0x1
+#define I2C_TIME_OUT_INT_ST_S 8
+/* I2C_TRANS_COMPLETE_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */
+/*description: The masked interrupt status for trans_complete_int interrupt.*/
+#define I2C_TRANS_COMPLETE_INT_ST (BIT(7))
+#define I2C_TRANS_COMPLETE_INT_ST_M (BIT(7))
+#define I2C_TRANS_COMPLETE_INT_ST_V 0x1
+#define I2C_TRANS_COMPLETE_INT_ST_S 7
+/* I2C_MASTER_TRAN_COMP_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */
+/*description: The masked interrupt status for master_tran_comp_int interrupt.*/
+#define I2C_MASTER_TRAN_COMP_INT_ST (BIT(6))
+#define I2C_MASTER_TRAN_COMP_INT_ST_M (BIT(6))
+#define I2C_MASTER_TRAN_COMP_INT_ST_V 0x1
+#define I2C_MASTER_TRAN_COMP_INT_ST_S 6
+/* I2C_ARBITRATION_LOST_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: The masked interrupt status for arbitration_lost_int interrupt.*/
+#define I2C_ARBITRATION_LOST_INT_ST (BIT(5))
+#define I2C_ARBITRATION_LOST_INT_ST_M (BIT(5))
+#define I2C_ARBITRATION_LOST_INT_ST_V 0x1
+#define I2C_ARBITRATION_LOST_INT_ST_S 5
+/* I2C_SLAVE_TRAN_COMP_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: The masked interrupt status for slave_tran_comp_int interrupt.*/
+#define I2C_SLAVE_TRAN_COMP_INT_ST (BIT(4))
+#define I2C_SLAVE_TRAN_COMP_INT_ST_M (BIT(4))
+#define I2C_SLAVE_TRAN_COMP_INT_ST_V 0x1
+#define I2C_SLAVE_TRAN_COMP_INT_ST_S 4
+/* I2C_END_DETECT_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: The masked interrupt status for end_detect_int interrupt.*/
+#define I2C_END_DETECT_INT_ST (BIT(3))
+#define I2C_END_DETECT_INT_ST_M (BIT(3))
+#define I2C_END_DETECT_INT_ST_V 0x1
+#define I2C_END_DETECT_INT_ST_S 3
+/* I2C_RXFIFO_OVF_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */
+/*description: The masked interrupt status for rxfifo_ovf_int interrupt.*/
+#define I2C_RXFIFO_OVF_INT_ST (BIT(2))
+#define I2C_RXFIFO_OVF_INT_ST_M (BIT(2))
+#define I2C_RXFIFO_OVF_INT_ST_V 0x1
+#define I2C_RXFIFO_OVF_INT_ST_S 2
+/* I2C_TXFIFO_EMPTY_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: The masked interrupt status for txfifo_empty_int interrupt.*/
+#define I2C_TXFIFO_EMPTY_INT_ST (BIT(1))
+#define I2C_TXFIFO_EMPTY_INT_ST_M (BIT(1))
+#define I2C_TXFIFO_EMPTY_INT_ST_V 0x1
+#define I2C_TXFIFO_EMPTY_INT_ST_S 1
+/* I2C_RXFIFO_FULL_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: The masked interrupt status for rxfifo_full_int interrupt.*/
+#define I2C_RXFIFO_FULL_INT_ST (BIT(0))
+#define I2C_RXFIFO_FULL_INT_ST_M (BIT(0))
+#define I2C_RXFIFO_FULL_INT_ST_V 0x1
+#define I2C_RXFIFO_FULL_INT_ST_S 0
+
+#define I2C_SDA_HOLD_REG(i) (REG_I2C_BASE(i) + 0x0030)
+/* I2C_SDA_HOLD_TIME : R/W ;bitpos:[9:0] ;default: 10'b0 ; */
+/*description: This register is used to configure the clock num I2C used to
+ hold the data after the negedge of SCL.*/
+#define I2C_SDA_HOLD_TIME 0x000003FF
+#define I2C_SDA_HOLD_TIME_M ((I2C_SDA_HOLD_TIME_V)<<(I2C_SDA_HOLD_TIME_S))
+#define I2C_SDA_HOLD_TIME_V 0x3FF
+#define I2C_SDA_HOLD_TIME_S 0
+
+#define I2C_SDA_SAMPLE_REG(i) (REG_I2C_BASE(i) + 0x0034)
+/* I2C_SDA_SAMPLE_TIME : R/W ;bitpos:[9:0] ;default: 10'b0 ; */
+/*description: This register is used to configure the clock num I2C used to
+ sample data on SDA after the posedge of SCL*/
+#define I2C_SDA_SAMPLE_TIME 0x000003FF
+#define I2C_SDA_SAMPLE_TIME_M ((I2C_SDA_SAMPLE_TIME_V)<<(I2C_SDA_SAMPLE_TIME_S))
+#define I2C_SDA_SAMPLE_TIME_V 0x3FF
+#define I2C_SDA_SAMPLE_TIME_S 0
+
+#define I2C_SCL_HIGH_PERIOD_REG(i) (REG_I2C_BASE(i) + 0x0038)
+/* I2C_SCL_HIGH_PERIOD : R/W ;bitpos:[13:0] ;default: 14'b0 ; */
+/*description: This register is used to configure the clock num during SCL is low level.*/
+#define I2C_SCL_HIGH_PERIOD 0x00003FFF
+#define I2C_SCL_HIGH_PERIOD_M ((I2C_SCL_HIGH_PERIOD_V)<<(I2C_SCL_HIGH_PERIOD_S))
+#define I2C_SCL_HIGH_PERIOD_V 0x3FFF
+#define I2C_SCL_HIGH_PERIOD_S 0
+
+#define I2C_SCL_START_HOLD_REG(i) (REG_I2C_BASE(i) + 0x0040)
+/* I2C_SCL_START_HOLD_TIME : R/W ;bitpos:[9:0] ;default: 10'b1000 ; */
+/*description: This register is used to configure the clock num between the
+ negedge of SDA and negedge of SCL for start mark.*/
+#define I2C_SCL_START_HOLD_TIME 0x000003FF
+#define I2C_SCL_START_HOLD_TIME_M ((I2C_SCL_START_HOLD_TIME_V)<<(I2C_SCL_START_HOLD_TIME_S))
+#define I2C_SCL_START_HOLD_TIME_V 0x3FF
+#define I2C_SCL_START_HOLD_TIME_S 0
+
+#define I2C_SCL_RSTART_SETUP_REG(i) (REG_I2C_BASE(i) + 0x0044)
+/* I2C_SCL_RSTART_SETUP_TIME : R/W ;bitpos:[9:0] ;default: 10'b1000 ; */
+/*description: This register is used to configure the clock num between the
+ posedge of SCL and the negedge of SDA for restart mark.*/
+#define I2C_SCL_RSTART_SETUP_TIME 0x000003FF
+#define I2C_SCL_RSTART_SETUP_TIME_M ((I2C_SCL_RSTART_SETUP_TIME_V)<<(I2C_SCL_RSTART_SETUP_TIME_S))
+#define I2C_SCL_RSTART_SETUP_TIME_V 0x3FF
+#define I2C_SCL_RSTART_SETUP_TIME_S 0
+
+#define I2C_SCL_STOP_HOLD_REG(i) (REG_I2C_BASE(i) + 0x0048)
+/* I2C_SCL_STOP_HOLD_TIME : R/W ;bitpos:[13:0] ;default: 14'b0 ; */
+/*description: This register is used to configure the clock num after the STOP bit's posedge.*/
+#define I2C_SCL_STOP_HOLD_TIME 0x00003FFF
+#define I2C_SCL_STOP_HOLD_TIME_M ((I2C_SCL_STOP_HOLD_TIME_V)<<(I2C_SCL_STOP_HOLD_TIME_S))
+#define I2C_SCL_STOP_HOLD_TIME_V 0x3FFF
+#define I2C_SCL_STOP_HOLD_TIME_S 0
+
+#define I2C_SCL_STOP_SETUP_REG(i) (REG_I2C_BASE(i) + 0x004C)
+/* I2C_SCL_STOP_SETUP_TIME : R/W ;bitpos:[9:0] ;default: 10'b0 ; */
+/*description: This register is used to configure the clock num between the
+ posedge of SCL and the posedge of SDA.*/
+#define I2C_SCL_STOP_SETUP_TIME 0x000003FF
+#define I2C_SCL_STOP_SETUP_TIME_M ((I2C_SCL_STOP_SETUP_TIME_V)<<(I2C_SCL_STOP_SETUP_TIME_S))
+#define I2C_SCL_STOP_SETUP_TIME_V 0x3FF
+#define I2C_SCL_STOP_SETUP_TIME_S 0
+
+#define I2C_SCL_FILTER_CFG_REG(i) (REG_I2C_BASE(i) + 0x0050)
+/* I2C_SCL_FILTER_EN : R/W ;bitpos:[3] ;default: 1'b1 ; */
+/*description: This is the filter enable bit for SCL.*/
+#define I2C_SCL_FILTER_EN (BIT(3))
+#define I2C_SCL_FILTER_EN_M (BIT(3))
+#define I2C_SCL_FILTER_EN_V 0x1
+#define I2C_SCL_FILTER_EN_S 3
+/* I2C_SCL_FILTER_THRES : R/W ;bitpos:[2:0] ;default: 3'b0 ; */
+/*description: When input SCL's pulse width is smaller than this register value
+ I2C ignores this pulse.*/
+#define I2C_SCL_FILTER_THRES 0x00000007
+#define I2C_SCL_FILTER_THRES_M ((I2C_SCL_FILTER_THRES_V)<<(I2C_SCL_FILTER_THRES_S))
+#define I2C_SCL_FILTER_THRES_V 0x7
+#define I2C_SCL_FILTER_THRES_S 0
+
+#define I2C_SDA_FILTER_CFG_REG(i) (REG_I2C_BASE(i) + 0x0054)
+/* I2C_SDA_FILTER_EN : R/W ;bitpos:[3] ;default: 1'b1 ; */
+/*description: This is the filter enable bit for SDA.*/
+#define I2C_SDA_FILTER_EN (BIT(3))
+#define I2C_SDA_FILTER_EN_M (BIT(3))
+#define I2C_SDA_FILTER_EN_V 0x1
+#define I2C_SDA_FILTER_EN_S 3
+/* I2C_SDA_FILTER_THRES : R/W ;bitpos:[2:0] ;default: 3'b0 ; */
+/*description: When input SCL's pulse width is smaller than this register value
+ I2C ignores this pulse.*/
+#define I2C_SDA_FILTER_THRES 0x00000007
+#define I2C_SDA_FILTER_THRES_M ((I2C_SDA_FILTER_THRES_V)<<(I2C_SDA_FILTER_THRES_S))
+#define I2C_SDA_FILTER_THRES_V 0x7
+#define I2C_SDA_FILTER_THRES_S 0
+
+#define I2C_COMD0_REG(i) (REG_I2C_BASE(i) + 0x0058)
+/* I2C_COMMAND0_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */
+/*description: When command0 is done in I2C Master mode this bit changes to high level.*/
+#define I2C_COMMAND0_DONE (BIT(31))
+#define I2C_COMMAND0_DONE_M (BIT(31))
+#define I2C_COMMAND0_DONE_V 0x1
+#define I2C_COMMAND0_DONE_S 31
+/* I2C_COMMAND0 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */
+/*description: This is the content of command0. It consists of three part. op_code
+ is the command 0: RSTART 1: WRITE 2: READ 3: STOP . 4:END. Byte_num represent the number of data need to be send or data need to be received. ack_check_en ack_exp and ack value are used to control the ack bit.*/
+#define I2C_COMMAND0 0x00003FFF
+#define I2C_COMMAND0_M ((I2C_COMMAND0_V)<<(I2C_COMMAND0_S))
+#define I2C_COMMAND0_V 0x3FFF
+#define I2C_COMMAND0_S 0
+
+#define I2C_COMD1_REG(i) (REG_I2C_BASE(i) + 0x005C)
+/* I2C_COMMAND1_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */
+/*description: When command1 is done in I2C Master mode this bit changes to high level.*/
+#define I2C_COMMAND1_DONE (BIT(31))
+#define I2C_COMMAND1_DONE_M (BIT(31))
+#define I2C_COMMAND1_DONE_V 0x1
+#define I2C_COMMAND1_DONE_S 31
+/* I2C_COMMAND1 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */
+/*description: This is the content of command1. It consists of three part. op_code
+ is the command 0: RSTART 1: WRITE 2: READ 3: STOP . 4:END. Byte_num represent the number of data need to be send or data need to be received. ack_check_en ack_exp and ack value are used to control the ack bit.*/
+#define I2C_COMMAND1 0x00003FFF
+#define I2C_COMMAND1_M ((I2C_COMMAND1_V)<<(I2C_COMMAND1_S))
+#define I2C_COMMAND1_V 0x3FFF
+#define I2C_COMMAND1_S 0
+
+#define I2C_COMD2_REG(i) (REG_I2C_BASE(i) + 0x0060)
+/* I2C_COMMAND2_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */
+/*description: When command2 is done in I2C Master mode this bit changes to high level.*/
+#define I2C_COMMAND2_DONE (BIT(31))
+#define I2C_COMMAND2_DONE_M (BIT(31))
+#define I2C_COMMAND2_DONE_V 0x1
+#define I2C_COMMAND2_DONE_S 31
+/* I2C_COMMAND2 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */
+/*description: This is the content of command2. It consists of three part. op_code
+ is the command 0: RSTART 1: WRITE 2: READ 3: STOP . 4:END. Byte_num represent the number of data need to be send or data need to be received. ack_check_en ack_exp and ack value are used to control the ack bit.*/
+#define I2C_COMMAND2 0x00003FFF
+#define I2C_COMMAND2_M ((I2C_COMMAND2_V)<<(I2C_COMMAND2_S))
+#define I2C_COMMAND2_V 0x3FFF
+#define I2C_COMMAND2_S 0
+
+#define I2C_COMD3_REG(i) (REG_I2C_BASE(i) + 0x0064)
+/* I2C_COMMAND3_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */
+/*description: When command3 is done in I2C Master mode this bit changes to high level.*/
+#define I2C_COMMAND3_DONE (BIT(31))
+#define I2C_COMMAND3_DONE_M (BIT(31))
+#define I2C_COMMAND3_DONE_V 0x1
+#define I2C_COMMAND3_DONE_S 31
+/* I2C_COMMAND3 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */
+/*description: This is the content of command3. It consists of three part. op_code
+ is the command 0: RSTART 1: WRITE 2: READ 3: STOP . 4:END. Byte_num represent the number of data need to be send or data need to be received. ack_check_en ack_exp and ack value are used to control the ack bit.*/
+#define I2C_COMMAND3 0x00003FFF
+#define I2C_COMMAND3_M ((I2C_COMMAND3_V)<<(I2C_COMMAND3_S))
+#define I2C_COMMAND3_V 0x3FFF
+#define I2C_COMMAND3_S 0
+
+#define I2C_COMD4_REG(i) (REG_I2C_BASE(i) + 0x0068)
+/* I2C_COMMAND4_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */
+/*description: When command4 is done in I2C Master mode this bit changes to high level.*/
+#define I2C_COMMAND4_DONE (BIT(31))
+#define I2C_COMMAND4_DONE_M (BIT(31))
+#define I2C_COMMAND4_DONE_V 0x1
+#define I2C_COMMAND4_DONE_S 31
+/* I2C_COMMAND4 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */
+/*description: This is the content of command4. It consists of three part. op_code
+ is the command 0: RSTART 1: WRITE 2: READ 3: STOP . 4:END. Byte_num represent the number of data need to be send or data need to be received. ack_check_en ack_exp and ack value are used to control the ack bit.*/
+#define I2C_COMMAND4 0x00003FFF
+#define I2C_COMMAND4_M ((I2C_COMMAND4_V)<<(I2C_COMMAND4_S))
+#define I2C_COMMAND4_V 0x3FFF
+#define I2C_COMMAND4_S 0
+
+#define I2C_COMD5_REG(i) (REG_I2C_BASE(i) + 0x006C)
+/* I2C_COMMAND5_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */
+/*description: When command5 is done in I2C Master mode this bit changes to high level.*/
+#define I2C_COMMAND5_DONE (BIT(31))
+#define I2C_COMMAND5_DONE_M (BIT(31))
+#define I2C_COMMAND5_DONE_V 0x1
+#define I2C_COMMAND5_DONE_S 31
+/* I2C_COMMAND5 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */
+/*description: This is the content of command5. It consists of three part. op_code
+ is the command 0: RSTART 1: WRITE 2: READ 3: STOP . 4:END. Byte_num represent the number of data need to be send or data need to be received. ack_check_en ack_exp and ack value are used to control the ack bit.*/
+#define I2C_COMMAND5 0x00003FFF
+#define I2C_COMMAND5_M ((I2C_COMMAND5_V)<<(I2C_COMMAND5_S))
+#define I2C_COMMAND5_V 0x3FFF
+#define I2C_COMMAND5_S 0
+
+#define I2C_COMD6_REG(i) (REG_I2C_BASE(i) + 0x0070)
+/* I2C_COMMAND6_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */
+/*description: When command6 is done in I2C Master mode this bit changes to high level.*/
+#define I2C_COMMAND6_DONE (BIT(31))
+#define I2C_COMMAND6_DONE_M (BIT(31))
+#define I2C_COMMAND6_DONE_V 0x1
+#define I2C_COMMAND6_DONE_S 31
+/* I2C_COMMAND6 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */
+/*description: This is the content of command6. It consists of three part. op_code
+ is the command 0: RSTART 1: WRITE 2: READ 3: STOP . 4:END. Byte_num represent the number of data need to be send or data need to be received. ack_check_en ack_exp and ack value are used to control the ack bit.*/
+#define I2C_COMMAND6 0x00003FFF
+#define I2C_COMMAND6_M ((I2C_COMMAND6_V)<<(I2C_COMMAND6_S))
+#define I2C_COMMAND6_V 0x3FFF
+#define I2C_COMMAND6_S 0
+
+#define I2C_COMD7_REG(i) (REG_I2C_BASE(i) + 0x0074)
+/* I2C_COMMAND7_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */
+/*description: When command7 is done in I2C Master mode this bit changes to high level.*/
+#define I2C_COMMAND7_DONE (BIT(31))
+#define I2C_COMMAND7_DONE_M (BIT(31))
+#define I2C_COMMAND7_DONE_V 0x1
+#define I2C_COMMAND7_DONE_S 31
+/* I2C_COMMAND7 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */
+/*description: This is the content of command7. It consists of three part. op_code
+ is the command 0: RSTART 1: WRITE 2: READ 3: STOP . 4:END. Byte_num represent the number of data need to be send or data need to be received. ack_check_en ack_exp and ack value are used to control the ack bit.*/
+#define I2C_COMMAND7 0x00003FFF
+#define I2C_COMMAND7_M ((I2C_COMMAND7_V)<<(I2C_COMMAND7_S))
+#define I2C_COMMAND7_V 0x3FFF
+#define I2C_COMMAND7_S 0
+
+#define I2C_COMD8_REG(i) (REG_I2C_BASE(i) + 0x0078)
+/* I2C_COMMAND8_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */
+/*description: When command8 is done in I2C Master mode this bit changes to high level.*/
+#define I2C_COMMAND8_DONE (BIT(31))
+#define I2C_COMMAND8_DONE_M (BIT(31))
+#define I2C_COMMAND8_DONE_V 0x1
+#define I2C_COMMAND8_DONE_S 31
+/* I2C_COMMAND8 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */
+/*description: This is the content of command8. It consists of three part. op_code
+ is the command 0: RSTART 1: WRITE 2: READ 3: STOP . 4:END. Byte_num represent the number of data need to be send or data need to be received. ack_check_en ack_exp and ack value are used to control the ack bit.*/
+#define I2C_COMMAND8 0x00003FFF
+#define I2C_COMMAND8_M ((I2C_COMMAND8_V)<<(I2C_COMMAND8_S))
+#define I2C_COMMAND8_V 0x3FFF
+#define I2C_COMMAND8_S 0
+
+#define I2C_COMD9_REG(i) (REG_I2C_BASE(i) + 0x007C)
+/* I2C_COMMAND9_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */
+/*description: When command9 is done in I2C Master mode this bit changes to high level.*/
+#define I2C_COMMAND9_DONE (BIT(31))
+#define I2C_COMMAND9_DONE_M (BIT(31))
+#define I2C_COMMAND9_DONE_V 0x1
+#define I2C_COMMAND9_DONE_S 31
+/* I2C_COMMAND9 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */
+/*description: This is the content of command9. It consists of three part. op_code
+ is the command 0: RSTART 1: WRITE 2: READ 3: STOP . 4:END. Byte_num represent the number of data need to be send or data need to be received. ack_check_en ack_exp and ack value are used to control the ack bit.*/
+#define I2C_COMMAND9 0x00003FFF
+#define I2C_COMMAND9_M ((I2C_COMMAND9_V)<<(I2C_COMMAND9_S))
+#define I2C_COMMAND9_V 0x3FFF
+#define I2C_COMMAND9_S 0
+
+#define I2C_COMD10_REG(i) (REG_I2C_BASE(i) + 0x0080)
+/* I2C_COMMAND10_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */
+/*description: When command10 is done in I2C Master mode this bit changes to high level.*/
+#define I2C_COMMAND10_DONE (BIT(31))
+#define I2C_COMMAND10_DONE_M (BIT(31))
+#define I2C_COMMAND10_DONE_V 0x1
+#define I2C_COMMAND10_DONE_S 31
+/* I2C_COMMAND10 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */
+/*description: This is the content of command10. It consists of three part.
+ op_code is the command 0: RSTART 1: WRITE 2: READ 3: STOP . 4:END. Byte_num represent the number of data need to be send or data need to be received. ack_check_en ack_exp and ack value are used to control the ack bit.*/
+#define I2C_COMMAND10 0x00003FFF
+#define I2C_COMMAND10_M ((I2C_COMMAND10_V)<<(I2C_COMMAND10_S))
+#define I2C_COMMAND10_V 0x3FFF
+#define I2C_COMMAND10_S 0
+
+#define I2C_COMD11_REG(i) (REG_I2C_BASE(i) + 0x0084)
+/* I2C_COMMAND11_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */
+/*description: When command11 is done in I2C Master mode this bit changes to high level.*/
+#define I2C_COMMAND11_DONE (BIT(31))
+#define I2C_COMMAND11_DONE_M (BIT(31))
+#define I2C_COMMAND11_DONE_V 0x1
+#define I2C_COMMAND11_DONE_S 31
+/* I2C_COMMAND11 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */
+/*description: This is the content of command11. It consists of three part.
+ op_code is the command 0: RSTART 1: WRITE 2: READ 3: STOP . 4:END. Byte_num represent the number of data need to be send or data need to be received. ack_check_en ack_exp and ack value are used to control the ack bit.*/
+#define I2C_COMMAND11 0x00003FFF
+#define I2C_COMMAND11_M ((I2C_COMMAND11_V)<<(I2C_COMMAND11_S))
+#define I2C_COMMAND11_V 0x3FFF
+#define I2C_COMMAND11_S 0
+
+#define I2C_COMD12_REG(i) (REG_I2C_BASE(i) + 0x0088)
+/* I2C_COMMAND12_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */
+/*description: When command12 is done in I2C Master mode this bit changes to high level.*/
+#define I2C_COMMAND12_DONE (BIT(31))
+#define I2C_COMMAND12_DONE_M (BIT(31))
+#define I2C_COMMAND12_DONE_V 0x1
+#define I2C_COMMAND12_DONE_S 31
+/* I2C_COMMAND12 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */
+/*description: This is the content of command12. It consists of three part.
+ op_code is the command 0: RSTART 1: WRITE 2: READ 3: STOP . 4:END. Byte_num represent the number of data need to be send or data need to be received. ack_check_en ack_exp and ack value are used to control the ack bit.*/
+#define I2C_COMMAND12 0x00003FFF
+#define I2C_COMMAND12_M ((I2C_COMMAND12_V)<<(I2C_COMMAND12_S))
+#define I2C_COMMAND12_V 0x3FFF
+#define I2C_COMMAND12_S 0
+
+#define I2C_COMD13_REG(i) (REG_I2C_BASE(i) + 0x008C)
+/* I2C_COMMAND13_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */
+/*description: When command13 is done in I2C Master mode this bit changes to high level.*/
+#define I2C_COMMAND13_DONE (BIT(31))
+#define I2C_COMMAND13_DONE_M (BIT(31))
+#define I2C_COMMAND13_DONE_V 0x1
+#define I2C_COMMAND13_DONE_S 31
+/* I2C_COMMAND13 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */
+/*description: This is the content of command13. It consists of three part.
+ op_code is the command 0: RSTART 1: WRITE 2: READ 3: STOP . 4:END. Byte_num represent the number of data need to be send or data need to be received. ack_check_en ack_exp and ack value are used to control the ack bit.*/
+#define I2C_COMMAND13 0x00003FFF
+#define I2C_COMMAND13_M ((I2C_COMMAND13_V)<<(I2C_COMMAND13_S))
+#define I2C_COMMAND13_V 0x3FFF
+#define I2C_COMMAND13_S 0
+
+#define I2C_COMD14_REG(i) (REG_I2C_BASE(i) + 0x0090)
+/* I2C_COMMAND14_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */
+/*description: When command14 is done in I2C Master mode this bit changes to high level.*/
+#define I2C_COMMAND14_DONE (BIT(31))
+#define I2C_COMMAND14_DONE_M (BIT(31))
+#define I2C_COMMAND14_DONE_V 0x1
+#define I2C_COMMAND14_DONE_S 31
+/* I2C_COMMAND14 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */
+/*description: This is the content of command14. It consists of three part.
+ op_code is the command 0: RSTART 1: WRITE 2: READ 3: STOP . 4:END. Byte_num represent the number of data need to be send or data need to be received. ack_check_en ack_exp and ack value are used to control the ack bit.*/
+#define I2C_COMMAND14 0x00003FFF
+#define I2C_COMMAND14_M ((I2C_COMMAND14_V)<<(I2C_COMMAND14_S))
+#define I2C_COMMAND14_V 0x3FFF
+#define I2C_COMMAND14_S 0
+
+#define I2C_COMD15_REG(i) (REG_I2C_BASE(i) + 0x0094)
+/* I2C_COMMAND15_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */
+/*description: When command15 is done in I2C Master mode this bit changes to high level.*/
+#define I2C_COMMAND15_DONE (BIT(31))
+#define I2C_COMMAND15_DONE_M (BIT(31))
+#define I2C_COMMAND15_DONE_V 0x1
+#define I2C_COMMAND15_DONE_S 31
+/* I2C_COMMAND15 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */
+/*description: This is the content of command15. It consists of three part.
+ op_code is the command 0: RSTART 1: WRITE 2: READ 3: STOP . 4:END. Byte_num represent the number of data need to be send or data need to be received. ack_check_en ack_exp and ack value are used to control the ack bit.*/
+#define I2C_COMMAND15 0x00003FFF
+#define I2C_COMMAND15_M ((I2C_COMMAND15_V)<<(I2C_COMMAND15_S))
+#define I2C_COMMAND15_V 0x3FFF
+#define I2C_COMMAND15_S 0
+
+#define I2C_DATE_REG(i) (REG_I2C_BASE(i) + 0x00F8)
+/* I2C_DATE : R/W ;bitpos:[31:0] ;default: 32'h16042000 ; */
+/*description: */
+#define I2C_DATE 0xFFFFFFFF
+#define I2C_DATE_M ((I2C_DATE_V)<<(I2C_DATE_S))
+#define I2C_DATE_V 0xFFFFFFFF
+#define I2C_DATE_S 0
+
+#define I2C_FIFO_START_ADDR_REG(i) (REG_I2C_BASE(i) + 0x0100)
+
+
+
+
+#endif /*_SOC_I2C_REG_H_ */
+
+
-// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD\r
-//\r
-// Licensed under the Apache License, Version 2.0 (the "License");\r
-// you may not use this file except in compliance with the License.\r
-// You may obtain a copy of the License at\r
-\r
-// http://www.apache.org/licenses/LICENSE-2.0\r
-//\r
-// Unless required by applicable law or agreed to in writing, software\r
-// distributed under the License is distributed on an "AS IS" BASIS,\r
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
-// See the License for the specific language governing permissions and\r
-// limitations under the License.\r
-#ifndef _SOC_LEDC_REG_H_\r
-#define _SOC_LEDC_REG_H_\r
-\r
-\r
-#include "soc.h"\r
-#define LEDC_HSCH0_CONF0_REG (DR_REG_LEDC_BASE + 0x0000)\r
-/* LEDC_CLK_EN : R/W ;bitpos:[31] ;default: 1'h0 ; */\r
-/*description: This bit is clock gating control signal. when software config\r
- LED_PWM internal registers it controls the register clock.*/\r
-#define LEDC_CLK_EN (BIT(31))\r
-#define LEDC_CLK_EN_M (BIT(31))\r
-#define LEDC_CLK_EN_V 0x1\r
-#define LEDC_CLK_EN_S 31\r
-/* LEDC_IDLE_LV_HSCH0 : R/W ;bitpos:[3] ;default: 1'b0 ; */\r
-/*description: This bit is used to control the output value when high speed channel0 is off.*/\r
-#define LEDC_IDLE_LV_HSCH0 (BIT(3))\r
-#define LEDC_IDLE_LV_HSCH0_M (BIT(3))\r
-#define LEDC_IDLE_LV_HSCH0_V 0x1\r
-#define LEDC_IDLE_LV_HSCH0_S 3\r
-/* LEDC_SIG_OUT_EN_HSCH0 : R/W ;bitpos:[2] ;default: 1'b0 ; */\r
-/*description: This is the output enable control bit for high speed channel0*/\r
-#define LEDC_SIG_OUT_EN_HSCH0 (BIT(2))\r
-#define LEDC_SIG_OUT_EN_HSCH0_M (BIT(2))\r
-#define LEDC_SIG_OUT_EN_HSCH0_V 0x1\r
-#define LEDC_SIG_OUT_EN_HSCH0_S 2\r
-/* LEDC_TIMER_SEL_HSCH0 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */\r
-/*description: There are four high speed timers the two bits are used to select\r
- one of them for high speed channel0. 2'b00: seletc hstimer0. 2'b01: select hstimer1. 2'b10: select hstimer2. 2'b11: select hstimer3.*/\r
-#define LEDC_TIMER_SEL_HSCH0 0x00000003\r
-#define LEDC_TIMER_SEL_HSCH0_M ((LEDC_TIMER_SEL_HSCH0_V)<<(LEDC_TIMER_SEL_HSCH0_S))\r
-#define LEDC_TIMER_SEL_HSCH0_V 0x3\r
-#define LEDC_TIMER_SEL_HSCH0_S 0\r
-\r
-#define LEDC_HSCH0_HPOINT_REG (DR_REG_LEDC_BASE + 0x0004)\r
-/* LEDC_HPOINT_HSCH0 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */\r
-/*description: The output value changes to high when htimerx(x=[0 3]) selected\r
- by high speed channel0 has reached reg_hpoint_hsch0[19:0]*/\r
-#define LEDC_HPOINT_HSCH0 0x000FFFFF\r
-#define LEDC_HPOINT_HSCH0_M ((LEDC_HPOINT_HSCH0_V)<<(LEDC_HPOINT_HSCH0_S))\r
-#define LEDC_HPOINT_HSCH0_V 0xFFFFF\r
-#define LEDC_HPOINT_HSCH0_S 0\r
-\r
-#define LEDC_HSCH0_DUTY_REG (DR_REG_LEDC_BASE + 0x0008)\r
-/* LEDC_DUTY_HSCH0 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */\r
-/*description: The register is used to control output duty. When hstimerx(x=[0\r
- 3]) choosed by high speed channel0 has reached reg_lpoint_hsch0 the output signal changes to low. reg_lpoint_hsch0=(reg_hpoint_hsch0[19:0]+reg_duty_hsch0[24:4]) (1) reg_lpoint_hsch0=(reg_hpoint_hsch0[19:0]+reg_duty_hsch0[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/\r
-#define LEDC_DUTY_HSCH0 0x01FFFFFF\r
-#define LEDC_DUTY_HSCH0_M ((LEDC_DUTY_HSCH0_V)<<(LEDC_DUTY_HSCH0_S))\r
-#define LEDC_DUTY_HSCH0_V 0x1FFFFFF\r
-#define LEDC_DUTY_HSCH0_S 0\r
-\r
-#define LEDC_HSCH0_CONF1_REG (DR_REG_LEDC_BASE + 0x000C)\r
-/* LEDC_DUTY_START_HSCH0 : R/W ;bitpos:[31] ;default: 1'b0 ; */\r
-/*description: When reg_duty_num_hsch0 reg_duty_cycle_hsch0 and reg_duty_scale_hsch0\r
- has been configured. these register won't take effect until set reg_duty_start_hsch0. this bit is automatically cleared by hardware.*/\r
-#define LEDC_DUTY_START_HSCH0 (BIT(31))\r
-#define LEDC_DUTY_START_HSCH0_M (BIT(31))\r
-#define LEDC_DUTY_START_HSCH0_V 0x1\r
-#define LEDC_DUTY_START_HSCH0_S 31\r
-/* LEDC_DUTY_INC_HSCH0 : R/W ;bitpos:[30] ;default: 1'b1 ; */\r
-/*description: This register is used to increase the duty of output signal or\r
- decrease the duty of output signal for high speed channel0.*/\r
-#define LEDC_DUTY_INC_HSCH0 (BIT(30))\r
-#define LEDC_DUTY_INC_HSCH0_M (BIT(30))\r
-#define LEDC_DUTY_INC_HSCH0_V 0x1\r
-#define LEDC_DUTY_INC_HSCH0_S 30\r
-/* LEDC_DUTY_NUM_HSCH0 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */\r
-/*description: This register is used to control the num of increased or decreased\r
- times for high speed channel0.*/\r
-#define LEDC_DUTY_NUM_HSCH0 0x000003FF\r
-#define LEDC_DUTY_NUM_HSCH0_M ((LEDC_DUTY_NUM_HSCH0_V)<<(LEDC_DUTY_NUM_HSCH0_S))\r
-#define LEDC_DUTY_NUM_HSCH0_V 0x3FF\r
-#define LEDC_DUTY_NUM_HSCH0_S 20\r
-/* LEDC_DUTY_CYCLE_HSCH0 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */\r
-/*description: This register is used to increase or decrease the duty every\r
- reg_duty_cycle_hsch0 cycles for high speed channel0.*/\r
-#define LEDC_DUTY_CYCLE_HSCH0 0x000003FF\r
-#define LEDC_DUTY_CYCLE_HSCH0_M ((LEDC_DUTY_CYCLE_HSCH0_V)<<(LEDC_DUTY_CYCLE_HSCH0_S))\r
-#define LEDC_DUTY_CYCLE_HSCH0_V 0x3FF\r
-#define LEDC_DUTY_CYCLE_HSCH0_S 10\r
-/* LEDC_DUTY_SCALE_HSCH0 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */\r
-/*description: This register controls the increase or decrease step scale for\r
- high speed channel0.*/\r
-#define LEDC_DUTY_SCALE_HSCH0 0x000003FF\r
-#define LEDC_DUTY_SCALE_HSCH0_M ((LEDC_DUTY_SCALE_HSCH0_V)<<(LEDC_DUTY_SCALE_HSCH0_S))\r
-#define LEDC_DUTY_SCALE_HSCH0_V 0x3FF\r
-#define LEDC_DUTY_SCALE_HSCH0_S 0\r
-\r
-#define LEDC_HSCH0_DUTY_R_REG (DR_REG_LEDC_BASE + 0x0010)\r
-/* LEDC_DUTY_HSCH0 : RO ;bitpos:[24:0] ;default: 25'h0 ; */\r
-/*description: This register represents the current duty of the output signal\r
- for high speed channel0.*/\r
-#define LEDC_DUTY_HSCH0 0x01FFFFFF\r
-#define LEDC_DUTY_HSCH0_M ((LEDC_DUTY_HSCH0_V)<<(LEDC_DUTY_HSCH0_S))\r
-#define LEDC_DUTY_HSCH0_V 0x1FFFFFF\r
-#define LEDC_DUTY_HSCH0_S 0\r
-\r
-#define LEDC_HSCH1_CONF0_REG (DR_REG_LEDC_BASE + 0x0014)\r
-/* LEDC_IDLE_LV_HSCH1 : R/W ;bitpos:[3] ;default: 1'b0 ; */\r
-/*description: This bit is used to control the output value when high speed channel1 is off.*/\r
-#define LEDC_IDLE_LV_HSCH1 (BIT(3))\r
-#define LEDC_IDLE_LV_HSCH1_M (BIT(3))\r
-#define LEDC_IDLE_LV_HSCH1_V 0x1\r
-#define LEDC_IDLE_LV_HSCH1_S 3\r
-/* LEDC_SIG_OUT_EN_HSCH1 : R/W ;bitpos:[2] ;default: 1'b0 ; */\r
-/*description: This is the output enable control bit for high speed channel1*/\r
-#define LEDC_SIG_OUT_EN_HSCH1 (BIT(2))\r
-#define LEDC_SIG_OUT_EN_HSCH1_M (BIT(2))\r
-#define LEDC_SIG_OUT_EN_HSCH1_V 0x1\r
-#define LEDC_SIG_OUT_EN_HSCH1_S 2\r
-/* LEDC_TIMER_SEL_HSCH1 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */\r
-/*description: There are four high speed timers the two bits are used to select\r
- one of them for high speed channel1. 2'b00: seletc hstimer0. 2'b01: select hstimer1. 2'b10: select hstimer2. 2'b11: select hstimer3.*/\r
-#define LEDC_TIMER_SEL_HSCH1 0x00000003\r
-#define LEDC_TIMER_SEL_HSCH1_M ((LEDC_TIMER_SEL_HSCH1_V)<<(LEDC_TIMER_SEL_HSCH1_S))\r
-#define LEDC_TIMER_SEL_HSCH1_V 0x3\r
-#define LEDC_TIMER_SEL_HSCH1_S 0\r
-\r
-#define LEDC_HSCH1_HPOINT_REG (DR_REG_LEDC_BASE + 0x0018)\r
-/* LEDC_HPOINT_HSCH1 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */\r
-/*description: The output value changes to high when htimerx(x=[0 3]) selected\r
- by high speed channel1 has reached reg_hpoint_hsch1[19:0]*/\r
-#define LEDC_HPOINT_HSCH1 0x000FFFFF\r
-#define LEDC_HPOINT_HSCH1_M ((LEDC_HPOINT_HSCH1_V)<<(LEDC_HPOINT_HSCH1_S))\r
-#define LEDC_HPOINT_HSCH1_V 0xFFFFF\r
-#define LEDC_HPOINT_HSCH1_S 0\r
-\r
-#define LEDC_HSCH1_DUTY_REG (DR_REG_LEDC_BASE + 0x001C)\r
-/* LEDC_DUTY_HSCH1 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */\r
-/*description: The register is used to control output duty. When hstimerx(x=[0\r
- 3]) choosed by high speed channel1 has reached reg_lpoint_hsch1 the output signal changes to low. reg_lpoint_hsch1=(reg_hpoint_hsch1[19:0]+reg_duty_hsch1[24:4]) (1) reg_lpoint_hsch1=(reg_hpoint_hsch1[19:0]+reg_duty_hsch1[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/\r
-#define LEDC_DUTY_HSCH1 0x01FFFFFF\r
-#define LEDC_DUTY_HSCH1_M ((LEDC_DUTY_HSCH1_V)<<(LEDC_DUTY_HSCH1_S))\r
-#define LEDC_DUTY_HSCH1_V 0x1FFFFFF\r
-#define LEDC_DUTY_HSCH1_S 0\r
-\r
-#define LEDC_HSCH1_CONF1_REG (DR_REG_LEDC_BASE + 0x0020)\r
-/* LEDC_DUTY_START_HSCH1 : R/W ;bitpos:[31] ;default: 1'b0 ; */\r
-/*description: When reg_duty_num_hsch1 reg_duty_cycle_hsch1 and reg_duty_scale_hsch1\r
- has been configured. these register won't take effect until set reg_duty_start_hsch1. this bit is automatically cleared by hardware.*/\r
-#define LEDC_DUTY_START_HSCH1 (BIT(31))\r
-#define LEDC_DUTY_START_HSCH1_M (BIT(31))\r
-#define LEDC_DUTY_START_HSCH1_V 0x1\r
-#define LEDC_DUTY_START_HSCH1_S 31\r
-/* LEDC_DUTY_INC_HSCH1 : R/W ;bitpos:[30] ;default: 1'b1 ; */\r
-/*description: This register is used to increase the duty of output signal or\r
- decrease the duty of output signal for high speed channel1.*/\r
-#define LEDC_DUTY_INC_HSCH1 (BIT(30))\r
-#define LEDC_DUTY_INC_HSCH1_M (BIT(30))\r
-#define LEDC_DUTY_INC_HSCH1_V 0x1\r
-#define LEDC_DUTY_INC_HSCH1_S 30\r
-/* LEDC_DUTY_NUM_HSCH1 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */\r
-/*description: This register is used to control the num of increased or decreased\r
- times for high speed channel1.*/\r
-#define LEDC_DUTY_NUM_HSCH1 0x000003FF\r
-#define LEDC_DUTY_NUM_HSCH1_M ((LEDC_DUTY_NUM_HSCH1_V)<<(LEDC_DUTY_NUM_HSCH1_S))\r
-#define LEDC_DUTY_NUM_HSCH1_V 0x3FF\r
-#define LEDC_DUTY_NUM_HSCH1_S 20\r
-/* LEDC_DUTY_CYCLE_HSCH1 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */\r
-/*description: This register is used to increase or decrease the duty every\r
- reg_duty_cycle_hsch1 cycles for high speed channel1.*/\r
-#define LEDC_DUTY_CYCLE_HSCH1 0x000003FF\r
-#define LEDC_DUTY_CYCLE_HSCH1_M ((LEDC_DUTY_CYCLE_HSCH1_V)<<(LEDC_DUTY_CYCLE_HSCH1_S))\r
-#define LEDC_DUTY_CYCLE_HSCH1_V 0x3FF\r
-#define LEDC_DUTY_CYCLE_HSCH1_S 10\r
-/* LEDC_DUTY_SCALE_HSCH1 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */\r
-/*description: This register controls the increase or decrease step scale for\r
- high speed channel1.*/\r
-#define LEDC_DUTY_SCALE_HSCH1 0x000003FF\r
-#define LEDC_DUTY_SCALE_HSCH1_M ((LEDC_DUTY_SCALE_HSCH1_V)<<(LEDC_DUTY_SCALE_HSCH1_S))\r
-#define LEDC_DUTY_SCALE_HSCH1_V 0x3FF\r
-#define LEDC_DUTY_SCALE_HSCH1_S 0\r
-\r
-#define LEDC_HSCH1_DUTY_R_REG (DR_REG_LEDC_BASE + 0x0024)\r
-/* LEDC_DUTY_HSCH1 : RO ;bitpos:[24:0] ;default: 25'h0 ; */\r
-/*description: This register represents the current duty of the output signal\r
- for high speed channel1.*/\r
-#define LEDC_DUTY_HSCH1 0x01FFFFFF\r
-#define LEDC_DUTY_HSCH1_M ((LEDC_DUTY_HSCH1_V)<<(LEDC_DUTY_HSCH1_S))\r
-#define LEDC_DUTY_HSCH1_V 0x1FFFFFF\r
-#define LEDC_DUTY_HSCH1_S 0\r
-\r
-#define LEDC_HSCH2_CONF0_REG (DR_REG_LEDC_BASE + 0x0028)\r
-/* LEDC_IDLE_LV_HSCH2 : R/W ;bitpos:[3] ;default: 1'b0 ; */\r
-/*description: This bit is used to control the output value when high speed channel2 is off.*/\r
-#define LEDC_IDLE_LV_HSCH2 (BIT(3))\r
-#define LEDC_IDLE_LV_HSCH2_M (BIT(3))\r
-#define LEDC_IDLE_LV_HSCH2_V 0x1\r
-#define LEDC_IDLE_LV_HSCH2_S 3\r
-/* LEDC_SIG_OUT_EN_HSCH2 : R/W ;bitpos:[2] ;default: 1'b0 ; */\r
-/*description: This is the output enable control bit for high speed channel2*/\r
-#define LEDC_SIG_OUT_EN_HSCH2 (BIT(2))\r
-#define LEDC_SIG_OUT_EN_HSCH2_M (BIT(2))\r
-#define LEDC_SIG_OUT_EN_HSCH2_V 0x1\r
-#define LEDC_SIG_OUT_EN_HSCH2_S 2\r
-/* LEDC_TIMER_SEL_HSCH2 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */\r
-/*description: There are four high speed timers the two bits are used to select\r
- one of them for high speed channel2. 2'b00: seletc hstimer0. 2'b01: select hstimer1. 2'b10: select hstimer2. 2'b11: select hstimer3.*/\r
-#define LEDC_TIMER_SEL_HSCH2 0x00000003\r
-#define LEDC_TIMER_SEL_HSCH2_M ((LEDC_TIMER_SEL_HSCH2_V)<<(LEDC_TIMER_SEL_HSCH2_S))\r
-#define LEDC_TIMER_SEL_HSCH2_V 0x3\r
-#define LEDC_TIMER_SEL_HSCH2_S 0\r
-\r
-#define LEDC_HSCH2_HPOINT_REG (DR_REG_LEDC_BASE + 0x002C)\r
-/* LEDC_HPOINT_HSCH2 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */\r
-/*description: The output value changes to high when htimerx(x=[0 3]) selected\r
- by high speed channel2 has reached reg_hpoint_hsch2[19:0]*/\r
-#define LEDC_HPOINT_HSCH2 0x000FFFFF\r
-#define LEDC_HPOINT_HSCH2_M ((LEDC_HPOINT_HSCH2_V)<<(LEDC_HPOINT_HSCH2_S))\r
-#define LEDC_HPOINT_HSCH2_V 0xFFFFF\r
-#define LEDC_HPOINT_HSCH2_S 0\r
-\r
-#define LEDC_HSCH2_DUTY_REG (DR_REG_LEDC_BASE + 0x0030)\r
-/* LEDC_DUTY_HSCH2 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */\r
-/*description: The register is used to control output duty. When hstimerx(x=[0\r
- 3]) choosed by high speed channel2 has reached reg_lpoint_hsch2 the output signal changes to low. reg_lpoint_hsch2=(reg_hpoint_hsch2[19:0]+reg_duty_hsch2[24:4]) (1) reg_lpoint_hsch2=(reg_hpoint_hsch2[19:0]+reg_duty_hsch2[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/\r
-#define LEDC_DUTY_HSCH2 0x01FFFFFF\r
-#define LEDC_DUTY_HSCH2_M ((LEDC_DUTY_HSCH2_V)<<(LEDC_DUTY_HSCH2_S))\r
-#define LEDC_DUTY_HSCH2_V 0x1FFFFFF\r
-#define LEDC_DUTY_HSCH2_S 0\r
-\r
-#define LEDC_HSCH2_CONF1_REG (DR_REG_LEDC_BASE + 0x0034)\r
-/* LEDC_DUTY_START_HSCH2 : R/W ;bitpos:[31] ;default: 1'b0 ; */\r
-/*description: When reg_duty_num_hsch2 reg_duty_cycle_hsch2 and reg_duty_scale_hsch2\r
- has been configured. these register won't take effect until set reg_duty_start_hsch2. this bit is automatically cleared by hardware.*/\r
-#define LEDC_DUTY_START_HSCH2 (BIT(31))\r
-#define LEDC_DUTY_START_HSCH2_M (BIT(31))\r
-#define LEDC_DUTY_START_HSCH2_V 0x1\r
-#define LEDC_DUTY_START_HSCH2_S 31\r
-/* LEDC_DUTY_INC_HSCH2 : R/W ;bitpos:[30] ;default: 1'b1 ; */\r
-/*description: This register is used to increase the duty of output signal or\r
- decrease the duty of output signal for high speed channel2.*/\r
-#define LEDC_DUTY_INC_HSCH2 (BIT(30))\r
-#define LEDC_DUTY_INC_HSCH2_M (BIT(30))\r
-#define LEDC_DUTY_INC_HSCH2_V 0x1\r
-#define LEDC_DUTY_INC_HSCH2_S 30\r
-/* LEDC_DUTY_NUM_HSCH2 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */\r
-/*description: This register is used to control the num of increased or decreased\r
- times for high speed channel2.*/\r
-#define LEDC_DUTY_NUM_HSCH2 0x000003FF\r
-#define LEDC_DUTY_NUM_HSCH2_M ((LEDC_DUTY_NUM_HSCH2_V)<<(LEDC_DUTY_NUM_HSCH2_S))\r
-#define LEDC_DUTY_NUM_HSCH2_V 0x3FF\r
-#define LEDC_DUTY_NUM_HSCH2_S 20\r
-/* LEDC_DUTY_CYCLE_HSCH2 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */\r
-/*description: This register is used to increase or decrease the duty every\r
- reg_duty_cycle_hsch2 cycles for high speed channel2.*/\r
-#define LEDC_DUTY_CYCLE_HSCH2 0x000003FF\r
-#define LEDC_DUTY_CYCLE_HSCH2_M ((LEDC_DUTY_CYCLE_HSCH2_V)<<(LEDC_DUTY_CYCLE_HSCH2_S))\r
-#define LEDC_DUTY_CYCLE_HSCH2_V 0x3FF\r
-#define LEDC_DUTY_CYCLE_HSCH2_S 10\r
-/* LEDC_DUTY_SCALE_HSCH2 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */\r
-/*description: This register controls the increase or decrease step scale for\r
- high speed channel2.*/\r
-#define LEDC_DUTY_SCALE_HSCH2 0x000003FF\r
-#define LEDC_DUTY_SCALE_HSCH2_M ((LEDC_DUTY_SCALE_HSCH2_V)<<(LEDC_DUTY_SCALE_HSCH2_S))\r
-#define LEDC_DUTY_SCALE_HSCH2_V 0x3FF\r
-#define LEDC_DUTY_SCALE_HSCH2_S 0\r
-\r
-#define LEDC_HSCH2_DUTY_R_REG (DR_REG_LEDC_BASE + 0x0038)\r
-/* LEDC_DUTY_HSCH2 : RO ;bitpos:[24:0] ;default: 25'h0 ; */\r
-/*description: This register represents the current duty of the output signal\r
- for high speed channel2.*/\r
-#define LEDC_DUTY_HSCH2 0x01FFFFFF\r
-#define LEDC_DUTY_HSCH2_M ((LEDC_DUTY_HSCH2_V)<<(LEDC_DUTY_HSCH2_S))\r
-#define LEDC_DUTY_HSCH2_V 0x1FFFFFF\r
-#define LEDC_DUTY_HSCH2_S 0\r
-\r
-#define LEDC_HSCH3_CONF0_REG (DR_REG_LEDC_BASE + 0x003C)\r
-/* LEDC_IDLE_LV_HSCH3 : R/W ;bitpos:[3] ;default: 1'b0 ; */\r
-/*description: This bit is used to control the output value when high speed channel3 is off.*/\r
-#define LEDC_IDLE_LV_HSCH3 (BIT(3))\r
-#define LEDC_IDLE_LV_HSCH3_M (BIT(3))\r
-#define LEDC_IDLE_LV_HSCH3_V 0x1\r
-#define LEDC_IDLE_LV_HSCH3_S 3\r
-/* LEDC_SIG_OUT_EN_HSCH3 : R/W ;bitpos:[2] ;default: 1'b0 ; */\r
-/*description: This is the output enable control bit for high speed channel3*/\r
-#define LEDC_SIG_OUT_EN_HSCH3 (BIT(2))\r
-#define LEDC_SIG_OUT_EN_HSCH3_M (BIT(2))\r
-#define LEDC_SIG_OUT_EN_HSCH3_V 0x1\r
-#define LEDC_SIG_OUT_EN_HSCH3_S 2\r
-/* LEDC_TIMER_SEL_HSCH3 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */\r
-/*description: There are four high speed timers the two bits are used to select\r
- one of them for high speed channel3. 2'b00: seletc hstimer0. 2'b01: select hstimer1. 2'b10: select hstimer2. 2'b11: select hstimer3.*/\r
-#define LEDC_TIMER_SEL_HSCH3 0x00000003\r
-#define LEDC_TIMER_SEL_HSCH3_M ((LEDC_TIMER_SEL_HSCH3_V)<<(LEDC_TIMER_SEL_HSCH3_S))\r
-#define LEDC_TIMER_SEL_HSCH3_V 0x3\r
-#define LEDC_TIMER_SEL_HSCH3_S 0\r
-\r
-#define LEDC_HSCH3_HPOINT_REG (DR_REG_LEDC_BASE + 0x0040)\r
-/* LEDC_HPOINT_HSCH3 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */\r
-/*description: The output value changes to high when htimerx(x=[0 3]) selected\r
- by high speed channel3 has reached reg_hpoint_hsch3[19:0]*/\r
-#define LEDC_HPOINT_HSCH3 0x000FFFFF\r
-#define LEDC_HPOINT_HSCH3_M ((LEDC_HPOINT_HSCH3_V)<<(LEDC_HPOINT_HSCH3_S))\r
-#define LEDC_HPOINT_HSCH3_V 0xFFFFF\r
-#define LEDC_HPOINT_HSCH3_S 0\r
-\r
-#define LEDC_HSCH3_DUTY_REG (DR_REG_LEDC_BASE + 0x0044)\r
-/* LEDC_DUTY_HSCH3 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */\r
-/*description: The register is used to control output duty. When hstimerx(x=[0\r
- 3]) choosed by high speed channel3 has reached reg_lpoint_hsch3 the output signal changes to low. reg_lpoint_hsch3=(reg_hpoint_hsch3[19:0]+reg_duty_hsch3[24:4]) (1) reg_lpoint_hsch3=(reg_hpoint_hsch3[19:0]+reg_duty_hsch3[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/\r
-#define LEDC_DUTY_HSCH3 0x01FFFFFF\r
-#define LEDC_DUTY_HSCH3_M ((LEDC_DUTY_HSCH3_V)<<(LEDC_DUTY_HSCH3_S))\r
-#define LEDC_DUTY_HSCH3_V 0x1FFFFFF\r
-#define LEDC_DUTY_HSCH3_S 0\r
-\r
-#define LEDC_HSCH3_CONF1_REG (DR_REG_LEDC_BASE + 0x0048)\r
-/* LEDC_DUTY_START_HSCH3 : R/W ;bitpos:[31] ;default: 1'b0 ; */\r
-/*description: When reg_duty_num_hsch3 reg_duty_cycle_hsch3 and reg_duty_scale_hsch3\r
- has been configured. these register won't take effect until set reg_duty_start_hsch3. this bit is automatically cleared by hardware.*/\r
-#define LEDC_DUTY_START_HSCH3 (BIT(31))\r
-#define LEDC_DUTY_START_HSCH3_M (BIT(31))\r
-#define LEDC_DUTY_START_HSCH3_V 0x1\r
-#define LEDC_DUTY_START_HSCH3_S 31\r
-/* LEDC_DUTY_INC_HSCH3 : R/W ;bitpos:[30] ;default: 1'b1 ; */\r
-/*description: This register is used to increase the duty of output signal or\r
- decrease the duty of output signal for high speed channel3.*/\r
-#define LEDC_DUTY_INC_HSCH3 (BIT(30))\r
-#define LEDC_DUTY_INC_HSCH3_M (BIT(30))\r
-#define LEDC_DUTY_INC_HSCH3_V 0x1\r
-#define LEDC_DUTY_INC_HSCH3_S 30\r
-/* LEDC_DUTY_NUM_HSCH3 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */\r
-/*description: This register is used to control the num of increased or decreased\r
- times for high speed channel3.*/\r
-#define LEDC_DUTY_NUM_HSCH3 0x000003FF\r
-#define LEDC_DUTY_NUM_HSCH3_M ((LEDC_DUTY_NUM_HSCH3_V)<<(LEDC_DUTY_NUM_HSCH3_S))\r
-#define LEDC_DUTY_NUM_HSCH3_V 0x3FF\r
-#define LEDC_DUTY_NUM_HSCH3_S 20\r
-/* LEDC_DUTY_CYCLE_HSCH3 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */\r
-/*description: This register is used to increase or decrease the duty every\r
- reg_duty_cycle_hsch3 cycles for high speed channel3.*/\r
-#define LEDC_DUTY_CYCLE_HSCH3 0x000003FF\r
-#define LEDC_DUTY_CYCLE_HSCH3_M ((LEDC_DUTY_CYCLE_HSCH3_V)<<(LEDC_DUTY_CYCLE_HSCH3_S))\r
-#define LEDC_DUTY_CYCLE_HSCH3_V 0x3FF\r
-#define LEDC_DUTY_CYCLE_HSCH3_S 10\r
-/* LEDC_DUTY_SCALE_HSCH3 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */\r
-/*description: This register controls the increase or decrease step scale for\r
- high speed channel3.*/\r
-#define LEDC_DUTY_SCALE_HSCH3 0x000003FF\r
-#define LEDC_DUTY_SCALE_HSCH3_M ((LEDC_DUTY_SCALE_HSCH3_V)<<(LEDC_DUTY_SCALE_HSCH3_S))\r
-#define LEDC_DUTY_SCALE_HSCH3_V 0x3FF\r
-#define LEDC_DUTY_SCALE_HSCH3_S 0\r
-\r
-#define LEDC_HSCH3_DUTY_R_REG (DR_REG_LEDC_BASE + 0x004C)\r
-/* LEDC_DUTY_HSCH3 : RO ;bitpos:[24:0] ;default: 25'h0 ; */\r
-/*description: This register represents the current duty of the output signal\r
- for high speed channel3.*/\r
-#define LEDC_DUTY_HSCH3 0x01FFFFFF\r
-#define LEDC_DUTY_HSCH3_M ((LEDC_DUTY_HSCH3_V)<<(LEDC_DUTY_HSCH3_S))\r
-#define LEDC_DUTY_HSCH3_V 0x1FFFFFF\r
-#define LEDC_DUTY_HSCH3_S 0\r
-\r
-#define LEDC_HSCH4_CONF0_REG (DR_REG_LEDC_BASE + 0x0050)\r
-/* LEDC_IDLE_LV_HSCH4 : R/W ;bitpos:[3] ;default: 1'b0 ; */\r
-/*description: This bit is used to control the output value when high speed channel4 is off.*/\r
-#define LEDC_IDLE_LV_HSCH4 (BIT(3))\r
-#define LEDC_IDLE_LV_HSCH4_M (BIT(3))\r
-#define LEDC_IDLE_LV_HSCH4_V 0x1\r
-#define LEDC_IDLE_LV_HSCH4_S 3\r
-/* LEDC_SIG_OUT_EN_HSCH4 : R/W ;bitpos:[2] ;default: 1'b0 ; */\r
-/*description: This is the output enable control bit for high speed channel4*/\r
-#define LEDC_SIG_OUT_EN_HSCH4 (BIT(2))\r
-#define LEDC_SIG_OUT_EN_HSCH4_M (BIT(2))\r
-#define LEDC_SIG_OUT_EN_HSCH4_V 0x1\r
-#define LEDC_SIG_OUT_EN_HSCH4_S 2\r
-/* LEDC_TIMER_SEL_HSCH4 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */\r
-/*description: There are four high speed timers the two bits are used to select\r
- one of them for high speed channel4. 2'b00: seletc hstimer0. 2'b01: select hstimer1. 2'b10: select hstimer2. 2'b11: select hstimer3.*/\r
-#define LEDC_TIMER_SEL_HSCH4 0x00000003\r
-#define LEDC_TIMER_SEL_HSCH4_M ((LEDC_TIMER_SEL_HSCH4_V)<<(LEDC_TIMER_SEL_HSCH4_S))\r
-#define LEDC_TIMER_SEL_HSCH4_V 0x3\r
-#define LEDC_TIMER_SEL_HSCH4_S 0\r
-\r
-#define LEDC_HSCH4_HPOINT_REG (DR_REG_LEDC_BASE + 0x0054)\r
-/* LEDC_HPOINT_HSCH4 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */\r
-/*description: The output value changes to high when htimerx(x=[0 3]) selected\r
- by high speed channel4 has reached reg_hpoint_hsch4[19:0]*/\r
-#define LEDC_HPOINT_HSCH4 0x000FFFFF\r
-#define LEDC_HPOINT_HSCH4_M ((LEDC_HPOINT_HSCH4_V)<<(LEDC_HPOINT_HSCH4_S))\r
-#define LEDC_HPOINT_HSCH4_V 0xFFFFF\r
-#define LEDC_HPOINT_HSCH4_S 0\r
-\r
-#define LEDC_HSCH4_DUTY_REG (DR_REG_LEDC_BASE + 0x0058)\r
-/* LEDC_DUTY_HSCH4 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */\r
-/*description: The register is used to control output duty. When hstimerx(x=[0\r
- 3]) choosed by high speed channel4 has reached reg_lpoint_hsch4 the output signal changes to low. reg_lpoint_hsch4=(reg_hpoint_hsch4[19:0]+reg_duty_hsch4[24:4]) (1) reg_lpoint_hsch4=(reg_hpoint_hsch4[19:0]+reg_duty_hsch4[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/\r
-#define LEDC_DUTY_HSCH4 0x01FFFFFF\r
-#define LEDC_DUTY_HSCH4_M ((LEDC_DUTY_HSCH4_V)<<(LEDC_DUTY_HSCH4_S))\r
-#define LEDC_DUTY_HSCH4_V 0x1FFFFFF\r
-#define LEDC_DUTY_HSCH4_S 0\r
-\r
-#define LEDC_HSCH4_CONF1_REG (DR_REG_LEDC_BASE + 0x005C)\r
-/* LEDC_DUTY_START_HSCH4 : R/W ;bitpos:[31] ;default: 1'b0 ; */\r
-/*description: When reg_duty_num_hsch1 reg_duty_cycle_hsch1 and reg_duty_scale_hsch1\r
- has been configured. these register won't take effect until set reg_duty_start_hsch1. this bit is automatically cleared by hardware.*/\r
-#define LEDC_DUTY_START_HSCH4 (BIT(31))\r
-#define LEDC_DUTY_START_HSCH4_M (BIT(31))\r
-#define LEDC_DUTY_START_HSCH4_V 0x1\r
-#define LEDC_DUTY_START_HSCH4_S 31\r
-/* LEDC_DUTY_INC_HSCH4 : R/W ;bitpos:[30] ;default: 1'b1 ; */\r
-/*description: This register is used to increase the duty of output signal or\r
- decrease the duty of output signal for high speed channel4.*/\r
-#define LEDC_DUTY_INC_HSCH4 (BIT(30))\r
-#define LEDC_DUTY_INC_HSCH4_M (BIT(30))\r
-#define LEDC_DUTY_INC_HSCH4_V 0x1\r
-#define LEDC_DUTY_INC_HSCH4_S 30\r
-/* LEDC_DUTY_NUM_HSCH4 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */\r
-/*description: This register is used to control the num of increased or decreased\r
- times for high speed channel1.*/\r
-#define LEDC_DUTY_NUM_HSCH4 0x000003FF\r
-#define LEDC_DUTY_NUM_HSCH4_M ((LEDC_DUTY_NUM_HSCH4_V)<<(LEDC_DUTY_NUM_HSCH4_S))\r
-#define LEDC_DUTY_NUM_HSCH4_V 0x3FF\r
-#define LEDC_DUTY_NUM_HSCH4_S 20\r
-/* LEDC_DUTY_CYCLE_HSCH4 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */\r
-/*description: This register is used to increase or decrease the duty every\r
- reg_duty_cycle_hsch4 cycles for high speed channel4.*/\r
-#define LEDC_DUTY_CYCLE_HSCH4 0x000003FF\r
-#define LEDC_DUTY_CYCLE_HSCH4_M ((LEDC_DUTY_CYCLE_HSCH4_V)<<(LEDC_DUTY_CYCLE_HSCH4_S))\r
-#define LEDC_DUTY_CYCLE_HSCH4_V 0x3FF\r
-#define LEDC_DUTY_CYCLE_HSCH4_S 10\r
-/* LEDC_DUTY_SCALE_HSCH4 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */\r
-/*description: This register controls the increase or decrease step scale for\r
- high speed channel4.*/\r
-#define LEDC_DUTY_SCALE_HSCH4 0x000003FF\r
-#define LEDC_DUTY_SCALE_HSCH4_M ((LEDC_DUTY_SCALE_HSCH4_V)<<(LEDC_DUTY_SCALE_HSCH4_S))\r
-#define LEDC_DUTY_SCALE_HSCH4_V 0x3FF\r
-#define LEDC_DUTY_SCALE_HSCH4_S 0\r
-\r
-#define LEDC_HSCH4_DUTY_R_REG (DR_REG_LEDC_BASE + 0x0060)\r
-/* LEDC_DUTY_HSCH4 : RO ;bitpos:[24:0] ;default: 25'h0 ; */\r
-/*description: This register represents the current duty of the output signal\r
- for high speed channel4.*/\r
-#define LEDC_DUTY_HSCH4 0x01FFFFFF\r
-#define LEDC_DUTY_HSCH4_M ((LEDC_DUTY_HSCH4_V)<<(LEDC_DUTY_HSCH4_S))\r
-#define LEDC_DUTY_HSCH4_V 0x1FFFFFF\r
-#define LEDC_DUTY_HSCH4_S 0\r
-\r
-#define LEDC_HSCH5_CONF0_REG (DR_REG_LEDC_BASE + 0x0064)\r
-/* LEDC_IDLE_LV_HSCH5 : R/W ;bitpos:[3] ;default: 1'b0 ; */\r
-/*description: This bit is used to control the output value when high speed channel5 is off.*/\r
-#define LEDC_IDLE_LV_HSCH5 (BIT(3))\r
-#define LEDC_IDLE_LV_HSCH5_M (BIT(3))\r
-#define LEDC_IDLE_LV_HSCH5_V 0x1\r
-#define LEDC_IDLE_LV_HSCH5_S 3\r
-/* LEDC_SIG_OUT_EN_HSCH5 : R/W ;bitpos:[2] ;default: 1'b0 ; */\r
-/*description: This is the output enable control bit for high speed channel5.*/\r
-#define LEDC_SIG_OUT_EN_HSCH5 (BIT(2))\r
-#define LEDC_SIG_OUT_EN_HSCH5_M (BIT(2))\r
-#define LEDC_SIG_OUT_EN_HSCH5_V 0x1\r
-#define LEDC_SIG_OUT_EN_HSCH5_S 2\r
-/* LEDC_TIMER_SEL_HSCH5 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */\r
-/*description: There are four high speed timers the two bits are used to select\r
- one of them for high speed channel5. 2'b00: seletc hstimer0. 2'b01: select hstimer1. 2'b10: select hstimer2. 2'b11: select hstimer3.*/\r
-#define LEDC_TIMER_SEL_HSCH5 0x00000003\r
-#define LEDC_TIMER_SEL_HSCH5_M ((LEDC_TIMER_SEL_HSCH5_V)<<(LEDC_TIMER_SEL_HSCH5_S))\r
-#define LEDC_TIMER_SEL_HSCH5_V 0x3\r
-#define LEDC_TIMER_SEL_HSCH5_S 0\r
-\r
-#define LEDC_HSCH5_HPOINT_REG (DR_REG_LEDC_BASE + 0x0068)\r
-/* LEDC_HPOINT_HSCH5 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */\r
-/*description: The output value changes to high when htimerx(x=[0 3]) selected\r
- by high speed channel5 has reached reg_hpoint_hsch5[19:0]*/\r
-#define LEDC_HPOINT_HSCH5 0x000FFFFF\r
-#define LEDC_HPOINT_HSCH5_M ((LEDC_HPOINT_HSCH5_V)<<(LEDC_HPOINT_HSCH5_S))\r
-#define LEDC_HPOINT_HSCH5_V 0xFFFFF\r
-#define LEDC_HPOINT_HSCH5_S 0\r
-\r
-#define LEDC_HSCH5_DUTY_REG (DR_REG_LEDC_BASE + 0x006C)\r
-/* LEDC_DUTY_HSCH5 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */\r
-/*description: The register is used to control output duty. When hstimerx(x=[0\r
- 3]) choosed by high speed channel5 has reached reg_lpoint_hsch5 the output signal changes to low. reg_lpoint_hsch5=(reg_hpoint_hsch5[19:0]+reg_duty_hsch5[24:4]) (1) reg_lpoint_hsch5=(reg_hpoint_hsch5[19:0]+reg_duty_hsch5[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/\r
-#define LEDC_DUTY_HSCH5 0x01FFFFFF\r
-#define LEDC_DUTY_HSCH5_M ((LEDC_DUTY_HSCH5_V)<<(LEDC_DUTY_HSCH5_S))\r
-#define LEDC_DUTY_HSCH5_V 0x1FFFFFF\r
-#define LEDC_DUTY_HSCH5_S 0\r
-\r
-#define LEDC_HSCH5_CONF1_REG (DR_REG_LEDC_BASE + 0x0070)\r
-/* LEDC_DUTY_START_HSCH5 : R/W ;bitpos:[31] ;default: 1'b0 ; */\r
-/*description: When reg_duty_num_hsch5 reg_duty_cycle_hsch5 and reg_duty_scale_hsch5\r
- has been configured. these register won't take effect until set reg_duty_start_hsch5. this bit is automatically cleared by hardware.*/\r
-#define LEDC_DUTY_START_HSCH5 (BIT(31))\r
-#define LEDC_DUTY_START_HSCH5_M (BIT(31))\r
-#define LEDC_DUTY_START_HSCH5_V 0x1\r
-#define LEDC_DUTY_START_HSCH5_S 31\r
-/* LEDC_DUTY_INC_HSCH5 : R/W ;bitpos:[30] ;default: 1'b1 ; */\r
-/*description: This register is used to increase the duty of output signal or\r
- decrease the duty of output signal for high speed channel5.*/\r
-#define LEDC_DUTY_INC_HSCH5 (BIT(30))\r
-#define LEDC_DUTY_INC_HSCH5_M (BIT(30))\r
-#define LEDC_DUTY_INC_HSCH5_V 0x1\r
-#define LEDC_DUTY_INC_HSCH5_S 30\r
-/* LEDC_DUTY_NUM_HSCH5 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */\r
-/*description: This register is used to control the num of increased or decreased\r
- times for high speed channel5.*/\r
-#define LEDC_DUTY_NUM_HSCH5 0x000003FF\r
-#define LEDC_DUTY_NUM_HSCH5_M ((LEDC_DUTY_NUM_HSCH5_V)<<(LEDC_DUTY_NUM_HSCH5_S))\r
-#define LEDC_DUTY_NUM_HSCH5_V 0x3FF\r
-#define LEDC_DUTY_NUM_HSCH5_S 20\r
-/* LEDC_DUTY_CYCLE_HSCH5 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */\r
-/*description: This register is used to increase or decrease the duty every\r
- reg_duty_cycle_hsch5 cycles for high speed channel5.*/\r
-#define LEDC_DUTY_CYCLE_HSCH5 0x000003FF\r
-#define LEDC_DUTY_CYCLE_HSCH5_M ((LEDC_DUTY_CYCLE_HSCH5_V)<<(LEDC_DUTY_CYCLE_HSCH5_S))\r
-#define LEDC_DUTY_CYCLE_HSCH5_V 0x3FF\r
-#define LEDC_DUTY_CYCLE_HSCH5_S 10\r
-/* LEDC_DUTY_SCALE_HSCH5 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */\r
-/*description: This register controls the increase or decrease step scale for\r
- high speed channel5.*/\r
-#define LEDC_DUTY_SCALE_HSCH5 0x000003FF\r
-#define LEDC_DUTY_SCALE_HSCH5_M ((LEDC_DUTY_SCALE_HSCH5_V)<<(LEDC_DUTY_SCALE_HSCH5_S))\r
-#define LEDC_DUTY_SCALE_HSCH5_V 0x3FF\r
-#define LEDC_DUTY_SCALE_HSCH5_S 0\r
-\r
-#define LEDC_HSCH5_DUTY_R_REG (DR_REG_LEDC_BASE + 0x0074)\r
-/* LEDC_DUTY_HSCH5 : RO ;bitpos:[24:0] ;default: 25'h0 ; */\r
-/*description: This register represents the current duty of the output signal\r
- for high speed channel5.*/\r
-#define LEDC_DUTY_HSCH5 0x01FFFFFF\r
-#define LEDC_DUTY_HSCH5_M ((LEDC_DUTY_HSCH5_V)<<(LEDC_DUTY_HSCH5_S))\r
-#define LEDC_DUTY_HSCH5_V 0x1FFFFFF\r
-#define LEDC_DUTY_HSCH5_S 0\r
-\r
-#define LEDC_HSCH6_CONF0_REG (DR_REG_LEDC_BASE + 0x0078)\r
-/* LEDC_IDLE_LV_HSCH6 : R/W ;bitpos:[3] ;default: 1'b0 ; */\r
-/*description: This bit is used to control the output value when high speed channel6 is off.*/\r
-#define LEDC_IDLE_LV_HSCH6 (BIT(3))\r
-#define LEDC_IDLE_LV_HSCH6_M (BIT(3))\r
-#define LEDC_IDLE_LV_HSCH6_V 0x1\r
-#define LEDC_IDLE_LV_HSCH6_S 3\r
-/* LEDC_SIG_OUT_EN_HSCH6 : R/W ;bitpos:[2] ;default: 1'b0 ; */\r
-/*description: This is the output enable control bit for high speed channel6*/\r
-#define LEDC_SIG_OUT_EN_HSCH6 (BIT(2))\r
-#define LEDC_SIG_OUT_EN_HSCH6_M (BIT(2))\r
-#define LEDC_SIG_OUT_EN_HSCH6_V 0x1\r
-#define LEDC_SIG_OUT_EN_HSCH6_S 2\r
-/* LEDC_TIMER_SEL_HSCH6 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */\r
-/*description: There are four high speed timers the two bits are used to select\r
- one of them for high speed channel6. 2'b00: seletc hstimer0. 2'b01: select hstimer1. 2'b10: select hstimer2. 2'b11: select hstimer3.*/\r
-#define LEDC_TIMER_SEL_HSCH6 0x00000003\r
-#define LEDC_TIMER_SEL_HSCH6_M ((LEDC_TIMER_SEL_HSCH6_V)<<(LEDC_TIMER_SEL_HSCH6_S))\r
-#define LEDC_TIMER_SEL_HSCH6_V 0x3\r
-#define LEDC_TIMER_SEL_HSCH6_S 0\r
-\r
-#define LEDC_HSCH6_HPOINT_REG (DR_REG_LEDC_BASE + 0x007C)\r
-/* LEDC_HPOINT_HSCH6 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */\r
-/*description: The output value changes to high when htimerx(x=[0 3]) selected\r
- by high speed channel6 has reached reg_hpoint_hsch6[19:0]*/\r
-#define LEDC_HPOINT_HSCH6 0x000FFFFF\r
-#define LEDC_HPOINT_HSCH6_M ((LEDC_HPOINT_HSCH6_V)<<(LEDC_HPOINT_HSCH6_S))\r
-#define LEDC_HPOINT_HSCH6_V 0xFFFFF\r
-#define LEDC_HPOINT_HSCH6_S 0\r
-\r
-#define LEDC_HSCH6_DUTY_REG (DR_REG_LEDC_BASE + 0x0080)\r
-/* LEDC_DUTY_HSCH6 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */\r
-/*description: The register is used to control output duty. When hstimerx(x=[0\r
- 3]) choosed by high speed channel6 has reached reg_lpoint_hsch6 the output signal changes to low. reg_lpoint_hsch6=(reg_hpoint_hsch6[19:0]+reg_duty_hsch6[24:4]) (1) reg_lpoint_hsch6=(reg_hpoint_hsch6[19:0]+reg_duty_hsch6[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/\r
-#define LEDC_DUTY_HSCH6 0x01FFFFFF\r
-#define LEDC_DUTY_HSCH6_M ((LEDC_DUTY_HSCH6_V)<<(LEDC_DUTY_HSCH6_S))\r
-#define LEDC_DUTY_HSCH6_V 0x1FFFFFF\r
-#define LEDC_DUTY_HSCH6_S 0\r
-\r
-#define LEDC_HSCH6_CONF1_REG (DR_REG_LEDC_BASE + 0x0084)\r
-/* LEDC_DUTY_START_HSCH6 : R/W ;bitpos:[31] ;default: 1'b0 ; */\r
-/*description: When reg_duty_num_hsch1 reg_duty_cycle_hsch1 and reg_duty_scale_hsch1\r
- has been configured. these register won't take effect until set reg_duty_start_hsch1. this bit is automatically cleared by hardware.*/\r
-#define LEDC_DUTY_START_HSCH6 (BIT(31))\r
-#define LEDC_DUTY_START_HSCH6_M (BIT(31))\r
-#define LEDC_DUTY_START_HSCH6_V 0x1\r
-#define LEDC_DUTY_START_HSCH6_S 31\r
-/* LEDC_DUTY_INC_HSCH6 : R/W ;bitpos:[30] ;default: 1'b1 ; */\r
-/*description: This register is used to increase the duty of output signal or\r
- decrease the duty of output signal for high speed channel6.*/\r
-#define LEDC_DUTY_INC_HSCH6 (BIT(30))\r
-#define LEDC_DUTY_INC_HSCH6_M (BIT(30))\r
-#define LEDC_DUTY_INC_HSCH6_V 0x1\r
-#define LEDC_DUTY_INC_HSCH6_S 30\r
-/* LEDC_DUTY_NUM_HSCH6 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */\r
-/*description: This register is used to control the num of increased or decreased\r
- times for high speed channel6.*/\r
-#define LEDC_DUTY_NUM_HSCH6 0x000003FF\r
-#define LEDC_DUTY_NUM_HSCH6_M ((LEDC_DUTY_NUM_HSCH6_V)<<(LEDC_DUTY_NUM_HSCH6_S))\r
-#define LEDC_DUTY_NUM_HSCH6_V 0x3FF\r
-#define LEDC_DUTY_NUM_HSCH6_S 20\r
-/* LEDC_DUTY_CYCLE_HSCH6 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */\r
-/*description: This register is used to increase or decrease the duty every\r
- reg_duty_cycle_hsch6 cycles for high speed channel6.*/\r
-#define LEDC_DUTY_CYCLE_HSCH6 0x000003FF\r
-#define LEDC_DUTY_CYCLE_HSCH6_M ((LEDC_DUTY_CYCLE_HSCH6_V)<<(LEDC_DUTY_CYCLE_HSCH6_S))\r
-#define LEDC_DUTY_CYCLE_HSCH6_V 0x3FF\r
-#define LEDC_DUTY_CYCLE_HSCH6_S 10\r
-/* LEDC_DUTY_SCALE_HSCH6 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */\r
-/*description: This register controls the increase or decrease step scale for\r
- high speed channel6.*/\r
-#define LEDC_DUTY_SCALE_HSCH6 0x000003FF\r
-#define LEDC_DUTY_SCALE_HSCH6_M ((LEDC_DUTY_SCALE_HSCH6_V)<<(LEDC_DUTY_SCALE_HSCH6_S))\r
-#define LEDC_DUTY_SCALE_HSCH6_V 0x3FF\r
-#define LEDC_DUTY_SCALE_HSCH6_S 0\r
-\r
-#define LEDC_HSCH6_DUTY_R_REG (DR_REG_LEDC_BASE + 0x0088)\r
-/* LEDC_DUTY_HSCH6 : RO ;bitpos:[24:0] ;default: 25'h0 ; */\r
-/*description: This register represents the current duty of the output signal\r
- for high speed channel6.*/\r
-#define LEDC_DUTY_HSCH6 0x01FFFFFF\r
-#define LEDC_DUTY_HSCH6_M ((LEDC_DUTY_HSCH6_V)<<(LEDC_DUTY_HSCH6_S))\r
-#define LEDC_DUTY_HSCH6_V 0x1FFFFFF\r
-#define LEDC_DUTY_HSCH6_S 0\r
-\r
-#define LEDC_HSCH7_CONF0_REG (DR_REG_LEDC_BASE + 0x008C)\r
-/* LEDC_IDLE_LV_HSCH7 : R/W ;bitpos:[3] ;default: 1'b0 ; */\r
-/*description: This bit is used to control the output value when high speed channel7 is off.*/\r
-#define LEDC_IDLE_LV_HSCH7 (BIT(3))\r
-#define LEDC_IDLE_LV_HSCH7_M (BIT(3))\r
-#define LEDC_IDLE_LV_HSCH7_V 0x1\r
-#define LEDC_IDLE_LV_HSCH7_S 3\r
-/* LEDC_SIG_OUT_EN_HSCH7 : R/W ;bitpos:[2] ;default: 1'b0 ; */\r
-/*description: This is the output enable control bit for high speed channel7.*/\r
-#define LEDC_SIG_OUT_EN_HSCH7 (BIT(2))\r
-#define LEDC_SIG_OUT_EN_HSCH7_M (BIT(2))\r
-#define LEDC_SIG_OUT_EN_HSCH7_V 0x1\r
-#define LEDC_SIG_OUT_EN_HSCH7_S 2\r
-/* LEDC_TIMER_SEL_HSCH7 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */\r
-/*description: There are four high speed timers the two bits are used to select\r
- one of them for high speed channel7. 2'b00: seletc hstimer0. 2'b01: select hstimer1. 2'b10: select hstimer2. 2'b11: select hstimer3.*/\r
-#define LEDC_TIMER_SEL_HSCH7 0x00000003\r
-#define LEDC_TIMER_SEL_HSCH7_M ((LEDC_TIMER_SEL_HSCH7_V)<<(LEDC_TIMER_SEL_HSCH7_S))\r
-#define LEDC_TIMER_SEL_HSCH7_V 0x3\r
-#define LEDC_TIMER_SEL_HSCH7_S 0\r
-\r
-#define LEDC_HSCH7_HPOINT_REG (DR_REG_LEDC_BASE + 0x0090)\r
-/* LEDC_HPOINT_HSCH7 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */\r
-/*description: The output value changes to high when htimerx(x=[0 3]) selected\r
- by high speed channel7 has reached reg_hpoint_hsch7[19:0]*/\r
-#define LEDC_HPOINT_HSCH7 0x000FFFFF\r
-#define LEDC_HPOINT_HSCH7_M ((LEDC_HPOINT_HSCH7_V)<<(LEDC_HPOINT_HSCH7_S))\r
-#define LEDC_HPOINT_HSCH7_V 0xFFFFF\r
-#define LEDC_HPOINT_HSCH7_S 0\r
-\r
-#define LEDC_HSCH7_DUTY_REG (DR_REG_LEDC_BASE + 0x0094)\r
-/* LEDC_DUTY_HSCH7 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */\r
-/*description: The register is used to control output duty. When hstimerx(x=[0\r
- 3]) choosed by high speed channel7 has reached reg_lpoint_hsch7 the output signal changes to low. reg_lpoint_hsch7=(reg_hpoint_hsch7[19:0]+reg_duty_hsch7[24:4]) (1) reg_lpoint_hsch7=(reg_hpoint_hsch7[19:0]+reg_duty_hsch7[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/\r
-#define LEDC_DUTY_HSCH7 0x01FFFFFF\r
-#define LEDC_DUTY_HSCH7_M ((LEDC_DUTY_HSCH7_V)<<(LEDC_DUTY_HSCH7_S))\r
-#define LEDC_DUTY_HSCH7_V 0x1FFFFFF\r
-#define LEDC_DUTY_HSCH7_S 0\r
-\r
-#define LEDC_HSCH7_CONF1_REG (DR_REG_LEDC_BASE + 0x0098)\r
-/* LEDC_DUTY_START_HSCH7 : R/W ;bitpos:[31] ;default: 1'b0 ; */\r
-/*description: When reg_duty_num_hsch1 reg_duty_cycle_hsch1 and reg_duty_scale_hsch1\r
- has been configured. these register won't take effect until set reg_duty_start_hsch1. this bit is automatically cleared by hardware.*/\r
-#define LEDC_DUTY_START_HSCH7 (BIT(31))\r
-#define LEDC_DUTY_START_HSCH7_M (BIT(31))\r
-#define LEDC_DUTY_START_HSCH7_V 0x1\r
-#define LEDC_DUTY_START_HSCH7_S 31\r
-/* LEDC_DUTY_INC_HSCH7 : R/W ;bitpos:[30] ;default: 1'b1 ; */\r
-/*description: This register is used to increase the duty of output signal or\r
- decrease the duty of output signal for high speed channel6.*/\r
-#define LEDC_DUTY_INC_HSCH7 (BIT(30))\r
-#define LEDC_DUTY_INC_HSCH7_M (BIT(30))\r
-#define LEDC_DUTY_INC_HSCH7_V 0x1\r
-#define LEDC_DUTY_INC_HSCH7_S 30\r
-/* LEDC_DUTY_NUM_HSCH7 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */\r
-/*description: This register is used to control the num of increased or decreased\r
- times for high speed channel6.*/\r
-#define LEDC_DUTY_NUM_HSCH7 0x000003FF\r
-#define LEDC_DUTY_NUM_HSCH7_M ((LEDC_DUTY_NUM_HSCH7_V)<<(LEDC_DUTY_NUM_HSCH7_S))\r
-#define LEDC_DUTY_NUM_HSCH7_V 0x3FF\r
-#define LEDC_DUTY_NUM_HSCH7_S 20\r
-/* LEDC_DUTY_CYCLE_HSCH7 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */\r
-/*description: This register is used to increase or decrease the duty every\r
- reg_duty_cycle_hsch7 cycles for high speed channel7.*/\r
-#define LEDC_DUTY_CYCLE_HSCH7 0x000003FF\r
-#define LEDC_DUTY_CYCLE_HSCH7_M ((LEDC_DUTY_CYCLE_HSCH7_V)<<(LEDC_DUTY_CYCLE_HSCH7_S))\r
-#define LEDC_DUTY_CYCLE_HSCH7_V 0x3FF\r
-#define LEDC_DUTY_CYCLE_HSCH7_S 10\r
-/* LEDC_DUTY_SCALE_HSCH7 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */\r
-/*description: This register controls the increase or decrease step scale for\r
- high speed channel7.*/\r
-#define LEDC_DUTY_SCALE_HSCH7 0x000003FF\r
-#define LEDC_DUTY_SCALE_HSCH7_M ((LEDC_DUTY_SCALE_HSCH7_V)<<(LEDC_DUTY_SCALE_HSCH7_S))\r
-#define LEDC_DUTY_SCALE_HSCH7_V 0x3FF\r
-#define LEDC_DUTY_SCALE_HSCH7_S 0\r
-\r
-#define LEDC_HSCH7_DUTY_R_REG (DR_REG_LEDC_BASE + 0x009C)\r
-/* LEDC_DUTY_HSCH7 : RO ;bitpos:[24:0] ;default: 25'h0 ; */\r
-/*description: This register represents the current duty of the output signal\r
- for high speed channel7.*/\r
-#define LEDC_DUTY_HSCH7 0x01FFFFFF\r
-#define LEDC_DUTY_HSCH7_M ((LEDC_DUTY_HSCH7_V)<<(LEDC_DUTY_HSCH7_S))\r
-#define LEDC_DUTY_HSCH7_V 0x1FFFFFF\r
-#define LEDC_DUTY_HSCH7_S 0\r
-\r
-#define LEDC_LSCH0_CONF0_REG (DR_REG_LEDC_BASE + 0x00A0)\r
-/* LEDC_PARA_UP_LSCH0 : R/W ;bitpos:[4] ;default: 1'b0 ; */\r
-/*description: This bit is used to update register LEDC_LSCH0_HPOINT and LEDC_LSCH0_DUTY\r
- for low speed channel0.*/\r
-#define LEDC_PARA_UP_LSCH0 (BIT(4))\r
-#define LEDC_PARA_UP_LSCH0_M (BIT(4))\r
-#define LEDC_PARA_UP_LSCH0_V 0x1\r
-#define LEDC_PARA_UP_LSCH0_S 4\r
-/* LEDC_IDLE_LV_LSCH0 : R/W ;bitpos:[3] ;default: 1'b0 ; */\r
-/*description: This bit is used to control the output value when low speed channel0 is off.*/\r
-#define LEDC_IDLE_LV_LSCH0 (BIT(3))\r
-#define LEDC_IDLE_LV_LSCH0_M (BIT(3))\r
-#define LEDC_IDLE_LV_LSCH0_V 0x1\r
-#define LEDC_IDLE_LV_LSCH0_S 3\r
-/* LEDC_SIG_OUT_EN_LSCH0 : R/W ;bitpos:[2] ;default: 1'b0 ; */\r
-/*description: This is the output enable control bit for low speed channel0.*/\r
-#define LEDC_SIG_OUT_EN_LSCH0 (BIT(2))\r
-#define LEDC_SIG_OUT_EN_LSCH0_M (BIT(2))\r
-#define LEDC_SIG_OUT_EN_LSCH0_V 0x1\r
-#define LEDC_SIG_OUT_EN_LSCH0_S 2\r
-/* LEDC_TIMER_SEL_LSCH0 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */\r
-/*description: There are four low speed timers the two bits are used to select\r
- one of them for low speed channel0. 2'b00: seletc lstimer0. 2'b01: select lstimer1. 2'b10: select lstimer2. 2'b11: select lstimer3.*/\r
-#define LEDC_TIMER_SEL_LSCH0 0x00000003\r
-#define LEDC_TIMER_SEL_LSCH0_M ((LEDC_TIMER_SEL_LSCH0_V)<<(LEDC_TIMER_SEL_LSCH0_S))\r
-#define LEDC_TIMER_SEL_LSCH0_V 0x3\r
-#define LEDC_TIMER_SEL_LSCH0_S 0\r
-\r
-#define LEDC_LSCH0_HPOINT_REG (DR_REG_LEDC_BASE + 0x00A4)\r
-/* LEDC_HPOINT_LSCH0 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */\r
-/*description: The output value changes to high when lstimerx(x=[0 3]) selected\r
- by low speed channel0 has reached reg_hpoint_lsch0[19:0]*/\r
-#define LEDC_HPOINT_LSCH0 0x000FFFFF\r
-#define LEDC_HPOINT_LSCH0_M ((LEDC_HPOINT_LSCH0_V)<<(LEDC_HPOINT_LSCH0_S))\r
-#define LEDC_HPOINT_LSCH0_V 0xFFFFF\r
-#define LEDC_HPOINT_LSCH0_S 0\r
-\r
-#define LEDC_LSCH0_DUTY_REG (DR_REG_LEDC_BASE + 0x00A8)\r
-/* LEDC_DUTY_LSCH0 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */\r
-/*description: The register is used to control output duty. When lstimerx(x=[0\r
- 3]) choosed by low speed channel0 has reached reg_lpoint_lsch0 the output signal changes to low. reg_lpoint_lsch0=(reg_hpoint_lsch0[19:0]+reg_duty_lsch0[24:4]) (1) reg_lpoint_lsch0=(reg_hpoint_lsch0[19:0]+reg_duty_lsch0[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/\r
-#define LEDC_DUTY_LSCH0 0x01FFFFFF\r
-#define LEDC_DUTY_LSCH0_M ((LEDC_DUTY_LSCH0_V)<<(LEDC_DUTY_LSCH0_S))\r
-#define LEDC_DUTY_LSCH0_V 0x1FFFFFF\r
-#define LEDC_DUTY_LSCH0_S 0\r
-\r
-#define LEDC_LSCH0_CONF1_REG (DR_REG_LEDC_BASE + 0x00AC)\r
-/* LEDC_DUTY_START_LSCH0 : R/W ;bitpos:[31] ;default: 1'b0 ; */\r
-/*description: When reg_duty_num_hsch1 reg_duty_cycle_hsch1 and reg_duty_scale_hsch1\r
- has been configured. these register won't take effect until set reg_duty_start_hsch1. this bit is automatically cleared by hardware.*/\r
-#define LEDC_DUTY_START_LSCH0 (BIT(31))\r
-#define LEDC_DUTY_START_LSCH0_M (BIT(31))\r
-#define LEDC_DUTY_START_LSCH0_V 0x1\r
-#define LEDC_DUTY_START_LSCH0_S 31\r
-/* LEDC_DUTY_INC_LSCH0 : R/W ;bitpos:[30] ;default: 1'b1 ; */\r
-/*description: This register is used to increase the duty of output signal or\r
- decrease the duty of output signal for low speed channel6.*/\r
-#define LEDC_DUTY_INC_LSCH0 (BIT(30))\r
-#define LEDC_DUTY_INC_LSCH0_M (BIT(30))\r
-#define LEDC_DUTY_INC_LSCH0_V 0x1\r
-#define LEDC_DUTY_INC_LSCH0_S 30\r
-/* LEDC_DUTY_NUM_LSCH0 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */\r
-/*description: This register is used to control the num of increased or decreased\r
- times for low speed channel6.*/\r
-#define LEDC_DUTY_NUM_LSCH0 0x000003FF\r
-#define LEDC_DUTY_NUM_LSCH0_M ((LEDC_DUTY_NUM_LSCH0_V)<<(LEDC_DUTY_NUM_LSCH0_S))\r
-#define LEDC_DUTY_NUM_LSCH0_V 0x3FF\r
-#define LEDC_DUTY_NUM_LSCH0_S 20\r
-/* LEDC_DUTY_CYCLE_LSCH0 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */\r
-/*description: This register is used to increase or decrease the duty every\r
- reg_duty_cycle_lsch0 cycles for low speed channel0.*/\r
-#define LEDC_DUTY_CYCLE_LSCH0 0x000003FF\r
-#define LEDC_DUTY_CYCLE_LSCH0_M ((LEDC_DUTY_CYCLE_LSCH0_V)<<(LEDC_DUTY_CYCLE_LSCH0_S))\r
-#define LEDC_DUTY_CYCLE_LSCH0_V 0x3FF\r
-#define LEDC_DUTY_CYCLE_LSCH0_S 10\r
-/* LEDC_DUTY_SCALE_LSCH0 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */\r
-/*description: This register controls the increase or decrease step scale for\r
- low speed channel0.*/\r
-#define LEDC_DUTY_SCALE_LSCH0 0x000003FF\r
-#define LEDC_DUTY_SCALE_LSCH0_M ((LEDC_DUTY_SCALE_LSCH0_V)<<(LEDC_DUTY_SCALE_LSCH0_S))\r
-#define LEDC_DUTY_SCALE_LSCH0_V 0x3FF\r
-#define LEDC_DUTY_SCALE_LSCH0_S 0\r
-\r
-#define LEDC_LSCH0_DUTY_R_REG (DR_REG_LEDC_BASE + 0x00B0)\r
-/* LEDC_DUTY_LSCH0 : RO ;bitpos:[24:0] ;default: 25'h0 ; */\r
-/*description: This register represents the current duty of the output signal\r
- for low speed channel0.*/\r
-#define LEDC_DUTY_LSCH0 0x01FFFFFF\r
-#define LEDC_DUTY_LSCH0_M ((LEDC_DUTY_LSCH0_V)<<(LEDC_DUTY_LSCH0_S))\r
-#define LEDC_DUTY_LSCH0_V 0x1FFFFFF\r
-#define LEDC_DUTY_LSCH0_S 0\r
-\r
-#define LEDC_LSCH1_CONF0_REG (DR_REG_LEDC_BASE + 0x00B4)\r
-/* LEDC_PARA_UP_LSCH1 : R/W ;bitpos:[4] ;default: 1'b0 ; */\r
-/*description: This bit is used to update register LEDC_LSCH1_HPOINT and LEDC_LSCH1_DUTY\r
- for low speed channel1.*/\r
-#define LEDC_PARA_UP_LSCH1 (BIT(4))\r
-#define LEDC_PARA_UP_LSCH1_M (BIT(4))\r
-#define LEDC_PARA_UP_LSCH1_V 0x1\r
-#define LEDC_PARA_UP_LSCH1_S 4\r
-/* LEDC_IDLE_LV_LSCH1 : R/W ;bitpos:[3] ;default: 1'b0 ; */\r
-/*description: This bit is used to control the output value when low speed channel1 is off.*/\r
-#define LEDC_IDLE_LV_LSCH1 (BIT(3))\r
-#define LEDC_IDLE_LV_LSCH1_M (BIT(3))\r
-#define LEDC_IDLE_LV_LSCH1_V 0x1\r
-#define LEDC_IDLE_LV_LSCH1_S 3\r
-/* LEDC_SIG_OUT_EN_LSCH1 : R/W ;bitpos:[2] ;default: 1'b0 ; */\r
-/*description: This is the output enable control bit for low speed channel1.*/\r
-#define LEDC_SIG_OUT_EN_LSCH1 (BIT(2))\r
-#define LEDC_SIG_OUT_EN_LSCH1_M (BIT(2))\r
-#define LEDC_SIG_OUT_EN_LSCH1_V 0x1\r
-#define LEDC_SIG_OUT_EN_LSCH1_S 2\r
-/* LEDC_TIMER_SEL_LSCH1 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */\r
-/*description: There are four low speed timers the two bits are used to select\r
- one of them for low speed channel1. 2'b00: seletc lstimer0. 2'b01: select lstimer1. 2'b10: select lstimer2. 2'b11: select lstimer3.*/\r
-#define LEDC_TIMER_SEL_LSCH1 0x00000003\r
-#define LEDC_TIMER_SEL_LSCH1_M ((LEDC_TIMER_SEL_LSCH1_V)<<(LEDC_TIMER_SEL_LSCH1_S))\r
-#define LEDC_TIMER_SEL_LSCH1_V 0x3\r
-#define LEDC_TIMER_SEL_LSCH1_S 0\r
-\r
-#define LEDC_LSCH1_HPOINT_REG (DR_REG_LEDC_BASE + 0x00B8)\r
-/* LEDC_HPOINT_LSCH1 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */\r
-/*description: The output value changes to high when lstimerx(x=[0 3]) selected\r
- by low speed channel1 has reached reg_hpoint_lsch1[19:0]*/\r
-#define LEDC_HPOINT_LSCH1 0x000FFFFF\r
-#define LEDC_HPOINT_LSCH1_M ((LEDC_HPOINT_LSCH1_V)<<(LEDC_HPOINT_LSCH1_S))\r
-#define LEDC_HPOINT_LSCH1_V 0xFFFFF\r
-#define LEDC_HPOINT_LSCH1_S 0\r
-\r
-#define LEDC_LSCH1_DUTY_REG (DR_REG_LEDC_BASE + 0x00BC)\r
-/* LEDC_DUTY_LSCH1 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */\r
-/*description: The register is used to control output duty. When lstimerx(x=[0\r
- 3]) choosed by low speed channel1 has reached reg_lpoint_lsch1 the output signal changes to low. reg_lpoint_lsch1=(reg_hpoint_lsch1[19:0]+reg_duty_lsch1[24:4]) (1) reg_lpoint_lsch1=(reg_hpoint_lsch1[19:0]+reg_duty_lsch1[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/\r
-#define LEDC_DUTY_LSCH1 0x01FFFFFF\r
-#define LEDC_DUTY_LSCH1_M ((LEDC_DUTY_LSCH1_V)<<(LEDC_DUTY_LSCH1_S))\r
-#define LEDC_DUTY_LSCH1_V 0x1FFFFFF\r
-#define LEDC_DUTY_LSCH1_S 0\r
-\r
-#define LEDC_LSCH1_CONF1_REG (DR_REG_LEDC_BASE + 0x00C0)\r
-/* LEDC_DUTY_START_LSCH1 : R/W ;bitpos:[31] ;default: 1'b0 ; */\r
-/*description: When reg_duty_num_hsch1 reg_duty_cycle_hsch1 and reg_duty_scale_hsch1\r
- has been configured. these register won't take effect until set reg_duty_start_hsch1. this bit is automatically cleared by hardware.*/\r
-#define LEDC_DUTY_START_LSCH1 (BIT(31))\r
-#define LEDC_DUTY_START_LSCH1_M (BIT(31))\r
-#define LEDC_DUTY_START_LSCH1_V 0x1\r
-#define LEDC_DUTY_START_LSCH1_S 31\r
-/* LEDC_DUTY_INC_LSCH1 : R/W ;bitpos:[30] ;default: 1'b1 ; */\r
-/*description: This register is used to increase the duty of output signal or\r
- decrease the duty of output signal for low speed channel1.*/\r
-#define LEDC_DUTY_INC_LSCH1 (BIT(30))\r
-#define LEDC_DUTY_INC_LSCH1_M (BIT(30))\r
-#define LEDC_DUTY_INC_LSCH1_V 0x1\r
-#define LEDC_DUTY_INC_LSCH1_S 30\r
-/* LEDC_DUTY_NUM_LSCH1 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */\r
-/*description: This register is used to control the num of increased or decreased\r
- times for low speed channel1.*/\r
-#define LEDC_DUTY_NUM_LSCH1 0x000003FF\r
-#define LEDC_DUTY_NUM_LSCH1_M ((LEDC_DUTY_NUM_LSCH1_V)<<(LEDC_DUTY_NUM_LSCH1_S))\r
-#define LEDC_DUTY_NUM_LSCH1_V 0x3FF\r
-#define LEDC_DUTY_NUM_LSCH1_S 20\r
-/* LEDC_DUTY_CYCLE_LSCH1 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */\r
-/*description: This register is used to increase or decrease the duty every\r
- reg_duty_cycle_lsch1 cycles for low speed channel1.*/\r
-#define LEDC_DUTY_CYCLE_LSCH1 0x000003FF\r
-#define LEDC_DUTY_CYCLE_LSCH1_M ((LEDC_DUTY_CYCLE_LSCH1_V)<<(LEDC_DUTY_CYCLE_LSCH1_S))\r
-#define LEDC_DUTY_CYCLE_LSCH1_V 0x3FF\r
-#define LEDC_DUTY_CYCLE_LSCH1_S 10\r
-/* LEDC_DUTY_SCALE_LSCH1 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */\r
-/*description: This register controls the increase or decrease step scale for\r
- low speed channel1.*/\r
-#define LEDC_DUTY_SCALE_LSCH1 0x000003FF\r
-#define LEDC_DUTY_SCALE_LSCH1_M ((LEDC_DUTY_SCALE_LSCH1_V)<<(LEDC_DUTY_SCALE_LSCH1_S))\r
-#define LEDC_DUTY_SCALE_LSCH1_V 0x3FF\r
-#define LEDC_DUTY_SCALE_LSCH1_S 0\r
-\r
-#define LEDC_LSCH1_DUTY_R_REG (DR_REG_LEDC_BASE + 0x00C4)\r
-/* LEDC_DUTY_LSCH1 : RO ;bitpos:[24:0] ;default: 25'h0 ; */\r
-/*description: This register represents the current duty of the output signal\r
- for low speed channel1.*/\r
-#define LEDC_DUTY_LSCH1 0x01FFFFFF\r
-#define LEDC_DUTY_LSCH1_M ((LEDC_DUTY_LSCH1_V)<<(LEDC_DUTY_LSCH1_S))\r
-#define LEDC_DUTY_LSCH1_V 0x1FFFFFF\r
-#define LEDC_DUTY_LSCH1_S 0\r
-\r
-#define LEDC_LSCH2_CONF0_REG (DR_REG_LEDC_BASE + 0x00C8)\r
-/* LEDC_PARA_UP_LSCH2 : R/W ;bitpos:[4] ;default: 1'b0 ; */\r
-/*description: This bit is used to update register LEDC_LSCH2_HPOINT and LEDC_LSCH2_DUTY\r
- for low speed channel2.*/\r
-#define LEDC_PARA_UP_LSCH2 (BIT(4))\r
-#define LEDC_PARA_UP_LSCH2_M (BIT(4))\r
-#define LEDC_PARA_UP_LSCH2_V 0x1\r
-#define LEDC_PARA_UP_LSCH2_S 4\r
-/* LEDC_IDLE_LV_LSCH2 : R/W ;bitpos:[3] ;default: 1'b0 ; */\r
-/*description: This bit is used to control the output value when low speed channel2 is off.*/\r
-#define LEDC_IDLE_LV_LSCH2 (BIT(3))\r
-#define LEDC_IDLE_LV_LSCH2_M (BIT(3))\r
-#define LEDC_IDLE_LV_LSCH2_V 0x1\r
-#define LEDC_IDLE_LV_LSCH2_S 3\r
-/* LEDC_SIG_OUT_EN_LSCH2 : R/W ;bitpos:[2] ;default: 1'b0 ; */\r
-/*description: This is the output enable control bit for low speed channel2.*/\r
-#define LEDC_SIG_OUT_EN_LSCH2 (BIT(2))\r
-#define LEDC_SIG_OUT_EN_LSCH2_M (BIT(2))\r
-#define LEDC_SIG_OUT_EN_LSCH2_V 0x1\r
-#define LEDC_SIG_OUT_EN_LSCH2_S 2\r
-/* LEDC_TIMER_SEL_LSCH2 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */\r
-/*description: There are four low speed timers the two bits are used to select\r
- one of them for low speed channel2. 2'b00: seletc lstimer0. 2'b01: select lstimer1. 2'b10: select lstimer2. 2'b11: select lstimer3.*/\r
-#define LEDC_TIMER_SEL_LSCH2 0x00000003\r
-#define LEDC_TIMER_SEL_LSCH2_M ((LEDC_TIMER_SEL_LSCH2_V)<<(LEDC_TIMER_SEL_LSCH2_S))\r
-#define LEDC_TIMER_SEL_LSCH2_V 0x3\r
-#define LEDC_TIMER_SEL_LSCH2_S 0\r
-\r
-#define LEDC_LSCH2_HPOINT_REG (DR_REG_LEDC_BASE + 0x00CC)\r
-/* LEDC_HPOINT_LSCH2 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */\r
-/*description: The output value changes to high when lstimerx(x=[0 3]) selected\r
- by low speed channel2 has reached reg_hpoint_lsch2[19:0]*/\r
-#define LEDC_HPOINT_LSCH2 0x000FFFFF\r
-#define LEDC_HPOINT_LSCH2_M ((LEDC_HPOINT_LSCH2_V)<<(LEDC_HPOINT_LSCH2_S))\r
-#define LEDC_HPOINT_LSCH2_V 0xFFFFF\r
-#define LEDC_HPOINT_LSCH2_S 0\r
-\r
-#define LEDC_LSCH2_DUTY_REG (DR_REG_LEDC_BASE + 0x00D0)\r
-/* LEDC_DUTY_LSCH2 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */\r
-/*description: The register is used to control output duty. When lstimerx(x=[0\r
- 3]) choosed by low speed channel2 has reached reg_lpoint_lsch2 the output signal changes to low. reg_lpoint_lsch2=(reg_hpoint_lsch2[19:0]+reg_duty_lsch2[24:4]) (1) reg_lpoint_lsch2=(reg_hpoint_lsch2[19:0]+reg_duty_lsch2[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/\r
-#define LEDC_DUTY_LSCH2 0x01FFFFFF\r
-#define LEDC_DUTY_LSCH2_M ((LEDC_DUTY_LSCH2_V)<<(LEDC_DUTY_LSCH2_S))\r
-#define LEDC_DUTY_LSCH2_V 0x1FFFFFF\r
-#define LEDC_DUTY_LSCH2_S 0\r
-\r
-#define LEDC_LSCH2_CONF1_REG (DR_REG_LEDC_BASE + 0x00D4)\r
-/* LEDC_DUTY_START_LSCH2 : R/W ;bitpos:[31] ;default: 1'b0 ; */\r
-/*description: When reg_duty_num_hsch2 reg_duty_cycle_hsch2 and reg_duty_scale_hsch2\r
- has been configured. these register won't take effect until set reg_duty_start_hsch2. this bit is automatically cleared by hardware.*/\r
-#define LEDC_DUTY_START_LSCH2 (BIT(31))\r
-#define LEDC_DUTY_START_LSCH2_M (BIT(31))\r
-#define LEDC_DUTY_START_LSCH2_V 0x1\r
-#define LEDC_DUTY_START_LSCH2_S 31\r
-/* LEDC_DUTY_INC_LSCH2 : R/W ;bitpos:[30] ;default: 1'b1 ; */\r
-/*description: This register is used to increase the duty of output signal or\r
- decrease the duty of output signal for low speed channel2.*/\r
-#define LEDC_DUTY_INC_LSCH2 (BIT(30))\r
-#define LEDC_DUTY_INC_LSCH2_M (BIT(30))\r
-#define LEDC_DUTY_INC_LSCH2_V 0x1\r
-#define LEDC_DUTY_INC_LSCH2_S 30\r
-/* LEDC_DUTY_NUM_LSCH2 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */\r
-/*description: This register is used to control the num of increased or decreased\r
- times for low speed channel2.*/\r
-#define LEDC_DUTY_NUM_LSCH2 0x000003FF\r
-#define LEDC_DUTY_NUM_LSCH2_M ((LEDC_DUTY_NUM_LSCH2_V)<<(LEDC_DUTY_NUM_LSCH2_S))\r
-#define LEDC_DUTY_NUM_LSCH2_V 0x3FF\r
-#define LEDC_DUTY_NUM_LSCH2_S 20\r
-/* LEDC_DUTY_CYCLE_LSCH2 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */\r
-/*description: This register is used to increase or decrease the duty every\r
- reg_duty_cycle_lsch2 cycles for low speed channel2.*/\r
-#define LEDC_DUTY_CYCLE_LSCH2 0x000003FF\r
-#define LEDC_DUTY_CYCLE_LSCH2_M ((LEDC_DUTY_CYCLE_LSCH2_V)<<(LEDC_DUTY_CYCLE_LSCH2_S))\r
-#define LEDC_DUTY_CYCLE_LSCH2_V 0x3FF\r
-#define LEDC_DUTY_CYCLE_LSCH2_S 10\r
-/* LEDC_DUTY_SCALE_LSCH2 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */\r
-/*description: This register controls the increase or decrease step scale for\r
- low speed channel2.*/\r
-#define LEDC_DUTY_SCALE_LSCH2 0x000003FF\r
-#define LEDC_DUTY_SCALE_LSCH2_M ((LEDC_DUTY_SCALE_LSCH2_V)<<(LEDC_DUTY_SCALE_LSCH2_S))\r
-#define LEDC_DUTY_SCALE_LSCH2_V 0x3FF\r
-#define LEDC_DUTY_SCALE_LSCH2_S 0\r
-\r
-#define LEDC_LSCH2_DUTY_R_REG (DR_REG_LEDC_BASE + 0x00D8)\r
-/* LEDC_DUTY_LSCH2 : RO ;bitpos:[24:0] ;default: 25'h0 ; */\r
-/*description: This register represents the current duty of the output signal\r
- for low speed channel2.*/\r
-#define LEDC_DUTY_LSCH2 0x01FFFFFF\r
-#define LEDC_DUTY_LSCH2_M ((LEDC_DUTY_LSCH2_V)<<(LEDC_DUTY_LSCH2_S))\r
-#define LEDC_DUTY_LSCH2_V 0x1FFFFFF\r
-#define LEDC_DUTY_LSCH2_S 0\r
-\r
-#define LEDC_LSCH3_CONF0_REG (DR_REG_LEDC_BASE + 0x00DC)\r
-/* LEDC_PARA_UP_LSCH3 : R/W ;bitpos:[4] ;default: 1'b0 ; */\r
-/*description: This bit is used to update register LEDC_LSCH3_HPOINT and LEDC_LSCH3_DUTY\r
- for low speed channel3.*/\r
-#define LEDC_PARA_UP_LSCH3 (BIT(4))\r
-#define LEDC_PARA_UP_LSCH3_M (BIT(4))\r
-#define LEDC_PARA_UP_LSCH3_V 0x1\r
-#define LEDC_PARA_UP_LSCH3_S 4\r
-/* LEDC_IDLE_LV_LSCH3 : R/W ;bitpos:[3] ;default: 1'b0 ; */\r
-/*description: This bit is used to control the output value when low speed channel3 is off.*/\r
-#define LEDC_IDLE_LV_LSCH3 (BIT(3))\r
-#define LEDC_IDLE_LV_LSCH3_M (BIT(3))\r
-#define LEDC_IDLE_LV_LSCH3_V 0x1\r
-#define LEDC_IDLE_LV_LSCH3_S 3\r
-/* LEDC_SIG_OUT_EN_LSCH3 : R/W ;bitpos:[2] ;default: 1'b0 ; */\r
-/*description: This is the output enable control bit for low speed channel3.*/\r
-#define LEDC_SIG_OUT_EN_LSCH3 (BIT(2))\r
-#define LEDC_SIG_OUT_EN_LSCH3_M (BIT(2))\r
-#define LEDC_SIG_OUT_EN_LSCH3_V 0x1\r
-#define LEDC_SIG_OUT_EN_LSCH3_S 2\r
-/* LEDC_TIMER_SEL_LSCH3 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */\r
-/*description: There are four low speed timers the two bits are used to select\r
- one of them for low speed channel3. 2'b00: seletc lstimer0. 2'b01: select lstimer1. 2'b10: select lstimer2. 2'b11: select lstimer3.*/\r
-#define LEDC_TIMER_SEL_LSCH3 0x00000003\r
-#define LEDC_TIMER_SEL_LSCH3_M ((LEDC_TIMER_SEL_LSCH3_V)<<(LEDC_TIMER_SEL_LSCH3_S))\r
-#define LEDC_TIMER_SEL_LSCH3_V 0x3\r
-#define LEDC_TIMER_SEL_LSCH3_S 0\r
-\r
-#define LEDC_LSCH3_HPOINT_REG (DR_REG_LEDC_BASE + 0x00E0)\r
-/* LEDC_HPOINT_LSCH3 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */\r
-/*description: The output value changes to high when lstimerx(x=[0 3]) selected\r
- by low speed channel3 has reached reg_hpoint_lsch3[19:0]*/\r
-#define LEDC_HPOINT_LSCH3 0x000FFFFF\r
-#define LEDC_HPOINT_LSCH3_M ((LEDC_HPOINT_LSCH3_V)<<(LEDC_HPOINT_LSCH3_S))\r
-#define LEDC_HPOINT_LSCH3_V 0xFFFFF\r
-#define LEDC_HPOINT_LSCH3_S 0\r
-\r
-#define LEDC_LSCH3_DUTY_REG (DR_REG_LEDC_BASE + 0x00E4)\r
-/* LEDC_DUTY_LSCH3 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */\r
-/*description: The register is used to control output duty. When lstimerx(x=[0\r
- 3]) choosed by low speed channel3 has reached reg_lpoint_lsch3 the output signal changes to low. reg_lpoint_lsch3=(reg_hpoint_lsch3[19:0]+reg_duty_lsch3[24:4]) (1) reg_lpoint_lsch3=(reg_hpoint_lsch3[19:0]+reg_duty_lsch3[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/\r
-#define LEDC_DUTY_LSCH3 0x01FFFFFF\r
-#define LEDC_DUTY_LSCH3_M ((LEDC_DUTY_LSCH3_V)<<(LEDC_DUTY_LSCH3_S))\r
-#define LEDC_DUTY_LSCH3_V 0x1FFFFFF\r
-#define LEDC_DUTY_LSCH3_S 0\r
-\r
-#define LEDC_LSCH3_CONF1_REG (DR_REG_LEDC_BASE + 0x00E8)\r
-/* LEDC_DUTY_START_LSCH3 : R/W ;bitpos:[31] ;default: 1'b0 ; */\r
-/*description: When reg_duty_num_hsch3 reg_duty_cycle_hsch3 and reg_duty_scale_hsch3\r
- has been configured. these register won't take effect until set reg_duty_start_hsch3. this bit is automatically cleared by hardware.*/\r
-#define LEDC_DUTY_START_LSCH3 (BIT(31))\r
-#define LEDC_DUTY_START_LSCH3_M (BIT(31))\r
-#define LEDC_DUTY_START_LSCH3_V 0x1\r
-#define LEDC_DUTY_START_LSCH3_S 31\r
-/* LEDC_DUTY_INC_LSCH3 : R/W ;bitpos:[30] ;default: 1'b1 ; */\r
-/*description: This register is used to increase the duty of output signal or\r
- decrease the duty of output signal for low speed channel3.*/\r
-#define LEDC_DUTY_INC_LSCH3 (BIT(30))\r
-#define LEDC_DUTY_INC_LSCH3_M (BIT(30))\r
-#define LEDC_DUTY_INC_LSCH3_V 0x1\r
-#define LEDC_DUTY_INC_LSCH3_S 30\r
-/* LEDC_DUTY_NUM_LSCH3 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */\r
-/*description: This register is used to control the num of increased or decreased\r
- times for low speed channel3.*/\r
-#define LEDC_DUTY_NUM_LSCH3 0x000003FF\r
-#define LEDC_DUTY_NUM_LSCH3_M ((LEDC_DUTY_NUM_LSCH3_V)<<(LEDC_DUTY_NUM_LSCH3_S))\r
-#define LEDC_DUTY_NUM_LSCH3_V 0x3FF\r
-#define LEDC_DUTY_NUM_LSCH3_S 20\r
-/* LEDC_DUTY_CYCLE_LSCH3 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */\r
-/*description: This register is used to increase or decrease the duty every\r
- reg_duty_cycle_lsch3 cycles for low speed channel3.*/\r
-#define LEDC_DUTY_CYCLE_LSCH3 0x000003FF\r
-#define LEDC_DUTY_CYCLE_LSCH3_M ((LEDC_DUTY_CYCLE_LSCH3_V)<<(LEDC_DUTY_CYCLE_LSCH3_S))\r
-#define LEDC_DUTY_CYCLE_LSCH3_V 0x3FF\r
-#define LEDC_DUTY_CYCLE_LSCH3_S 10\r
-/* LEDC_DUTY_SCALE_LSCH3 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */\r
-/*description: This register controls the increase or decrease step scale for\r
- low speed channel3.*/\r
-#define LEDC_DUTY_SCALE_LSCH3 0x000003FF\r
-#define LEDC_DUTY_SCALE_LSCH3_M ((LEDC_DUTY_SCALE_LSCH3_V)<<(LEDC_DUTY_SCALE_LSCH3_S))\r
-#define LEDC_DUTY_SCALE_LSCH3_V 0x3FF\r
-#define LEDC_DUTY_SCALE_LSCH3_S 0\r
-\r
-#define LEDC_LSCH3_DUTY_R_REG (DR_REG_LEDC_BASE + 0x00EC)\r
-/* LEDC_DUTY_LSCH3 : RO ;bitpos:[24:0] ;default: 25'h0 ; */\r
-/*description: This register represents the current duty of the output signal\r
- for low speed channel3.*/\r
-#define LEDC_DUTY_LSCH3 0x01FFFFFF\r
-#define LEDC_DUTY_LSCH3_M ((LEDC_DUTY_LSCH3_V)<<(LEDC_DUTY_LSCH3_S))\r
-#define LEDC_DUTY_LSCH3_V 0x1FFFFFF\r
-#define LEDC_DUTY_LSCH3_S 0\r
-\r
-#define LEDC_LSCH4_CONF0_REG (DR_REG_LEDC_BASE + 0x00F0)\r
-/* LEDC_PARA_UP_LSCH4 : R/W ;bitpos:[4] ;default: 1'b0 ; */\r
-/*description: This bit is used to update register LEDC_LSCH4_HPOINT and LEDC_LSCH4_DUTY\r
- for low speed channel4.*/\r
-#define LEDC_PARA_UP_LSCH4 (BIT(4))\r
-#define LEDC_PARA_UP_LSCH4_M (BIT(4))\r
-#define LEDC_PARA_UP_LSCH4_V 0x1\r
-#define LEDC_PARA_UP_LSCH4_S 4\r
-/* LEDC_IDLE_LV_LSCH4 : R/W ;bitpos:[3] ;default: 1'b0 ; */\r
-/*description: This bit is used to control the output value when low speed channel4 is off.*/\r
-#define LEDC_IDLE_LV_LSCH4 (BIT(3))\r
-#define LEDC_IDLE_LV_LSCH4_M (BIT(3))\r
-#define LEDC_IDLE_LV_LSCH4_V 0x1\r
-#define LEDC_IDLE_LV_LSCH4_S 3\r
-/* LEDC_SIG_OUT_EN_LSCH4 : R/W ;bitpos:[2] ;default: 1'b0 ; */\r
-/*description: This is the output enable control bit for low speed channel4.*/\r
-#define LEDC_SIG_OUT_EN_LSCH4 (BIT(2))\r
-#define LEDC_SIG_OUT_EN_LSCH4_M (BIT(2))\r
-#define LEDC_SIG_OUT_EN_LSCH4_V 0x1\r
-#define LEDC_SIG_OUT_EN_LSCH4_S 2\r
-/* LEDC_TIMER_SEL_LSCH4 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */\r
-/*description: There are four low speed timers the two bits are used to select\r
- one of them for low speed channel4. 2'b00: seletc lstimer0. 2'b01: select lstimer1. 2'b10: select lstimer2. 2'b11: select lstimer3.*/\r
-#define LEDC_TIMER_SEL_LSCH4 0x00000003\r
-#define LEDC_TIMER_SEL_LSCH4_M ((LEDC_TIMER_SEL_LSCH4_V)<<(LEDC_TIMER_SEL_LSCH4_S))\r
-#define LEDC_TIMER_SEL_LSCH4_V 0x3\r
-#define LEDC_TIMER_SEL_LSCH4_S 0\r
-\r
-#define LEDC_LSCH4_HPOINT_REG (DR_REG_LEDC_BASE + 0x00F4)\r
-/* LEDC_HPOINT_LSCH4 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */\r
-/*description: The output value changes to high when lstimerx(x=[0 3]) selected\r
- by low speed channel4 has reached reg_hpoint_lsch4[19:0]*/\r
-#define LEDC_HPOINT_LSCH4 0x000FFFFF\r
-#define LEDC_HPOINT_LSCH4_M ((LEDC_HPOINT_LSCH4_V)<<(LEDC_HPOINT_LSCH4_S))\r
-#define LEDC_HPOINT_LSCH4_V 0xFFFFF\r
-#define LEDC_HPOINT_LSCH4_S 0\r
-\r
-#define LEDC_LSCH4_DUTY_REG (DR_REG_LEDC_BASE + 0x00F8)\r
-/* LEDC_DUTY_LSCH4 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */\r
-/*description: The register is used to control output duty. When lstimerx(x=[0\r
- 3]) choosed by low speed channel4 has reached reg_lpoint_lsch4 the output signal changes to low. reg_lpoint_lsch4=(reg_hpoint_lsch4[19:0]+reg_duty_lsch4[24:4]) (1) reg_lpoint_lsch4=(reg_hpoint_lsch4[19:0]+reg_duty_lsch4[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/\r
-#define LEDC_DUTY_LSCH4 0x01FFFFFF\r
-#define LEDC_DUTY_LSCH4_M ((LEDC_DUTY_LSCH4_V)<<(LEDC_DUTY_LSCH4_S))\r
-#define LEDC_DUTY_LSCH4_V 0x1FFFFFF\r
-#define LEDC_DUTY_LSCH4_S 0\r
-\r
-#define LEDC_LSCH4_CONF1_REG (DR_REG_LEDC_BASE + 0x00FC)\r
-/* LEDC_DUTY_START_LSCH4 : R/W ;bitpos:[31] ;default: 1'b0 ; */\r
-/*description: When reg_duty_num_hsch4 reg_duty_cycle_hsch4 and reg_duty_scale_hsch4\r
- has been configured. these register won't take effect until set reg_duty_start_hsch4. this bit is automatically cleared by hardware.*/\r
-#define LEDC_DUTY_START_LSCH4 (BIT(31))\r
-#define LEDC_DUTY_START_LSCH4_M (BIT(31))\r
-#define LEDC_DUTY_START_LSCH4_V 0x1\r
-#define LEDC_DUTY_START_LSCH4_S 31\r
-/* LEDC_DUTY_INC_LSCH4 : R/W ;bitpos:[30] ;default: 1'b1 ; */\r
-/*description: This register is used to increase the duty of output signal or\r
- decrease the duty of output signal for low speed channel4.*/\r
-#define LEDC_DUTY_INC_LSCH4 (BIT(30))\r
-#define LEDC_DUTY_INC_LSCH4_M (BIT(30))\r
-#define LEDC_DUTY_INC_LSCH4_V 0x1\r
-#define LEDC_DUTY_INC_LSCH4_S 30\r
-/* LEDC_DUTY_NUM_LSCH4 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */\r
-/*description: This register is used to control the num of increased or decreased\r
- times for low speed channel4.*/\r
-#define LEDC_DUTY_NUM_LSCH4 0x000003FF\r
-#define LEDC_DUTY_NUM_LSCH4_M ((LEDC_DUTY_NUM_LSCH4_V)<<(LEDC_DUTY_NUM_LSCH4_S))\r
-#define LEDC_DUTY_NUM_LSCH4_V 0x3FF\r
-#define LEDC_DUTY_NUM_LSCH4_S 20\r
-/* LEDC_DUTY_CYCLE_LSCH4 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */\r
-/*description: This register is used to increase or decrease the duty every\r
- reg_duty_cycle_lsch4 cycles for low speed channel4.*/\r
-#define LEDC_DUTY_CYCLE_LSCH4 0x000003FF\r
-#define LEDC_DUTY_CYCLE_LSCH4_M ((LEDC_DUTY_CYCLE_LSCH4_V)<<(LEDC_DUTY_CYCLE_LSCH4_S))\r
-#define LEDC_DUTY_CYCLE_LSCH4_V 0x3FF\r
-#define LEDC_DUTY_CYCLE_LSCH4_S 10\r
-/* LEDC_DUTY_SCALE_LSCH4 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */\r
-/*description: This register controls the increase or decrease step scale for\r
- low speed channel4.*/\r
-#define LEDC_DUTY_SCALE_LSCH4 0x000003FF\r
-#define LEDC_DUTY_SCALE_LSCH4_M ((LEDC_DUTY_SCALE_LSCH4_V)<<(LEDC_DUTY_SCALE_LSCH4_S))\r
-#define LEDC_DUTY_SCALE_LSCH4_V 0x3FF\r
-#define LEDC_DUTY_SCALE_LSCH4_S 0\r
-\r
-#define LEDC_LSCH4_DUTY_R_REG (DR_REG_LEDC_BASE + 0x0100)\r
-/* LEDC_DUTY_LSCH4 : RO ;bitpos:[24:0] ;default: 25'h0 ; */\r
-/*description: This register represents the current duty of the output signal\r
- for low speed channel4.*/\r
-#define LEDC_DUTY_LSCH4 0x01FFFFFF\r
-#define LEDC_DUTY_LSCH4_M ((LEDC_DUTY_LSCH4_V)<<(LEDC_DUTY_LSCH4_S))\r
-#define LEDC_DUTY_LSCH4_V 0x1FFFFFF\r
-#define LEDC_DUTY_LSCH4_S 0\r
-\r
-#define LEDC_LSCH5_CONF0_REG (DR_REG_LEDC_BASE + 0x0104)\r
-/* LEDC_PARA_UP_LSCH5 : R/W ;bitpos:[4] ;default: 1'b0 ; */\r
-/*description: This bit is used to update register LEDC_LSCH5_HPOINT and LEDC_LSCH5_DUTY\r
- for low speed channel5.*/\r
-#define LEDC_PARA_UP_LSCH5 (BIT(4))\r
-#define LEDC_PARA_UP_LSCH5_M (BIT(4))\r
-#define LEDC_PARA_UP_LSCH5_V 0x1\r
-#define LEDC_PARA_UP_LSCH5_S 4\r
-/* LEDC_IDLE_LV_LSCH5 : R/W ;bitpos:[3] ;default: 1'b0 ; */\r
-/*description: This bit is used to control the output value when low speed channel5 is off.*/\r
-#define LEDC_IDLE_LV_LSCH5 (BIT(3))\r
-#define LEDC_IDLE_LV_LSCH5_M (BIT(3))\r
-#define LEDC_IDLE_LV_LSCH5_V 0x1\r
-#define LEDC_IDLE_LV_LSCH5_S 3\r
-/* LEDC_SIG_OUT_EN_LSCH5 : R/W ;bitpos:[2] ;default: 1'b0 ; */\r
-/*description: This is the output enable control bit for low speed channel5.*/\r
-#define LEDC_SIG_OUT_EN_LSCH5 (BIT(2))\r
-#define LEDC_SIG_OUT_EN_LSCH5_M (BIT(2))\r
-#define LEDC_SIG_OUT_EN_LSCH5_V 0x1\r
-#define LEDC_SIG_OUT_EN_LSCH5_S 2\r
-/* LEDC_TIMER_SEL_LSCH5 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */\r
-/*description: There are four low speed timers the two bits are used to select\r
- one of them for low speed channel5. 2'b00: seletc lstimer0. 2'b01: select lstimer1. 2'b10: select lstimer2. 2'b11: select lstimer3.*/\r
-#define LEDC_TIMER_SEL_LSCH5 0x00000003\r
-#define LEDC_TIMER_SEL_LSCH5_M ((LEDC_TIMER_SEL_LSCH5_V)<<(LEDC_TIMER_SEL_LSCH5_S))\r
-#define LEDC_TIMER_SEL_LSCH5_V 0x3\r
-#define LEDC_TIMER_SEL_LSCH5_S 0\r
-\r
-#define LEDC_LSCH5_HPOINT_REG (DR_REG_LEDC_BASE + 0x0108)\r
-/* LEDC_HPOINT_LSCH5 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */\r
-/*description: The output value changes to high when lstimerx(x=[0 3]) selected\r
- by low speed channel5 has reached reg_hpoint_lsch5[19:0]*/\r
-#define LEDC_HPOINT_LSCH5 0x000FFFFF\r
-#define LEDC_HPOINT_LSCH5_M ((LEDC_HPOINT_LSCH5_V)<<(LEDC_HPOINT_LSCH5_S))\r
-#define LEDC_HPOINT_LSCH5_V 0xFFFFF\r
-#define LEDC_HPOINT_LSCH5_S 0\r
-\r
-#define LEDC_LSCH5_DUTY_REG (DR_REG_LEDC_BASE + 0x010C)\r
-/* LEDC_DUTY_LSCH5 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */\r
-/*description: The register is used to control output duty. When lstimerx(x=[0\r
- 3]) choosed by low speed channel5 has reached reg_lpoint_lsch5 the output signal changes to low. reg_lpoint_lsch5=(reg_hpoint_lsch5[19:0]+reg_duty_lsch5[24:4]) (1) reg_lpoint_lsch5=(reg_hpoint_lsch5[19:0]+reg_duty_lsch5[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/\r
-#define LEDC_DUTY_LSCH5 0x01FFFFFF\r
-#define LEDC_DUTY_LSCH5_M ((LEDC_DUTY_LSCH5_V)<<(LEDC_DUTY_LSCH5_S))\r
-#define LEDC_DUTY_LSCH5_V 0x1FFFFFF\r
-#define LEDC_DUTY_LSCH5_S 0\r
-\r
-#define LEDC_LSCH5_CONF1_REG (DR_REG_LEDC_BASE + 0x0110)\r
-/* LEDC_DUTY_START_LSCH5 : R/W ;bitpos:[31] ;default: 1'b0 ; */\r
-/*description: When reg_duty_num_hsch4 reg_duty_cycle_hsch4 and reg_duty_scale_hsch4\r
- has been configured. these register won't take effect until set reg_duty_start_hsch4. this bit is automatically cleared by hardware.*/\r
-#define LEDC_DUTY_START_LSCH5 (BIT(31))\r
-#define LEDC_DUTY_START_LSCH5_M (BIT(31))\r
-#define LEDC_DUTY_START_LSCH5_V 0x1\r
-#define LEDC_DUTY_START_LSCH5_S 31\r
-/* LEDC_DUTY_INC_LSCH5 : R/W ;bitpos:[30] ;default: 1'b1 ; */\r
-/*description: This register is used to increase the duty of output signal or\r
- decrease the duty of output signal for low speed channel5.*/\r
-#define LEDC_DUTY_INC_LSCH5 (BIT(30))\r
-#define LEDC_DUTY_INC_LSCH5_M (BIT(30))\r
-#define LEDC_DUTY_INC_LSCH5_V 0x1\r
-#define LEDC_DUTY_INC_LSCH5_S 30\r
-/* LEDC_DUTY_NUM_LSCH5 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */\r
-/*description: This register is used to control the num of increased or decreased\r
- times for low speed channel5.*/\r
-#define LEDC_DUTY_NUM_LSCH5 0x000003FF\r
-#define LEDC_DUTY_NUM_LSCH5_M ((LEDC_DUTY_NUM_LSCH5_V)<<(LEDC_DUTY_NUM_LSCH5_S))\r
-#define LEDC_DUTY_NUM_LSCH5_V 0x3FF\r
-#define LEDC_DUTY_NUM_LSCH5_S 20\r
-/* LEDC_DUTY_CYCLE_LSCH5 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */\r
-/*description: This register is used to increase or decrease the duty every\r
- reg_duty_cycle_lsch5 cycles for low speed channel4.*/\r
-#define LEDC_DUTY_CYCLE_LSCH5 0x000003FF\r
-#define LEDC_DUTY_CYCLE_LSCH5_M ((LEDC_DUTY_CYCLE_LSCH5_V)<<(LEDC_DUTY_CYCLE_LSCH5_S))\r
-#define LEDC_DUTY_CYCLE_LSCH5_V 0x3FF\r
-#define LEDC_DUTY_CYCLE_LSCH5_S 10\r
-/* LEDC_DUTY_SCALE_LSCH5 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */\r
-/*description: This register controls the increase or decrease step scale for\r
- low speed channel5.*/\r
-#define LEDC_DUTY_SCALE_LSCH5 0x000003FF\r
-#define LEDC_DUTY_SCALE_LSCH5_M ((LEDC_DUTY_SCALE_LSCH5_V)<<(LEDC_DUTY_SCALE_LSCH5_S))\r
-#define LEDC_DUTY_SCALE_LSCH5_V 0x3FF\r
-#define LEDC_DUTY_SCALE_LSCH5_S 0\r
-\r
-#define LEDC_LSCH5_DUTY_R_REG (DR_REG_LEDC_BASE + 0x0114)\r
-/* LEDC_DUTY_LSCH5 : RO ;bitpos:[24:0] ;default: 25'h0 ; */\r
-/*description: This register represents the current duty of the output signal\r
- for low speed channel5.*/\r
-#define LEDC_DUTY_LSCH5 0x01FFFFFF\r
-#define LEDC_DUTY_LSCH5_M ((LEDC_DUTY_LSCH5_V)<<(LEDC_DUTY_LSCH5_S))\r
-#define LEDC_DUTY_LSCH5_V 0x1FFFFFF\r
-#define LEDC_DUTY_LSCH5_S 0\r
-\r
-#define LEDC_LSCH6_CONF0_REG (DR_REG_LEDC_BASE + 0x0118)\r
-/* LEDC_PARA_UP_LSCH6 : R/W ;bitpos:[4] ;default: 1'b0 ; */\r
-/*description: This bit is used to update register LEDC_LSCH6_HPOINT and LEDC_LSCH6_DUTY\r
- for low speed channel6.*/\r
-#define LEDC_PARA_UP_LSCH6 (BIT(4))\r
-#define LEDC_PARA_UP_LSCH6_M (BIT(4))\r
-#define LEDC_PARA_UP_LSCH6_V 0x1\r
-#define LEDC_PARA_UP_LSCH6_S 4\r
-/* LEDC_IDLE_LV_LSCH6 : R/W ;bitpos:[3] ;default: 1'b0 ; */\r
-/*description: This bit is used to control the output value when low speed channel6 is off.*/\r
-#define LEDC_IDLE_LV_LSCH6 (BIT(3))\r
-#define LEDC_IDLE_LV_LSCH6_M (BIT(3))\r
-#define LEDC_IDLE_LV_LSCH6_V 0x1\r
-#define LEDC_IDLE_LV_LSCH6_S 3\r
-/* LEDC_SIG_OUT_EN_LSCH6 : R/W ;bitpos:[2] ;default: 1'b0 ; */\r
-/*description: This is the output enable control bit for low speed channel6.*/\r
-#define LEDC_SIG_OUT_EN_LSCH6 (BIT(2))\r
-#define LEDC_SIG_OUT_EN_LSCH6_M (BIT(2))\r
-#define LEDC_SIG_OUT_EN_LSCH6_V 0x1\r
-#define LEDC_SIG_OUT_EN_LSCH6_S 2\r
-/* LEDC_TIMER_SEL_LSCH6 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */\r
-/*description: There are four low speed timers the two bits are used to select\r
- one of them for low speed channel6. 2'b00: seletc lstimer0. 2'b01: select lstimer1. 2'b10: select lstimer2. 2'b11: select lstimer3.*/\r
-#define LEDC_TIMER_SEL_LSCH6 0x00000003\r
-#define LEDC_TIMER_SEL_LSCH6_M ((LEDC_TIMER_SEL_LSCH6_V)<<(LEDC_TIMER_SEL_LSCH6_S))\r
-#define LEDC_TIMER_SEL_LSCH6_V 0x3\r
-#define LEDC_TIMER_SEL_LSCH6_S 0\r
-\r
-#define LEDC_LSCH6_HPOINT_REG (DR_REG_LEDC_BASE + 0x011C)\r
-/* LEDC_HPOINT_LSCH6 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */\r
-/*description: The output value changes to high when lstimerx(x=[0 3]) selected\r
- by low speed channel6 has reached reg_hpoint_lsch6[19:0]*/\r
-#define LEDC_HPOINT_LSCH6 0x000FFFFF\r
-#define LEDC_HPOINT_LSCH6_M ((LEDC_HPOINT_LSCH6_V)<<(LEDC_HPOINT_LSCH6_S))\r
-#define LEDC_HPOINT_LSCH6_V 0xFFFFF\r
-#define LEDC_HPOINT_LSCH6_S 0\r
-\r
-#define LEDC_LSCH6_DUTY_REG (DR_REG_LEDC_BASE + 0x0120)\r
-/* LEDC_DUTY_LSCH6 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */\r
-/*description: The register is used to control output duty. When lstimerx(x=[0\r
- 3]) choosed by low speed channel6 has reached reg_lpoint_lsch6 the output signal changes to low. reg_lpoint_lsch6=(reg_hpoint_lsch6[19:0]+reg_duty_lsch6[24:4]) (1) reg_lpoint_lsch6=(reg_hpoint_lsch6[19:0]+reg_duty_lsch6[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/\r
-#define LEDC_DUTY_LSCH6 0x01FFFFFF\r
-#define LEDC_DUTY_LSCH6_M ((LEDC_DUTY_LSCH6_V)<<(LEDC_DUTY_LSCH6_S))\r
-#define LEDC_DUTY_LSCH6_V 0x1FFFFFF\r
-#define LEDC_DUTY_LSCH6_S 0\r
-\r
-#define LEDC_LSCH6_CONF1_REG (DR_REG_LEDC_BASE + 0x0124)\r
-/* LEDC_DUTY_START_LSCH6 : R/W ;bitpos:[31] ;default: 1'b0 ; */\r
-/*description: When reg_duty_num_hsch6 reg_duty_cycle_hsch6 and reg_duty_scale_hsch6\r
- has been configured. these register won't take effect until set reg_duty_start_hsch6. this bit is automatically cleared by hardware.*/\r
-#define LEDC_DUTY_START_LSCH6 (BIT(31))\r
-#define LEDC_DUTY_START_LSCH6_M (BIT(31))\r
-#define LEDC_DUTY_START_LSCH6_V 0x1\r
-#define LEDC_DUTY_START_LSCH6_S 31\r
-/* LEDC_DUTY_INC_LSCH6 : R/W ;bitpos:[30] ;default: 1'b1 ; */\r
-/*description: This register is used to increase the duty of output signal or\r
- decrease the duty of output signal for low speed channel6.*/\r
-#define LEDC_DUTY_INC_LSCH6 (BIT(30))\r
-#define LEDC_DUTY_INC_LSCH6_M (BIT(30))\r
-#define LEDC_DUTY_INC_LSCH6_V 0x1\r
-#define LEDC_DUTY_INC_LSCH6_S 30\r
-/* LEDC_DUTY_NUM_LSCH6 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */\r
-/*description: This register is used to control the num of increased or decreased\r
- times for low speed channel6.*/\r
-#define LEDC_DUTY_NUM_LSCH6 0x000003FF\r
-#define LEDC_DUTY_NUM_LSCH6_M ((LEDC_DUTY_NUM_LSCH6_V)<<(LEDC_DUTY_NUM_LSCH6_S))\r
-#define LEDC_DUTY_NUM_LSCH6_V 0x3FF\r
-#define LEDC_DUTY_NUM_LSCH6_S 20\r
-/* LEDC_DUTY_CYCLE_LSCH6 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */\r
-/*description: This register is used to increase or decrease the duty every\r
- reg_duty_cycle_lsch6 cycles for low speed channel6.*/\r
-#define LEDC_DUTY_CYCLE_LSCH6 0x000003FF\r
-#define LEDC_DUTY_CYCLE_LSCH6_M ((LEDC_DUTY_CYCLE_LSCH6_V)<<(LEDC_DUTY_CYCLE_LSCH6_S))\r
-#define LEDC_DUTY_CYCLE_LSCH6_V 0x3FF\r
-#define LEDC_DUTY_CYCLE_LSCH6_S 10\r
-/* LEDC_DUTY_SCALE_LSCH6 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */\r
-/*description: This register controls the increase or decrease step scale for\r
- low speed channel6.*/\r
-#define LEDC_DUTY_SCALE_LSCH6 0x000003FF\r
-#define LEDC_DUTY_SCALE_LSCH6_M ((LEDC_DUTY_SCALE_LSCH6_V)<<(LEDC_DUTY_SCALE_LSCH6_S))\r
-#define LEDC_DUTY_SCALE_LSCH6_V 0x3FF\r
-#define LEDC_DUTY_SCALE_LSCH6_S 0\r
-\r
-#define LEDC_LSCH6_DUTY_R_REG (DR_REG_LEDC_BASE + 0x0128)\r
-/* LEDC_DUTY_LSCH6 : RO ;bitpos:[24:0] ;default: 25'h0 ; */\r
-/*description: This register represents the current duty of the output signal\r
- for low speed channel6.*/\r
-#define LEDC_DUTY_LSCH6 0x01FFFFFF\r
-#define LEDC_DUTY_LSCH6_M ((LEDC_DUTY_LSCH6_V)<<(LEDC_DUTY_LSCH6_S))\r
-#define LEDC_DUTY_LSCH6_V 0x1FFFFFF\r
-#define LEDC_DUTY_LSCH6_S 0\r
-\r
-#define LEDC_LSCH7_CONF0_REG (DR_REG_LEDC_BASE + 0x012C)\r
-/* LEDC_PARA_UP_LSCH7 : R/W ;bitpos:[4] ;default: 1'b0 ; */\r
-/*description: This bit is used to update register LEDC_LSCH7_HPOINT and LEDC_LSCH7_DUTY\r
- for low speed channel7.*/\r
-#define LEDC_PARA_UP_LSCH7 (BIT(4))\r
-#define LEDC_PARA_UP_LSCH7_M (BIT(4))\r
-#define LEDC_PARA_UP_LSCH7_V 0x1\r
-#define LEDC_PARA_UP_LSCH7_S 4\r
-/* LEDC_IDLE_LV_LSCH7 : R/W ;bitpos:[3] ;default: 1'b0 ; */\r
-/*description: This bit is used to control the output value when low speed channel7 is off.*/\r
-#define LEDC_IDLE_LV_LSCH7 (BIT(3))\r
-#define LEDC_IDLE_LV_LSCH7_M (BIT(3))\r
-#define LEDC_IDLE_LV_LSCH7_V 0x1\r
-#define LEDC_IDLE_LV_LSCH7_S 3\r
-/* LEDC_SIG_OUT_EN_LSCH7 : R/W ;bitpos:[2] ;default: 1'b0 ; */\r
-/*description: This is the output enable control bit for low speed channel7.*/\r
-#define LEDC_SIG_OUT_EN_LSCH7 (BIT(2))\r
-#define LEDC_SIG_OUT_EN_LSCH7_M (BIT(2))\r
-#define LEDC_SIG_OUT_EN_LSCH7_V 0x1\r
-#define LEDC_SIG_OUT_EN_LSCH7_S 2\r
-/* LEDC_TIMER_SEL_LSCH7 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */\r
-/*description: There are four low speed timers the two bits are used to select\r
- one of them for low speed channel7. 2'b00: seletc lstimer0. 2'b01: select lstimer1. 2'b10: select lstimer2. 2'b11: select lstimer3.*/\r
-#define LEDC_TIMER_SEL_LSCH7 0x00000003\r
-#define LEDC_TIMER_SEL_LSCH7_M ((LEDC_TIMER_SEL_LSCH7_V)<<(LEDC_TIMER_SEL_LSCH7_S))\r
-#define LEDC_TIMER_SEL_LSCH7_V 0x3\r
-#define LEDC_TIMER_SEL_LSCH7_S 0\r
-\r
-#define LEDC_LSCH7_HPOINT_REG (DR_REG_LEDC_BASE + 0x0130)\r
-/* LEDC_HPOINT_LSCH7 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */\r
-/*description: The output value changes to high when lstimerx(x=[0 3]) selected\r
- by low speed channel7 has reached reg_hpoint_lsch7[19:0]*/\r
-#define LEDC_HPOINT_LSCH7 0x000FFFFF\r
-#define LEDC_HPOINT_LSCH7_M ((LEDC_HPOINT_LSCH7_V)<<(LEDC_HPOINT_LSCH7_S))\r
-#define LEDC_HPOINT_LSCH7_V 0xFFFFF\r
-#define LEDC_HPOINT_LSCH7_S 0\r
-\r
-#define LEDC_LSCH7_DUTY_REG (DR_REG_LEDC_BASE + 0x0134)\r
-/* LEDC_DUTY_LSCH7 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */\r
-/*description: The register is used to control output duty. When lstimerx(x=[0\r
- 3]) choosed by low speed channel7 has reached reg_lpoint_lsch7 the output signal changes to low. reg_lpoint_lsch7=(reg_hpoint_lsch7[19:0]+reg_duty_lsch7[24:4]) (1) reg_lpoint_lsch7=(reg_hpoint_lsch7[19:0]+reg_duty_lsch7[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/\r
-#define LEDC_DUTY_LSCH7 0x01FFFFFF\r
-#define LEDC_DUTY_LSCH7_M ((LEDC_DUTY_LSCH7_V)<<(LEDC_DUTY_LSCH7_S))\r
-#define LEDC_DUTY_LSCH7_V 0x1FFFFFF\r
-#define LEDC_DUTY_LSCH7_S 0\r
-\r
-#define LEDC_LSCH7_CONF1_REG (DR_REG_LEDC_BASE + 0x0138)\r
-/* LEDC_DUTY_START_LSCH7 : R/W ;bitpos:[31] ;default: 1'b0 ; */\r
-/*description: When reg_duty_num_hsch4 reg_duty_cycle_hsch4 and reg_duty_scale_hsch4\r
- has been configured. these register won't take effect until set reg_duty_start_hsch4. this bit is automatically cleared by hardware.*/\r
-#define LEDC_DUTY_START_LSCH7 (BIT(31))\r
-#define LEDC_DUTY_START_LSCH7_M (BIT(31))\r
-#define LEDC_DUTY_START_LSCH7_V 0x1\r
-#define LEDC_DUTY_START_LSCH7_S 31\r
-/* LEDC_DUTY_INC_LSCH7 : R/W ;bitpos:[30] ;default: 1'b1 ; */\r
-/*description: This register is used to increase the duty of output signal or\r
- decrease the duty of output signal for low speed channel4.*/\r
-#define LEDC_DUTY_INC_LSCH7 (BIT(30))\r
-#define LEDC_DUTY_INC_LSCH7_M (BIT(30))\r
-#define LEDC_DUTY_INC_LSCH7_V 0x1\r
-#define LEDC_DUTY_INC_LSCH7_S 30\r
-/* LEDC_DUTY_NUM_LSCH7 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */\r
-/*description: This register is used to control the num of increased or decreased\r
- times for low speed channel4.*/\r
-#define LEDC_DUTY_NUM_LSCH7 0x000003FF\r
-#define LEDC_DUTY_NUM_LSCH7_M ((LEDC_DUTY_NUM_LSCH7_V)<<(LEDC_DUTY_NUM_LSCH7_S))\r
-#define LEDC_DUTY_NUM_LSCH7_V 0x3FF\r
-#define LEDC_DUTY_NUM_LSCH7_S 20\r
-/* LEDC_DUTY_CYCLE_LSCH7 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */\r
-/*description: This register is used to increase or decrease the duty every\r
- reg_duty_cycle_lsch7 cycles for low speed channel7.*/\r
-#define LEDC_DUTY_CYCLE_LSCH7 0x000003FF\r
-#define LEDC_DUTY_CYCLE_LSCH7_M ((LEDC_DUTY_CYCLE_LSCH7_V)<<(LEDC_DUTY_CYCLE_LSCH7_S))\r
-#define LEDC_DUTY_CYCLE_LSCH7_V 0x3FF\r
-#define LEDC_DUTY_CYCLE_LSCH7_S 10\r
-/* LEDC_DUTY_SCALE_LSCH7 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */\r
-/*description: This register controls the increase or decrease step scale for\r
- low speed channel7.*/\r
-#define LEDC_DUTY_SCALE_LSCH7 0x000003FF\r
-#define LEDC_DUTY_SCALE_LSCH7_M ((LEDC_DUTY_SCALE_LSCH7_V)<<(LEDC_DUTY_SCALE_LSCH7_S))\r
-#define LEDC_DUTY_SCALE_LSCH7_V 0x3FF\r
-#define LEDC_DUTY_SCALE_LSCH7_S 0\r
-\r
-#define LEDC_LSCH7_DUTY_R_REG (DR_REG_LEDC_BASE + 0x013C)\r
-/* LEDC_DUTY_LSCH7 : RO ;bitpos:[24:0] ;default: 25'h0 ; */\r
-/*description: This register represents the current duty of the output signal\r
- for low speed channel7.*/\r
-#define LEDC_DUTY_LSCH7 0x01FFFFFF\r
-#define LEDC_DUTY_LSCH7_M ((LEDC_DUTY_LSCH7_V)<<(LEDC_DUTY_LSCH7_S))\r
-#define LEDC_DUTY_LSCH7_V 0x1FFFFFF\r
-#define LEDC_DUTY_LSCH7_S 0\r
-\r
-#define LEDC_HSTIMER0_CONF_REG (DR_REG_LEDC_BASE + 0x0140)\r
-/* LEDC_TICK_SEL_HSTIMER0 : R/W ;bitpos:[25] ;default: 1'b0 ; */\r
-/*description: This bit is used to choose apb_clk or ref_tick for high speed\r
- timer0. 1'b1:apb_clk 0:ref_tick*/\r
-#define LEDC_TICK_SEL_HSTIMER0 (BIT(25))\r
-#define LEDC_TICK_SEL_HSTIMER0_M (BIT(25))\r
-#define LEDC_TICK_SEL_HSTIMER0_V 0x1\r
-#define LEDC_TICK_SEL_HSTIMER0_S 25\r
-/* LEDC_HSTIMER0_RST : R/W ;bitpos:[24] ;default: 1'b1 ; */\r
-/*description: This bit is used to reset high speed timer0 the counter will be 0 after reset.*/\r
-#define LEDC_HSTIMER0_RST (BIT(24))\r
-#define LEDC_HSTIMER0_RST_M (BIT(24))\r
-#define LEDC_HSTIMER0_RST_V 0x1\r
-#define LEDC_HSTIMER0_RST_S 24\r
-/* LEDC_HSTIMER0_PAUSE : R/W ;bitpos:[23] ;default: 1'b0 ; */\r
-/*description: This bit is used to pause the counter in high speed timer0*/\r
-#define LEDC_HSTIMER0_PAUSE (BIT(23))\r
-#define LEDC_HSTIMER0_PAUSE_M (BIT(23))\r
-#define LEDC_HSTIMER0_PAUSE_V 0x1\r
-#define LEDC_HSTIMER0_PAUSE_S 23\r
-/* LEDC_DIV_NUM_HSTIMER0 : R/W ;bitpos:[22:5] ;default: 18'h0 ; */\r
-/*description: This register is used to configure parameter for divider in high\r
- speed timer0 the least significant eight bits represent the decimal part.*/\r
-#define LEDC_DIV_NUM_HSTIMER0 0x0003FFFF\r
-#define LEDC_DIV_NUM_HSTIMER0_M ((LEDC_DIV_NUM_HSTIMER0_V)<<(LEDC_DIV_NUM_HSTIMER0_S))\r
-#define LEDC_DIV_NUM_HSTIMER0_V 0x3FFFF\r
-#define LEDC_DIV_NUM_HSTIMER0_S 5\r
-/* LEDC_HSTIMER0_LIM : R/W ;bitpos:[4:0] ;default: 5'h0 ; */\r
-/*description: This register controls the range of the counter in high speed\r
- timer0. the counter range is [0 2**reg_hstimer0_lim] the max bit width for counter is 20.*/\r
-#define LEDC_HSTIMER0_LIM 0x0000001F\r
-#define LEDC_HSTIMER0_LIM_M ((LEDC_HSTIMER0_LIM_V)<<(LEDC_HSTIMER0_LIM_S))\r
-#define LEDC_HSTIMER0_LIM_V 0x1F\r
-#define LEDC_HSTIMER0_LIM_S 0\r
-\r
-#define LEDC_HSTIMER0_VALUE_REG (DR_REG_LEDC_BASE + 0x0144)\r
-/* LEDC_HSTIMER0_CNT : RO ;bitpos:[19:0] ;default: 20'b0 ; */\r
-/*description: software can read this register to get the current counter value\r
- in high speed timer0*/\r
-#define LEDC_HSTIMER0_CNT 0x000FFFFF\r
-#define LEDC_HSTIMER0_CNT_M ((LEDC_HSTIMER0_CNT_V)<<(LEDC_HSTIMER0_CNT_S))\r
-#define LEDC_HSTIMER0_CNT_V 0xFFFFF\r
-#define LEDC_HSTIMER0_CNT_S 0\r
-\r
-#define LEDC_HSTIMER1_CONF_REG (DR_REG_LEDC_BASE + 0x0148)\r
-/* LEDC_TICK_SEL_HSTIMER1 : R/W ;bitpos:[25] ;default: 1'b0 ; */\r
-/*description: This bit is used to choose apb_clk or ref_tick for high speed\r
- timer1. 1'b1:apb_clk 0:ref_tick*/\r
-#define LEDC_TICK_SEL_HSTIMER1 (BIT(25))\r
-#define LEDC_TICK_SEL_HSTIMER1_M (BIT(25))\r
-#define LEDC_TICK_SEL_HSTIMER1_V 0x1\r
-#define LEDC_TICK_SEL_HSTIMER1_S 25\r
-/* LEDC_HSTIMER1_RST : R/W ;bitpos:[24] ;default: 1'b1 ; */\r
-/*description: This bit is used to reset high speed timer1 the counter will be 0 after reset.*/\r
-#define LEDC_HSTIMER1_RST (BIT(24))\r
-#define LEDC_HSTIMER1_RST_M (BIT(24))\r
-#define LEDC_HSTIMER1_RST_V 0x1\r
-#define LEDC_HSTIMER1_RST_S 24\r
-/* LEDC_HSTIMER1_PAUSE : R/W ;bitpos:[23] ;default: 1'b0 ; */\r
-/*description: This bit is used to pause the counter in high speed timer1*/\r
-#define LEDC_HSTIMER1_PAUSE (BIT(23))\r
-#define LEDC_HSTIMER1_PAUSE_M (BIT(23))\r
-#define LEDC_HSTIMER1_PAUSE_V 0x1\r
-#define LEDC_HSTIMER1_PAUSE_S 23\r
-/* LEDC_DIV_NUM_HSTIMER1 : R/W ;bitpos:[22:5] ;default: 18'h0 ; */\r
-/*description: This register is used to configure parameter for divider in high\r
- speed timer1 the least significant eight bits represent the decimal part.*/\r
-#define LEDC_DIV_NUM_HSTIMER1 0x0003FFFF\r
-#define LEDC_DIV_NUM_HSTIMER1_M ((LEDC_DIV_NUM_HSTIMER1_V)<<(LEDC_DIV_NUM_HSTIMER1_S))\r
-#define LEDC_DIV_NUM_HSTIMER1_V 0x3FFFF\r
-#define LEDC_DIV_NUM_HSTIMER1_S 5\r
-/* LEDC_HSTIMER1_LIM : R/W ;bitpos:[4:0] ;default: 5'h0 ; */\r
-/*description: This register controls the range of the counter in high speed\r
- timer1. the counter range is [0 2**reg_hstimer1_lim] the max bit width for counter is 20.*/\r
-#define LEDC_HSTIMER1_LIM 0x0000001F\r
-#define LEDC_HSTIMER1_LIM_M ((LEDC_HSTIMER1_LIM_V)<<(LEDC_HSTIMER1_LIM_S))\r
-#define LEDC_HSTIMER1_LIM_V 0x1F\r
-#define LEDC_HSTIMER1_LIM_S 0\r
-\r
-#define LEDC_HSTIMER1_VALUE_REG (DR_REG_LEDC_BASE + 0x014C)\r
-/* LEDC_HSTIMER1_CNT : RO ;bitpos:[19:0] ;default: 20'b0 ; */\r
-/*description: software can read this register to get the current counter value\r
- in high speed timer1.*/\r
-#define LEDC_HSTIMER1_CNT 0x000FFFFF\r
-#define LEDC_HSTIMER1_CNT_M ((LEDC_HSTIMER1_CNT_V)<<(LEDC_HSTIMER1_CNT_S))\r
-#define LEDC_HSTIMER1_CNT_V 0xFFFFF\r
-#define LEDC_HSTIMER1_CNT_S 0\r
-\r
-#define LEDC_HSTIMER2_CONF_REG (DR_REG_LEDC_BASE + 0x0150)\r
-/* LEDC_TICK_SEL_HSTIMER2 : R/W ;bitpos:[25] ;default: 1'b0 ; */\r
-/*description: This bit is used to choose apb_clk or ref_tick for high speed\r
- timer2. 1'b1:apb_clk 0:ref_tick*/\r
-#define LEDC_TICK_SEL_HSTIMER2 (BIT(25))\r
-#define LEDC_TICK_SEL_HSTIMER2_M (BIT(25))\r
-#define LEDC_TICK_SEL_HSTIMER2_V 0x1\r
-#define LEDC_TICK_SEL_HSTIMER2_S 25\r
-/* LEDC_HSTIMER2_RST : R/W ;bitpos:[24] ;default: 1'b1 ; */\r
-/*description: This bit is used to reset high speed timer2 the counter will be 0 after reset.*/\r
-#define LEDC_HSTIMER2_RST (BIT(24))\r
-#define LEDC_HSTIMER2_RST_M (BIT(24))\r
-#define LEDC_HSTIMER2_RST_V 0x1\r
-#define LEDC_HSTIMER2_RST_S 24\r
-/* LEDC_HSTIMER2_PAUSE : R/W ;bitpos:[23] ;default: 1'b0 ; */\r
-/*description: This bit is used to pause the counter in high speed timer2*/\r
-#define LEDC_HSTIMER2_PAUSE (BIT(23))\r
-#define LEDC_HSTIMER2_PAUSE_M (BIT(23))\r
-#define LEDC_HSTIMER2_PAUSE_V 0x1\r
-#define LEDC_HSTIMER2_PAUSE_S 23\r
-/* LEDC_DIV_NUM_HSTIMER2 : R/W ;bitpos:[22:5] ;default: 18'h0 ; */\r
-/*description: This register is used to configure parameter for divider in high\r
- speed timer2 the least significant eight bits represent the decimal part.*/\r
-#define LEDC_DIV_NUM_HSTIMER2 0x0003FFFF\r
-#define LEDC_DIV_NUM_HSTIMER2_M ((LEDC_DIV_NUM_HSTIMER2_V)<<(LEDC_DIV_NUM_HSTIMER2_S))\r
-#define LEDC_DIV_NUM_HSTIMER2_V 0x3FFFF\r
-#define LEDC_DIV_NUM_HSTIMER2_S 5\r
-/* LEDC_HSTIMER2_LIM : R/W ;bitpos:[4:0] ;default: 5'h0 ; */\r
-/*description: This register controls the range of the counter in high speed\r
- timer2. the counter range is [0 2**reg_hstimer2_lim] the max bit width for counter is 20.*/\r
-#define LEDC_HSTIMER2_LIM 0x0000001F\r
-#define LEDC_HSTIMER2_LIM_M ((LEDC_HSTIMER2_LIM_V)<<(LEDC_HSTIMER2_LIM_S))\r
-#define LEDC_HSTIMER2_LIM_V 0x1F\r
-#define LEDC_HSTIMER2_LIM_S 0\r
-\r
-#define LEDC_HSTIMER2_VALUE_REG (DR_REG_LEDC_BASE + 0x0154)\r
-/* LEDC_HSTIMER2_CNT : RO ;bitpos:[19:0] ;default: 20'b0 ; */\r
-/*description: software can read this register to get the current counter value\r
- in high speed timer2*/\r
-#define LEDC_HSTIMER2_CNT 0x000FFFFF\r
-#define LEDC_HSTIMER2_CNT_M ((LEDC_HSTIMER2_CNT_V)<<(LEDC_HSTIMER2_CNT_S))\r
-#define LEDC_HSTIMER2_CNT_V 0xFFFFF\r
-#define LEDC_HSTIMER2_CNT_S 0\r
-\r
-#define LEDC_HSTIMER3_CONF_REG (DR_REG_LEDC_BASE + 0x0158)\r
-/* LEDC_TICK_SEL_HSTIMER3 : R/W ;bitpos:[25] ;default: 1'b0 ; */\r
-/*description: This bit is used to choose apb_clk or ref_tick for high speed\r
- timer3. 1'b1:apb_clk 0:ref_tick*/\r
-#define LEDC_TICK_SEL_HSTIMER3 (BIT(25))\r
-#define LEDC_TICK_SEL_HSTIMER3_M (BIT(25))\r
-#define LEDC_TICK_SEL_HSTIMER3_V 0x1\r
-#define LEDC_TICK_SEL_HSTIMER3_S 25\r
-/* LEDC_HSTIMER3_RST : R/W ;bitpos:[24] ;default: 1'b1 ; */\r
-/*description: This bit is used to reset high speed timer3 the counter will be 0 after reset.*/\r
-#define LEDC_HSTIMER3_RST (BIT(24))\r
-#define LEDC_HSTIMER3_RST_M (BIT(24))\r
-#define LEDC_HSTIMER3_RST_V 0x1\r
-#define LEDC_HSTIMER3_RST_S 24\r
-/* LEDC_HSTIMER3_PAUSE : R/W ;bitpos:[23] ;default: 1'b0 ; */\r
-/*description: This bit is used to pause the counter in high speed timer3*/\r
-#define LEDC_HSTIMER3_PAUSE (BIT(23))\r
-#define LEDC_HSTIMER3_PAUSE_M (BIT(23))\r
-#define LEDC_HSTIMER3_PAUSE_V 0x1\r
-#define LEDC_HSTIMER3_PAUSE_S 23\r
-/* LEDC_DIV_NUM_HSTIMER3 : R/W ;bitpos:[22:5] ;default: 18'h0 ; */\r
-/*description: This register is used to configure parameter for divider in high\r
- speed timer3 the least significant eight bits represent the decimal part.*/\r
-#define LEDC_DIV_NUM_HSTIMER3 0x0003FFFF\r
-#define LEDC_DIV_NUM_HSTIMER3_M ((LEDC_DIV_NUM_HSTIMER3_V)<<(LEDC_DIV_NUM_HSTIMER3_S))\r
-#define LEDC_DIV_NUM_HSTIMER3_V 0x3FFFF\r
-#define LEDC_DIV_NUM_HSTIMER3_S 5\r
-/* LEDC_HSTIMER3_LIM : R/W ;bitpos:[4:0] ;default: 5'h0 ; */\r
-/*description: This register controls the range of the counter in high speed\r
- timer3. the counter range is [0 2**reg_hstimer3_lim] the max bit width for counter is 20.*/\r
-#define LEDC_HSTIMER3_LIM 0x0000001F\r
-#define LEDC_HSTIMER3_LIM_M ((LEDC_HSTIMER3_LIM_V)<<(LEDC_HSTIMER3_LIM_S))\r
-#define LEDC_HSTIMER3_LIM_V 0x1F\r
-#define LEDC_HSTIMER3_LIM_S 0\r
-\r
-#define LEDC_HSTIMER3_VALUE_REG (DR_REG_LEDC_BASE + 0x015C)\r
-/* LEDC_HSTIMER3_CNT : RO ;bitpos:[19:0] ;default: 20'b0 ; */\r
-/*description: software can read this register to get the current counter value\r
- in high speed timer3*/\r
-#define LEDC_HSTIMER3_CNT 0x000FFFFF\r
-#define LEDC_HSTIMER3_CNT_M ((LEDC_HSTIMER3_CNT_V)<<(LEDC_HSTIMER3_CNT_S))\r
-#define LEDC_HSTIMER3_CNT_V 0xFFFFF\r
-#define LEDC_HSTIMER3_CNT_S 0\r
-\r
-#define LEDC_LSTIMER0_CONF_REG (DR_REG_LEDC_BASE + 0x0160)\r
-/* LEDC_LSTIMER0_PARA_UP : R/W ;bitpos:[26] ;default: 1'h0 ; */\r
-/*description: Set this bit to update reg_div_num_lstime0 and reg_lstimer0_lim.*/\r
-#define LEDC_LSTIMER0_PARA_UP (BIT(26))\r
-#define LEDC_LSTIMER0_PARA_UP_M (BIT(26))\r
-#define LEDC_LSTIMER0_PARA_UP_V 0x1\r
-#define LEDC_LSTIMER0_PARA_UP_S 26\r
-/* LEDC_TICK_SEL_LSTIMER0 : R/W ;bitpos:[25] ;default: 1'b0 ; */\r
-/*description: This bit is used to choose slow_clk or ref_tick for low speed\r
- timer0. 1'b1:slow_clk 0:ref_tick*/\r
-#define LEDC_TICK_SEL_LSTIMER0 (BIT(25))\r
-#define LEDC_TICK_SEL_LSTIMER0_M (BIT(25))\r
-#define LEDC_TICK_SEL_LSTIMER0_V 0x1\r
-#define LEDC_TICK_SEL_LSTIMER0_S 25\r
-/* LEDC_LSTIMER0_RST : R/W ;bitpos:[24] ;default: 1'b1 ; */\r
-/*description: This bit is used to reset low speed timer0 the counter will be 0 after reset.*/\r
-#define LEDC_LSTIMER0_RST (BIT(24))\r
-#define LEDC_LSTIMER0_RST_M (BIT(24))\r
-#define LEDC_LSTIMER0_RST_V 0x1\r
-#define LEDC_LSTIMER0_RST_S 24\r
-/* LEDC_LSTIMER0_PAUSE : R/W ;bitpos:[23] ;default: 1'b0 ; */\r
-/*description: This bit is used to pause the counter in low speed timer0.*/\r
-#define LEDC_LSTIMER0_PAUSE (BIT(23))\r
-#define LEDC_LSTIMER0_PAUSE_M (BIT(23))\r
-#define LEDC_LSTIMER0_PAUSE_V 0x1\r
-#define LEDC_LSTIMER0_PAUSE_S 23\r
-/* LEDC_DIV_NUM_LSTIMER0 : R/W ;bitpos:[22:5] ;default: 18'h0 ; */\r
-/*description: This register is used to configure parameter for divider in low\r
- speed timer0 the least significant eight bits represent the decimal part.*/\r
-#define LEDC_DIV_NUM_LSTIMER0 0x0003FFFF\r
-#define LEDC_DIV_NUM_LSTIMER0_M ((LEDC_DIV_NUM_LSTIMER0_V)<<(LEDC_DIV_NUM_LSTIMER0_S))\r
-#define LEDC_DIV_NUM_LSTIMER0_V 0x3FFFF\r
-#define LEDC_DIV_NUM_LSTIMER0_S 5\r
-/* LEDC_LSTIMER0_LIM : R/W ;bitpos:[4:0] ;default: 5'h0 ; */\r
-/*description: This register controls the range of the counter in low speed\r
- timer0. the counter range is [0 2**reg_lstimer0_lim] the max bit width for counter is 20.*/\r
-#define LEDC_LSTIMER0_LIM 0x0000001F\r
-#define LEDC_LSTIMER0_LIM_M ((LEDC_LSTIMER0_LIM_V)<<(LEDC_LSTIMER0_LIM_S))\r
-#define LEDC_LSTIMER0_LIM_V 0x1F\r
-#define LEDC_LSTIMER0_LIM_S 0\r
-\r
-#define LEDC_LSTIMER0_VALUE_REG (DR_REG_LEDC_BASE + 0x0164)\r
-/* LEDC_LSTIMER0_CNT : RO ;bitpos:[19:0] ;default: 20'b0 ; */\r
-/*description: software can read this register to get the current counter value\r
- in low speed timer0.*/\r
-#define LEDC_LSTIMER0_CNT 0x000FFFFF\r
-#define LEDC_LSTIMER0_CNT_M ((LEDC_LSTIMER0_CNT_V)<<(LEDC_LSTIMER0_CNT_S))\r
-#define LEDC_LSTIMER0_CNT_V 0xFFFFF\r
-#define LEDC_LSTIMER0_CNT_S 0\r
-\r
-#define LEDC_LSTIMER1_CONF_REG (DR_REG_LEDC_BASE + 0x0168)\r
-/* LEDC_LSTIMER1_PARA_UP : R/W ;bitpos:[26] ;default: 1'h0 ; */\r
-/*description: Set this bit to update reg_div_num_lstime1 and reg_lstimer1_lim.*/\r
-#define LEDC_LSTIMER1_PARA_UP (BIT(26))\r
-#define LEDC_LSTIMER1_PARA_UP_M (BIT(26))\r
-#define LEDC_LSTIMER1_PARA_UP_V 0x1\r
-#define LEDC_LSTIMER1_PARA_UP_S 26\r
-/* LEDC_TICK_SEL_LSTIMER1 : R/W ;bitpos:[25] ;default: 1'b0 ; */\r
-/*description: This bit is used to choose slow_clk or ref_tick for low speed\r
- timer1. 1'b1:slow_clk 0:ref_tick*/\r
-#define LEDC_TICK_SEL_LSTIMER1 (BIT(25))\r
-#define LEDC_TICK_SEL_LSTIMER1_M (BIT(25))\r
-#define LEDC_TICK_SEL_LSTIMER1_V 0x1\r
-#define LEDC_TICK_SEL_LSTIMER1_S 25\r
-/* LEDC_LSTIMER1_RST : R/W ;bitpos:[24] ;default: 1'b1 ; */\r
-/*description: This bit is used to reset low speed timer1 the counter will be 0 after reset.*/\r
-#define LEDC_LSTIMER1_RST (BIT(24))\r
-#define LEDC_LSTIMER1_RST_M (BIT(24))\r
-#define LEDC_LSTIMER1_RST_V 0x1\r
-#define LEDC_LSTIMER1_RST_S 24\r
-/* LEDC_LSTIMER1_PAUSE : R/W ;bitpos:[23] ;default: 1'b0 ; */\r
-/*description: This bit is used to pause the counter in low speed timer1.*/\r
-#define LEDC_LSTIMER1_PAUSE (BIT(23))\r
-#define LEDC_LSTIMER1_PAUSE_M (BIT(23))\r
-#define LEDC_LSTIMER1_PAUSE_V 0x1\r
-#define LEDC_LSTIMER1_PAUSE_S 23\r
-/* LEDC_DIV_NUM_LSTIMER1 : R/W ;bitpos:[22:5] ;default: 18'h0 ; */\r
-/*description: This register is used to configure parameter for divider in low\r
- speed timer1 the least significant eight bits represent the decimal part.*/\r
-#define LEDC_DIV_NUM_LSTIMER1 0x0003FFFF\r
-#define LEDC_DIV_NUM_LSTIMER1_M ((LEDC_DIV_NUM_LSTIMER1_V)<<(LEDC_DIV_NUM_LSTIMER1_S))\r
-#define LEDC_DIV_NUM_LSTIMER1_V 0x3FFFF\r
-#define LEDC_DIV_NUM_LSTIMER1_S 5\r
-/* LEDC_LSTIMER1_LIM : R/W ;bitpos:[4:0] ;default: 5'h0 ; */\r
-/*description: This register controls the range of the counter in low speed\r
- timer1. the counter range is [0 2**reg_lstimer1_lim] the max bit width for counter is 20.*/\r
-#define LEDC_LSTIMER1_LIM 0x0000001F\r
-#define LEDC_LSTIMER1_LIM_M ((LEDC_LSTIMER1_LIM_V)<<(LEDC_LSTIMER1_LIM_S))\r
-#define LEDC_LSTIMER1_LIM_V 0x1F\r
-#define LEDC_LSTIMER1_LIM_S 0\r
-\r
-#define LEDC_LSTIMER1_VALUE_REG (DR_REG_LEDC_BASE + 0x016C)\r
-/* LEDC_LSTIMER1_CNT : RO ;bitpos:[19:0] ;default: 20'b0 ; */\r
-/*description: software can read this register to get the current counter value\r
- in low speed timer1.*/\r
-#define LEDC_LSTIMER1_CNT 0x000FFFFF\r
-#define LEDC_LSTIMER1_CNT_M ((LEDC_LSTIMER1_CNT_V)<<(LEDC_LSTIMER1_CNT_S))\r
-#define LEDC_LSTIMER1_CNT_V 0xFFFFF\r
-#define LEDC_LSTIMER1_CNT_S 0\r
-\r
-#define LEDC_LSTIMER2_CONF_REG (DR_REG_LEDC_BASE + 0x0170)\r
-/* LEDC_LSTIMER2_PARA_UP : R/W ;bitpos:[26] ;default: 1'h0 ; */\r
-/*description: Set this bit to update reg_div_num_lstime2 and reg_lstimer2_lim.*/\r
-#define LEDC_LSTIMER2_PARA_UP (BIT(26))\r
-#define LEDC_LSTIMER2_PARA_UP_M (BIT(26))\r
-#define LEDC_LSTIMER2_PARA_UP_V 0x1\r
-#define LEDC_LSTIMER2_PARA_UP_S 26\r
-/* LEDC_TICK_SEL_LSTIMER2 : R/W ;bitpos:[25] ;default: 1'b0 ; */\r
-/*description: This bit is used to choose slow_clk or ref_tick for low speed\r
- timer2. 1'b1:slow_clk 0:ref_tick*/\r
-#define LEDC_TICK_SEL_LSTIMER2 (BIT(25))\r
-#define LEDC_TICK_SEL_LSTIMER2_M (BIT(25))\r
-#define LEDC_TICK_SEL_LSTIMER2_V 0x1\r
-#define LEDC_TICK_SEL_LSTIMER2_S 25\r
-/* LEDC_LSTIMER2_RST : R/W ;bitpos:[24] ;default: 1'b1 ; */\r
-/*description: This bit is used to reset low speed timer2 the counter will be 0 after reset.*/\r
-#define LEDC_LSTIMER2_RST (BIT(24))\r
-#define LEDC_LSTIMER2_RST_M (BIT(24))\r
-#define LEDC_LSTIMER2_RST_V 0x1\r
-#define LEDC_LSTIMER2_RST_S 24\r
-/* LEDC_LSTIMER2_PAUSE : R/W ;bitpos:[23] ;default: 1'b0 ; */\r
-/*description: This bit is used to pause the counter in low speed timer2.*/\r
-#define LEDC_LSTIMER2_PAUSE (BIT(23))\r
-#define LEDC_LSTIMER2_PAUSE_M (BIT(23))\r
-#define LEDC_LSTIMER2_PAUSE_V 0x1\r
-#define LEDC_LSTIMER2_PAUSE_S 23\r
-/* LEDC_DIV_NUM_LSTIMER2 : R/W ;bitpos:[22:5] ;default: 18'h0 ; */\r
-/*description: This register is used to configure parameter for divider in low\r
- speed timer2 the least significant eight bits represent the decimal part.*/\r
-#define LEDC_DIV_NUM_LSTIMER2 0x0003FFFF\r
-#define LEDC_DIV_NUM_LSTIMER2_M ((LEDC_DIV_NUM_LSTIMER2_V)<<(LEDC_DIV_NUM_LSTIMER2_S))\r
-#define LEDC_DIV_NUM_LSTIMER2_V 0x3FFFF\r
-#define LEDC_DIV_NUM_LSTIMER2_S 5\r
-/* LEDC_LSTIMER2_LIM : R/W ;bitpos:[4:0] ;default: 5'h0 ; */\r
-/*description: This register controls the range of the counter in low speed\r
- timer2. the counter range is [0 2**reg_lstimer2_lim] the max bit width for counter is 20.*/\r
-#define LEDC_LSTIMER2_LIM 0x0000001F\r
-#define LEDC_LSTIMER2_LIM_M ((LEDC_LSTIMER2_LIM_V)<<(LEDC_LSTIMER2_LIM_S))\r
-#define LEDC_LSTIMER2_LIM_V 0x1F\r
-#define LEDC_LSTIMER2_LIM_S 0\r
-\r
-#define LEDC_LSTIMER2_VALUE_REG (DR_REG_LEDC_BASE + 0x0174)\r
-/* LEDC_LSTIMER2_CNT : RO ;bitpos:[19:0] ;default: 20'b0 ; */\r
-/*description: software can read this register to get the current counter value\r
- in low speed timer2.*/\r
-#define LEDC_LSTIMER2_CNT 0x000FFFFF\r
-#define LEDC_LSTIMER2_CNT_M ((LEDC_LSTIMER2_CNT_V)<<(LEDC_LSTIMER2_CNT_S))\r
-#define LEDC_LSTIMER2_CNT_V 0xFFFFF\r
-#define LEDC_LSTIMER2_CNT_S 0\r
-\r
-#define LEDC_LSTIMER3_CONF_REG (DR_REG_LEDC_BASE + 0x0178)\r
-/* LEDC_LSTIMER3_PARA_UP : R/W ;bitpos:[26] ;default: 1'h0 ; */\r
-/*description: Set this bit to update reg_div_num_lstime3 and reg_lstimer3_lim.*/\r
-#define LEDC_LSTIMER3_PARA_UP (BIT(26))\r
-#define LEDC_LSTIMER3_PARA_UP_M (BIT(26))\r
-#define LEDC_LSTIMER3_PARA_UP_V 0x1\r
-#define LEDC_LSTIMER3_PARA_UP_S 26\r
-/* LEDC_TICK_SEL_LSTIMER3 : R/W ;bitpos:[25] ;default: 1'b0 ; */\r
-/*description: This bit is used to choose slow_clk or ref_tick for low speed\r
- timer3. 1'b1:slow_clk 0:ref_tick*/\r
-#define LEDC_TICK_SEL_LSTIMER3 (BIT(25))\r
-#define LEDC_TICK_SEL_LSTIMER3_M (BIT(25))\r
-#define LEDC_TICK_SEL_LSTIMER3_V 0x1\r
-#define LEDC_TICK_SEL_LSTIMER3_S 25\r
-/* LEDC_LSTIMER3_RST : R/W ;bitpos:[24] ;default: 1'b1 ; */\r
-/*description: This bit is used to reset low speed timer3 the counter will be 0 after reset.*/\r
-#define LEDC_LSTIMER3_RST (BIT(24))\r
-#define LEDC_LSTIMER3_RST_M (BIT(24))\r
-#define LEDC_LSTIMER3_RST_V 0x1\r
-#define LEDC_LSTIMER3_RST_S 24\r
-/* LEDC_LSTIMER3_PAUSE : R/W ;bitpos:[23] ;default: 1'b0 ; */\r
-/*description: This bit is used to pause the counter in low speed timer3.*/\r
-#define LEDC_LSTIMER3_PAUSE (BIT(23))\r
-#define LEDC_LSTIMER3_PAUSE_M (BIT(23))\r
-#define LEDC_LSTIMER3_PAUSE_V 0x1\r
-#define LEDC_LSTIMER3_PAUSE_S 23\r
-/* LEDC_DIV_NUM_LSTIMER3 : R/W ;bitpos:[22:5] ;default: 18'h0 ; */\r
-/*description: This register is used to configure parameter for divider in low\r
- speed timer3 the least significant eight bits represent the decimal part.*/\r
-#define LEDC_DIV_NUM_LSTIMER3 0x0003FFFF\r
-#define LEDC_DIV_NUM_LSTIMER3_M ((LEDC_DIV_NUM_LSTIMER3_V)<<(LEDC_DIV_NUM_LSTIMER3_S))\r
-#define LEDC_DIV_NUM_LSTIMER3_V 0x3FFFF\r
-#define LEDC_DIV_NUM_LSTIMER3_S 5\r
-/* LEDC_LSTIMER3_LIM : R/W ;bitpos:[4:0] ;default: 5'h0 ; */\r
-/*description: This register controls the range of the counter in low speed\r
- timer3. the counter range is [0 2**reg_lstimer3_lim] the max bit width for counter is 20.*/\r
-#define LEDC_LSTIMER3_LIM 0x0000001F\r
-#define LEDC_LSTIMER3_LIM_M ((LEDC_LSTIMER3_LIM_V)<<(LEDC_LSTIMER3_LIM_S))\r
-#define LEDC_LSTIMER3_LIM_V 0x1F\r
-#define LEDC_LSTIMER3_LIM_S 0\r
-\r
-#define LEDC_LSTIMER3_VALUE_REG (DR_REG_LEDC_BASE + 0x017C)\r
-/* LEDC_LSTIMER3_CNT : RO ;bitpos:[19:0] ;default: 20'b0 ; */\r
-/*description: software can read this register to get the current counter value\r
- in low speed timer3.*/\r
-#define LEDC_LSTIMER3_CNT 0x000FFFFF\r
-#define LEDC_LSTIMER3_CNT_M ((LEDC_LSTIMER3_CNT_V)<<(LEDC_LSTIMER3_CNT_S))\r
-#define LEDC_LSTIMER3_CNT_V 0xFFFFF\r
-#define LEDC_LSTIMER3_CNT_S 0\r
-\r
-#define LEDC_INT_RAW_REG (DR_REG_LEDC_BASE + 0x0180)\r
-/* LEDC_DUTY_CHNG_END_LSCH7_INT_RAW : RO ;bitpos:[23] ;default: 1'b0 ; */\r
-/*description: The interrupt raw bit for low speed channel 7 duty change done.*/\r
-#define LEDC_DUTY_CHNG_END_LSCH7_INT_RAW (BIT(23))\r
-#define LEDC_DUTY_CHNG_END_LSCH7_INT_RAW_M (BIT(23))\r
-#define LEDC_DUTY_CHNG_END_LSCH7_INT_RAW_V 0x1\r
-#define LEDC_DUTY_CHNG_END_LSCH7_INT_RAW_S 23\r
-/* LEDC_DUTY_CHNG_END_LSCH6_INT_RAW : RO ;bitpos:[22] ;default: 1'b0 ; */\r
-/*description: The interrupt raw bit for low speed channel 6 duty change done.*/\r
-#define LEDC_DUTY_CHNG_END_LSCH6_INT_RAW (BIT(22))\r
-#define LEDC_DUTY_CHNG_END_LSCH6_INT_RAW_M (BIT(22))\r
-#define LEDC_DUTY_CHNG_END_LSCH6_INT_RAW_V 0x1\r
-#define LEDC_DUTY_CHNG_END_LSCH6_INT_RAW_S 22\r
-/* LEDC_DUTY_CHNG_END_LSCH5_INT_RAW : RO ;bitpos:[21] ;default: 1'b0 ; */\r
-/*description: The interrupt raw bit for low speed channel 5 duty change done.*/\r
-#define LEDC_DUTY_CHNG_END_LSCH5_INT_RAW (BIT(21))\r
-#define LEDC_DUTY_CHNG_END_LSCH5_INT_RAW_M (BIT(21))\r
-#define LEDC_DUTY_CHNG_END_LSCH5_INT_RAW_V 0x1\r
-#define LEDC_DUTY_CHNG_END_LSCH5_INT_RAW_S 21\r
-/* LEDC_DUTY_CHNG_END_LSCH4_INT_RAW : RO ;bitpos:[20] ;default: 1'b0 ; */\r
-/*description: The interrupt raw bit for low speed channel 4 duty change done.*/\r
-#define LEDC_DUTY_CHNG_END_LSCH4_INT_RAW (BIT(20))\r
-#define LEDC_DUTY_CHNG_END_LSCH4_INT_RAW_M (BIT(20))\r
-#define LEDC_DUTY_CHNG_END_LSCH4_INT_RAW_V 0x1\r
-#define LEDC_DUTY_CHNG_END_LSCH4_INT_RAW_S 20\r
-/* LEDC_DUTY_CHNG_END_LSCH3_INT_RAW : RO ;bitpos:[19] ;default: 1'b0 ; */\r
-/*description: The interrupt raw bit for low speed channel 3 duty change done.*/\r
-#define LEDC_DUTY_CHNG_END_LSCH3_INT_RAW (BIT(19))\r
-#define LEDC_DUTY_CHNG_END_LSCH3_INT_RAW_M (BIT(19))\r
-#define LEDC_DUTY_CHNG_END_LSCH3_INT_RAW_V 0x1\r
-#define LEDC_DUTY_CHNG_END_LSCH3_INT_RAW_S 19\r
-/* LEDC_DUTY_CHNG_END_LSCH2_INT_RAW : RO ;bitpos:[18] ;default: 1'b0 ; */\r
-/*description: The interrupt raw bit for low speed channel 2 duty change done.*/\r
-#define LEDC_DUTY_CHNG_END_LSCH2_INT_RAW (BIT(18))\r
-#define LEDC_DUTY_CHNG_END_LSCH2_INT_RAW_M (BIT(18))\r
-#define LEDC_DUTY_CHNG_END_LSCH2_INT_RAW_V 0x1\r
-#define LEDC_DUTY_CHNG_END_LSCH2_INT_RAW_S 18\r
-/* LEDC_DUTY_CHNG_END_LSCH1_INT_RAW : RO ;bitpos:[17] ;default: 1'b0 ; */\r
-/*description: The interrupt raw bit for low speed channel 1 duty change done.*/\r
-#define LEDC_DUTY_CHNG_END_LSCH1_INT_RAW (BIT(17))\r
-#define LEDC_DUTY_CHNG_END_LSCH1_INT_RAW_M (BIT(17))\r
-#define LEDC_DUTY_CHNG_END_LSCH1_INT_RAW_V 0x1\r
-#define LEDC_DUTY_CHNG_END_LSCH1_INT_RAW_S 17\r
-/* LEDC_DUTY_CHNG_END_LSCH0_INT_RAW : RO ;bitpos:[16] ;default: 1'b0 ; */\r
-/*description: The interrupt raw bit for low speed channel 0 duty change done.*/\r
-#define LEDC_DUTY_CHNG_END_LSCH0_INT_RAW (BIT(16))\r
-#define LEDC_DUTY_CHNG_END_LSCH0_INT_RAW_M (BIT(16))\r
-#define LEDC_DUTY_CHNG_END_LSCH0_INT_RAW_V 0x1\r
-#define LEDC_DUTY_CHNG_END_LSCH0_INT_RAW_S 16\r
-/* LEDC_DUTY_CHNG_END_HSCH7_INT_RAW : RO ;bitpos:[15] ;default: 1'b0 ; */\r
-/*description: The interrupt raw bit for high speed channel 7 duty change done.*/\r
-#define LEDC_DUTY_CHNG_END_HSCH7_INT_RAW (BIT(15))\r
-#define LEDC_DUTY_CHNG_END_HSCH7_INT_RAW_M (BIT(15))\r
-#define LEDC_DUTY_CHNG_END_HSCH7_INT_RAW_V 0x1\r
-#define LEDC_DUTY_CHNG_END_HSCH7_INT_RAW_S 15\r
-/* LEDC_DUTY_CHNG_END_HSCH6_INT_RAW : RO ;bitpos:[14] ;default: 1'b0 ; */\r
-/*description: The interrupt raw bit for high speed channel 6 duty change done.*/\r
-#define LEDC_DUTY_CHNG_END_HSCH6_INT_RAW (BIT(14))\r
-#define LEDC_DUTY_CHNG_END_HSCH6_INT_RAW_M (BIT(14))\r
-#define LEDC_DUTY_CHNG_END_HSCH6_INT_RAW_V 0x1\r
-#define LEDC_DUTY_CHNG_END_HSCH6_INT_RAW_S 14\r
-/* LEDC_DUTY_CHNG_END_HSCH5_INT_RAW : RO ;bitpos:[13] ;default: 1'b0 ; */\r
-/*description: The interrupt raw bit for high speed channel 5 duty change done.*/\r
-#define LEDC_DUTY_CHNG_END_HSCH5_INT_RAW (BIT(13))\r
-#define LEDC_DUTY_CHNG_END_HSCH5_INT_RAW_M (BIT(13))\r
-#define LEDC_DUTY_CHNG_END_HSCH5_INT_RAW_V 0x1\r
-#define LEDC_DUTY_CHNG_END_HSCH5_INT_RAW_S 13\r
-/* LEDC_DUTY_CHNG_END_HSCH4_INT_RAW : RO ;bitpos:[12] ;default: 1'b0 ; */\r
-/*description: The interrupt raw bit for high speed channel 4 duty change done.*/\r
-#define LEDC_DUTY_CHNG_END_HSCH4_INT_RAW (BIT(12))\r
-#define LEDC_DUTY_CHNG_END_HSCH4_INT_RAW_M (BIT(12))\r
-#define LEDC_DUTY_CHNG_END_HSCH4_INT_RAW_V 0x1\r
-#define LEDC_DUTY_CHNG_END_HSCH4_INT_RAW_S 12\r
-/* LEDC_DUTY_CHNG_END_HSCH3_INT_RAW : RO ;bitpos:[11] ;default: 1'b0 ; */\r
-/*description: The interrupt raw bit for high speed channel 3 duty change done.*/\r
-#define LEDC_DUTY_CHNG_END_HSCH3_INT_RAW (BIT(11))\r
-#define LEDC_DUTY_CHNG_END_HSCH3_INT_RAW_M (BIT(11))\r
-#define LEDC_DUTY_CHNG_END_HSCH3_INT_RAW_V 0x1\r
-#define LEDC_DUTY_CHNG_END_HSCH3_INT_RAW_S 11\r
-/* LEDC_DUTY_CHNG_END_HSCH2_INT_RAW : RO ;bitpos:[10] ;default: 1'b0 ; */\r
-/*description: The interrupt raw bit for high speed channel 2 duty change done.*/\r
-#define LEDC_DUTY_CHNG_END_HSCH2_INT_RAW (BIT(10))\r
-#define LEDC_DUTY_CHNG_END_HSCH2_INT_RAW_M (BIT(10))\r
-#define LEDC_DUTY_CHNG_END_HSCH2_INT_RAW_V 0x1\r
-#define LEDC_DUTY_CHNG_END_HSCH2_INT_RAW_S 10\r
-/* LEDC_DUTY_CHNG_END_HSCH1_INT_RAW : RO ;bitpos:[9] ;default: 1'b0 ; */\r
-/*description: The interrupt raw bit for high speed channel 1 duty change done.*/\r
-#define LEDC_DUTY_CHNG_END_HSCH1_INT_RAW (BIT(9))\r
-#define LEDC_DUTY_CHNG_END_HSCH1_INT_RAW_M (BIT(9))\r
-#define LEDC_DUTY_CHNG_END_HSCH1_INT_RAW_V 0x1\r
-#define LEDC_DUTY_CHNG_END_HSCH1_INT_RAW_S 9\r
-/* LEDC_DUTY_CHNG_END_HSCH0_INT_RAW : RO ;bitpos:[8] ;default: 1'b0 ; */\r
-/*description: The interrupt raw bit for high speed channel 0 duty change done.*/\r
-#define LEDC_DUTY_CHNG_END_HSCH0_INT_RAW (BIT(8))\r
-#define LEDC_DUTY_CHNG_END_HSCH0_INT_RAW_M (BIT(8))\r
-#define LEDC_DUTY_CHNG_END_HSCH0_INT_RAW_V 0x1\r
-#define LEDC_DUTY_CHNG_END_HSCH0_INT_RAW_S 8\r
-/* LEDC_LSTIMER3_OVF_INT_RAW : RO ;bitpos:[7] ;default: 1'b0 ; */\r
-/*description: The interrupt raw bit for low speed channel3 counter overflow.*/\r
-#define LEDC_LSTIMER3_OVF_INT_RAW (BIT(7))\r
-#define LEDC_LSTIMER3_OVF_INT_RAW_M (BIT(7))\r
-#define LEDC_LSTIMER3_OVF_INT_RAW_V 0x1\r
-#define LEDC_LSTIMER3_OVF_INT_RAW_S 7\r
-/* LEDC_LSTIMER2_OVF_INT_RAW : RO ;bitpos:[6] ;default: 1'b0 ; */\r
-/*description: The interrupt raw bit for low speed channel2 counter overflow.*/\r
-#define LEDC_LSTIMER2_OVF_INT_RAW (BIT(6))\r
-#define LEDC_LSTIMER2_OVF_INT_RAW_M (BIT(6))\r
-#define LEDC_LSTIMER2_OVF_INT_RAW_V 0x1\r
-#define LEDC_LSTIMER2_OVF_INT_RAW_S 6\r
-/* LEDC_LSTIMER1_OVF_INT_RAW : RO ;bitpos:[5] ;default: 1'b0 ; */\r
-/*description: The interrupt raw bit for low speed channel1 counter overflow.*/\r
-#define LEDC_LSTIMER1_OVF_INT_RAW (BIT(5))\r
-#define LEDC_LSTIMER1_OVF_INT_RAW_M (BIT(5))\r
-#define LEDC_LSTIMER1_OVF_INT_RAW_V 0x1\r
-#define LEDC_LSTIMER1_OVF_INT_RAW_S 5\r
-/* LEDC_LSTIMER0_OVF_INT_RAW : RO ;bitpos:[4] ;default: 1'b0 ; */\r
-/*description: The interrupt raw bit for low speed channel0 counter overflow.*/\r
-#define LEDC_LSTIMER0_OVF_INT_RAW (BIT(4))\r
-#define LEDC_LSTIMER0_OVF_INT_RAW_M (BIT(4))\r
-#define LEDC_LSTIMER0_OVF_INT_RAW_V 0x1\r
-#define LEDC_LSTIMER0_OVF_INT_RAW_S 4\r
-/* LEDC_HSTIMER3_OVF_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */\r
-/*description: The interrupt raw bit for high speed channel3 counter overflow.*/\r
-#define LEDC_HSTIMER3_OVF_INT_RAW (BIT(3))\r
-#define LEDC_HSTIMER3_OVF_INT_RAW_M (BIT(3))\r
-#define LEDC_HSTIMER3_OVF_INT_RAW_V 0x1\r
-#define LEDC_HSTIMER3_OVF_INT_RAW_S 3\r
-/* LEDC_HSTIMER2_OVF_INT_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */\r
-/*description: The interrupt raw bit for high speed channel2 counter overflow.*/\r
-#define LEDC_HSTIMER2_OVF_INT_RAW (BIT(2))\r
-#define LEDC_HSTIMER2_OVF_INT_RAW_M (BIT(2))\r
-#define LEDC_HSTIMER2_OVF_INT_RAW_V 0x1\r
-#define LEDC_HSTIMER2_OVF_INT_RAW_S 2\r
-/* LEDC_HSTIMER1_OVF_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */\r
-/*description: The interrupt raw bit for high speed channel1 counter overflow.*/\r
-#define LEDC_HSTIMER1_OVF_INT_RAW (BIT(1))\r
-#define LEDC_HSTIMER1_OVF_INT_RAW_M (BIT(1))\r
-#define LEDC_HSTIMER1_OVF_INT_RAW_V 0x1\r
-#define LEDC_HSTIMER1_OVF_INT_RAW_S 1\r
-/* LEDC_HSTIMER0_OVF_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */\r
-/*description: The interrupt raw bit for high speed channel0 counter overflow.*/\r
-#define LEDC_HSTIMER0_OVF_INT_RAW (BIT(0))\r
-#define LEDC_HSTIMER0_OVF_INT_RAW_M (BIT(0))\r
-#define LEDC_HSTIMER0_OVF_INT_RAW_V 0x1\r
-#define LEDC_HSTIMER0_OVF_INT_RAW_S 0\r
-\r
-#define LEDC_INT_ST_REG (DR_REG_LEDC_BASE + 0x0184)\r
-/* LEDC_DUTY_CHNG_END_LSCH7_INT_ST : RO ;bitpos:[23] ;default: 1'h0 ; */\r
-/*description: The interrupt status bit for low speed channel 7 duty change done event*/\r
-#define LEDC_DUTY_CHNG_END_LSCH7_INT_ST (BIT(23))\r
-#define LEDC_DUTY_CHNG_END_LSCH7_INT_ST_M (BIT(23))\r
-#define LEDC_DUTY_CHNG_END_LSCH7_INT_ST_V 0x1\r
-#define LEDC_DUTY_CHNG_END_LSCH7_INT_ST_S 23\r
-/* LEDC_DUTY_CHNG_END_LSCH6_INT_ST : RO ;bitpos:[22] ;default: 1'b0 ; */\r
-/*description: The interrupt status bit for low speed channel 6 duty change done event.*/\r
-#define LEDC_DUTY_CHNG_END_LSCH6_INT_ST (BIT(22))\r
-#define LEDC_DUTY_CHNG_END_LSCH6_INT_ST_M (BIT(22))\r
-#define LEDC_DUTY_CHNG_END_LSCH6_INT_ST_V 0x1\r
-#define LEDC_DUTY_CHNG_END_LSCH6_INT_ST_S 22\r
-/* LEDC_DUTY_CHNG_END_LSCH5_INT_ST : RO ;bitpos:[21] ;default: 1'b0 ; */\r
-/*description: The interrupt status bit for low speed channel 5 duty change done event.*/\r
-#define LEDC_DUTY_CHNG_END_LSCH5_INT_ST (BIT(21))\r
-#define LEDC_DUTY_CHNG_END_LSCH5_INT_ST_M (BIT(21))\r
-#define LEDC_DUTY_CHNG_END_LSCH5_INT_ST_V 0x1\r
-#define LEDC_DUTY_CHNG_END_LSCH5_INT_ST_S 21\r
-/* LEDC_DUTY_CHNG_END_LSCH4_INT_ST : RO ;bitpos:[20] ;default: 1'b0 ; */\r
-/*description: The interrupt status bit for low speed channel 4 duty change done event.*/\r
-#define LEDC_DUTY_CHNG_END_LSCH4_INT_ST (BIT(20))\r
-#define LEDC_DUTY_CHNG_END_LSCH4_INT_ST_M (BIT(20))\r
-#define LEDC_DUTY_CHNG_END_LSCH4_INT_ST_V 0x1\r
-#define LEDC_DUTY_CHNG_END_LSCH4_INT_ST_S 20\r
-/* LEDC_DUTY_CHNG_END_LSCH3_INT_ST : RO ;bitpos:[19] ;default: 1'b0 ; */\r
-/*description: The interrupt status bit for low speed channel 3 duty change done event.*/\r
-#define LEDC_DUTY_CHNG_END_LSCH3_INT_ST (BIT(19))\r
-#define LEDC_DUTY_CHNG_END_LSCH3_INT_ST_M (BIT(19))\r
-#define LEDC_DUTY_CHNG_END_LSCH3_INT_ST_V 0x1\r
-#define LEDC_DUTY_CHNG_END_LSCH3_INT_ST_S 19\r
-/* LEDC_DUTY_CHNG_END_LSCH2_INT_ST : RO ;bitpos:[18] ;default: 1'b0 ; */\r
-/*description: The interrupt status bit for low speed channel 2 duty change done event.*/\r
-#define LEDC_DUTY_CHNG_END_LSCH2_INT_ST (BIT(18))\r
-#define LEDC_DUTY_CHNG_END_LSCH2_INT_ST_M (BIT(18))\r
-#define LEDC_DUTY_CHNG_END_LSCH2_INT_ST_V 0x1\r
-#define LEDC_DUTY_CHNG_END_LSCH2_INT_ST_S 18\r
-/* LEDC_DUTY_CHNG_END_LSCH1_INT_ST : RO ;bitpos:[17] ;default: 1'b0 ; */\r
-/*description: The interrupt status bit for low speed channel 1 duty change done event.*/\r
-#define LEDC_DUTY_CHNG_END_LSCH1_INT_ST (BIT(17))\r
-#define LEDC_DUTY_CHNG_END_LSCH1_INT_ST_M (BIT(17))\r
-#define LEDC_DUTY_CHNG_END_LSCH1_INT_ST_V 0x1\r
-#define LEDC_DUTY_CHNG_END_LSCH1_INT_ST_S 17\r
-/* LEDC_DUTY_CHNG_END_LSCH0_INT_ST : RO ;bitpos:[16] ;default: 1'b0 ; */\r
-/*description: The interrupt status bit for low speed channel 0 duty change done event.*/\r
-#define LEDC_DUTY_CHNG_END_LSCH0_INT_ST (BIT(16))\r
-#define LEDC_DUTY_CHNG_END_LSCH0_INT_ST_M (BIT(16))\r
-#define LEDC_DUTY_CHNG_END_LSCH0_INT_ST_V 0x1\r
-#define LEDC_DUTY_CHNG_END_LSCH0_INT_ST_S 16\r
-/* LEDC_DUTY_CHNG_END_HSCH7_INT_ST : RO ;bitpos:[15] ;default: 1'b0 ; */\r
-/*description: The interrupt status bit for high speed channel 7 duty change done event.*/\r
-#define LEDC_DUTY_CHNG_END_HSCH7_INT_ST (BIT(15))\r
-#define LEDC_DUTY_CHNG_END_HSCH7_INT_ST_M (BIT(15))\r
-#define LEDC_DUTY_CHNG_END_HSCH7_INT_ST_V 0x1\r
-#define LEDC_DUTY_CHNG_END_HSCH7_INT_ST_S 15\r
-/* LEDC_DUTY_CHNG_END_HSCH6_INT_ST : RO ;bitpos:[14] ;default: 1'b0 ; */\r
-/*description: The interrupt status bit for high speed channel 6 duty change done event.*/\r
-#define LEDC_DUTY_CHNG_END_HSCH6_INT_ST (BIT(14))\r
-#define LEDC_DUTY_CHNG_END_HSCH6_INT_ST_M (BIT(14))\r
-#define LEDC_DUTY_CHNG_END_HSCH6_INT_ST_V 0x1\r
-#define LEDC_DUTY_CHNG_END_HSCH6_INT_ST_S 14\r
-/* LEDC_DUTY_CHNG_END_HSCH5_INT_ST : RO ;bitpos:[13] ;default: 1'b0 ; */\r
-/*description: The interrupt status bit for high speed channel 5 duty change done event.*/\r
-#define LEDC_DUTY_CHNG_END_HSCH5_INT_ST (BIT(13))\r
-#define LEDC_DUTY_CHNG_END_HSCH5_INT_ST_M (BIT(13))\r
-#define LEDC_DUTY_CHNG_END_HSCH5_INT_ST_V 0x1\r
-#define LEDC_DUTY_CHNG_END_HSCH5_INT_ST_S 13\r
-/* LEDC_DUTY_CHNG_END_HSCH4_INT_ST : RO ;bitpos:[12] ;default: 1'b0 ; */\r
-/*description: The interrupt status bit for high speed channel 4 duty change done event.*/\r
-#define LEDC_DUTY_CHNG_END_HSCH4_INT_ST (BIT(12))\r
-#define LEDC_DUTY_CHNG_END_HSCH4_INT_ST_M (BIT(12))\r
-#define LEDC_DUTY_CHNG_END_HSCH4_INT_ST_V 0x1\r
-#define LEDC_DUTY_CHNG_END_HSCH4_INT_ST_S 12\r
-/* LEDC_DUTY_CHNG_END_HSCH3_INT_ST : RO ;bitpos:[11] ;default: 1'b0 ; */\r
-/*description: The interrupt status bit for high speed channel 3 duty change done event.*/\r
-#define LEDC_DUTY_CHNG_END_HSCH3_INT_ST (BIT(11))\r
-#define LEDC_DUTY_CHNG_END_HSCH3_INT_ST_M (BIT(11))\r
-#define LEDC_DUTY_CHNG_END_HSCH3_INT_ST_V 0x1\r
-#define LEDC_DUTY_CHNG_END_HSCH3_INT_ST_S 11\r
-/* LEDC_DUTY_CHNG_END_HSCH2_INT_ST : RO ;bitpos:[10] ;default: 1'b0 ; */\r
-/*description: The interrupt status bit for high speed channel 2 duty change done event.*/\r
-#define LEDC_DUTY_CHNG_END_HSCH2_INT_ST (BIT(10))\r
-#define LEDC_DUTY_CHNG_END_HSCH2_INT_ST_M (BIT(10))\r
-#define LEDC_DUTY_CHNG_END_HSCH2_INT_ST_V 0x1\r
-#define LEDC_DUTY_CHNG_END_HSCH2_INT_ST_S 10\r
-/* LEDC_DUTY_CHNG_END_HSCH1_INT_ST : RO ;bitpos:[9] ;default: 1'b0 ; */\r
-/*description: The interrupt status bit for high speed channel 1 duty change done event.*/\r
-#define LEDC_DUTY_CHNG_END_HSCH1_INT_ST (BIT(9))\r
-#define LEDC_DUTY_CHNG_END_HSCH1_INT_ST_M (BIT(9))\r
-#define LEDC_DUTY_CHNG_END_HSCH1_INT_ST_V 0x1\r
-#define LEDC_DUTY_CHNG_END_HSCH1_INT_ST_S 9\r
-/* LEDC_DUTY_CHNG_END_HSCH0_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */\r
-/*description: The interrupt status bit for high speed channel 0 duty change done event.*/\r
-#define LEDC_DUTY_CHNG_END_HSCH0_INT_ST (BIT(8))\r
-#define LEDC_DUTY_CHNG_END_HSCH0_INT_ST_M (BIT(8))\r
-#define LEDC_DUTY_CHNG_END_HSCH0_INT_ST_V 0x1\r
-#define LEDC_DUTY_CHNG_END_HSCH0_INT_ST_S 8\r
-/* LEDC_LSTIMER3_OVF_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */\r
-/*description: The interrupt status bit for low speed channel3 counter overflow event.*/\r
-#define LEDC_LSTIMER3_OVF_INT_ST (BIT(7))\r
-#define LEDC_LSTIMER3_OVF_INT_ST_M (BIT(7))\r
-#define LEDC_LSTIMER3_OVF_INT_ST_V 0x1\r
-#define LEDC_LSTIMER3_OVF_INT_ST_S 7\r
-/* LEDC_LSTIMER2_OVF_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */\r
-/*description: The interrupt status bit for low speed channel2 counter overflow event.*/\r
-#define LEDC_LSTIMER2_OVF_INT_ST (BIT(6))\r
-#define LEDC_LSTIMER2_OVF_INT_ST_M (BIT(6))\r
-#define LEDC_LSTIMER2_OVF_INT_ST_V 0x1\r
-#define LEDC_LSTIMER2_OVF_INT_ST_S 6\r
-/* LEDC_LSTIMER1_OVF_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */\r
-/*description: The interrupt status bit for low speed channel1 counter overflow event.*/\r
-#define LEDC_LSTIMER1_OVF_INT_ST (BIT(5))\r
-#define LEDC_LSTIMER1_OVF_INT_ST_M (BIT(5))\r
-#define LEDC_LSTIMER1_OVF_INT_ST_V 0x1\r
-#define LEDC_LSTIMER1_OVF_INT_ST_S 5\r
-/* LEDC_LSTIMER0_OVF_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */\r
-/*description: The interrupt status bit for low speed channel0 counter overflow event.*/\r
-#define LEDC_LSTIMER0_OVF_INT_ST (BIT(4))\r
-#define LEDC_LSTIMER0_OVF_INT_ST_M (BIT(4))\r
-#define LEDC_LSTIMER0_OVF_INT_ST_V 0x1\r
-#define LEDC_LSTIMER0_OVF_INT_ST_S 4\r
-/* LEDC_HSTIMER3_OVF_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */\r
-/*description: The interrupt status bit for high speed channel3 counter overflow event.*/\r
-#define LEDC_HSTIMER3_OVF_INT_ST (BIT(3))\r
-#define LEDC_HSTIMER3_OVF_INT_ST_M (BIT(3))\r
-#define LEDC_HSTIMER3_OVF_INT_ST_V 0x1\r
-#define LEDC_HSTIMER3_OVF_INT_ST_S 3\r
-/* LEDC_HSTIMER2_OVF_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */\r
-/*description: The interrupt status bit for high speed channel2 counter overflow event.*/\r
-#define LEDC_HSTIMER2_OVF_INT_ST (BIT(2))\r
-#define LEDC_HSTIMER2_OVF_INT_ST_M (BIT(2))\r
-#define LEDC_HSTIMER2_OVF_INT_ST_V 0x1\r
-#define LEDC_HSTIMER2_OVF_INT_ST_S 2\r
-/* LEDC_HSTIMER1_OVF_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */\r
-/*description: The interrupt status bit for high speed channel1 counter overflow event.*/\r
-#define LEDC_HSTIMER1_OVF_INT_ST (BIT(1))\r
-#define LEDC_HSTIMER1_OVF_INT_ST_M (BIT(1))\r
-#define LEDC_HSTIMER1_OVF_INT_ST_V 0x1\r
-#define LEDC_HSTIMER1_OVF_INT_ST_S 1\r
-/* LEDC_HSTIMER0_OVF_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */\r
-/*description: The interrupt status bit for high speed channel0 counter overflow event.*/\r
-#define LEDC_HSTIMER0_OVF_INT_ST (BIT(0))\r
-#define LEDC_HSTIMER0_OVF_INT_ST_M (BIT(0))\r
-#define LEDC_HSTIMER0_OVF_INT_ST_V 0x1\r
-#define LEDC_HSTIMER0_OVF_INT_ST_S 0\r
-\r
-#define LEDC_INT_ENA_REG (DR_REG_LEDC_BASE + 0x0188)\r
-/* LEDC_DUTY_CHNG_END_LSCH7_INT_ENA : R/W ;bitpos:[23] ;default: 1'h0 ; */\r
-/*description: The interrupt enable bit for low speed channel 7 duty change done interrupt.*/\r
-#define LEDC_DUTY_CHNG_END_LSCH7_INT_ENA (BIT(23))\r
-#define LEDC_DUTY_CHNG_END_LSCH7_INT_ENA_M (BIT(23))\r
-#define LEDC_DUTY_CHNG_END_LSCH7_INT_ENA_V 0x1\r
-#define LEDC_DUTY_CHNG_END_LSCH7_INT_ENA_S 23\r
-/* LEDC_DUTY_CHNG_END_LSCH6_INT_ENA : R/W ;bitpos:[22] ;default: 1'b0 ; */\r
-/*description: The interrupt enable bit for low speed channel 6 duty change done interrupt.*/\r
-#define LEDC_DUTY_CHNG_END_LSCH6_INT_ENA (BIT(22))\r
-#define LEDC_DUTY_CHNG_END_LSCH6_INT_ENA_M (BIT(22))\r
-#define LEDC_DUTY_CHNG_END_LSCH6_INT_ENA_V 0x1\r
-#define LEDC_DUTY_CHNG_END_LSCH6_INT_ENA_S 22\r
-/* LEDC_DUTY_CHNG_END_LSCH5_INT_ENA : R/W ;bitpos:[21] ;default: 1'b0 ; */\r
-/*description: The interrupt enable bit for low speed channel 5 duty change done interrupt.*/\r
-#define LEDC_DUTY_CHNG_END_LSCH5_INT_ENA (BIT(21))\r
-#define LEDC_DUTY_CHNG_END_LSCH5_INT_ENA_M (BIT(21))\r
-#define LEDC_DUTY_CHNG_END_LSCH5_INT_ENA_V 0x1\r
-#define LEDC_DUTY_CHNG_END_LSCH5_INT_ENA_S 21\r
-/* LEDC_DUTY_CHNG_END_LSCH4_INT_ENA : R/W ;bitpos:[20] ;default: 1'b0 ; */\r
-/*description: The interrupt enable bit for low speed channel 4 duty change done interrupt.*/\r
-#define LEDC_DUTY_CHNG_END_LSCH4_INT_ENA (BIT(20))\r
-#define LEDC_DUTY_CHNG_END_LSCH4_INT_ENA_M (BIT(20))\r
-#define LEDC_DUTY_CHNG_END_LSCH4_INT_ENA_V 0x1\r
-#define LEDC_DUTY_CHNG_END_LSCH4_INT_ENA_S 20\r
-/* LEDC_DUTY_CHNG_END_LSCH3_INT_ENA : R/W ;bitpos:[19] ;default: 1'b0 ; */\r
-/*description: The interrupt enable bit for low speed channel 3 duty change done interrupt.*/\r
-#define LEDC_DUTY_CHNG_END_LSCH3_INT_ENA (BIT(19))\r
-#define LEDC_DUTY_CHNG_END_LSCH3_INT_ENA_M (BIT(19))\r
-#define LEDC_DUTY_CHNG_END_LSCH3_INT_ENA_V 0x1\r
-#define LEDC_DUTY_CHNG_END_LSCH3_INT_ENA_S 19\r
-/* LEDC_DUTY_CHNG_END_LSCH2_INT_ENA : R/W ;bitpos:[18] ;default: 1'b0 ; */\r
-/*description: The interrupt enable bit for low speed channel 2 duty change done interrupt.*/\r
-#define LEDC_DUTY_CHNG_END_LSCH2_INT_ENA (BIT(18))\r
-#define LEDC_DUTY_CHNG_END_LSCH2_INT_ENA_M (BIT(18))\r
-#define LEDC_DUTY_CHNG_END_LSCH2_INT_ENA_V 0x1\r
-#define LEDC_DUTY_CHNG_END_LSCH2_INT_ENA_S 18\r
-/* LEDC_DUTY_CHNG_END_LSCH1_INT_ENA : R/W ;bitpos:[17] ;default: 1'b0 ; */\r
-/*description: The interrupt enable bit for low speed channel 1 duty change done interrupt.*/\r
-#define LEDC_DUTY_CHNG_END_LSCH1_INT_ENA (BIT(17))\r
-#define LEDC_DUTY_CHNG_END_LSCH1_INT_ENA_M (BIT(17))\r
-#define LEDC_DUTY_CHNG_END_LSCH1_INT_ENA_V 0x1\r
-#define LEDC_DUTY_CHNG_END_LSCH1_INT_ENA_S 17\r
-/* LEDC_DUTY_CHNG_END_LSCH0_INT_ENA : R/W ;bitpos:[16] ;default: 1'b0 ; */\r
-/*description: The interrupt enable bit for low speed channel 0 duty change done interrupt.*/\r
-#define LEDC_DUTY_CHNG_END_LSCH0_INT_ENA (BIT(16))\r
-#define LEDC_DUTY_CHNG_END_LSCH0_INT_ENA_M (BIT(16))\r
-#define LEDC_DUTY_CHNG_END_LSCH0_INT_ENA_V 0x1\r
-#define LEDC_DUTY_CHNG_END_LSCH0_INT_ENA_S 16\r
-/* LEDC_DUTY_CHNG_END_HSCH7_INT_ENA : R/W ;bitpos:[15] ;default: 1'b0 ; */\r
-/*description: The interrupt enable bit for high speed channel 7 duty change done interrupt.*/\r
-#define LEDC_DUTY_CHNG_END_HSCH7_INT_ENA (BIT(15))\r
-#define LEDC_DUTY_CHNG_END_HSCH7_INT_ENA_M (BIT(15))\r
-#define LEDC_DUTY_CHNG_END_HSCH7_INT_ENA_V 0x1\r
-#define LEDC_DUTY_CHNG_END_HSCH7_INT_ENA_S 15\r
-/* LEDC_DUTY_CHNG_END_HSCH6_INT_ENA : R/W ;bitpos:[14] ;default: 1'b0 ; */\r
-/*description: The interrupt enable bit for high speed channel 6 duty change done interrupt.*/\r
-#define LEDC_DUTY_CHNG_END_HSCH6_INT_ENA (BIT(14))\r
-#define LEDC_DUTY_CHNG_END_HSCH6_INT_ENA_M (BIT(14))\r
-#define LEDC_DUTY_CHNG_END_HSCH6_INT_ENA_V 0x1\r
-#define LEDC_DUTY_CHNG_END_HSCH6_INT_ENA_S 14\r
-/* LEDC_DUTY_CHNG_END_HSCH5_INT_ENA : R/W ;bitpos:[13] ;default: 1'b0 ; */\r
-/*description: The interrupt enable bit for high speed channel 5 duty change done interrupt.*/\r
-#define LEDC_DUTY_CHNG_END_HSCH5_INT_ENA (BIT(13))\r
-#define LEDC_DUTY_CHNG_END_HSCH5_INT_ENA_M (BIT(13))\r
-#define LEDC_DUTY_CHNG_END_HSCH5_INT_ENA_V 0x1\r
-#define LEDC_DUTY_CHNG_END_HSCH5_INT_ENA_S 13\r
-/* LEDC_DUTY_CHNG_END_HSCH4_INT_ENA : R/W ;bitpos:[12] ;default: 1'b0 ; */\r
-/*description: The interrupt enable bit for high speed channel 4 duty change done interrupt.*/\r
-#define LEDC_DUTY_CHNG_END_HSCH4_INT_ENA (BIT(12))\r
-#define LEDC_DUTY_CHNG_END_HSCH4_INT_ENA_M (BIT(12))\r
-#define LEDC_DUTY_CHNG_END_HSCH4_INT_ENA_V 0x1\r
-#define LEDC_DUTY_CHNG_END_HSCH4_INT_ENA_S 12\r
-/* LEDC_DUTY_CHNG_END_HSCH3_INT_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */\r
-/*description: The interrupt enable bit for high speed channel 3 duty change done interrupt.*/\r
-#define LEDC_DUTY_CHNG_END_HSCH3_INT_ENA (BIT(11))\r
-#define LEDC_DUTY_CHNG_END_HSCH3_INT_ENA_M (BIT(11))\r
-#define LEDC_DUTY_CHNG_END_HSCH3_INT_ENA_V 0x1\r
-#define LEDC_DUTY_CHNG_END_HSCH3_INT_ENA_S 11\r
-/* LEDC_DUTY_CHNG_END_HSCH2_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */\r
-/*description: The interrupt enable bit for high speed channel 2 duty change done interrupt.*/\r
-#define LEDC_DUTY_CHNG_END_HSCH2_INT_ENA (BIT(10))\r
-#define LEDC_DUTY_CHNG_END_HSCH2_INT_ENA_M (BIT(10))\r
-#define LEDC_DUTY_CHNG_END_HSCH2_INT_ENA_V 0x1\r
-#define LEDC_DUTY_CHNG_END_HSCH2_INT_ENA_S 10\r
-/* LEDC_DUTY_CHNG_END_HSCH1_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */\r
-/*description: The interrupt enable bit for high speed channel 1 duty change done interrupt.*/\r
-#define LEDC_DUTY_CHNG_END_HSCH1_INT_ENA (BIT(9))\r
-#define LEDC_DUTY_CHNG_END_HSCH1_INT_ENA_M (BIT(9))\r
-#define LEDC_DUTY_CHNG_END_HSCH1_INT_ENA_V 0x1\r
-#define LEDC_DUTY_CHNG_END_HSCH1_INT_ENA_S 9\r
-/* LEDC_DUTY_CHNG_END_HSCH0_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */\r
-/*description: The interrupt enable bit for high speed channel 0 duty change done interrupt.*/\r
-#define LEDC_DUTY_CHNG_END_HSCH0_INT_ENA (BIT(8))\r
-#define LEDC_DUTY_CHNG_END_HSCH0_INT_ENA_M (BIT(8))\r
-#define LEDC_DUTY_CHNG_END_HSCH0_INT_ENA_V 0x1\r
-#define LEDC_DUTY_CHNG_END_HSCH0_INT_ENA_S 8\r
-/* LEDC_LSTIMER3_OVF_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */\r
-/*description: The interrupt enable bit for low speed channel3 counter overflow interrupt.*/\r
-#define LEDC_LSTIMER3_OVF_INT_ENA (BIT(7))\r
-#define LEDC_LSTIMER3_OVF_INT_ENA_M (BIT(7))\r
-#define LEDC_LSTIMER3_OVF_INT_ENA_V 0x1\r
-#define LEDC_LSTIMER3_OVF_INT_ENA_S 7\r
-/* LEDC_LSTIMER2_OVF_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */\r
-/*description: The interrupt enable bit for low speed channel2 counter overflow interrupt.*/\r
-#define LEDC_LSTIMER2_OVF_INT_ENA (BIT(6))\r
-#define LEDC_LSTIMER2_OVF_INT_ENA_M (BIT(6))\r
-#define LEDC_LSTIMER2_OVF_INT_ENA_V 0x1\r
-#define LEDC_LSTIMER2_OVF_INT_ENA_S 6\r
-/* LEDC_LSTIMER1_OVF_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */\r
-/*description: The interrupt enable bit for low speed channel1 counter overflow interrupt.*/\r
-#define LEDC_LSTIMER1_OVF_INT_ENA (BIT(5))\r
-#define LEDC_LSTIMER1_OVF_INT_ENA_M (BIT(5))\r
-#define LEDC_LSTIMER1_OVF_INT_ENA_V 0x1\r
-#define LEDC_LSTIMER1_OVF_INT_ENA_S 5\r
-/* LEDC_LSTIMER0_OVF_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */\r
-/*description: The interrupt enable bit for low speed channel0 counter overflow interrupt.*/\r
-#define LEDC_LSTIMER0_OVF_INT_ENA (BIT(4))\r
-#define LEDC_LSTIMER0_OVF_INT_ENA_M (BIT(4))\r
-#define LEDC_LSTIMER0_OVF_INT_ENA_V 0x1\r
-#define LEDC_LSTIMER0_OVF_INT_ENA_S 4\r
-/* LEDC_HSTIMER3_OVF_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */\r
-/*description: The interrupt enable bit for high speed channel3 counter overflow interrupt.*/\r
-#define LEDC_HSTIMER3_OVF_INT_ENA (BIT(3))\r
-#define LEDC_HSTIMER3_OVF_INT_ENA_M (BIT(3))\r
-#define LEDC_HSTIMER3_OVF_INT_ENA_V 0x1\r
-#define LEDC_HSTIMER3_OVF_INT_ENA_S 3\r
-/* LEDC_HSTIMER2_OVF_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */\r
-/*description: The interrupt enable bit for high speed channel2 counter overflow interrupt.*/\r
-#define LEDC_HSTIMER2_OVF_INT_ENA (BIT(2))\r
-#define LEDC_HSTIMER2_OVF_INT_ENA_M (BIT(2))\r
-#define LEDC_HSTIMER2_OVF_INT_ENA_V 0x1\r
-#define LEDC_HSTIMER2_OVF_INT_ENA_S 2\r
-/* LEDC_HSTIMER1_OVF_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */\r
-/*description: The interrupt enable bit for high speed channel1 counter overflow interrupt.*/\r
-#define LEDC_HSTIMER1_OVF_INT_ENA (BIT(1))\r
-#define LEDC_HSTIMER1_OVF_INT_ENA_M (BIT(1))\r
-#define LEDC_HSTIMER1_OVF_INT_ENA_V 0x1\r
-#define LEDC_HSTIMER1_OVF_INT_ENA_S 1\r
-/* LEDC_HSTIMER0_OVF_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */\r
-/*description: The interrupt enable bit for high speed channel0 counter overflow interrupt.*/\r
-#define LEDC_HSTIMER0_OVF_INT_ENA (BIT(0))\r
-#define LEDC_HSTIMER0_OVF_INT_ENA_M (BIT(0))\r
-#define LEDC_HSTIMER0_OVF_INT_ENA_V 0x1\r
-#define LEDC_HSTIMER0_OVF_INT_ENA_S 0\r
-\r
-#define LEDC_INT_CLR_REG (DR_REG_LEDC_BASE + 0x018C)\r
-/* LEDC_DUTY_CHNG_END_LSCH7_INT_CLR : WO ;bitpos:[23] ;default: 1'h0 ; */\r
-/*description: Set this bit to clear low speed channel 7 duty change done interrupt.*/\r
-#define LEDC_DUTY_CHNG_END_LSCH7_INT_CLR (BIT(23))\r
-#define LEDC_DUTY_CHNG_END_LSCH7_INT_CLR_M (BIT(23))\r
-#define LEDC_DUTY_CHNG_END_LSCH7_INT_CLR_V 0x1\r
-#define LEDC_DUTY_CHNG_END_LSCH7_INT_CLR_S 23\r
-/* LEDC_DUTY_CHNG_END_LSCH6_INT_CLR : WO ;bitpos:[22] ;default: 1'b0 ; */\r
-/*description: Set this bit to clear low speed channel 6 duty change done interrupt.*/\r
-#define LEDC_DUTY_CHNG_END_LSCH6_INT_CLR (BIT(22))\r
-#define LEDC_DUTY_CHNG_END_LSCH6_INT_CLR_M (BIT(22))\r
-#define LEDC_DUTY_CHNG_END_LSCH6_INT_CLR_V 0x1\r
-#define LEDC_DUTY_CHNG_END_LSCH6_INT_CLR_S 22\r
-/* LEDC_DUTY_CHNG_END_LSCH5_INT_CLR : WO ;bitpos:[21] ;default: 1'b0 ; */\r
-/*description: Set this bit to clear low speed channel 5 duty change done interrupt.*/\r
-#define LEDC_DUTY_CHNG_END_LSCH5_INT_CLR (BIT(21))\r
-#define LEDC_DUTY_CHNG_END_LSCH5_INT_CLR_M (BIT(21))\r
-#define LEDC_DUTY_CHNG_END_LSCH5_INT_CLR_V 0x1\r
-#define LEDC_DUTY_CHNG_END_LSCH5_INT_CLR_S 21\r
-/* LEDC_DUTY_CHNG_END_LSCH4_INT_CLR : WO ;bitpos:[20] ;default: 1'b0 ; */\r
-/*description: Set this bit to clear low speed channel 4 duty change done interrupt.*/\r
-#define LEDC_DUTY_CHNG_END_LSCH4_INT_CLR (BIT(20))\r
-#define LEDC_DUTY_CHNG_END_LSCH4_INT_CLR_M (BIT(20))\r
-#define LEDC_DUTY_CHNG_END_LSCH4_INT_CLR_V 0x1\r
-#define LEDC_DUTY_CHNG_END_LSCH4_INT_CLR_S 20\r
-/* LEDC_DUTY_CHNG_END_LSCH3_INT_CLR : WO ;bitpos:[19] ;default: 1'b0 ; */\r
-/*description: Set this bit to clear low speed channel 3 duty change done interrupt.*/\r
-#define LEDC_DUTY_CHNG_END_LSCH3_INT_CLR (BIT(19))\r
-#define LEDC_DUTY_CHNG_END_LSCH3_INT_CLR_M (BIT(19))\r
-#define LEDC_DUTY_CHNG_END_LSCH3_INT_CLR_V 0x1\r
-#define LEDC_DUTY_CHNG_END_LSCH3_INT_CLR_S 19\r
-/* LEDC_DUTY_CHNG_END_LSCH2_INT_CLR : WO ;bitpos:[18] ;default: 1'b0 ; */\r
-/*description: Set this bit to clear low speed channel 2 duty change done interrupt.*/\r
-#define LEDC_DUTY_CHNG_END_LSCH2_INT_CLR (BIT(18))\r
-#define LEDC_DUTY_CHNG_END_LSCH2_INT_CLR_M (BIT(18))\r
-#define LEDC_DUTY_CHNG_END_LSCH2_INT_CLR_V 0x1\r
-#define LEDC_DUTY_CHNG_END_LSCH2_INT_CLR_S 18\r
-/* LEDC_DUTY_CHNG_END_LSCH1_INT_CLR : WO ;bitpos:[17] ;default: 1'b0 ; */\r
-/*description: Set this bit to clear low speed channel 1 duty change done interrupt.*/\r
-#define LEDC_DUTY_CHNG_END_LSCH1_INT_CLR (BIT(17))\r
-#define LEDC_DUTY_CHNG_END_LSCH1_INT_CLR_M (BIT(17))\r
-#define LEDC_DUTY_CHNG_END_LSCH1_INT_CLR_V 0x1\r
-#define LEDC_DUTY_CHNG_END_LSCH1_INT_CLR_S 17\r
-/* LEDC_DUTY_CHNG_END_LSCH0_INT_CLR : WO ;bitpos:[16] ;default: 1'b0 ; */\r
-/*description: Set this bit to clear low speed channel 0 duty change done interrupt.*/\r
-#define LEDC_DUTY_CHNG_END_LSCH0_INT_CLR (BIT(16))\r
-#define LEDC_DUTY_CHNG_END_LSCH0_INT_CLR_M (BIT(16))\r
-#define LEDC_DUTY_CHNG_END_LSCH0_INT_CLR_V 0x1\r
-#define LEDC_DUTY_CHNG_END_LSCH0_INT_CLR_S 16\r
-/* LEDC_DUTY_CHNG_END_HSCH7_INT_CLR : WO ;bitpos:[15] ;default: 1'b0 ; */\r
-/*description: Set this bit to clear high speed channel 7 duty change done interrupt.*/\r
-#define LEDC_DUTY_CHNG_END_HSCH7_INT_CLR (BIT(15))\r
-#define LEDC_DUTY_CHNG_END_HSCH7_INT_CLR_M (BIT(15))\r
-#define LEDC_DUTY_CHNG_END_HSCH7_INT_CLR_V 0x1\r
-#define LEDC_DUTY_CHNG_END_HSCH7_INT_CLR_S 15\r
-/* LEDC_DUTY_CHNG_END_HSCH6_INT_CLR : WO ;bitpos:[14] ;default: 1'b0 ; */\r
-/*description: Set this bit to clear high speed channel 6 duty change done interrupt.*/\r
-#define LEDC_DUTY_CHNG_END_HSCH6_INT_CLR (BIT(14))\r
-#define LEDC_DUTY_CHNG_END_HSCH6_INT_CLR_M (BIT(14))\r
-#define LEDC_DUTY_CHNG_END_HSCH6_INT_CLR_V 0x1\r
-#define LEDC_DUTY_CHNG_END_HSCH6_INT_CLR_S 14\r
-/* LEDC_DUTY_CHNG_END_HSCH5_INT_CLR : WO ;bitpos:[13] ;default: 1'b0 ; */\r
-/*description: Set this bit to clear high speed channel 5 duty change done interrupt.*/\r
-#define LEDC_DUTY_CHNG_END_HSCH5_INT_CLR (BIT(13))\r
-#define LEDC_DUTY_CHNG_END_HSCH5_INT_CLR_M (BIT(13))\r
-#define LEDC_DUTY_CHNG_END_HSCH5_INT_CLR_V 0x1\r
-#define LEDC_DUTY_CHNG_END_HSCH5_INT_CLR_S 13\r
-/* LEDC_DUTY_CHNG_END_HSCH4_INT_CLR : WO ;bitpos:[12] ;default: 1'b0 ; */\r
-/*description: Set this bit to clear high speed channel 4 duty change done interrupt.*/\r
-#define LEDC_DUTY_CHNG_END_HSCH4_INT_CLR (BIT(12))\r
-#define LEDC_DUTY_CHNG_END_HSCH4_INT_CLR_M (BIT(12))\r
-#define LEDC_DUTY_CHNG_END_HSCH4_INT_CLR_V 0x1\r
-#define LEDC_DUTY_CHNG_END_HSCH4_INT_CLR_S 12\r
-/* LEDC_DUTY_CHNG_END_HSCH3_INT_CLR : WO ;bitpos:[11] ;default: 1'b0 ; */\r
-/*description: Set this bit to clear high speed channel 3 duty change done interrupt.*/\r
-#define LEDC_DUTY_CHNG_END_HSCH3_INT_CLR (BIT(11))\r
-#define LEDC_DUTY_CHNG_END_HSCH3_INT_CLR_M (BIT(11))\r
-#define LEDC_DUTY_CHNG_END_HSCH3_INT_CLR_V 0x1\r
-#define LEDC_DUTY_CHNG_END_HSCH3_INT_CLR_S 11\r
-/* LEDC_DUTY_CHNG_END_HSCH2_INT_CLR : WO ;bitpos:[10] ;default: 1'b0 ; */\r
-/*description: Set this bit to clear high speed channel 2 duty change done interrupt.*/\r
-#define LEDC_DUTY_CHNG_END_HSCH2_INT_CLR (BIT(10))\r
-#define LEDC_DUTY_CHNG_END_HSCH2_INT_CLR_M (BIT(10))\r
-#define LEDC_DUTY_CHNG_END_HSCH2_INT_CLR_V 0x1\r
-#define LEDC_DUTY_CHNG_END_HSCH2_INT_CLR_S 10\r
-/* LEDC_DUTY_CHNG_END_HSCH1_INT_CLR : WO ;bitpos:[9] ;default: 1'b0 ; */\r
-/*description: Set this bit to clear high speed channel 1 duty change done interrupt.*/\r
-#define LEDC_DUTY_CHNG_END_HSCH1_INT_CLR (BIT(9))\r
-#define LEDC_DUTY_CHNG_END_HSCH1_INT_CLR_M (BIT(9))\r
-#define LEDC_DUTY_CHNG_END_HSCH1_INT_CLR_V 0x1\r
-#define LEDC_DUTY_CHNG_END_HSCH1_INT_CLR_S 9\r
-/* LEDC_DUTY_CHNG_END_HSCH0_INT_CLR : WO ;bitpos:[8] ;default: 1'b0 ; */\r
-/*description: Set this bit to clear high speed channel 0 duty change done interrupt.*/\r
-#define LEDC_DUTY_CHNG_END_HSCH0_INT_CLR (BIT(8))\r
-#define LEDC_DUTY_CHNG_END_HSCH0_INT_CLR_M (BIT(8))\r
-#define LEDC_DUTY_CHNG_END_HSCH0_INT_CLR_V 0x1\r
-#define LEDC_DUTY_CHNG_END_HSCH0_INT_CLR_S 8\r
-/* LEDC_LSTIMER3_OVF_INT_CLR : WO ;bitpos:[7] ;default: 1'b0 ; */\r
-/*description: Set this bit to clear low speed channel3 counter overflow interrupt.*/\r
-#define LEDC_LSTIMER3_OVF_INT_CLR (BIT(7))\r
-#define LEDC_LSTIMER3_OVF_INT_CLR_M (BIT(7))\r
-#define LEDC_LSTIMER3_OVF_INT_CLR_V 0x1\r
-#define LEDC_LSTIMER3_OVF_INT_CLR_S 7\r
-/* LEDC_LSTIMER2_OVF_INT_CLR : WO ;bitpos:[6] ;default: 1'b0 ; */\r
-/*description: Set this bit to clear low speed channel2 counter overflow interrupt.*/\r
-#define LEDC_LSTIMER2_OVF_INT_CLR (BIT(6))\r
-#define LEDC_LSTIMER2_OVF_INT_CLR_M (BIT(6))\r
-#define LEDC_LSTIMER2_OVF_INT_CLR_V 0x1\r
-#define LEDC_LSTIMER2_OVF_INT_CLR_S 6\r
-/* LEDC_LSTIMER1_OVF_INT_CLR : WO ;bitpos:[5] ;default: 1'b0 ; */\r
-/*description: Set this bit to clear low speed channel1 counter overflow interrupt.*/\r
-#define LEDC_LSTIMER1_OVF_INT_CLR (BIT(5))\r
-#define LEDC_LSTIMER1_OVF_INT_CLR_M (BIT(5))\r
-#define LEDC_LSTIMER1_OVF_INT_CLR_V 0x1\r
-#define LEDC_LSTIMER1_OVF_INT_CLR_S 5\r
-/* LEDC_LSTIMER0_OVF_INT_CLR : WO ;bitpos:[4] ;default: 1'b0 ; */\r
-/*description: Set this bit to clear low speed channel0 counter overflow interrupt.*/\r
-#define LEDC_LSTIMER0_OVF_INT_CLR (BIT(4))\r
-#define LEDC_LSTIMER0_OVF_INT_CLR_M (BIT(4))\r
-#define LEDC_LSTIMER0_OVF_INT_CLR_V 0x1\r
-#define LEDC_LSTIMER0_OVF_INT_CLR_S 4\r
-/* LEDC_HSTIMER3_OVF_INT_CLR : WO ;bitpos:[3] ;default: 1'b0 ; */\r
-/*description: Set this bit to clear high speed channel3 counter overflow interrupt.*/\r
-#define LEDC_HSTIMER3_OVF_INT_CLR (BIT(3))\r
-#define LEDC_HSTIMER3_OVF_INT_CLR_M (BIT(3))\r
-#define LEDC_HSTIMER3_OVF_INT_CLR_V 0x1\r
-#define LEDC_HSTIMER3_OVF_INT_CLR_S 3\r
-/* LEDC_HSTIMER2_OVF_INT_CLR : WO ;bitpos:[2] ;default: 1'b0 ; */\r
-/*description: Set this bit to clear high speed channel2 counter overflow interrupt.*/\r
-#define LEDC_HSTIMER2_OVF_INT_CLR (BIT(2))\r
-#define LEDC_HSTIMER2_OVF_INT_CLR_M (BIT(2))\r
-#define LEDC_HSTIMER2_OVF_INT_CLR_V 0x1\r
-#define LEDC_HSTIMER2_OVF_INT_CLR_S 2\r
-/* LEDC_HSTIMER1_OVF_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */\r
-/*description: Set this bit to clear high speed channel1 counter overflow interrupt.*/\r
-#define LEDC_HSTIMER1_OVF_INT_CLR (BIT(1))\r
-#define LEDC_HSTIMER1_OVF_INT_CLR_M (BIT(1))\r
-#define LEDC_HSTIMER1_OVF_INT_CLR_V 0x1\r
-#define LEDC_HSTIMER1_OVF_INT_CLR_S 1\r
-/* LEDC_HSTIMER0_OVF_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */\r
-/*description: Set this bit to clear high speed channel0 counter overflow interrupt.*/\r
-#define LEDC_HSTIMER0_OVF_INT_CLR (BIT(0))\r
-#define LEDC_HSTIMER0_OVF_INT_CLR_M (BIT(0))\r
-#define LEDC_HSTIMER0_OVF_INT_CLR_V 0x1\r
-#define LEDC_HSTIMER0_OVF_INT_CLR_S 0\r
-\r
-#define LEDC_CONF_REG (DR_REG_LEDC_BASE + 0x0190)\r
-/* LEDC_APB_CLK_SEL : R/W ;bitpos:[0] ;default: 1'b0 ; */\r
-/*description: This bit is used to set the frequency of slow_clk. 1'b1:80mhz 1'b0:8mhz*/\r
-#define LEDC_APB_CLK_SEL (BIT(0))\r
-#define LEDC_APB_CLK_SEL_M (BIT(0))\r
-#define LEDC_APB_CLK_SEL_V 0x1\r
-#define LEDC_APB_CLK_SEL_S 0\r
-\r
-#define LEDC_DATE_REG (DR_REG_LEDC_BASE + 0x01FC)\r
-/* LEDC_DATE : R/W ;bitpos:[31:0] ;default: 32'h16031700 ; */\r
-/*description: This register represents the version .*/\r
-#define LEDC_DATE 0xFFFFFFFF\r
-#define LEDC_DATE_M ((LEDC_DATE_V)<<(LEDC_DATE_S))\r
-#define LEDC_DATE_V 0xFFFFFFFF\r
-#define LEDC_DATE_S 0\r
-\r
-\r
-\r
-\r
-#endif /*_SOC_LEDC_REG_H_ */\r
-\r
-\r
+// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+#ifndef _SOC_LEDC_REG_H_
+#define _SOC_LEDC_REG_H_
+
+
+#include "soc.h"
+#define LEDC_HSCH0_CONF0_REG (DR_REG_LEDC_BASE + 0x0000)
+/* LEDC_CLK_EN : R/W ;bitpos:[31] ;default: 1'h0 ; */
+/*description: This bit is clock gating control signal. when software config
+ LED_PWM internal registers it controls the register clock.*/
+#define LEDC_CLK_EN (BIT(31))
+#define LEDC_CLK_EN_M (BIT(31))
+#define LEDC_CLK_EN_V 0x1
+#define LEDC_CLK_EN_S 31
+/* LEDC_IDLE_LV_HSCH0 : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: This bit is used to control the output value when high speed channel0 is off.*/
+#define LEDC_IDLE_LV_HSCH0 (BIT(3))
+#define LEDC_IDLE_LV_HSCH0_M (BIT(3))
+#define LEDC_IDLE_LV_HSCH0_V 0x1
+#define LEDC_IDLE_LV_HSCH0_S 3
+/* LEDC_SIG_OUT_EN_HSCH0 : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: This is the output enable control bit for high speed channel0*/
+#define LEDC_SIG_OUT_EN_HSCH0 (BIT(2))
+#define LEDC_SIG_OUT_EN_HSCH0_M (BIT(2))
+#define LEDC_SIG_OUT_EN_HSCH0_V 0x1
+#define LEDC_SIG_OUT_EN_HSCH0_S 2
+/* LEDC_TIMER_SEL_HSCH0 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */
+/*description: There are four high speed timers the two bits are used to select
+ one of them for high speed channel0. 2'b00: seletc hstimer0. 2'b01: select hstimer1. 2'b10: select hstimer2. 2'b11: select hstimer3.*/
+#define LEDC_TIMER_SEL_HSCH0 0x00000003
+#define LEDC_TIMER_SEL_HSCH0_M ((LEDC_TIMER_SEL_HSCH0_V)<<(LEDC_TIMER_SEL_HSCH0_S))
+#define LEDC_TIMER_SEL_HSCH0_V 0x3
+#define LEDC_TIMER_SEL_HSCH0_S 0
+
+#define LEDC_HSCH0_HPOINT_REG (DR_REG_LEDC_BASE + 0x0004)
+/* LEDC_HPOINT_HSCH0 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */
+/*description: The output value changes to high when htimerx(x=[0 3]) selected
+ by high speed channel0 has reached reg_hpoint_hsch0[19:0]*/
+#define LEDC_HPOINT_HSCH0 0x000FFFFF
+#define LEDC_HPOINT_HSCH0_M ((LEDC_HPOINT_HSCH0_V)<<(LEDC_HPOINT_HSCH0_S))
+#define LEDC_HPOINT_HSCH0_V 0xFFFFF
+#define LEDC_HPOINT_HSCH0_S 0
+
+#define LEDC_HSCH0_DUTY_REG (DR_REG_LEDC_BASE + 0x0008)
+/* LEDC_DUTY_HSCH0 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */
+/*description: The register is used to control output duty. When hstimerx(x=[0
+ 3]) choosed by high speed channel0 has reached reg_lpoint_hsch0 the output signal changes to low. reg_lpoint_hsch0=(reg_hpoint_hsch0[19:0]+reg_duty_hsch0[24:4]) (1) reg_lpoint_hsch0=(reg_hpoint_hsch0[19:0]+reg_duty_hsch0[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/
+#define LEDC_DUTY_HSCH0 0x01FFFFFF
+#define LEDC_DUTY_HSCH0_M ((LEDC_DUTY_HSCH0_V)<<(LEDC_DUTY_HSCH0_S))
+#define LEDC_DUTY_HSCH0_V 0x1FFFFFF
+#define LEDC_DUTY_HSCH0_S 0
+
+#define LEDC_HSCH0_CONF1_REG (DR_REG_LEDC_BASE + 0x000C)
+/* LEDC_DUTY_START_HSCH0 : R/W ;bitpos:[31] ;default: 1'b0 ; */
+/*description: When reg_duty_num_hsch0 reg_duty_cycle_hsch0 and reg_duty_scale_hsch0
+ has been configured. these register won't take effect until set reg_duty_start_hsch0. this bit is automatically cleared by hardware.*/
+#define LEDC_DUTY_START_HSCH0 (BIT(31))
+#define LEDC_DUTY_START_HSCH0_M (BIT(31))
+#define LEDC_DUTY_START_HSCH0_V 0x1
+#define LEDC_DUTY_START_HSCH0_S 31
+/* LEDC_DUTY_INC_HSCH0 : R/W ;bitpos:[30] ;default: 1'b1 ; */
+/*description: This register is used to increase the duty of output signal or
+ decrease the duty of output signal for high speed channel0.*/
+#define LEDC_DUTY_INC_HSCH0 (BIT(30))
+#define LEDC_DUTY_INC_HSCH0_M (BIT(30))
+#define LEDC_DUTY_INC_HSCH0_V 0x1
+#define LEDC_DUTY_INC_HSCH0_S 30
+/* LEDC_DUTY_NUM_HSCH0 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */
+/*description: This register is used to control the num of increased or decreased
+ times for high speed channel0.*/
+#define LEDC_DUTY_NUM_HSCH0 0x000003FF
+#define LEDC_DUTY_NUM_HSCH0_M ((LEDC_DUTY_NUM_HSCH0_V)<<(LEDC_DUTY_NUM_HSCH0_S))
+#define LEDC_DUTY_NUM_HSCH0_V 0x3FF
+#define LEDC_DUTY_NUM_HSCH0_S 20
+/* LEDC_DUTY_CYCLE_HSCH0 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */
+/*description: This register is used to increase or decrease the duty every
+ reg_duty_cycle_hsch0 cycles for high speed channel0.*/
+#define LEDC_DUTY_CYCLE_HSCH0 0x000003FF
+#define LEDC_DUTY_CYCLE_HSCH0_M ((LEDC_DUTY_CYCLE_HSCH0_V)<<(LEDC_DUTY_CYCLE_HSCH0_S))
+#define LEDC_DUTY_CYCLE_HSCH0_V 0x3FF
+#define LEDC_DUTY_CYCLE_HSCH0_S 10
+/* LEDC_DUTY_SCALE_HSCH0 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */
+/*description: This register controls the increase or decrease step scale for
+ high speed channel0.*/
+#define LEDC_DUTY_SCALE_HSCH0 0x000003FF
+#define LEDC_DUTY_SCALE_HSCH0_M ((LEDC_DUTY_SCALE_HSCH0_V)<<(LEDC_DUTY_SCALE_HSCH0_S))
+#define LEDC_DUTY_SCALE_HSCH0_V 0x3FF
+#define LEDC_DUTY_SCALE_HSCH0_S 0
+
+#define LEDC_HSCH0_DUTY_R_REG (DR_REG_LEDC_BASE + 0x0010)
+/* LEDC_DUTY_HSCH0 : RO ;bitpos:[24:0] ;default: 25'h0 ; */
+/*description: This register represents the current duty of the output signal
+ for high speed channel0.*/
+#define LEDC_DUTY_HSCH0 0x01FFFFFF
+#define LEDC_DUTY_HSCH0_M ((LEDC_DUTY_HSCH0_V)<<(LEDC_DUTY_HSCH0_S))
+#define LEDC_DUTY_HSCH0_V 0x1FFFFFF
+#define LEDC_DUTY_HSCH0_S 0
+
+#define LEDC_HSCH1_CONF0_REG (DR_REG_LEDC_BASE + 0x0014)
+/* LEDC_IDLE_LV_HSCH1 : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: This bit is used to control the output value when high speed channel1 is off.*/
+#define LEDC_IDLE_LV_HSCH1 (BIT(3))
+#define LEDC_IDLE_LV_HSCH1_M (BIT(3))
+#define LEDC_IDLE_LV_HSCH1_V 0x1
+#define LEDC_IDLE_LV_HSCH1_S 3
+/* LEDC_SIG_OUT_EN_HSCH1 : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: This is the output enable control bit for high speed channel1*/
+#define LEDC_SIG_OUT_EN_HSCH1 (BIT(2))
+#define LEDC_SIG_OUT_EN_HSCH1_M (BIT(2))
+#define LEDC_SIG_OUT_EN_HSCH1_V 0x1
+#define LEDC_SIG_OUT_EN_HSCH1_S 2
+/* LEDC_TIMER_SEL_HSCH1 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */
+/*description: There are four high speed timers the two bits are used to select
+ one of them for high speed channel1. 2'b00: seletc hstimer0. 2'b01: select hstimer1. 2'b10: select hstimer2. 2'b11: select hstimer3.*/
+#define LEDC_TIMER_SEL_HSCH1 0x00000003
+#define LEDC_TIMER_SEL_HSCH1_M ((LEDC_TIMER_SEL_HSCH1_V)<<(LEDC_TIMER_SEL_HSCH1_S))
+#define LEDC_TIMER_SEL_HSCH1_V 0x3
+#define LEDC_TIMER_SEL_HSCH1_S 0
+
+#define LEDC_HSCH1_HPOINT_REG (DR_REG_LEDC_BASE + 0x0018)
+/* LEDC_HPOINT_HSCH1 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */
+/*description: The output value changes to high when htimerx(x=[0 3]) selected
+ by high speed channel1 has reached reg_hpoint_hsch1[19:0]*/
+#define LEDC_HPOINT_HSCH1 0x000FFFFF
+#define LEDC_HPOINT_HSCH1_M ((LEDC_HPOINT_HSCH1_V)<<(LEDC_HPOINT_HSCH1_S))
+#define LEDC_HPOINT_HSCH1_V 0xFFFFF
+#define LEDC_HPOINT_HSCH1_S 0
+
+#define LEDC_HSCH1_DUTY_REG (DR_REG_LEDC_BASE + 0x001C)
+/* LEDC_DUTY_HSCH1 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */
+/*description: The register is used to control output duty. When hstimerx(x=[0
+ 3]) choosed by high speed channel1 has reached reg_lpoint_hsch1 the output signal changes to low. reg_lpoint_hsch1=(reg_hpoint_hsch1[19:0]+reg_duty_hsch1[24:4]) (1) reg_lpoint_hsch1=(reg_hpoint_hsch1[19:0]+reg_duty_hsch1[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/
+#define LEDC_DUTY_HSCH1 0x01FFFFFF
+#define LEDC_DUTY_HSCH1_M ((LEDC_DUTY_HSCH1_V)<<(LEDC_DUTY_HSCH1_S))
+#define LEDC_DUTY_HSCH1_V 0x1FFFFFF
+#define LEDC_DUTY_HSCH1_S 0
+
+#define LEDC_HSCH1_CONF1_REG (DR_REG_LEDC_BASE + 0x0020)
+/* LEDC_DUTY_START_HSCH1 : R/W ;bitpos:[31] ;default: 1'b0 ; */
+/*description: When reg_duty_num_hsch1 reg_duty_cycle_hsch1 and reg_duty_scale_hsch1
+ has been configured. these register won't take effect until set reg_duty_start_hsch1. this bit is automatically cleared by hardware.*/
+#define LEDC_DUTY_START_HSCH1 (BIT(31))
+#define LEDC_DUTY_START_HSCH1_M (BIT(31))
+#define LEDC_DUTY_START_HSCH1_V 0x1
+#define LEDC_DUTY_START_HSCH1_S 31
+/* LEDC_DUTY_INC_HSCH1 : R/W ;bitpos:[30] ;default: 1'b1 ; */
+/*description: This register is used to increase the duty of output signal or
+ decrease the duty of output signal for high speed channel1.*/
+#define LEDC_DUTY_INC_HSCH1 (BIT(30))
+#define LEDC_DUTY_INC_HSCH1_M (BIT(30))
+#define LEDC_DUTY_INC_HSCH1_V 0x1
+#define LEDC_DUTY_INC_HSCH1_S 30
+/* LEDC_DUTY_NUM_HSCH1 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */
+/*description: This register is used to control the num of increased or decreased
+ times for high speed channel1.*/
+#define LEDC_DUTY_NUM_HSCH1 0x000003FF
+#define LEDC_DUTY_NUM_HSCH1_M ((LEDC_DUTY_NUM_HSCH1_V)<<(LEDC_DUTY_NUM_HSCH1_S))
+#define LEDC_DUTY_NUM_HSCH1_V 0x3FF
+#define LEDC_DUTY_NUM_HSCH1_S 20
+/* LEDC_DUTY_CYCLE_HSCH1 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */
+/*description: This register is used to increase or decrease the duty every
+ reg_duty_cycle_hsch1 cycles for high speed channel1.*/
+#define LEDC_DUTY_CYCLE_HSCH1 0x000003FF
+#define LEDC_DUTY_CYCLE_HSCH1_M ((LEDC_DUTY_CYCLE_HSCH1_V)<<(LEDC_DUTY_CYCLE_HSCH1_S))
+#define LEDC_DUTY_CYCLE_HSCH1_V 0x3FF
+#define LEDC_DUTY_CYCLE_HSCH1_S 10
+/* LEDC_DUTY_SCALE_HSCH1 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */
+/*description: This register controls the increase or decrease step scale for
+ high speed channel1.*/
+#define LEDC_DUTY_SCALE_HSCH1 0x000003FF
+#define LEDC_DUTY_SCALE_HSCH1_M ((LEDC_DUTY_SCALE_HSCH1_V)<<(LEDC_DUTY_SCALE_HSCH1_S))
+#define LEDC_DUTY_SCALE_HSCH1_V 0x3FF
+#define LEDC_DUTY_SCALE_HSCH1_S 0
+
+#define LEDC_HSCH1_DUTY_R_REG (DR_REG_LEDC_BASE + 0x0024)
+/* LEDC_DUTY_HSCH1 : RO ;bitpos:[24:0] ;default: 25'h0 ; */
+/*description: This register represents the current duty of the output signal
+ for high speed channel1.*/
+#define LEDC_DUTY_HSCH1 0x01FFFFFF
+#define LEDC_DUTY_HSCH1_M ((LEDC_DUTY_HSCH1_V)<<(LEDC_DUTY_HSCH1_S))
+#define LEDC_DUTY_HSCH1_V 0x1FFFFFF
+#define LEDC_DUTY_HSCH1_S 0
+
+#define LEDC_HSCH2_CONF0_REG (DR_REG_LEDC_BASE + 0x0028)
+/* LEDC_IDLE_LV_HSCH2 : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: This bit is used to control the output value when high speed channel2 is off.*/
+#define LEDC_IDLE_LV_HSCH2 (BIT(3))
+#define LEDC_IDLE_LV_HSCH2_M (BIT(3))
+#define LEDC_IDLE_LV_HSCH2_V 0x1
+#define LEDC_IDLE_LV_HSCH2_S 3
+/* LEDC_SIG_OUT_EN_HSCH2 : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: This is the output enable control bit for high speed channel2*/
+#define LEDC_SIG_OUT_EN_HSCH2 (BIT(2))
+#define LEDC_SIG_OUT_EN_HSCH2_M (BIT(2))
+#define LEDC_SIG_OUT_EN_HSCH2_V 0x1
+#define LEDC_SIG_OUT_EN_HSCH2_S 2
+/* LEDC_TIMER_SEL_HSCH2 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */
+/*description: There are four high speed timers the two bits are used to select
+ one of them for high speed channel2. 2'b00: seletc hstimer0. 2'b01: select hstimer1. 2'b10: select hstimer2. 2'b11: select hstimer3.*/
+#define LEDC_TIMER_SEL_HSCH2 0x00000003
+#define LEDC_TIMER_SEL_HSCH2_M ((LEDC_TIMER_SEL_HSCH2_V)<<(LEDC_TIMER_SEL_HSCH2_S))
+#define LEDC_TIMER_SEL_HSCH2_V 0x3
+#define LEDC_TIMER_SEL_HSCH2_S 0
+
+#define LEDC_HSCH2_HPOINT_REG (DR_REG_LEDC_BASE + 0x002C)
+/* LEDC_HPOINT_HSCH2 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */
+/*description: The output value changes to high when htimerx(x=[0 3]) selected
+ by high speed channel2 has reached reg_hpoint_hsch2[19:0]*/
+#define LEDC_HPOINT_HSCH2 0x000FFFFF
+#define LEDC_HPOINT_HSCH2_M ((LEDC_HPOINT_HSCH2_V)<<(LEDC_HPOINT_HSCH2_S))
+#define LEDC_HPOINT_HSCH2_V 0xFFFFF
+#define LEDC_HPOINT_HSCH2_S 0
+
+#define LEDC_HSCH2_DUTY_REG (DR_REG_LEDC_BASE + 0x0030)
+/* LEDC_DUTY_HSCH2 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */
+/*description: The register is used to control output duty. When hstimerx(x=[0
+ 3]) choosed by high speed channel2 has reached reg_lpoint_hsch2 the output signal changes to low. reg_lpoint_hsch2=(reg_hpoint_hsch2[19:0]+reg_duty_hsch2[24:4]) (1) reg_lpoint_hsch2=(reg_hpoint_hsch2[19:0]+reg_duty_hsch2[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/
+#define LEDC_DUTY_HSCH2 0x01FFFFFF
+#define LEDC_DUTY_HSCH2_M ((LEDC_DUTY_HSCH2_V)<<(LEDC_DUTY_HSCH2_S))
+#define LEDC_DUTY_HSCH2_V 0x1FFFFFF
+#define LEDC_DUTY_HSCH2_S 0
+
+#define LEDC_HSCH2_CONF1_REG (DR_REG_LEDC_BASE + 0x0034)
+/* LEDC_DUTY_START_HSCH2 : R/W ;bitpos:[31] ;default: 1'b0 ; */
+/*description: When reg_duty_num_hsch2 reg_duty_cycle_hsch2 and reg_duty_scale_hsch2
+ has been configured. these register won't take effect until set reg_duty_start_hsch2. this bit is automatically cleared by hardware.*/
+#define LEDC_DUTY_START_HSCH2 (BIT(31))
+#define LEDC_DUTY_START_HSCH2_M (BIT(31))
+#define LEDC_DUTY_START_HSCH2_V 0x1
+#define LEDC_DUTY_START_HSCH2_S 31
+/* LEDC_DUTY_INC_HSCH2 : R/W ;bitpos:[30] ;default: 1'b1 ; */
+/*description: This register is used to increase the duty of output signal or
+ decrease the duty of output signal for high speed channel2.*/
+#define LEDC_DUTY_INC_HSCH2 (BIT(30))
+#define LEDC_DUTY_INC_HSCH2_M (BIT(30))
+#define LEDC_DUTY_INC_HSCH2_V 0x1
+#define LEDC_DUTY_INC_HSCH2_S 30
+/* LEDC_DUTY_NUM_HSCH2 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */
+/*description: This register is used to control the num of increased or decreased
+ times for high speed channel2.*/
+#define LEDC_DUTY_NUM_HSCH2 0x000003FF
+#define LEDC_DUTY_NUM_HSCH2_M ((LEDC_DUTY_NUM_HSCH2_V)<<(LEDC_DUTY_NUM_HSCH2_S))
+#define LEDC_DUTY_NUM_HSCH2_V 0x3FF
+#define LEDC_DUTY_NUM_HSCH2_S 20
+/* LEDC_DUTY_CYCLE_HSCH2 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */
+/*description: This register is used to increase or decrease the duty every
+ reg_duty_cycle_hsch2 cycles for high speed channel2.*/
+#define LEDC_DUTY_CYCLE_HSCH2 0x000003FF
+#define LEDC_DUTY_CYCLE_HSCH2_M ((LEDC_DUTY_CYCLE_HSCH2_V)<<(LEDC_DUTY_CYCLE_HSCH2_S))
+#define LEDC_DUTY_CYCLE_HSCH2_V 0x3FF
+#define LEDC_DUTY_CYCLE_HSCH2_S 10
+/* LEDC_DUTY_SCALE_HSCH2 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */
+/*description: This register controls the increase or decrease step scale for
+ high speed channel2.*/
+#define LEDC_DUTY_SCALE_HSCH2 0x000003FF
+#define LEDC_DUTY_SCALE_HSCH2_M ((LEDC_DUTY_SCALE_HSCH2_V)<<(LEDC_DUTY_SCALE_HSCH2_S))
+#define LEDC_DUTY_SCALE_HSCH2_V 0x3FF
+#define LEDC_DUTY_SCALE_HSCH2_S 0
+
+#define LEDC_HSCH2_DUTY_R_REG (DR_REG_LEDC_BASE + 0x0038)
+/* LEDC_DUTY_HSCH2 : RO ;bitpos:[24:0] ;default: 25'h0 ; */
+/*description: This register represents the current duty of the output signal
+ for high speed channel2.*/
+#define LEDC_DUTY_HSCH2 0x01FFFFFF
+#define LEDC_DUTY_HSCH2_M ((LEDC_DUTY_HSCH2_V)<<(LEDC_DUTY_HSCH2_S))
+#define LEDC_DUTY_HSCH2_V 0x1FFFFFF
+#define LEDC_DUTY_HSCH2_S 0
+
+#define LEDC_HSCH3_CONF0_REG (DR_REG_LEDC_BASE + 0x003C)
+/* LEDC_IDLE_LV_HSCH3 : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: This bit is used to control the output value when high speed channel3 is off.*/
+#define LEDC_IDLE_LV_HSCH3 (BIT(3))
+#define LEDC_IDLE_LV_HSCH3_M (BIT(3))
+#define LEDC_IDLE_LV_HSCH3_V 0x1
+#define LEDC_IDLE_LV_HSCH3_S 3
+/* LEDC_SIG_OUT_EN_HSCH3 : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: This is the output enable control bit for high speed channel3*/
+#define LEDC_SIG_OUT_EN_HSCH3 (BIT(2))
+#define LEDC_SIG_OUT_EN_HSCH3_M (BIT(2))
+#define LEDC_SIG_OUT_EN_HSCH3_V 0x1
+#define LEDC_SIG_OUT_EN_HSCH3_S 2
+/* LEDC_TIMER_SEL_HSCH3 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */
+/*description: There are four high speed timers the two bits are used to select
+ one of them for high speed channel3. 2'b00: seletc hstimer0. 2'b01: select hstimer1. 2'b10: select hstimer2. 2'b11: select hstimer3.*/
+#define LEDC_TIMER_SEL_HSCH3 0x00000003
+#define LEDC_TIMER_SEL_HSCH3_M ((LEDC_TIMER_SEL_HSCH3_V)<<(LEDC_TIMER_SEL_HSCH3_S))
+#define LEDC_TIMER_SEL_HSCH3_V 0x3
+#define LEDC_TIMER_SEL_HSCH3_S 0
+
+#define LEDC_HSCH3_HPOINT_REG (DR_REG_LEDC_BASE + 0x0040)
+/* LEDC_HPOINT_HSCH3 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */
+/*description: The output value changes to high when htimerx(x=[0 3]) selected
+ by high speed channel3 has reached reg_hpoint_hsch3[19:0]*/
+#define LEDC_HPOINT_HSCH3 0x000FFFFF
+#define LEDC_HPOINT_HSCH3_M ((LEDC_HPOINT_HSCH3_V)<<(LEDC_HPOINT_HSCH3_S))
+#define LEDC_HPOINT_HSCH3_V 0xFFFFF
+#define LEDC_HPOINT_HSCH3_S 0
+
+#define LEDC_HSCH3_DUTY_REG (DR_REG_LEDC_BASE + 0x0044)
+/* LEDC_DUTY_HSCH3 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */
+/*description: The register is used to control output duty. When hstimerx(x=[0
+ 3]) choosed by high speed channel3 has reached reg_lpoint_hsch3 the output signal changes to low. reg_lpoint_hsch3=(reg_hpoint_hsch3[19:0]+reg_duty_hsch3[24:4]) (1) reg_lpoint_hsch3=(reg_hpoint_hsch3[19:0]+reg_duty_hsch3[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/
+#define LEDC_DUTY_HSCH3 0x01FFFFFF
+#define LEDC_DUTY_HSCH3_M ((LEDC_DUTY_HSCH3_V)<<(LEDC_DUTY_HSCH3_S))
+#define LEDC_DUTY_HSCH3_V 0x1FFFFFF
+#define LEDC_DUTY_HSCH3_S 0
+
+#define LEDC_HSCH3_CONF1_REG (DR_REG_LEDC_BASE + 0x0048)
+/* LEDC_DUTY_START_HSCH3 : R/W ;bitpos:[31] ;default: 1'b0 ; */
+/*description: When reg_duty_num_hsch3 reg_duty_cycle_hsch3 and reg_duty_scale_hsch3
+ has been configured. these register won't take effect until set reg_duty_start_hsch3. this bit is automatically cleared by hardware.*/
+#define LEDC_DUTY_START_HSCH3 (BIT(31))
+#define LEDC_DUTY_START_HSCH3_M (BIT(31))
+#define LEDC_DUTY_START_HSCH3_V 0x1
+#define LEDC_DUTY_START_HSCH3_S 31
+/* LEDC_DUTY_INC_HSCH3 : R/W ;bitpos:[30] ;default: 1'b1 ; */
+/*description: This register is used to increase the duty of output signal or
+ decrease the duty of output signal for high speed channel3.*/
+#define LEDC_DUTY_INC_HSCH3 (BIT(30))
+#define LEDC_DUTY_INC_HSCH3_M (BIT(30))
+#define LEDC_DUTY_INC_HSCH3_V 0x1
+#define LEDC_DUTY_INC_HSCH3_S 30
+/* LEDC_DUTY_NUM_HSCH3 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */
+/*description: This register is used to control the num of increased or decreased
+ times for high speed channel3.*/
+#define LEDC_DUTY_NUM_HSCH3 0x000003FF
+#define LEDC_DUTY_NUM_HSCH3_M ((LEDC_DUTY_NUM_HSCH3_V)<<(LEDC_DUTY_NUM_HSCH3_S))
+#define LEDC_DUTY_NUM_HSCH3_V 0x3FF
+#define LEDC_DUTY_NUM_HSCH3_S 20
+/* LEDC_DUTY_CYCLE_HSCH3 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */
+/*description: This register is used to increase or decrease the duty every
+ reg_duty_cycle_hsch3 cycles for high speed channel3.*/
+#define LEDC_DUTY_CYCLE_HSCH3 0x000003FF
+#define LEDC_DUTY_CYCLE_HSCH3_M ((LEDC_DUTY_CYCLE_HSCH3_V)<<(LEDC_DUTY_CYCLE_HSCH3_S))
+#define LEDC_DUTY_CYCLE_HSCH3_V 0x3FF
+#define LEDC_DUTY_CYCLE_HSCH3_S 10
+/* LEDC_DUTY_SCALE_HSCH3 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */
+/*description: This register controls the increase or decrease step scale for
+ high speed channel3.*/
+#define LEDC_DUTY_SCALE_HSCH3 0x000003FF
+#define LEDC_DUTY_SCALE_HSCH3_M ((LEDC_DUTY_SCALE_HSCH3_V)<<(LEDC_DUTY_SCALE_HSCH3_S))
+#define LEDC_DUTY_SCALE_HSCH3_V 0x3FF
+#define LEDC_DUTY_SCALE_HSCH3_S 0
+
+#define LEDC_HSCH3_DUTY_R_REG (DR_REG_LEDC_BASE + 0x004C)
+/* LEDC_DUTY_HSCH3 : RO ;bitpos:[24:0] ;default: 25'h0 ; */
+/*description: This register represents the current duty of the output signal
+ for high speed channel3.*/
+#define LEDC_DUTY_HSCH3 0x01FFFFFF
+#define LEDC_DUTY_HSCH3_M ((LEDC_DUTY_HSCH3_V)<<(LEDC_DUTY_HSCH3_S))
+#define LEDC_DUTY_HSCH3_V 0x1FFFFFF
+#define LEDC_DUTY_HSCH3_S 0
+
+#define LEDC_HSCH4_CONF0_REG (DR_REG_LEDC_BASE + 0x0050)
+/* LEDC_IDLE_LV_HSCH4 : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: This bit is used to control the output value when high speed channel4 is off.*/
+#define LEDC_IDLE_LV_HSCH4 (BIT(3))
+#define LEDC_IDLE_LV_HSCH4_M (BIT(3))
+#define LEDC_IDLE_LV_HSCH4_V 0x1
+#define LEDC_IDLE_LV_HSCH4_S 3
+/* LEDC_SIG_OUT_EN_HSCH4 : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: This is the output enable control bit for high speed channel4*/
+#define LEDC_SIG_OUT_EN_HSCH4 (BIT(2))
+#define LEDC_SIG_OUT_EN_HSCH4_M (BIT(2))
+#define LEDC_SIG_OUT_EN_HSCH4_V 0x1
+#define LEDC_SIG_OUT_EN_HSCH4_S 2
+/* LEDC_TIMER_SEL_HSCH4 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */
+/*description: There are four high speed timers the two bits are used to select
+ one of them for high speed channel4. 2'b00: seletc hstimer0. 2'b01: select hstimer1. 2'b10: select hstimer2. 2'b11: select hstimer3.*/
+#define LEDC_TIMER_SEL_HSCH4 0x00000003
+#define LEDC_TIMER_SEL_HSCH4_M ((LEDC_TIMER_SEL_HSCH4_V)<<(LEDC_TIMER_SEL_HSCH4_S))
+#define LEDC_TIMER_SEL_HSCH4_V 0x3
+#define LEDC_TIMER_SEL_HSCH4_S 0
+
+#define LEDC_HSCH4_HPOINT_REG (DR_REG_LEDC_BASE + 0x0054)
+/* LEDC_HPOINT_HSCH4 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */
+/*description: The output value changes to high when htimerx(x=[0 3]) selected
+ by high speed channel4 has reached reg_hpoint_hsch4[19:0]*/
+#define LEDC_HPOINT_HSCH4 0x000FFFFF
+#define LEDC_HPOINT_HSCH4_M ((LEDC_HPOINT_HSCH4_V)<<(LEDC_HPOINT_HSCH4_S))
+#define LEDC_HPOINT_HSCH4_V 0xFFFFF
+#define LEDC_HPOINT_HSCH4_S 0
+
+#define LEDC_HSCH4_DUTY_REG (DR_REG_LEDC_BASE + 0x0058)
+/* LEDC_DUTY_HSCH4 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */
+/*description: The register is used to control output duty. When hstimerx(x=[0
+ 3]) choosed by high speed channel4 has reached reg_lpoint_hsch4 the output signal changes to low. reg_lpoint_hsch4=(reg_hpoint_hsch4[19:0]+reg_duty_hsch4[24:4]) (1) reg_lpoint_hsch4=(reg_hpoint_hsch4[19:0]+reg_duty_hsch4[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/
+#define LEDC_DUTY_HSCH4 0x01FFFFFF
+#define LEDC_DUTY_HSCH4_M ((LEDC_DUTY_HSCH4_V)<<(LEDC_DUTY_HSCH4_S))
+#define LEDC_DUTY_HSCH4_V 0x1FFFFFF
+#define LEDC_DUTY_HSCH4_S 0
+
+#define LEDC_HSCH4_CONF1_REG (DR_REG_LEDC_BASE + 0x005C)
+/* LEDC_DUTY_START_HSCH4 : R/W ;bitpos:[31] ;default: 1'b0 ; */
+/*description: When reg_duty_num_hsch1 reg_duty_cycle_hsch1 and reg_duty_scale_hsch1
+ has been configured. these register won't take effect until set reg_duty_start_hsch1. this bit is automatically cleared by hardware.*/
+#define LEDC_DUTY_START_HSCH4 (BIT(31))
+#define LEDC_DUTY_START_HSCH4_M (BIT(31))
+#define LEDC_DUTY_START_HSCH4_V 0x1
+#define LEDC_DUTY_START_HSCH4_S 31
+/* LEDC_DUTY_INC_HSCH4 : R/W ;bitpos:[30] ;default: 1'b1 ; */
+/*description: This register is used to increase the duty of output signal or
+ decrease the duty of output signal for high speed channel4.*/
+#define LEDC_DUTY_INC_HSCH4 (BIT(30))
+#define LEDC_DUTY_INC_HSCH4_M (BIT(30))
+#define LEDC_DUTY_INC_HSCH4_V 0x1
+#define LEDC_DUTY_INC_HSCH4_S 30
+/* LEDC_DUTY_NUM_HSCH4 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */
+/*description: This register is used to control the num of increased or decreased
+ times for high speed channel1.*/
+#define LEDC_DUTY_NUM_HSCH4 0x000003FF
+#define LEDC_DUTY_NUM_HSCH4_M ((LEDC_DUTY_NUM_HSCH4_V)<<(LEDC_DUTY_NUM_HSCH4_S))
+#define LEDC_DUTY_NUM_HSCH4_V 0x3FF
+#define LEDC_DUTY_NUM_HSCH4_S 20
+/* LEDC_DUTY_CYCLE_HSCH4 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */
+/*description: This register is used to increase or decrease the duty every
+ reg_duty_cycle_hsch4 cycles for high speed channel4.*/
+#define LEDC_DUTY_CYCLE_HSCH4 0x000003FF
+#define LEDC_DUTY_CYCLE_HSCH4_M ((LEDC_DUTY_CYCLE_HSCH4_V)<<(LEDC_DUTY_CYCLE_HSCH4_S))
+#define LEDC_DUTY_CYCLE_HSCH4_V 0x3FF
+#define LEDC_DUTY_CYCLE_HSCH4_S 10
+/* LEDC_DUTY_SCALE_HSCH4 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */
+/*description: This register controls the increase or decrease step scale for
+ high speed channel4.*/
+#define LEDC_DUTY_SCALE_HSCH4 0x000003FF
+#define LEDC_DUTY_SCALE_HSCH4_M ((LEDC_DUTY_SCALE_HSCH4_V)<<(LEDC_DUTY_SCALE_HSCH4_S))
+#define LEDC_DUTY_SCALE_HSCH4_V 0x3FF
+#define LEDC_DUTY_SCALE_HSCH4_S 0
+
+#define LEDC_HSCH4_DUTY_R_REG (DR_REG_LEDC_BASE + 0x0060)
+/* LEDC_DUTY_HSCH4 : RO ;bitpos:[24:0] ;default: 25'h0 ; */
+/*description: This register represents the current duty of the output signal
+ for high speed channel4.*/
+#define LEDC_DUTY_HSCH4 0x01FFFFFF
+#define LEDC_DUTY_HSCH4_M ((LEDC_DUTY_HSCH4_V)<<(LEDC_DUTY_HSCH4_S))
+#define LEDC_DUTY_HSCH4_V 0x1FFFFFF
+#define LEDC_DUTY_HSCH4_S 0
+
+#define LEDC_HSCH5_CONF0_REG (DR_REG_LEDC_BASE + 0x0064)
+/* LEDC_IDLE_LV_HSCH5 : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: This bit is used to control the output value when high speed channel5 is off.*/
+#define LEDC_IDLE_LV_HSCH5 (BIT(3))
+#define LEDC_IDLE_LV_HSCH5_M (BIT(3))
+#define LEDC_IDLE_LV_HSCH5_V 0x1
+#define LEDC_IDLE_LV_HSCH5_S 3
+/* LEDC_SIG_OUT_EN_HSCH5 : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: This is the output enable control bit for high speed channel5.*/
+#define LEDC_SIG_OUT_EN_HSCH5 (BIT(2))
+#define LEDC_SIG_OUT_EN_HSCH5_M (BIT(2))
+#define LEDC_SIG_OUT_EN_HSCH5_V 0x1
+#define LEDC_SIG_OUT_EN_HSCH5_S 2
+/* LEDC_TIMER_SEL_HSCH5 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */
+/*description: There are four high speed timers the two bits are used to select
+ one of them for high speed channel5. 2'b00: seletc hstimer0. 2'b01: select hstimer1. 2'b10: select hstimer2. 2'b11: select hstimer3.*/
+#define LEDC_TIMER_SEL_HSCH5 0x00000003
+#define LEDC_TIMER_SEL_HSCH5_M ((LEDC_TIMER_SEL_HSCH5_V)<<(LEDC_TIMER_SEL_HSCH5_S))
+#define LEDC_TIMER_SEL_HSCH5_V 0x3
+#define LEDC_TIMER_SEL_HSCH5_S 0
+
+#define LEDC_HSCH5_HPOINT_REG (DR_REG_LEDC_BASE + 0x0068)
+/* LEDC_HPOINT_HSCH5 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */
+/*description: The output value changes to high when htimerx(x=[0 3]) selected
+ by high speed channel5 has reached reg_hpoint_hsch5[19:0]*/
+#define LEDC_HPOINT_HSCH5 0x000FFFFF
+#define LEDC_HPOINT_HSCH5_M ((LEDC_HPOINT_HSCH5_V)<<(LEDC_HPOINT_HSCH5_S))
+#define LEDC_HPOINT_HSCH5_V 0xFFFFF
+#define LEDC_HPOINT_HSCH5_S 0
+
+#define LEDC_HSCH5_DUTY_REG (DR_REG_LEDC_BASE + 0x006C)
+/* LEDC_DUTY_HSCH5 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */
+/*description: The register is used to control output duty. When hstimerx(x=[0
+ 3]) choosed by high speed channel5 has reached reg_lpoint_hsch5 the output signal changes to low. reg_lpoint_hsch5=(reg_hpoint_hsch5[19:0]+reg_duty_hsch5[24:4]) (1) reg_lpoint_hsch5=(reg_hpoint_hsch5[19:0]+reg_duty_hsch5[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/
+#define LEDC_DUTY_HSCH5 0x01FFFFFF
+#define LEDC_DUTY_HSCH5_M ((LEDC_DUTY_HSCH5_V)<<(LEDC_DUTY_HSCH5_S))
+#define LEDC_DUTY_HSCH5_V 0x1FFFFFF
+#define LEDC_DUTY_HSCH5_S 0
+
+#define LEDC_HSCH5_CONF1_REG (DR_REG_LEDC_BASE + 0x0070)
+/* LEDC_DUTY_START_HSCH5 : R/W ;bitpos:[31] ;default: 1'b0 ; */
+/*description: When reg_duty_num_hsch5 reg_duty_cycle_hsch5 and reg_duty_scale_hsch5
+ has been configured. these register won't take effect until set reg_duty_start_hsch5. this bit is automatically cleared by hardware.*/
+#define LEDC_DUTY_START_HSCH5 (BIT(31))
+#define LEDC_DUTY_START_HSCH5_M (BIT(31))
+#define LEDC_DUTY_START_HSCH5_V 0x1
+#define LEDC_DUTY_START_HSCH5_S 31
+/* LEDC_DUTY_INC_HSCH5 : R/W ;bitpos:[30] ;default: 1'b1 ; */
+/*description: This register is used to increase the duty of output signal or
+ decrease the duty of output signal for high speed channel5.*/
+#define LEDC_DUTY_INC_HSCH5 (BIT(30))
+#define LEDC_DUTY_INC_HSCH5_M (BIT(30))
+#define LEDC_DUTY_INC_HSCH5_V 0x1
+#define LEDC_DUTY_INC_HSCH5_S 30
+/* LEDC_DUTY_NUM_HSCH5 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */
+/*description: This register is used to control the num of increased or decreased
+ times for high speed channel5.*/
+#define LEDC_DUTY_NUM_HSCH5 0x000003FF
+#define LEDC_DUTY_NUM_HSCH5_M ((LEDC_DUTY_NUM_HSCH5_V)<<(LEDC_DUTY_NUM_HSCH5_S))
+#define LEDC_DUTY_NUM_HSCH5_V 0x3FF
+#define LEDC_DUTY_NUM_HSCH5_S 20
+/* LEDC_DUTY_CYCLE_HSCH5 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */
+/*description: This register is used to increase or decrease the duty every
+ reg_duty_cycle_hsch5 cycles for high speed channel5.*/
+#define LEDC_DUTY_CYCLE_HSCH5 0x000003FF
+#define LEDC_DUTY_CYCLE_HSCH5_M ((LEDC_DUTY_CYCLE_HSCH5_V)<<(LEDC_DUTY_CYCLE_HSCH5_S))
+#define LEDC_DUTY_CYCLE_HSCH5_V 0x3FF
+#define LEDC_DUTY_CYCLE_HSCH5_S 10
+/* LEDC_DUTY_SCALE_HSCH5 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */
+/*description: This register controls the increase or decrease step scale for
+ high speed channel5.*/
+#define LEDC_DUTY_SCALE_HSCH5 0x000003FF
+#define LEDC_DUTY_SCALE_HSCH5_M ((LEDC_DUTY_SCALE_HSCH5_V)<<(LEDC_DUTY_SCALE_HSCH5_S))
+#define LEDC_DUTY_SCALE_HSCH5_V 0x3FF
+#define LEDC_DUTY_SCALE_HSCH5_S 0
+
+#define LEDC_HSCH5_DUTY_R_REG (DR_REG_LEDC_BASE + 0x0074)
+/* LEDC_DUTY_HSCH5 : RO ;bitpos:[24:0] ;default: 25'h0 ; */
+/*description: This register represents the current duty of the output signal
+ for high speed channel5.*/
+#define LEDC_DUTY_HSCH5 0x01FFFFFF
+#define LEDC_DUTY_HSCH5_M ((LEDC_DUTY_HSCH5_V)<<(LEDC_DUTY_HSCH5_S))
+#define LEDC_DUTY_HSCH5_V 0x1FFFFFF
+#define LEDC_DUTY_HSCH5_S 0
+
+#define LEDC_HSCH6_CONF0_REG (DR_REG_LEDC_BASE + 0x0078)
+/* LEDC_IDLE_LV_HSCH6 : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: This bit is used to control the output value when high speed channel6 is off.*/
+#define LEDC_IDLE_LV_HSCH6 (BIT(3))
+#define LEDC_IDLE_LV_HSCH6_M (BIT(3))
+#define LEDC_IDLE_LV_HSCH6_V 0x1
+#define LEDC_IDLE_LV_HSCH6_S 3
+/* LEDC_SIG_OUT_EN_HSCH6 : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: This is the output enable control bit for high speed channel6*/
+#define LEDC_SIG_OUT_EN_HSCH6 (BIT(2))
+#define LEDC_SIG_OUT_EN_HSCH6_M (BIT(2))
+#define LEDC_SIG_OUT_EN_HSCH6_V 0x1
+#define LEDC_SIG_OUT_EN_HSCH6_S 2
+/* LEDC_TIMER_SEL_HSCH6 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */
+/*description: There are four high speed timers the two bits are used to select
+ one of them for high speed channel6. 2'b00: seletc hstimer0. 2'b01: select hstimer1. 2'b10: select hstimer2. 2'b11: select hstimer3.*/
+#define LEDC_TIMER_SEL_HSCH6 0x00000003
+#define LEDC_TIMER_SEL_HSCH6_M ((LEDC_TIMER_SEL_HSCH6_V)<<(LEDC_TIMER_SEL_HSCH6_S))
+#define LEDC_TIMER_SEL_HSCH6_V 0x3
+#define LEDC_TIMER_SEL_HSCH6_S 0
+
+#define LEDC_HSCH6_HPOINT_REG (DR_REG_LEDC_BASE + 0x007C)
+/* LEDC_HPOINT_HSCH6 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */
+/*description: The output value changes to high when htimerx(x=[0 3]) selected
+ by high speed channel6 has reached reg_hpoint_hsch6[19:0]*/
+#define LEDC_HPOINT_HSCH6 0x000FFFFF
+#define LEDC_HPOINT_HSCH6_M ((LEDC_HPOINT_HSCH6_V)<<(LEDC_HPOINT_HSCH6_S))
+#define LEDC_HPOINT_HSCH6_V 0xFFFFF
+#define LEDC_HPOINT_HSCH6_S 0
+
+#define LEDC_HSCH6_DUTY_REG (DR_REG_LEDC_BASE + 0x0080)
+/* LEDC_DUTY_HSCH6 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */
+/*description: The register is used to control output duty. When hstimerx(x=[0
+ 3]) choosed by high speed channel6 has reached reg_lpoint_hsch6 the output signal changes to low. reg_lpoint_hsch6=(reg_hpoint_hsch6[19:0]+reg_duty_hsch6[24:4]) (1) reg_lpoint_hsch6=(reg_hpoint_hsch6[19:0]+reg_duty_hsch6[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/
+#define LEDC_DUTY_HSCH6 0x01FFFFFF
+#define LEDC_DUTY_HSCH6_M ((LEDC_DUTY_HSCH6_V)<<(LEDC_DUTY_HSCH6_S))
+#define LEDC_DUTY_HSCH6_V 0x1FFFFFF
+#define LEDC_DUTY_HSCH6_S 0
+
+#define LEDC_HSCH6_CONF1_REG (DR_REG_LEDC_BASE + 0x0084)
+/* LEDC_DUTY_START_HSCH6 : R/W ;bitpos:[31] ;default: 1'b0 ; */
+/*description: When reg_duty_num_hsch1 reg_duty_cycle_hsch1 and reg_duty_scale_hsch1
+ has been configured. these register won't take effect until set reg_duty_start_hsch1. this bit is automatically cleared by hardware.*/
+#define LEDC_DUTY_START_HSCH6 (BIT(31))
+#define LEDC_DUTY_START_HSCH6_M (BIT(31))
+#define LEDC_DUTY_START_HSCH6_V 0x1
+#define LEDC_DUTY_START_HSCH6_S 31
+/* LEDC_DUTY_INC_HSCH6 : R/W ;bitpos:[30] ;default: 1'b1 ; */
+/*description: This register is used to increase the duty of output signal or
+ decrease the duty of output signal for high speed channel6.*/
+#define LEDC_DUTY_INC_HSCH6 (BIT(30))
+#define LEDC_DUTY_INC_HSCH6_M (BIT(30))
+#define LEDC_DUTY_INC_HSCH6_V 0x1
+#define LEDC_DUTY_INC_HSCH6_S 30
+/* LEDC_DUTY_NUM_HSCH6 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */
+/*description: This register is used to control the num of increased or decreased
+ times for high speed channel6.*/
+#define LEDC_DUTY_NUM_HSCH6 0x000003FF
+#define LEDC_DUTY_NUM_HSCH6_M ((LEDC_DUTY_NUM_HSCH6_V)<<(LEDC_DUTY_NUM_HSCH6_S))
+#define LEDC_DUTY_NUM_HSCH6_V 0x3FF
+#define LEDC_DUTY_NUM_HSCH6_S 20
+/* LEDC_DUTY_CYCLE_HSCH6 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */
+/*description: This register is used to increase or decrease the duty every
+ reg_duty_cycle_hsch6 cycles for high speed channel6.*/
+#define LEDC_DUTY_CYCLE_HSCH6 0x000003FF
+#define LEDC_DUTY_CYCLE_HSCH6_M ((LEDC_DUTY_CYCLE_HSCH6_V)<<(LEDC_DUTY_CYCLE_HSCH6_S))
+#define LEDC_DUTY_CYCLE_HSCH6_V 0x3FF
+#define LEDC_DUTY_CYCLE_HSCH6_S 10
+/* LEDC_DUTY_SCALE_HSCH6 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */
+/*description: This register controls the increase or decrease step scale for
+ high speed channel6.*/
+#define LEDC_DUTY_SCALE_HSCH6 0x000003FF
+#define LEDC_DUTY_SCALE_HSCH6_M ((LEDC_DUTY_SCALE_HSCH6_V)<<(LEDC_DUTY_SCALE_HSCH6_S))
+#define LEDC_DUTY_SCALE_HSCH6_V 0x3FF
+#define LEDC_DUTY_SCALE_HSCH6_S 0
+
+#define LEDC_HSCH6_DUTY_R_REG (DR_REG_LEDC_BASE + 0x0088)
+/* LEDC_DUTY_HSCH6 : RO ;bitpos:[24:0] ;default: 25'h0 ; */
+/*description: This register represents the current duty of the output signal
+ for high speed channel6.*/
+#define LEDC_DUTY_HSCH6 0x01FFFFFF
+#define LEDC_DUTY_HSCH6_M ((LEDC_DUTY_HSCH6_V)<<(LEDC_DUTY_HSCH6_S))
+#define LEDC_DUTY_HSCH6_V 0x1FFFFFF
+#define LEDC_DUTY_HSCH6_S 0
+
+#define LEDC_HSCH7_CONF0_REG (DR_REG_LEDC_BASE + 0x008C)
+/* LEDC_IDLE_LV_HSCH7 : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: This bit is used to control the output value when high speed channel7 is off.*/
+#define LEDC_IDLE_LV_HSCH7 (BIT(3))
+#define LEDC_IDLE_LV_HSCH7_M (BIT(3))
+#define LEDC_IDLE_LV_HSCH7_V 0x1
+#define LEDC_IDLE_LV_HSCH7_S 3
+/* LEDC_SIG_OUT_EN_HSCH7 : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: This is the output enable control bit for high speed channel7.*/
+#define LEDC_SIG_OUT_EN_HSCH7 (BIT(2))
+#define LEDC_SIG_OUT_EN_HSCH7_M (BIT(2))
+#define LEDC_SIG_OUT_EN_HSCH7_V 0x1
+#define LEDC_SIG_OUT_EN_HSCH7_S 2
+/* LEDC_TIMER_SEL_HSCH7 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */
+/*description: There are four high speed timers the two bits are used to select
+ one of them for high speed channel7. 2'b00: seletc hstimer0. 2'b01: select hstimer1. 2'b10: select hstimer2. 2'b11: select hstimer3.*/
+#define LEDC_TIMER_SEL_HSCH7 0x00000003
+#define LEDC_TIMER_SEL_HSCH7_M ((LEDC_TIMER_SEL_HSCH7_V)<<(LEDC_TIMER_SEL_HSCH7_S))
+#define LEDC_TIMER_SEL_HSCH7_V 0x3
+#define LEDC_TIMER_SEL_HSCH7_S 0
+
+#define LEDC_HSCH7_HPOINT_REG (DR_REG_LEDC_BASE + 0x0090)
+/* LEDC_HPOINT_HSCH7 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */
+/*description: The output value changes to high when htimerx(x=[0 3]) selected
+ by high speed channel7 has reached reg_hpoint_hsch7[19:0]*/
+#define LEDC_HPOINT_HSCH7 0x000FFFFF
+#define LEDC_HPOINT_HSCH7_M ((LEDC_HPOINT_HSCH7_V)<<(LEDC_HPOINT_HSCH7_S))
+#define LEDC_HPOINT_HSCH7_V 0xFFFFF
+#define LEDC_HPOINT_HSCH7_S 0
+
+#define LEDC_HSCH7_DUTY_REG (DR_REG_LEDC_BASE + 0x0094)
+/* LEDC_DUTY_HSCH7 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */
+/*description: The register is used to control output duty. When hstimerx(x=[0
+ 3]) choosed by high speed channel7 has reached reg_lpoint_hsch7 the output signal changes to low. reg_lpoint_hsch7=(reg_hpoint_hsch7[19:0]+reg_duty_hsch7[24:4]) (1) reg_lpoint_hsch7=(reg_hpoint_hsch7[19:0]+reg_duty_hsch7[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/
+#define LEDC_DUTY_HSCH7 0x01FFFFFF
+#define LEDC_DUTY_HSCH7_M ((LEDC_DUTY_HSCH7_V)<<(LEDC_DUTY_HSCH7_S))
+#define LEDC_DUTY_HSCH7_V 0x1FFFFFF
+#define LEDC_DUTY_HSCH7_S 0
+
+#define LEDC_HSCH7_CONF1_REG (DR_REG_LEDC_BASE + 0x0098)
+/* LEDC_DUTY_START_HSCH7 : R/W ;bitpos:[31] ;default: 1'b0 ; */
+/*description: When reg_duty_num_hsch1 reg_duty_cycle_hsch1 and reg_duty_scale_hsch1
+ has been configured. these register won't take effect until set reg_duty_start_hsch1. this bit is automatically cleared by hardware.*/
+#define LEDC_DUTY_START_HSCH7 (BIT(31))
+#define LEDC_DUTY_START_HSCH7_M (BIT(31))
+#define LEDC_DUTY_START_HSCH7_V 0x1
+#define LEDC_DUTY_START_HSCH7_S 31
+/* LEDC_DUTY_INC_HSCH7 : R/W ;bitpos:[30] ;default: 1'b1 ; */
+/*description: This register is used to increase the duty of output signal or
+ decrease the duty of output signal for high speed channel6.*/
+#define LEDC_DUTY_INC_HSCH7 (BIT(30))
+#define LEDC_DUTY_INC_HSCH7_M (BIT(30))
+#define LEDC_DUTY_INC_HSCH7_V 0x1
+#define LEDC_DUTY_INC_HSCH7_S 30
+/* LEDC_DUTY_NUM_HSCH7 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */
+/*description: This register is used to control the num of increased or decreased
+ times for high speed channel6.*/
+#define LEDC_DUTY_NUM_HSCH7 0x000003FF
+#define LEDC_DUTY_NUM_HSCH7_M ((LEDC_DUTY_NUM_HSCH7_V)<<(LEDC_DUTY_NUM_HSCH7_S))
+#define LEDC_DUTY_NUM_HSCH7_V 0x3FF
+#define LEDC_DUTY_NUM_HSCH7_S 20
+/* LEDC_DUTY_CYCLE_HSCH7 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */
+/*description: This register is used to increase or decrease the duty every
+ reg_duty_cycle_hsch7 cycles for high speed channel7.*/
+#define LEDC_DUTY_CYCLE_HSCH7 0x000003FF
+#define LEDC_DUTY_CYCLE_HSCH7_M ((LEDC_DUTY_CYCLE_HSCH7_V)<<(LEDC_DUTY_CYCLE_HSCH7_S))
+#define LEDC_DUTY_CYCLE_HSCH7_V 0x3FF
+#define LEDC_DUTY_CYCLE_HSCH7_S 10
+/* LEDC_DUTY_SCALE_HSCH7 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */
+/*description: This register controls the increase or decrease step scale for
+ high speed channel7.*/
+#define LEDC_DUTY_SCALE_HSCH7 0x000003FF
+#define LEDC_DUTY_SCALE_HSCH7_M ((LEDC_DUTY_SCALE_HSCH7_V)<<(LEDC_DUTY_SCALE_HSCH7_S))
+#define LEDC_DUTY_SCALE_HSCH7_V 0x3FF
+#define LEDC_DUTY_SCALE_HSCH7_S 0
+
+#define LEDC_HSCH7_DUTY_R_REG (DR_REG_LEDC_BASE + 0x009C)
+/* LEDC_DUTY_HSCH7 : RO ;bitpos:[24:0] ;default: 25'h0 ; */
+/*description: This register represents the current duty of the output signal
+ for high speed channel7.*/
+#define LEDC_DUTY_HSCH7 0x01FFFFFF
+#define LEDC_DUTY_HSCH7_M ((LEDC_DUTY_HSCH7_V)<<(LEDC_DUTY_HSCH7_S))
+#define LEDC_DUTY_HSCH7_V 0x1FFFFFF
+#define LEDC_DUTY_HSCH7_S 0
+
+#define LEDC_LSCH0_CONF0_REG (DR_REG_LEDC_BASE + 0x00A0)
+/* LEDC_PARA_UP_LSCH0 : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: This bit is used to update register LEDC_LSCH0_HPOINT and LEDC_LSCH0_DUTY
+ for low speed channel0.*/
+#define LEDC_PARA_UP_LSCH0 (BIT(4))
+#define LEDC_PARA_UP_LSCH0_M (BIT(4))
+#define LEDC_PARA_UP_LSCH0_V 0x1
+#define LEDC_PARA_UP_LSCH0_S 4
+/* LEDC_IDLE_LV_LSCH0 : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: This bit is used to control the output value when low speed channel0 is off.*/
+#define LEDC_IDLE_LV_LSCH0 (BIT(3))
+#define LEDC_IDLE_LV_LSCH0_M (BIT(3))
+#define LEDC_IDLE_LV_LSCH0_V 0x1
+#define LEDC_IDLE_LV_LSCH0_S 3
+/* LEDC_SIG_OUT_EN_LSCH0 : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: This is the output enable control bit for low speed channel0.*/
+#define LEDC_SIG_OUT_EN_LSCH0 (BIT(2))
+#define LEDC_SIG_OUT_EN_LSCH0_M (BIT(2))
+#define LEDC_SIG_OUT_EN_LSCH0_V 0x1
+#define LEDC_SIG_OUT_EN_LSCH0_S 2
+/* LEDC_TIMER_SEL_LSCH0 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */
+/*description: There are four low speed timers the two bits are used to select
+ one of them for low speed channel0. 2'b00: seletc lstimer0. 2'b01: select lstimer1. 2'b10: select lstimer2. 2'b11: select lstimer3.*/
+#define LEDC_TIMER_SEL_LSCH0 0x00000003
+#define LEDC_TIMER_SEL_LSCH0_M ((LEDC_TIMER_SEL_LSCH0_V)<<(LEDC_TIMER_SEL_LSCH0_S))
+#define LEDC_TIMER_SEL_LSCH0_V 0x3
+#define LEDC_TIMER_SEL_LSCH0_S 0
+
+#define LEDC_LSCH0_HPOINT_REG (DR_REG_LEDC_BASE + 0x00A4)
+/* LEDC_HPOINT_LSCH0 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */
+/*description: The output value changes to high when lstimerx(x=[0 3]) selected
+ by low speed channel0 has reached reg_hpoint_lsch0[19:0]*/
+#define LEDC_HPOINT_LSCH0 0x000FFFFF
+#define LEDC_HPOINT_LSCH0_M ((LEDC_HPOINT_LSCH0_V)<<(LEDC_HPOINT_LSCH0_S))
+#define LEDC_HPOINT_LSCH0_V 0xFFFFF
+#define LEDC_HPOINT_LSCH0_S 0
+
+#define LEDC_LSCH0_DUTY_REG (DR_REG_LEDC_BASE + 0x00A8)
+/* LEDC_DUTY_LSCH0 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */
+/*description: The register is used to control output duty. When lstimerx(x=[0
+ 3]) choosed by low speed channel0 has reached reg_lpoint_lsch0 the output signal changes to low. reg_lpoint_lsch0=(reg_hpoint_lsch0[19:0]+reg_duty_lsch0[24:4]) (1) reg_lpoint_lsch0=(reg_hpoint_lsch0[19:0]+reg_duty_lsch0[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/
+#define LEDC_DUTY_LSCH0 0x01FFFFFF
+#define LEDC_DUTY_LSCH0_M ((LEDC_DUTY_LSCH0_V)<<(LEDC_DUTY_LSCH0_S))
+#define LEDC_DUTY_LSCH0_V 0x1FFFFFF
+#define LEDC_DUTY_LSCH0_S 0
+
+#define LEDC_LSCH0_CONF1_REG (DR_REG_LEDC_BASE + 0x00AC)
+/* LEDC_DUTY_START_LSCH0 : R/W ;bitpos:[31] ;default: 1'b0 ; */
+/*description: When reg_duty_num_hsch1 reg_duty_cycle_hsch1 and reg_duty_scale_hsch1
+ has been configured. these register won't take effect until set reg_duty_start_hsch1. this bit is automatically cleared by hardware.*/
+#define LEDC_DUTY_START_LSCH0 (BIT(31))
+#define LEDC_DUTY_START_LSCH0_M (BIT(31))
+#define LEDC_DUTY_START_LSCH0_V 0x1
+#define LEDC_DUTY_START_LSCH0_S 31
+/* LEDC_DUTY_INC_LSCH0 : R/W ;bitpos:[30] ;default: 1'b1 ; */
+/*description: This register is used to increase the duty of output signal or
+ decrease the duty of output signal for low speed channel6.*/
+#define LEDC_DUTY_INC_LSCH0 (BIT(30))
+#define LEDC_DUTY_INC_LSCH0_M (BIT(30))
+#define LEDC_DUTY_INC_LSCH0_V 0x1
+#define LEDC_DUTY_INC_LSCH0_S 30
+/* LEDC_DUTY_NUM_LSCH0 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */
+/*description: This register is used to control the num of increased or decreased
+ times for low speed channel6.*/
+#define LEDC_DUTY_NUM_LSCH0 0x000003FF
+#define LEDC_DUTY_NUM_LSCH0_M ((LEDC_DUTY_NUM_LSCH0_V)<<(LEDC_DUTY_NUM_LSCH0_S))
+#define LEDC_DUTY_NUM_LSCH0_V 0x3FF
+#define LEDC_DUTY_NUM_LSCH0_S 20
+/* LEDC_DUTY_CYCLE_LSCH0 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */
+/*description: This register is used to increase or decrease the duty every
+ reg_duty_cycle_lsch0 cycles for low speed channel0.*/
+#define LEDC_DUTY_CYCLE_LSCH0 0x000003FF
+#define LEDC_DUTY_CYCLE_LSCH0_M ((LEDC_DUTY_CYCLE_LSCH0_V)<<(LEDC_DUTY_CYCLE_LSCH0_S))
+#define LEDC_DUTY_CYCLE_LSCH0_V 0x3FF
+#define LEDC_DUTY_CYCLE_LSCH0_S 10
+/* LEDC_DUTY_SCALE_LSCH0 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */
+/*description: This register controls the increase or decrease step scale for
+ low speed channel0.*/
+#define LEDC_DUTY_SCALE_LSCH0 0x000003FF
+#define LEDC_DUTY_SCALE_LSCH0_M ((LEDC_DUTY_SCALE_LSCH0_V)<<(LEDC_DUTY_SCALE_LSCH0_S))
+#define LEDC_DUTY_SCALE_LSCH0_V 0x3FF
+#define LEDC_DUTY_SCALE_LSCH0_S 0
+
+#define LEDC_LSCH0_DUTY_R_REG (DR_REG_LEDC_BASE + 0x00B0)
+/* LEDC_DUTY_LSCH0 : RO ;bitpos:[24:0] ;default: 25'h0 ; */
+/*description: This register represents the current duty of the output signal
+ for low speed channel0.*/
+#define LEDC_DUTY_LSCH0 0x01FFFFFF
+#define LEDC_DUTY_LSCH0_M ((LEDC_DUTY_LSCH0_V)<<(LEDC_DUTY_LSCH0_S))
+#define LEDC_DUTY_LSCH0_V 0x1FFFFFF
+#define LEDC_DUTY_LSCH0_S 0
+
+#define LEDC_LSCH1_CONF0_REG (DR_REG_LEDC_BASE + 0x00B4)
+/* LEDC_PARA_UP_LSCH1 : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: This bit is used to update register LEDC_LSCH1_HPOINT and LEDC_LSCH1_DUTY
+ for low speed channel1.*/
+#define LEDC_PARA_UP_LSCH1 (BIT(4))
+#define LEDC_PARA_UP_LSCH1_M (BIT(4))
+#define LEDC_PARA_UP_LSCH1_V 0x1
+#define LEDC_PARA_UP_LSCH1_S 4
+/* LEDC_IDLE_LV_LSCH1 : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: This bit is used to control the output value when low speed channel1 is off.*/
+#define LEDC_IDLE_LV_LSCH1 (BIT(3))
+#define LEDC_IDLE_LV_LSCH1_M (BIT(3))
+#define LEDC_IDLE_LV_LSCH1_V 0x1
+#define LEDC_IDLE_LV_LSCH1_S 3
+/* LEDC_SIG_OUT_EN_LSCH1 : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: This is the output enable control bit for low speed channel1.*/
+#define LEDC_SIG_OUT_EN_LSCH1 (BIT(2))
+#define LEDC_SIG_OUT_EN_LSCH1_M (BIT(2))
+#define LEDC_SIG_OUT_EN_LSCH1_V 0x1
+#define LEDC_SIG_OUT_EN_LSCH1_S 2
+/* LEDC_TIMER_SEL_LSCH1 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */
+/*description: There are four low speed timers the two bits are used to select
+ one of them for low speed channel1. 2'b00: seletc lstimer0. 2'b01: select lstimer1. 2'b10: select lstimer2. 2'b11: select lstimer3.*/
+#define LEDC_TIMER_SEL_LSCH1 0x00000003
+#define LEDC_TIMER_SEL_LSCH1_M ((LEDC_TIMER_SEL_LSCH1_V)<<(LEDC_TIMER_SEL_LSCH1_S))
+#define LEDC_TIMER_SEL_LSCH1_V 0x3
+#define LEDC_TIMER_SEL_LSCH1_S 0
+
+#define LEDC_LSCH1_HPOINT_REG (DR_REG_LEDC_BASE + 0x00B8)
+/* LEDC_HPOINT_LSCH1 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */
+/*description: The output value changes to high when lstimerx(x=[0 3]) selected
+ by low speed channel1 has reached reg_hpoint_lsch1[19:0]*/
+#define LEDC_HPOINT_LSCH1 0x000FFFFF
+#define LEDC_HPOINT_LSCH1_M ((LEDC_HPOINT_LSCH1_V)<<(LEDC_HPOINT_LSCH1_S))
+#define LEDC_HPOINT_LSCH1_V 0xFFFFF
+#define LEDC_HPOINT_LSCH1_S 0
+
+#define LEDC_LSCH1_DUTY_REG (DR_REG_LEDC_BASE + 0x00BC)
+/* LEDC_DUTY_LSCH1 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */
+/*description: The register is used to control output duty. When lstimerx(x=[0
+ 3]) choosed by low speed channel1 has reached reg_lpoint_lsch1 the output signal changes to low. reg_lpoint_lsch1=(reg_hpoint_lsch1[19:0]+reg_duty_lsch1[24:4]) (1) reg_lpoint_lsch1=(reg_hpoint_lsch1[19:0]+reg_duty_lsch1[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/
+#define LEDC_DUTY_LSCH1 0x01FFFFFF
+#define LEDC_DUTY_LSCH1_M ((LEDC_DUTY_LSCH1_V)<<(LEDC_DUTY_LSCH1_S))
+#define LEDC_DUTY_LSCH1_V 0x1FFFFFF
+#define LEDC_DUTY_LSCH1_S 0
+
+#define LEDC_LSCH1_CONF1_REG (DR_REG_LEDC_BASE + 0x00C0)
+/* LEDC_DUTY_START_LSCH1 : R/W ;bitpos:[31] ;default: 1'b0 ; */
+/*description: When reg_duty_num_hsch1 reg_duty_cycle_hsch1 and reg_duty_scale_hsch1
+ has been configured. these register won't take effect until set reg_duty_start_hsch1. this bit is automatically cleared by hardware.*/
+#define LEDC_DUTY_START_LSCH1 (BIT(31))
+#define LEDC_DUTY_START_LSCH1_M (BIT(31))
+#define LEDC_DUTY_START_LSCH1_V 0x1
+#define LEDC_DUTY_START_LSCH1_S 31
+/* LEDC_DUTY_INC_LSCH1 : R/W ;bitpos:[30] ;default: 1'b1 ; */
+/*description: This register is used to increase the duty of output signal or
+ decrease the duty of output signal for low speed channel1.*/
+#define LEDC_DUTY_INC_LSCH1 (BIT(30))
+#define LEDC_DUTY_INC_LSCH1_M (BIT(30))
+#define LEDC_DUTY_INC_LSCH1_V 0x1
+#define LEDC_DUTY_INC_LSCH1_S 30
+/* LEDC_DUTY_NUM_LSCH1 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */
+/*description: This register is used to control the num of increased or decreased
+ times for low speed channel1.*/
+#define LEDC_DUTY_NUM_LSCH1 0x000003FF
+#define LEDC_DUTY_NUM_LSCH1_M ((LEDC_DUTY_NUM_LSCH1_V)<<(LEDC_DUTY_NUM_LSCH1_S))
+#define LEDC_DUTY_NUM_LSCH1_V 0x3FF
+#define LEDC_DUTY_NUM_LSCH1_S 20
+/* LEDC_DUTY_CYCLE_LSCH1 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */
+/*description: This register is used to increase or decrease the duty every
+ reg_duty_cycle_lsch1 cycles for low speed channel1.*/
+#define LEDC_DUTY_CYCLE_LSCH1 0x000003FF
+#define LEDC_DUTY_CYCLE_LSCH1_M ((LEDC_DUTY_CYCLE_LSCH1_V)<<(LEDC_DUTY_CYCLE_LSCH1_S))
+#define LEDC_DUTY_CYCLE_LSCH1_V 0x3FF
+#define LEDC_DUTY_CYCLE_LSCH1_S 10
+/* LEDC_DUTY_SCALE_LSCH1 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */
+/*description: This register controls the increase or decrease step scale for
+ low speed channel1.*/
+#define LEDC_DUTY_SCALE_LSCH1 0x000003FF
+#define LEDC_DUTY_SCALE_LSCH1_M ((LEDC_DUTY_SCALE_LSCH1_V)<<(LEDC_DUTY_SCALE_LSCH1_S))
+#define LEDC_DUTY_SCALE_LSCH1_V 0x3FF
+#define LEDC_DUTY_SCALE_LSCH1_S 0
+
+#define LEDC_LSCH1_DUTY_R_REG (DR_REG_LEDC_BASE + 0x00C4)
+/* LEDC_DUTY_LSCH1 : RO ;bitpos:[24:0] ;default: 25'h0 ; */
+/*description: This register represents the current duty of the output signal
+ for low speed channel1.*/
+#define LEDC_DUTY_LSCH1 0x01FFFFFF
+#define LEDC_DUTY_LSCH1_M ((LEDC_DUTY_LSCH1_V)<<(LEDC_DUTY_LSCH1_S))
+#define LEDC_DUTY_LSCH1_V 0x1FFFFFF
+#define LEDC_DUTY_LSCH1_S 0
+
+#define LEDC_LSCH2_CONF0_REG (DR_REG_LEDC_BASE + 0x00C8)
+/* LEDC_PARA_UP_LSCH2 : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: This bit is used to update register LEDC_LSCH2_HPOINT and LEDC_LSCH2_DUTY
+ for low speed channel2.*/
+#define LEDC_PARA_UP_LSCH2 (BIT(4))
+#define LEDC_PARA_UP_LSCH2_M (BIT(4))
+#define LEDC_PARA_UP_LSCH2_V 0x1
+#define LEDC_PARA_UP_LSCH2_S 4
+/* LEDC_IDLE_LV_LSCH2 : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: This bit is used to control the output value when low speed channel2 is off.*/
+#define LEDC_IDLE_LV_LSCH2 (BIT(3))
+#define LEDC_IDLE_LV_LSCH2_M (BIT(3))
+#define LEDC_IDLE_LV_LSCH2_V 0x1
+#define LEDC_IDLE_LV_LSCH2_S 3
+/* LEDC_SIG_OUT_EN_LSCH2 : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: This is the output enable control bit for low speed channel2.*/
+#define LEDC_SIG_OUT_EN_LSCH2 (BIT(2))
+#define LEDC_SIG_OUT_EN_LSCH2_M (BIT(2))
+#define LEDC_SIG_OUT_EN_LSCH2_V 0x1
+#define LEDC_SIG_OUT_EN_LSCH2_S 2
+/* LEDC_TIMER_SEL_LSCH2 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */
+/*description: There are four low speed timers the two bits are used to select
+ one of them for low speed channel2. 2'b00: seletc lstimer0. 2'b01: select lstimer1. 2'b10: select lstimer2. 2'b11: select lstimer3.*/
+#define LEDC_TIMER_SEL_LSCH2 0x00000003
+#define LEDC_TIMER_SEL_LSCH2_M ((LEDC_TIMER_SEL_LSCH2_V)<<(LEDC_TIMER_SEL_LSCH2_S))
+#define LEDC_TIMER_SEL_LSCH2_V 0x3
+#define LEDC_TIMER_SEL_LSCH2_S 0
+
+#define LEDC_LSCH2_HPOINT_REG (DR_REG_LEDC_BASE + 0x00CC)
+/* LEDC_HPOINT_LSCH2 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */
+/*description: The output value changes to high when lstimerx(x=[0 3]) selected
+ by low speed channel2 has reached reg_hpoint_lsch2[19:0]*/
+#define LEDC_HPOINT_LSCH2 0x000FFFFF
+#define LEDC_HPOINT_LSCH2_M ((LEDC_HPOINT_LSCH2_V)<<(LEDC_HPOINT_LSCH2_S))
+#define LEDC_HPOINT_LSCH2_V 0xFFFFF
+#define LEDC_HPOINT_LSCH2_S 0
+
+#define LEDC_LSCH2_DUTY_REG (DR_REG_LEDC_BASE + 0x00D0)
+/* LEDC_DUTY_LSCH2 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */
+/*description: The register is used to control output duty. When lstimerx(x=[0
+ 3]) choosed by low speed channel2 has reached reg_lpoint_lsch2 the output signal changes to low. reg_lpoint_lsch2=(reg_hpoint_lsch2[19:0]+reg_duty_lsch2[24:4]) (1) reg_lpoint_lsch2=(reg_hpoint_lsch2[19:0]+reg_duty_lsch2[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/
+#define LEDC_DUTY_LSCH2 0x01FFFFFF
+#define LEDC_DUTY_LSCH2_M ((LEDC_DUTY_LSCH2_V)<<(LEDC_DUTY_LSCH2_S))
+#define LEDC_DUTY_LSCH2_V 0x1FFFFFF
+#define LEDC_DUTY_LSCH2_S 0
+
+#define LEDC_LSCH2_CONF1_REG (DR_REG_LEDC_BASE + 0x00D4)
+/* LEDC_DUTY_START_LSCH2 : R/W ;bitpos:[31] ;default: 1'b0 ; */
+/*description: When reg_duty_num_hsch2 reg_duty_cycle_hsch2 and reg_duty_scale_hsch2
+ has been configured. these register won't take effect until set reg_duty_start_hsch2. this bit is automatically cleared by hardware.*/
+#define LEDC_DUTY_START_LSCH2 (BIT(31))
+#define LEDC_DUTY_START_LSCH2_M (BIT(31))
+#define LEDC_DUTY_START_LSCH2_V 0x1
+#define LEDC_DUTY_START_LSCH2_S 31
+/* LEDC_DUTY_INC_LSCH2 : R/W ;bitpos:[30] ;default: 1'b1 ; */
+/*description: This register is used to increase the duty of output signal or
+ decrease the duty of output signal for low speed channel2.*/
+#define LEDC_DUTY_INC_LSCH2 (BIT(30))
+#define LEDC_DUTY_INC_LSCH2_M (BIT(30))
+#define LEDC_DUTY_INC_LSCH2_V 0x1
+#define LEDC_DUTY_INC_LSCH2_S 30
+/* LEDC_DUTY_NUM_LSCH2 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */
+/*description: This register is used to control the num of increased or decreased
+ times for low speed channel2.*/
+#define LEDC_DUTY_NUM_LSCH2 0x000003FF
+#define LEDC_DUTY_NUM_LSCH2_M ((LEDC_DUTY_NUM_LSCH2_V)<<(LEDC_DUTY_NUM_LSCH2_S))
+#define LEDC_DUTY_NUM_LSCH2_V 0x3FF
+#define LEDC_DUTY_NUM_LSCH2_S 20
+/* LEDC_DUTY_CYCLE_LSCH2 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */
+/*description: This register is used to increase or decrease the duty every
+ reg_duty_cycle_lsch2 cycles for low speed channel2.*/
+#define LEDC_DUTY_CYCLE_LSCH2 0x000003FF
+#define LEDC_DUTY_CYCLE_LSCH2_M ((LEDC_DUTY_CYCLE_LSCH2_V)<<(LEDC_DUTY_CYCLE_LSCH2_S))
+#define LEDC_DUTY_CYCLE_LSCH2_V 0x3FF
+#define LEDC_DUTY_CYCLE_LSCH2_S 10
+/* LEDC_DUTY_SCALE_LSCH2 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */
+/*description: This register controls the increase or decrease step scale for
+ low speed channel2.*/
+#define LEDC_DUTY_SCALE_LSCH2 0x000003FF
+#define LEDC_DUTY_SCALE_LSCH2_M ((LEDC_DUTY_SCALE_LSCH2_V)<<(LEDC_DUTY_SCALE_LSCH2_S))
+#define LEDC_DUTY_SCALE_LSCH2_V 0x3FF
+#define LEDC_DUTY_SCALE_LSCH2_S 0
+
+#define LEDC_LSCH2_DUTY_R_REG (DR_REG_LEDC_BASE + 0x00D8)
+/* LEDC_DUTY_LSCH2 : RO ;bitpos:[24:0] ;default: 25'h0 ; */
+/*description: This register represents the current duty of the output signal
+ for low speed channel2.*/
+#define LEDC_DUTY_LSCH2 0x01FFFFFF
+#define LEDC_DUTY_LSCH2_M ((LEDC_DUTY_LSCH2_V)<<(LEDC_DUTY_LSCH2_S))
+#define LEDC_DUTY_LSCH2_V 0x1FFFFFF
+#define LEDC_DUTY_LSCH2_S 0
+
+#define LEDC_LSCH3_CONF0_REG (DR_REG_LEDC_BASE + 0x00DC)
+/* LEDC_PARA_UP_LSCH3 : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: This bit is used to update register LEDC_LSCH3_HPOINT and LEDC_LSCH3_DUTY
+ for low speed channel3.*/
+#define LEDC_PARA_UP_LSCH3 (BIT(4))
+#define LEDC_PARA_UP_LSCH3_M (BIT(4))
+#define LEDC_PARA_UP_LSCH3_V 0x1
+#define LEDC_PARA_UP_LSCH3_S 4
+/* LEDC_IDLE_LV_LSCH3 : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: This bit is used to control the output value when low speed channel3 is off.*/
+#define LEDC_IDLE_LV_LSCH3 (BIT(3))
+#define LEDC_IDLE_LV_LSCH3_M (BIT(3))
+#define LEDC_IDLE_LV_LSCH3_V 0x1
+#define LEDC_IDLE_LV_LSCH3_S 3
+/* LEDC_SIG_OUT_EN_LSCH3 : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: This is the output enable control bit for low speed channel3.*/
+#define LEDC_SIG_OUT_EN_LSCH3 (BIT(2))
+#define LEDC_SIG_OUT_EN_LSCH3_M (BIT(2))
+#define LEDC_SIG_OUT_EN_LSCH3_V 0x1
+#define LEDC_SIG_OUT_EN_LSCH3_S 2
+/* LEDC_TIMER_SEL_LSCH3 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */
+/*description: There are four low speed timers the two bits are used to select
+ one of them for low speed channel3. 2'b00: seletc lstimer0. 2'b01: select lstimer1. 2'b10: select lstimer2. 2'b11: select lstimer3.*/
+#define LEDC_TIMER_SEL_LSCH3 0x00000003
+#define LEDC_TIMER_SEL_LSCH3_M ((LEDC_TIMER_SEL_LSCH3_V)<<(LEDC_TIMER_SEL_LSCH3_S))
+#define LEDC_TIMER_SEL_LSCH3_V 0x3
+#define LEDC_TIMER_SEL_LSCH3_S 0
+
+#define LEDC_LSCH3_HPOINT_REG (DR_REG_LEDC_BASE + 0x00E0)
+/* LEDC_HPOINT_LSCH3 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */
+/*description: The output value changes to high when lstimerx(x=[0 3]) selected
+ by low speed channel3 has reached reg_hpoint_lsch3[19:0]*/
+#define LEDC_HPOINT_LSCH3 0x000FFFFF
+#define LEDC_HPOINT_LSCH3_M ((LEDC_HPOINT_LSCH3_V)<<(LEDC_HPOINT_LSCH3_S))
+#define LEDC_HPOINT_LSCH3_V 0xFFFFF
+#define LEDC_HPOINT_LSCH3_S 0
+
+#define LEDC_LSCH3_DUTY_REG (DR_REG_LEDC_BASE + 0x00E4)
+/* LEDC_DUTY_LSCH3 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */
+/*description: The register is used to control output duty. When lstimerx(x=[0
+ 3]) choosed by low speed channel3 has reached reg_lpoint_lsch3 the output signal changes to low. reg_lpoint_lsch3=(reg_hpoint_lsch3[19:0]+reg_duty_lsch3[24:4]) (1) reg_lpoint_lsch3=(reg_hpoint_lsch3[19:0]+reg_duty_lsch3[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/
+#define LEDC_DUTY_LSCH3 0x01FFFFFF
+#define LEDC_DUTY_LSCH3_M ((LEDC_DUTY_LSCH3_V)<<(LEDC_DUTY_LSCH3_S))
+#define LEDC_DUTY_LSCH3_V 0x1FFFFFF
+#define LEDC_DUTY_LSCH3_S 0
+
+#define LEDC_LSCH3_CONF1_REG (DR_REG_LEDC_BASE + 0x00E8)
+/* LEDC_DUTY_START_LSCH3 : R/W ;bitpos:[31] ;default: 1'b0 ; */
+/*description: When reg_duty_num_hsch3 reg_duty_cycle_hsch3 and reg_duty_scale_hsch3
+ has been configured. these register won't take effect until set reg_duty_start_hsch3. this bit is automatically cleared by hardware.*/
+#define LEDC_DUTY_START_LSCH3 (BIT(31))
+#define LEDC_DUTY_START_LSCH3_M (BIT(31))
+#define LEDC_DUTY_START_LSCH3_V 0x1
+#define LEDC_DUTY_START_LSCH3_S 31
+/* LEDC_DUTY_INC_LSCH3 : R/W ;bitpos:[30] ;default: 1'b1 ; */
+/*description: This register is used to increase the duty of output signal or
+ decrease the duty of output signal for low speed channel3.*/
+#define LEDC_DUTY_INC_LSCH3 (BIT(30))
+#define LEDC_DUTY_INC_LSCH3_M (BIT(30))
+#define LEDC_DUTY_INC_LSCH3_V 0x1
+#define LEDC_DUTY_INC_LSCH3_S 30
+/* LEDC_DUTY_NUM_LSCH3 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */
+/*description: This register is used to control the num of increased or decreased
+ times for low speed channel3.*/
+#define LEDC_DUTY_NUM_LSCH3 0x000003FF
+#define LEDC_DUTY_NUM_LSCH3_M ((LEDC_DUTY_NUM_LSCH3_V)<<(LEDC_DUTY_NUM_LSCH3_S))
+#define LEDC_DUTY_NUM_LSCH3_V 0x3FF
+#define LEDC_DUTY_NUM_LSCH3_S 20
+/* LEDC_DUTY_CYCLE_LSCH3 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */
+/*description: This register is used to increase or decrease the duty every
+ reg_duty_cycle_lsch3 cycles for low speed channel3.*/
+#define LEDC_DUTY_CYCLE_LSCH3 0x000003FF
+#define LEDC_DUTY_CYCLE_LSCH3_M ((LEDC_DUTY_CYCLE_LSCH3_V)<<(LEDC_DUTY_CYCLE_LSCH3_S))
+#define LEDC_DUTY_CYCLE_LSCH3_V 0x3FF
+#define LEDC_DUTY_CYCLE_LSCH3_S 10
+/* LEDC_DUTY_SCALE_LSCH3 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */
+/*description: This register controls the increase or decrease step scale for
+ low speed channel3.*/
+#define LEDC_DUTY_SCALE_LSCH3 0x000003FF
+#define LEDC_DUTY_SCALE_LSCH3_M ((LEDC_DUTY_SCALE_LSCH3_V)<<(LEDC_DUTY_SCALE_LSCH3_S))
+#define LEDC_DUTY_SCALE_LSCH3_V 0x3FF
+#define LEDC_DUTY_SCALE_LSCH3_S 0
+
+#define LEDC_LSCH3_DUTY_R_REG (DR_REG_LEDC_BASE + 0x00EC)
+/* LEDC_DUTY_LSCH3 : RO ;bitpos:[24:0] ;default: 25'h0 ; */
+/*description: This register represents the current duty of the output signal
+ for low speed channel3.*/
+#define LEDC_DUTY_LSCH3 0x01FFFFFF
+#define LEDC_DUTY_LSCH3_M ((LEDC_DUTY_LSCH3_V)<<(LEDC_DUTY_LSCH3_S))
+#define LEDC_DUTY_LSCH3_V 0x1FFFFFF
+#define LEDC_DUTY_LSCH3_S 0
+
+#define LEDC_LSCH4_CONF0_REG (DR_REG_LEDC_BASE + 0x00F0)
+/* LEDC_PARA_UP_LSCH4 : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: This bit is used to update register LEDC_LSCH4_HPOINT and LEDC_LSCH4_DUTY
+ for low speed channel4.*/
+#define LEDC_PARA_UP_LSCH4 (BIT(4))
+#define LEDC_PARA_UP_LSCH4_M (BIT(4))
+#define LEDC_PARA_UP_LSCH4_V 0x1
+#define LEDC_PARA_UP_LSCH4_S 4
+/* LEDC_IDLE_LV_LSCH4 : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: This bit is used to control the output value when low speed channel4 is off.*/
+#define LEDC_IDLE_LV_LSCH4 (BIT(3))
+#define LEDC_IDLE_LV_LSCH4_M (BIT(3))
+#define LEDC_IDLE_LV_LSCH4_V 0x1
+#define LEDC_IDLE_LV_LSCH4_S 3
+/* LEDC_SIG_OUT_EN_LSCH4 : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: This is the output enable control bit for low speed channel4.*/
+#define LEDC_SIG_OUT_EN_LSCH4 (BIT(2))
+#define LEDC_SIG_OUT_EN_LSCH4_M (BIT(2))
+#define LEDC_SIG_OUT_EN_LSCH4_V 0x1
+#define LEDC_SIG_OUT_EN_LSCH4_S 2
+/* LEDC_TIMER_SEL_LSCH4 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */
+/*description: There are four low speed timers the two bits are used to select
+ one of them for low speed channel4. 2'b00: seletc lstimer0. 2'b01: select lstimer1. 2'b10: select lstimer2. 2'b11: select lstimer3.*/
+#define LEDC_TIMER_SEL_LSCH4 0x00000003
+#define LEDC_TIMER_SEL_LSCH4_M ((LEDC_TIMER_SEL_LSCH4_V)<<(LEDC_TIMER_SEL_LSCH4_S))
+#define LEDC_TIMER_SEL_LSCH4_V 0x3
+#define LEDC_TIMER_SEL_LSCH4_S 0
+
+#define LEDC_LSCH4_HPOINT_REG (DR_REG_LEDC_BASE + 0x00F4)
+/* LEDC_HPOINT_LSCH4 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */
+/*description: The output value changes to high when lstimerx(x=[0 3]) selected
+ by low speed channel4 has reached reg_hpoint_lsch4[19:0]*/
+#define LEDC_HPOINT_LSCH4 0x000FFFFF
+#define LEDC_HPOINT_LSCH4_M ((LEDC_HPOINT_LSCH4_V)<<(LEDC_HPOINT_LSCH4_S))
+#define LEDC_HPOINT_LSCH4_V 0xFFFFF
+#define LEDC_HPOINT_LSCH4_S 0
+
+#define LEDC_LSCH4_DUTY_REG (DR_REG_LEDC_BASE + 0x00F8)
+/* LEDC_DUTY_LSCH4 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */
+/*description: The register is used to control output duty. When lstimerx(x=[0
+ 3]) choosed by low speed channel4 has reached reg_lpoint_lsch4 the output signal changes to low. reg_lpoint_lsch4=(reg_hpoint_lsch4[19:0]+reg_duty_lsch4[24:4]) (1) reg_lpoint_lsch4=(reg_hpoint_lsch4[19:0]+reg_duty_lsch4[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/
+#define LEDC_DUTY_LSCH4 0x01FFFFFF
+#define LEDC_DUTY_LSCH4_M ((LEDC_DUTY_LSCH4_V)<<(LEDC_DUTY_LSCH4_S))
+#define LEDC_DUTY_LSCH4_V 0x1FFFFFF
+#define LEDC_DUTY_LSCH4_S 0
+
+#define LEDC_LSCH4_CONF1_REG (DR_REG_LEDC_BASE + 0x00FC)
+/* LEDC_DUTY_START_LSCH4 : R/W ;bitpos:[31] ;default: 1'b0 ; */
+/*description: When reg_duty_num_hsch4 reg_duty_cycle_hsch4 and reg_duty_scale_hsch4
+ has been configured. these register won't take effect until set reg_duty_start_hsch4. this bit is automatically cleared by hardware.*/
+#define LEDC_DUTY_START_LSCH4 (BIT(31))
+#define LEDC_DUTY_START_LSCH4_M (BIT(31))
+#define LEDC_DUTY_START_LSCH4_V 0x1
+#define LEDC_DUTY_START_LSCH4_S 31
+/* LEDC_DUTY_INC_LSCH4 : R/W ;bitpos:[30] ;default: 1'b1 ; */
+/*description: This register is used to increase the duty of output signal or
+ decrease the duty of output signal for low speed channel4.*/
+#define LEDC_DUTY_INC_LSCH4 (BIT(30))
+#define LEDC_DUTY_INC_LSCH4_M (BIT(30))
+#define LEDC_DUTY_INC_LSCH4_V 0x1
+#define LEDC_DUTY_INC_LSCH4_S 30
+/* LEDC_DUTY_NUM_LSCH4 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */
+/*description: This register is used to control the num of increased or decreased
+ times for low speed channel4.*/
+#define LEDC_DUTY_NUM_LSCH4 0x000003FF
+#define LEDC_DUTY_NUM_LSCH4_M ((LEDC_DUTY_NUM_LSCH4_V)<<(LEDC_DUTY_NUM_LSCH4_S))
+#define LEDC_DUTY_NUM_LSCH4_V 0x3FF
+#define LEDC_DUTY_NUM_LSCH4_S 20
+/* LEDC_DUTY_CYCLE_LSCH4 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */
+/*description: This register is used to increase or decrease the duty every
+ reg_duty_cycle_lsch4 cycles for low speed channel4.*/
+#define LEDC_DUTY_CYCLE_LSCH4 0x000003FF
+#define LEDC_DUTY_CYCLE_LSCH4_M ((LEDC_DUTY_CYCLE_LSCH4_V)<<(LEDC_DUTY_CYCLE_LSCH4_S))
+#define LEDC_DUTY_CYCLE_LSCH4_V 0x3FF
+#define LEDC_DUTY_CYCLE_LSCH4_S 10
+/* LEDC_DUTY_SCALE_LSCH4 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */
+/*description: This register controls the increase or decrease step scale for
+ low speed channel4.*/
+#define LEDC_DUTY_SCALE_LSCH4 0x000003FF
+#define LEDC_DUTY_SCALE_LSCH4_M ((LEDC_DUTY_SCALE_LSCH4_V)<<(LEDC_DUTY_SCALE_LSCH4_S))
+#define LEDC_DUTY_SCALE_LSCH4_V 0x3FF
+#define LEDC_DUTY_SCALE_LSCH4_S 0
+
+#define LEDC_LSCH4_DUTY_R_REG (DR_REG_LEDC_BASE + 0x0100)
+/* LEDC_DUTY_LSCH4 : RO ;bitpos:[24:0] ;default: 25'h0 ; */
+/*description: This register represents the current duty of the output signal
+ for low speed channel4.*/
+#define LEDC_DUTY_LSCH4 0x01FFFFFF
+#define LEDC_DUTY_LSCH4_M ((LEDC_DUTY_LSCH4_V)<<(LEDC_DUTY_LSCH4_S))
+#define LEDC_DUTY_LSCH4_V 0x1FFFFFF
+#define LEDC_DUTY_LSCH4_S 0
+
+#define LEDC_LSCH5_CONF0_REG (DR_REG_LEDC_BASE + 0x0104)
+/* LEDC_PARA_UP_LSCH5 : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: This bit is used to update register LEDC_LSCH5_HPOINT and LEDC_LSCH5_DUTY
+ for low speed channel5.*/
+#define LEDC_PARA_UP_LSCH5 (BIT(4))
+#define LEDC_PARA_UP_LSCH5_M (BIT(4))
+#define LEDC_PARA_UP_LSCH5_V 0x1
+#define LEDC_PARA_UP_LSCH5_S 4
+/* LEDC_IDLE_LV_LSCH5 : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: This bit is used to control the output value when low speed channel5 is off.*/
+#define LEDC_IDLE_LV_LSCH5 (BIT(3))
+#define LEDC_IDLE_LV_LSCH5_M (BIT(3))
+#define LEDC_IDLE_LV_LSCH5_V 0x1
+#define LEDC_IDLE_LV_LSCH5_S 3
+/* LEDC_SIG_OUT_EN_LSCH5 : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: This is the output enable control bit for low speed channel5.*/
+#define LEDC_SIG_OUT_EN_LSCH5 (BIT(2))
+#define LEDC_SIG_OUT_EN_LSCH5_M (BIT(2))
+#define LEDC_SIG_OUT_EN_LSCH5_V 0x1
+#define LEDC_SIG_OUT_EN_LSCH5_S 2
+/* LEDC_TIMER_SEL_LSCH5 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */
+/*description: There are four low speed timers the two bits are used to select
+ one of them for low speed channel5. 2'b00: seletc lstimer0. 2'b01: select lstimer1. 2'b10: select lstimer2. 2'b11: select lstimer3.*/
+#define LEDC_TIMER_SEL_LSCH5 0x00000003
+#define LEDC_TIMER_SEL_LSCH5_M ((LEDC_TIMER_SEL_LSCH5_V)<<(LEDC_TIMER_SEL_LSCH5_S))
+#define LEDC_TIMER_SEL_LSCH5_V 0x3
+#define LEDC_TIMER_SEL_LSCH5_S 0
+
+#define LEDC_LSCH5_HPOINT_REG (DR_REG_LEDC_BASE + 0x0108)
+/* LEDC_HPOINT_LSCH5 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */
+/*description: The output value changes to high when lstimerx(x=[0 3]) selected
+ by low speed channel5 has reached reg_hpoint_lsch5[19:0]*/
+#define LEDC_HPOINT_LSCH5 0x000FFFFF
+#define LEDC_HPOINT_LSCH5_M ((LEDC_HPOINT_LSCH5_V)<<(LEDC_HPOINT_LSCH5_S))
+#define LEDC_HPOINT_LSCH5_V 0xFFFFF
+#define LEDC_HPOINT_LSCH5_S 0
+
+#define LEDC_LSCH5_DUTY_REG (DR_REG_LEDC_BASE + 0x010C)
+/* LEDC_DUTY_LSCH5 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */
+/*description: The register is used to control output duty. When lstimerx(x=[0
+ 3]) choosed by low speed channel5 has reached reg_lpoint_lsch5 the output signal changes to low. reg_lpoint_lsch5=(reg_hpoint_lsch5[19:0]+reg_duty_lsch5[24:4]) (1) reg_lpoint_lsch5=(reg_hpoint_lsch5[19:0]+reg_duty_lsch5[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/
+#define LEDC_DUTY_LSCH5 0x01FFFFFF
+#define LEDC_DUTY_LSCH5_M ((LEDC_DUTY_LSCH5_V)<<(LEDC_DUTY_LSCH5_S))
+#define LEDC_DUTY_LSCH5_V 0x1FFFFFF
+#define LEDC_DUTY_LSCH5_S 0
+
+#define LEDC_LSCH5_CONF1_REG (DR_REG_LEDC_BASE + 0x0110)
+/* LEDC_DUTY_START_LSCH5 : R/W ;bitpos:[31] ;default: 1'b0 ; */
+/*description: When reg_duty_num_hsch4 reg_duty_cycle_hsch4 and reg_duty_scale_hsch4
+ has been configured. these register won't take effect until set reg_duty_start_hsch4. this bit is automatically cleared by hardware.*/
+#define LEDC_DUTY_START_LSCH5 (BIT(31))
+#define LEDC_DUTY_START_LSCH5_M (BIT(31))
+#define LEDC_DUTY_START_LSCH5_V 0x1
+#define LEDC_DUTY_START_LSCH5_S 31
+/* LEDC_DUTY_INC_LSCH5 : R/W ;bitpos:[30] ;default: 1'b1 ; */
+/*description: This register is used to increase the duty of output signal or
+ decrease the duty of output signal for low speed channel5.*/
+#define LEDC_DUTY_INC_LSCH5 (BIT(30))
+#define LEDC_DUTY_INC_LSCH5_M (BIT(30))
+#define LEDC_DUTY_INC_LSCH5_V 0x1
+#define LEDC_DUTY_INC_LSCH5_S 30
+/* LEDC_DUTY_NUM_LSCH5 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */
+/*description: This register is used to control the num of increased or decreased
+ times for low speed channel5.*/
+#define LEDC_DUTY_NUM_LSCH5 0x000003FF
+#define LEDC_DUTY_NUM_LSCH5_M ((LEDC_DUTY_NUM_LSCH5_V)<<(LEDC_DUTY_NUM_LSCH5_S))
+#define LEDC_DUTY_NUM_LSCH5_V 0x3FF
+#define LEDC_DUTY_NUM_LSCH5_S 20
+/* LEDC_DUTY_CYCLE_LSCH5 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */
+/*description: This register is used to increase or decrease the duty every
+ reg_duty_cycle_lsch5 cycles for low speed channel4.*/
+#define LEDC_DUTY_CYCLE_LSCH5 0x000003FF
+#define LEDC_DUTY_CYCLE_LSCH5_M ((LEDC_DUTY_CYCLE_LSCH5_V)<<(LEDC_DUTY_CYCLE_LSCH5_S))
+#define LEDC_DUTY_CYCLE_LSCH5_V 0x3FF
+#define LEDC_DUTY_CYCLE_LSCH5_S 10
+/* LEDC_DUTY_SCALE_LSCH5 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */
+/*description: This register controls the increase or decrease step scale for
+ low speed channel5.*/
+#define LEDC_DUTY_SCALE_LSCH5 0x000003FF
+#define LEDC_DUTY_SCALE_LSCH5_M ((LEDC_DUTY_SCALE_LSCH5_V)<<(LEDC_DUTY_SCALE_LSCH5_S))
+#define LEDC_DUTY_SCALE_LSCH5_V 0x3FF
+#define LEDC_DUTY_SCALE_LSCH5_S 0
+
+#define LEDC_LSCH5_DUTY_R_REG (DR_REG_LEDC_BASE + 0x0114)
+/* LEDC_DUTY_LSCH5 : RO ;bitpos:[24:0] ;default: 25'h0 ; */
+/*description: This register represents the current duty of the output signal
+ for low speed channel5.*/
+#define LEDC_DUTY_LSCH5 0x01FFFFFF
+#define LEDC_DUTY_LSCH5_M ((LEDC_DUTY_LSCH5_V)<<(LEDC_DUTY_LSCH5_S))
+#define LEDC_DUTY_LSCH5_V 0x1FFFFFF
+#define LEDC_DUTY_LSCH5_S 0
+
+#define LEDC_LSCH6_CONF0_REG (DR_REG_LEDC_BASE + 0x0118)
+/* LEDC_PARA_UP_LSCH6 : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: This bit is used to update register LEDC_LSCH6_HPOINT and LEDC_LSCH6_DUTY
+ for low speed channel6.*/
+#define LEDC_PARA_UP_LSCH6 (BIT(4))
+#define LEDC_PARA_UP_LSCH6_M (BIT(4))
+#define LEDC_PARA_UP_LSCH6_V 0x1
+#define LEDC_PARA_UP_LSCH6_S 4
+/* LEDC_IDLE_LV_LSCH6 : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: This bit is used to control the output value when low speed channel6 is off.*/
+#define LEDC_IDLE_LV_LSCH6 (BIT(3))
+#define LEDC_IDLE_LV_LSCH6_M (BIT(3))
+#define LEDC_IDLE_LV_LSCH6_V 0x1
+#define LEDC_IDLE_LV_LSCH6_S 3
+/* LEDC_SIG_OUT_EN_LSCH6 : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: This is the output enable control bit for low speed channel6.*/
+#define LEDC_SIG_OUT_EN_LSCH6 (BIT(2))
+#define LEDC_SIG_OUT_EN_LSCH6_M (BIT(2))
+#define LEDC_SIG_OUT_EN_LSCH6_V 0x1
+#define LEDC_SIG_OUT_EN_LSCH6_S 2
+/* LEDC_TIMER_SEL_LSCH6 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */
+/*description: There are four low speed timers the two bits are used to select
+ one of them for low speed channel6. 2'b00: seletc lstimer0. 2'b01: select lstimer1. 2'b10: select lstimer2. 2'b11: select lstimer3.*/
+#define LEDC_TIMER_SEL_LSCH6 0x00000003
+#define LEDC_TIMER_SEL_LSCH6_M ((LEDC_TIMER_SEL_LSCH6_V)<<(LEDC_TIMER_SEL_LSCH6_S))
+#define LEDC_TIMER_SEL_LSCH6_V 0x3
+#define LEDC_TIMER_SEL_LSCH6_S 0
+
+#define LEDC_LSCH6_HPOINT_REG (DR_REG_LEDC_BASE + 0x011C)
+/* LEDC_HPOINT_LSCH6 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */
+/*description: The output value changes to high when lstimerx(x=[0 3]) selected
+ by low speed channel6 has reached reg_hpoint_lsch6[19:0]*/
+#define LEDC_HPOINT_LSCH6 0x000FFFFF
+#define LEDC_HPOINT_LSCH6_M ((LEDC_HPOINT_LSCH6_V)<<(LEDC_HPOINT_LSCH6_S))
+#define LEDC_HPOINT_LSCH6_V 0xFFFFF
+#define LEDC_HPOINT_LSCH6_S 0
+
+#define LEDC_LSCH6_DUTY_REG (DR_REG_LEDC_BASE + 0x0120)
+/* LEDC_DUTY_LSCH6 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */
+/*description: The register is used to control output duty. When lstimerx(x=[0
+ 3]) choosed by low speed channel6 has reached reg_lpoint_lsch6 the output signal changes to low. reg_lpoint_lsch6=(reg_hpoint_lsch6[19:0]+reg_duty_lsch6[24:4]) (1) reg_lpoint_lsch6=(reg_hpoint_lsch6[19:0]+reg_duty_lsch6[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/
+#define LEDC_DUTY_LSCH6 0x01FFFFFF
+#define LEDC_DUTY_LSCH6_M ((LEDC_DUTY_LSCH6_V)<<(LEDC_DUTY_LSCH6_S))
+#define LEDC_DUTY_LSCH6_V 0x1FFFFFF
+#define LEDC_DUTY_LSCH6_S 0
+
+#define LEDC_LSCH6_CONF1_REG (DR_REG_LEDC_BASE + 0x0124)
+/* LEDC_DUTY_START_LSCH6 : R/W ;bitpos:[31] ;default: 1'b0 ; */
+/*description: When reg_duty_num_hsch6 reg_duty_cycle_hsch6 and reg_duty_scale_hsch6
+ has been configured. these register won't take effect until set reg_duty_start_hsch6. this bit is automatically cleared by hardware.*/
+#define LEDC_DUTY_START_LSCH6 (BIT(31))
+#define LEDC_DUTY_START_LSCH6_M (BIT(31))
+#define LEDC_DUTY_START_LSCH6_V 0x1
+#define LEDC_DUTY_START_LSCH6_S 31
+/* LEDC_DUTY_INC_LSCH6 : R/W ;bitpos:[30] ;default: 1'b1 ; */
+/*description: This register is used to increase the duty of output signal or
+ decrease the duty of output signal for low speed channel6.*/
+#define LEDC_DUTY_INC_LSCH6 (BIT(30))
+#define LEDC_DUTY_INC_LSCH6_M (BIT(30))
+#define LEDC_DUTY_INC_LSCH6_V 0x1
+#define LEDC_DUTY_INC_LSCH6_S 30
+/* LEDC_DUTY_NUM_LSCH6 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */
+/*description: This register is used to control the num of increased or decreased
+ times for low speed channel6.*/
+#define LEDC_DUTY_NUM_LSCH6 0x000003FF
+#define LEDC_DUTY_NUM_LSCH6_M ((LEDC_DUTY_NUM_LSCH6_V)<<(LEDC_DUTY_NUM_LSCH6_S))
+#define LEDC_DUTY_NUM_LSCH6_V 0x3FF
+#define LEDC_DUTY_NUM_LSCH6_S 20
+/* LEDC_DUTY_CYCLE_LSCH6 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */
+/*description: This register is used to increase or decrease the duty every
+ reg_duty_cycle_lsch6 cycles for low speed channel6.*/
+#define LEDC_DUTY_CYCLE_LSCH6 0x000003FF
+#define LEDC_DUTY_CYCLE_LSCH6_M ((LEDC_DUTY_CYCLE_LSCH6_V)<<(LEDC_DUTY_CYCLE_LSCH6_S))
+#define LEDC_DUTY_CYCLE_LSCH6_V 0x3FF
+#define LEDC_DUTY_CYCLE_LSCH6_S 10
+/* LEDC_DUTY_SCALE_LSCH6 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */
+/*description: This register controls the increase or decrease step scale for
+ low speed channel6.*/
+#define LEDC_DUTY_SCALE_LSCH6 0x000003FF
+#define LEDC_DUTY_SCALE_LSCH6_M ((LEDC_DUTY_SCALE_LSCH6_V)<<(LEDC_DUTY_SCALE_LSCH6_S))
+#define LEDC_DUTY_SCALE_LSCH6_V 0x3FF
+#define LEDC_DUTY_SCALE_LSCH6_S 0
+
+#define LEDC_LSCH6_DUTY_R_REG (DR_REG_LEDC_BASE + 0x0128)
+/* LEDC_DUTY_LSCH6 : RO ;bitpos:[24:0] ;default: 25'h0 ; */
+/*description: This register represents the current duty of the output signal
+ for low speed channel6.*/
+#define LEDC_DUTY_LSCH6 0x01FFFFFF
+#define LEDC_DUTY_LSCH6_M ((LEDC_DUTY_LSCH6_V)<<(LEDC_DUTY_LSCH6_S))
+#define LEDC_DUTY_LSCH6_V 0x1FFFFFF
+#define LEDC_DUTY_LSCH6_S 0
+
+#define LEDC_LSCH7_CONF0_REG (DR_REG_LEDC_BASE + 0x012C)
+/* LEDC_PARA_UP_LSCH7 : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: This bit is used to update register LEDC_LSCH7_HPOINT and LEDC_LSCH7_DUTY
+ for low speed channel7.*/
+#define LEDC_PARA_UP_LSCH7 (BIT(4))
+#define LEDC_PARA_UP_LSCH7_M (BIT(4))
+#define LEDC_PARA_UP_LSCH7_V 0x1
+#define LEDC_PARA_UP_LSCH7_S 4
+/* LEDC_IDLE_LV_LSCH7 : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: This bit is used to control the output value when low speed channel7 is off.*/
+#define LEDC_IDLE_LV_LSCH7 (BIT(3))
+#define LEDC_IDLE_LV_LSCH7_M (BIT(3))
+#define LEDC_IDLE_LV_LSCH7_V 0x1
+#define LEDC_IDLE_LV_LSCH7_S 3
+/* LEDC_SIG_OUT_EN_LSCH7 : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: This is the output enable control bit for low speed channel7.*/
+#define LEDC_SIG_OUT_EN_LSCH7 (BIT(2))
+#define LEDC_SIG_OUT_EN_LSCH7_M (BIT(2))
+#define LEDC_SIG_OUT_EN_LSCH7_V 0x1
+#define LEDC_SIG_OUT_EN_LSCH7_S 2
+/* LEDC_TIMER_SEL_LSCH7 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */
+/*description: There are four low speed timers the two bits are used to select
+ one of them for low speed channel7. 2'b00: seletc lstimer0. 2'b01: select lstimer1. 2'b10: select lstimer2. 2'b11: select lstimer3.*/
+#define LEDC_TIMER_SEL_LSCH7 0x00000003
+#define LEDC_TIMER_SEL_LSCH7_M ((LEDC_TIMER_SEL_LSCH7_V)<<(LEDC_TIMER_SEL_LSCH7_S))
+#define LEDC_TIMER_SEL_LSCH7_V 0x3
+#define LEDC_TIMER_SEL_LSCH7_S 0
+
+#define LEDC_LSCH7_HPOINT_REG (DR_REG_LEDC_BASE + 0x0130)
+/* LEDC_HPOINT_LSCH7 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */
+/*description: The output value changes to high when lstimerx(x=[0 3]) selected
+ by low speed channel7 has reached reg_hpoint_lsch7[19:0]*/
+#define LEDC_HPOINT_LSCH7 0x000FFFFF
+#define LEDC_HPOINT_LSCH7_M ((LEDC_HPOINT_LSCH7_V)<<(LEDC_HPOINT_LSCH7_S))
+#define LEDC_HPOINT_LSCH7_V 0xFFFFF
+#define LEDC_HPOINT_LSCH7_S 0
+
+#define LEDC_LSCH7_DUTY_REG (DR_REG_LEDC_BASE + 0x0134)
+/* LEDC_DUTY_LSCH7 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */
+/*description: The register is used to control output duty. When lstimerx(x=[0
+ 3]) choosed by low speed channel7 has reached reg_lpoint_lsch7 the output signal changes to low. reg_lpoint_lsch7=(reg_hpoint_lsch7[19:0]+reg_duty_lsch7[24:4]) (1) reg_lpoint_lsch7=(reg_hpoint_lsch7[19:0]+reg_duty_lsch7[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/
+#define LEDC_DUTY_LSCH7 0x01FFFFFF
+#define LEDC_DUTY_LSCH7_M ((LEDC_DUTY_LSCH7_V)<<(LEDC_DUTY_LSCH7_S))
+#define LEDC_DUTY_LSCH7_V 0x1FFFFFF
+#define LEDC_DUTY_LSCH7_S 0
+
+#define LEDC_LSCH7_CONF1_REG (DR_REG_LEDC_BASE + 0x0138)
+/* LEDC_DUTY_START_LSCH7 : R/W ;bitpos:[31] ;default: 1'b0 ; */
+/*description: When reg_duty_num_hsch4 reg_duty_cycle_hsch4 and reg_duty_scale_hsch4
+ has been configured. these register won't take effect until set reg_duty_start_hsch4. this bit is automatically cleared by hardware.*/
+#define LEDC_DUTY_START_LSCH7 (BIT(31))
+#define LEDC_DUTY_START_LSCH7_M (BIT(31))
+#define LEDC_DUTY_START_LSCH7_V 0x1
+#define LEDC_DUTY_START_LSCH7_S 31
+/* LEDC_DUTY_INC_LSCH7 : R/W ;bitpos:[30] ;default: 1'b1 ; */
+/*description: This register is used to increase the duty of output signal or
+ decrease the duty of output signal for low speed channel4.*/
+#define LEDC_DUTY_INC_LSCH7 (BIT(30))
+#define LEDC_DUTY_INC_LSCH7_M (BIT(30))
+#define LEDC_DUTY_INC_LSCH7_V 0x1
+#define LEDC_DUTY_INC_LSCH7_S 30
+/* LEDC_DUTY_NUM_LSCH7 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */
+/*description: This register is used to control the num of increased or decreased
+ times for low speed channel4.*/
+#define LEDC_DUTY_NUM_LSCH7 0x000003FF
+#define LEDC_DUTY_NUM_LSCH7_M ((LEDC_DUTY_NUM_LSCH7_V)<<(LEDC_DUTY_NUM_LSCH7_S))
+#define LEDC_DUTY_NUM_LSCH7_V 0x3FF
+#define LEDC_DUTY_NUM_LSCH7_S 20
+/* LEDC_DUTY_CYCLE_LSCH7 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */
+/*description: This register is used to increase or decrease the duty every
+ reg_duty_cycle_lsch7 cycles for low speed channel7.*/
+#define LEDC_DUTY_CYCLE_LSCH7 0x000003FF
+#define LEDC_DUTY_CYCLE_LSCH7_M ((LEDC_DUTY_CYCLE_LSCH7_V)<<(LEDC_DUTY_CYCLE_LSCH7_S))
+#define LEDC_DUTY_CYCLE_LSCH7_V 0x3FF
+#define LEDC_DUTY_CYCLE_LSCH7_S 10
+/* LEDC_DUTY_SCALE_LSCH7 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */
+/*description: This register controls the increase or decrease step scale for
+ low speed channel7.*/
+#define LEDC_DUTY_SCALE_LSCH7 0x000003FF
+#define LEDC_DUTY_SCALE_LSCH7_M ((LEDC_DUTY_SCALE_LSCH7_V)<<(LEDC_DUTY_SCALE_LSCH7_S))
+#define LEDC_DUTY_SCALE_LSCH7_V 0x3FF
+#define LEDC_DUTY_SCALE_LSCH7_S 0
+
+#define LEDC_LSCH7_DUTY_R_REG (DR_REG_LEDC_BASE + 0x013C)
+/* LEDC_DUTY_LSCH7 : RO ;bitpos:[24:0] ;default: 25'h0 ; */
+/*description: This register represents the current duty of the output signal
+ for low speed channel7.*/
+#define LEDC_DUTY_LSCH7 0x01FFFFFF
+#define LEDC_DUTY_LSCH7_M ((LEDC_DUTY_LSCH7_V)<<(LEDC_DUTY_LSCH7_S))
+#define LEDC_DUTY_LSCH7_V 0x1FFFFFF
+#define LEDC_DUTY_LSCH7_S 0
+
+#define LEDC_HSTIMER0_CONF_REG (DR_REG_LEDC_BASE + 0x0140)
+/* LEDC_TICK_SEL_HSTIMER0 : R/W ;bitpos:[25] ;default: 1'b0 ; */
+/*description: This bit is used to choose apb_clk or ref_tick for high speed
+ timer0. 1'b1:apb_clk 0:ref_tick*/
+#define LEDC_TICK_SEL_HSTIMER0 (BIT(25))
+#define LEDC_TICK_SEL_HSTIMER0_M (BIT(25))
+#define LEDC_TICK_SEL_HSTIMER0_V 0x1
+#define LEDC_TICK_SEL_HSTIMER0_S 25
+/* LEDC_HSTIMER0_RST : R/W ;bitpos:[24] ;default: 1'b1 ; */
+/*description: This bit is used to reset high speed timer0 the counter will be 0 after reset.*/
+#define LEDC_HSTIMER0_RST (BIT(24))
+#define LEDC_HSTIMER0_RST_M (BIT(24))
+#define LEDC_HSTIMER0_RST_V 0x1
+#define LEDC_HSTIMER0_RST_S 24
+/* LEDC_HSTIMER0_PAUSE : R/W ;bitpos:[23] ;default: 1'b0 ; */
+/*description: This bit is used to pause the counter in high speed timer0*/
+#define LEDC_HSTIMER0_PAUSE (BIT(23))
+#define LEDC_HSTIMER0_PAUSE_M (BIT(23))
+#define LEDC_HSTIMER0_PAUSE_V 0x1
+#define LEDC_HSTIMER0_PAUSE_S 23
+/* LEDC_DIV_NUM_HSTIMER0 : R/W ;bitpos:[22:5] ;default: 18'h0 ; */
+/*description: This register is used to configure parameter for divider in high
+ speed timer0 the least significant eight bits represent the decimal part.*/
+#define LEDC_DIV_NUM_HSTIMER0 0x0003FFFF
+#define LEDC_DIV_NUM_HSTIMER0_M ((LEDC_DIV_NUM_HSTIMER0_V)<<(LEDC_DIV_NUM_HSTIMER0_S))
+#define LEDC_DIV_NUM_HSTIMER0_V 0x3FFFF
+#define LEDC_DIV_NUM_HSTIMER0_S 5
+/* LEDC_HSTIMER0_LIM : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: This register controls the range of the counter in high speed
+ timer0. the counter range is [0 2**reg_hstimer0_lim] the max bit width for counter is 20.*/
+#define LEDC_HSTIMER0_LIM 0x0000001F
+#define LEDC_HSTIMER0_LIM_M ((LEDC_HSTIMER0_LIM_V)<<(LEDC_HSTIMER0_LIM_S))
+#define LEDC_HSTIMER0_LIM_V 0x1F
+#define LEDC_HSTIMER0_LIM_S 0
+
+#define LEDC_HSTIMER0_VALUE_REG (DR_REG_LEDC_BASE + 0x0144)
+/* LEDC_HSTIMER0_CNT : RO ;bitpos:[19:0] ;default: 20'b0 ; */
+/*description: software can read this register to get the current counter value
+ in high speed timer0*/
+#define LEDC_HSTIMER0_CNT 0x000FFFFF
+#define LEDC_HSTIMER0_CNT_M ((LEDC_HSTIMER0_CNT_V)<<(LEDC_HSTIMER0_CNT_S))
+#define LEDC_HSTIMER0_CNT_V 0xFFFFF
+#define LEDC_HSTIMER0_CNT_S 0
+
+#define LEDC_HSTIMER1_CONF_REG (DR_REG_LEDC_BASE + 0x0148)
+/* LEDC_TICK_SEL_HSTIMER1 : R/W ;bitpos:[25] ;default: 1'b0 ; */
+/*description: This bit is used to choose apb_clk or ref_tick for high speed
+ timer1. 1'b1:apb_clk 0:ref_tick*/
+#define LEDC_TICK_SEL_HSTIMER1 (BIT(25))
+#define LEDC_TICK_SEL_HSTIMER1_M (BIT(25))
+#define LEDC_TICK_SEL_HSTIMER1_V 0x1
+#define LEDC_TICK_SEL_HSTIMER1_S 25
+/* LEDC_HSTIMER1_RST : R/W ;bitpos:[24] ;default: 1'b1 ; */
+/*description: This bit is used to reset high speed timer1 the counter will be 0 after reset.*/
+#define LEDC_HSTIMER1_RST (BIT(24))
+#define LEDC_HSTIMER1_RST_M (BIT(24))
+#define LEDC_HSTIMER1_RST_V 0x1
+#define LEDC_HSTIMER1_RST_S 24
+/* LEDC_HSTIMER1_PAUSE : R/W ;bitpos:[23] ;default: 1'b0 ; */
+/*description: This bit is used to pause the counter in high speed timer1*/
+#define LEDC_HSTIMER1_PAUSE (BIT(23))
+#define LEDC_HSTIMER1_PAUSE_M (BIT(23))
+#define LEDC_HSTIMER1_PAUSE_V 0x1
+#define LEDC_HSTIMER1_PAUSE_S 23
+/* LEDC_DIV_NUM_HSTIMER1 : R/W ;bitpos:[22:5] ;default: 18'h0 ; */
+/*description: This register is used to configure parameter for divider in high
+ speed timer1 the least significant eight bits represent the decimal part.*/
+#define LEDC_DIV_NUM_HSTIMER1 0x0003FFFF
+#define LEDC_DIV_NUM_HSTIMER1_M ((LEDC_DIV_NUM_HSTIMER1_V)<<(LEDC_DIV_NUM_HSTIMER1_S))
+#define LEDC_DIV_NUM_HSTIMER1_V 0x3FFFF
+#define LEDC_DIV_NUM_HSTIMER1_S 5
+/* LEDC_HSTIMER1_LIM : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: This register controls the range of the counter in high speed
+ timer1. the counter range is [0 2**reg_hstimer1_lim] the max bit width for counter is 20.*/
+#define LEDC_HSTIMER1_LIM 0x0000001F
+#define LEDC_HSTIMER1_LIM_M ((LEDC_HSTIMER1_LIM_V)<<(LEDC_HSTIMER1_LIM_S))
+#define LEDC_HSTIMER1_LIM_V 0x1F
+#define LEDC_HSTIMER1_LIM_S 0
+
+#define LEDC_HSTIMER1_VALUE_REG (DR_REG_LEDC_BASE + 0x014C)
+/* LEDC_HSTIMER1_CNT : RO ;bitpos:[19:0] ;default: 20'b0 ; */
+/*description: software can read this register to get the current counter value
+ in high speed timer1.*/
+#define LEDC_HSTIMER1_CNT 0x000FFFFF
+#define LEDC_HSTIMER1_CNT_M ((LEDC_HSTIMER1_CNT_V)<<(LEDC_HSTIMER1_CNT_S))
+#define LEDC_HSTIMER1_CNT_V 0xFFFFF
+#define LEDC_HSTIMER1_CNT_S 0
+
+#define LEDC_HSTIMER2_CONF_REG (DR_REG_LEDC_BASE + 0x0150)
+/* LEDC_TICK_SEL_HSTIMER2 : R/W ;bitpos:[25] ;default: 1'b0 ; */
+/*description: This bit is used to choose apb_clk or ref_tick for high speed
+ timer2. 1'b1:apb_clk 0:ref_tick*/
+#define LEDC_TICK_SEL_HSTIMER2 (BIT(25))
+#define LEDC_TICK_SEL_HSTIMER2_M (BIT(25))
+#define LEDC_TICK_SEL_HSTIMER2_V 0x1
+#define LEDC_TICK_SEL_HSTIMER2_S 25
+/* LEDC_HSTIMER2_RST : R/W ;bitpos:[24] ;default: 1'b1 ; */
+/*description: This bit is used to reset high speed timer2 the counter will be 0 after reset.*/
+#define LEDC_HSTIMER2_RST (BIT(24))
+#define LEDC_HSTIMER2_RST_M (BIT(24))
+#define LEDC_HSTIMER2_RST_V 0x1
+#define LEDC_HSTIMER2_RST_S 24
+/* LEDC_HSTIMER2_PAUSE : R/W ;bitpos:[23] ;default: 1'b0 ; */
+/*description: This bit is used to pause the counter in high speed timer2*/
+#define LEDC_HSTIMER2_PAUSE (BIT(23))
+#define LEDC_HSTIMER2_PAUSE_M (BIT(23))
+#define LEDC_HSTIMER2_PAUSE_V 0x1
+#define LEDC_HSTIMER2_PAUSE_S 23
+/* LEDC_DIV_NUM_HSTIMER2 : R/W ;bitpos:[22:5] ;default: 18'h0 ; */
+/*description: This register is used to configure parameter for divider in high
+ speed timer2 the least significant eight bits represent the decimal part.*/
+#define LEDC_DIV_NUM_HSTIMER2 0x0003FFFF
+#define LEDC_DIV_NUM_HSTIMER2_M ((LEDC_DIV_NUM_HSTIMER2_V)<<(LEDC_DIV_NUM_HSTIMER2_S))
+#define LEDC_DIV_NUM_HSTIMER2_V 0x3FFFF
+#define LEDC_DIV_NUM_HSTIMER2_S 5
+/* LEDC_HSTIMER2_LIM : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: This register controls the range of the counter in high speed
+ timer2. the counter range is [0 2**reg_hstimer2_lim] the max bit width for counter is 20.*/
+#define LEDC_HSTIMER2_LIM 0x0000001F
+#define LEDC_HSTIMER2_LIM_M ((LEDC_HSTIMER2_LIM_V)<<(LEDC_HSTIMER2_LIM_S))
+#define LEDC_HSTIMER2_LIM_V 0x1F
+#define LEDC_HSTIMER2_LIM_S 0
+
+#define LEDC_HSTIMER2_VALUE_REG (DR_REG_LEDC_BASE + 0x0154)
+/* LEDC_HSTIMER2_CNT : RO ;bitpos:[19:0] ;default: 20'b0 ; */
+/*description: software can read this register to get the current counter value
+ in high speed timer2*/
+#define LEDC_HSTIMER2_CNT 0x000FFFFF
+#define LEDC_HSTIMER2_CNT_M ((LEDC_HSTIMER2_CNT_V)<<(LEDC_HSTIMER2_CNT_S))
+#define LEDC_HSTIMER2_CNT_V 0xFFFFF
+#define LEDC_HSTIMER2_CNT_S 0
+
+#define LEDC_HSTIMER3_CONF_REG (DR_REG_LEDC_BASE + 0x0158)
+/* LEDC_TICK_SEL_HSTIMER3 : R/W ;bitpos:[25] ;default: 1'b0 ; */
+/*description: This bit is used to choose apb_clk or ref_tick for high speed
+ timer3. 1'b1:apb_clk 0:ref_tick*/
+#define LEDC_TICK_SEL_HSTIMER3 (BIT(25))
+#define LEDC_TICK_SEL_HSTIMER3_M (BIT(25))
+#define LEDC_TICK_SEL_HSTIMER3_V 0x1
+#define LEDC_TICK_SEL_HSTIMER3_S 25
+/* LEDC_HSTIMER3_RST : R/W ;bitpos:[24] ;default: 1'b1 ; */
+/*description: This bit is used to reset high speed timer3 the counter will be 0 after reset.*/
+#define LEDC_HSTIMER3_RST (BIT(24))
+#define LEDC_HSTIMER3_RST_M (BIT(24))
+#define LEDC_HSTIMER3_RST_V 0x1
+#define LEDC_HSTIMER3_RST_S 24
+/* LEDC_HSTIMER3_PAUSE : R/W ;bitpos:[23] ;default: 1'b0 ; */
+/*description: This bit is used to pause the counter in high speed timer3*/
+#define LEDC_HSTIMER3_PAUSE (BIT(23))
+#define LEDC_HSTIMER3_PAUSE_M (BIT(23))
+#define LEDC_HSTIMER3_PAUSE_V 0x1
+#define LEDC_HSTIMER3_PAUSE_S 23
+/* LEDC_DIV_NUM_HSTIMER3 : R/W ;bitpos:[22:5] ;default: 18'h0 ; */
+/*description: This register is used to configure parameter for divider in high
+ speed timer3 the least significant eight bits represent the decimal part.*/
+#define LEDC_DIV_NUM_HSTIMER3 0x0003FFFF
+#define LEDC_DIV_NUM_HSTIMER3_M ((LEDC_DIV_NUM_HSTIMER3_V)<<(LEDC_DIV_NUM_HSTIMER3_S))
+#define LEDC_DIV_NUM_HSTIMER3_V 0x3FFFF
+#define LEDC_DIV_NUM_HSTIMER3_S 5
+/* LEDC_HSTIMER3_LIM : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: This register controls the range of the counter in high speed
+ timer3. the counter range is [0 2**reg_hstimer3_lim] the max bit width for counter is 20.*/
+#define LEDC_HSTIMER3_LIM 0x0000001F
+#define LEDC_HSTIMER3_LIM_M ((LEDC_HSTIMER3_LIM_V)<<(LEDC_HSTIMER3_LIM_S))
+#define LEDC_HSTIMER3_LIM_V 0x1F
+#define LEDC_HSTIMER3_LIM_S 0
+
+#define LEDC_HSTIMER3_VALUE_REG (DR_REG_LEDC_BASE + 0x015C)
+/* LEDC_HSTIMER3_CNT : RO ;bitpos:[19:0] ;default: 20'b0 ; */
+/*description: software can read this register to get the current counter value
+ in high speed timer3*/
+#define LEDC_HSTIMER3_CNT 0x000FFFFF
+#define LEDC_HSTIMER3_CNT_M ((LEDC_HSTIMER3_CNT_V)<<(LEDC_HSTIMER3_CNT_S))
+#define LEDC_HSTIMER3_CNT_V 0xFFFFF
+#define LEDC_HSTIMER3_CNT_S 0
+
+#define LEDC_LSTIMER0_CONF_REG (DR_REG_LEDC_BASE + 0x0160)
+/* LEDC_LSTIMER0_PARA_UP : R/W ;bitpos:[26] ;default: 1'h0 ; */
+/*description: Set this bit to update reg_div_num_lstime0 and reg_lstimer0_lim.*/
+#define LEDC_LSTIMER0_PARA_UP (BIT(26))
+#define LEDC_LSTIMER0_PARA_UP_M (BIT(26))
+#define LEDC_LSTIMER0_PARA_UP_V 0x1
+#define LEDC_LSTIMER0_PARA_UP_S 26
+/* LEDC_TICK_SEL_LSTIMER0 : R/W ;bitpos:[25] ;default: 1'b0 ; */
+/*description: This bit is used to choose slow_clk or ref_tick for low speed
+ timer0. 1'b1:slow_clk 0:ref_tick*/
+#define LEDC_TICK_SEL_LSTIMER0 (BIT(25))
+#define LEDC_TICK_SEL_LSTIMER0_M (BIT(25))
+#define LEDC_TICK_SEL_LSTIMER0_V 0x1
+#define LEDC_TICK_SEL_LSTIMER0_S 25
+/* LEDC_LSTIMER0_RST : R/W ;bitpos:[24] ;default: 1'b1 ; */
+/*description: This bit is used to reset low speed timer0 the counter will be 0 after reset.*/
+#define LEDC_LSTIMER0_RST (BIT(24))
+#define LEDC_LSTIMER0_RST_M (BIT(24))
+#define LEDC_LSTIMER0_RST_V 0x1
+#define LEDC_LSTIMER0_RST_S 24
+/* LEDC_LSTIMER0_PAUSE : R/W ;bitpos:[23] ;default: 1'b0 ; */
+/*description: This bit is used to pause the counter in low speed timer0.*/
+#define LEDC_LSTIMER0_PAUSE (BIT(23))
+#define LEDC_LSTIMER0_PAUSE_M (BIT(23))
+#define LEDC_LSTIMER0_PAUSE_V 0x1
+#define LEDC_LSTIMER0_PAUSE_S 23
+/* LEDC_DIV_NUM_LSTIMER0 : R/W ;bitpos:[22:5] ;default: 18'h0 ; */
+/*description: This register is used to configure parameter for divider in low
+ speed timer0 the least significant eight bits represent the decimal part.*/
+#define LEDC_DIV_NUM_LSTIMER0 0x0003FFFF
+#define LEDC_DIV_NUM_LSTIMER0_M ((LEDC_DIV_NUM_LSTIMER0_V)<<(LEDC_DIV_NUM_LSTIMER0_S))
+#define LEDC_DIV_NUM_LSTIMER0_V 0x3FFFF
+#define LEDC_DIV_NUM_LSTIMER0_S 5
+/* LEDC_LSTIMER0_LIM : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: This register controls the range of the counter in low speed
+ timer0. the counter range is [0 2**reg_lstimer0_lim] the max bit width for counter is 20.*/
+#define LEDC_LSTIMER0_LIM 0x0000001F
+#define LEDC_LSTIMER0_LIM_M ((LEDC_LSTIMER0_LIM_V)<<(LEDC_LSTIMER0_LIM_S))
+#define LEDC_LSTIMER0_LIM_V 0x1F
+#define LEDC_LSTIMER0_LIM_S 0
+
+#define LEDC_LSTIMER0_VALUE_REG (DR_REG_LEDC_BASE + 0x0164)
+/* LEDC_LSTIMER0_CNT : RO ;bitpos:[19:0] ;default: 20'b0 ; */
+/*description: software can read this register to get the current counter value
+ in low speed timer0.*/
+#define LEDC_LSTIMER0_CNT 0x000FFFFF
+#define LEDC_LSTIMER0_CNT_M ((LEDC_LSTIMER0_CNT_V)<<(LEDC_LSTIMER0_CNT_S))
+#define LEDC_LSTIMER0_CNT_V 0xFFFFF
+#define LEDC_LSTIMER0_CNT_S 0
+
+#define LEDC_LSTIMER1_CONF_REG (DR_REG_LEDC_BASE + 0x0168)
+/* LEDC_LSTIMER1_PARA_UP : R/W ;bitpos:[26] ;default: 1'h0 ; */
+/*description: Set this bit to update reg_div_num_lstime1 and reg_lstimer1_lim.*/
+#define LEDC_LSTIMER1_PARA_UP (BIT(26))
+#define LEDC_LSTIMER1_PARA_UP_M (BIT(26))
+#define LEDC_LSTIMER1_PARA_UP_V 0x1
+#define LEDC_LSTIMER1_PARA_UP_S 26
+/* LEDC_TICK_SEL_LSTIMER1 : R/W ;bitpos:[25] ;default: 1'b0 ; */
+/*description: This bit is used to choose slow_clk or ref_tick for low speed
+ timer1. 1'b1:slow_clk 0:ref_tick*/
+#define LEDC_TICK_SEL_LSTIMER1 (BIT(25))
+#define LEDC_TICK_SEL_LSTIMER1_M (BIT(25))
+#define LEDC_TICK_SEL_LSTIMER1_V 0x1
+#define LEDC_TICK_SEL_LSTIMER1_S 25
+/* LEDC_LSTIMER1_RST : R/W ;bitpos:[24] ;default: 1'b1 ; */
+/*description: This bit is used to reset low speed timer1 the counter will be 0 after reset.*/
+#define LEDC_LSTIMER1_RST (BIT(24))
+#define LEDC_LSTIMER1_RST_M (BIT(24))
+#define LEDC_LSTIMER1_RST_V 0x1
+#define LEDC_LSTIMER1_RST_S 24
+/* LEDC_LSTIMER1_PAUSE : R/W ;bitpos:[23] ;default: 1'b0 ; */
+/*description: This bit is used to pause the counter in low speed timer1.*/
+#define LEDC_LSTIMER1_PAUSE (BIT(23))
+#define LEDC_LSTIMER1_PAUSE_M (BIT(23))
+#define LEDC_LSTIMER1_PAUSE_V 0x1
+#define LEDC_LSTIMER1_PAUSE_S 23
+/* LEDC_DIV_NUM_LSTIMER1 : R/W ;bitpos:[22:5] ;default: 18'h0 ; */
+/*description: This register is used to configure parameter for divider in low
+ speed timer1 the least significant eight bits represent the decimal part.*/
+#define LEDC_DIV_NUM_LSTIMER1 0x0003FFFF
+#define LEDC_DIV_NUM_LSTIMER1_M ((LEDC_DIV_NUM_LSTIMER1_V)<<(LEDC_DIV_NUM_LSTIMER1_S))
+#define LEDC_DIV_NUM_LSTIMER1_V 0x3FFFF
+#define LEDC_DIV_NUM_LSTIMER1_S 5
+/* LEDC_LSTIMER1_LIM : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: This register controls the range of the counter in low speed
+ timer1. the counter range is [0 2**reg_lstimer1_lim] the max bit width for counter is 20.*/
+#define LEDC_LSTIMER1_LIM 0x0000001F
+#define LEDC_LSTIMER1_LIM_M ((LEDC_LSTIMER1_LIM_V)<<(LEDC_LSTIMER1_LIM_S))
+#define LEDC_LSTIMER1_LIM_V 0x1F
+#define LEDC_LSTIMER1_LIM_S 0
+
+#define LEDC_LSTIMER1_VALUE_REG (DR_REG_LEDC_BASE + 0x016C)
+/* LEDC_LSTIMER1_CNT : RO ;bitpos:[19:0] ;default: 20'b0 ; */
+/*description: software can read this register to get the current counter value
+ in low speed timer1.*/
+#define LEDC_LSTIMER1_CNT 0x000FFFFF
+#define LEDC_LSTIMER1_CNT_M ((LEDC_LSTIMER1_CNT_V)<<(LEDC_LSTIMER1_CNT_S))
+#define LEDC_LSTIMER1_CNT_V 0xFFFFF
+#define LEDC_LSTIMER1_CNT_S 0
+
+#define LEDC_LSTIMER2_CONF_REG (DR_REG_LEDC_BASE + 0x0170)
+/* LEDC_LSTIMER2_PARA_UP : R/W ;bitpos:[26] ;default: 1'h0 ; */
+/*description: Set this bit to update reg_div_num_lstime2 and reg_lstimer2_lim.*/
+#define LEDC_LSTIMER2_PARA_UP (BIT(26))
+#define LEDC_LSTIMER2_PARA_UP_M (BIT(26))
+#define LEDC_LSTIMER2_PARA_UP_V 0x1
+#define LEDC_LSTIMER2_PARA_UP_S 26
+/* LEDC_TICK_SEL_LSTIMER2 : R/W ;bitpos:[25] ;default: 1'b0 ; */
+/*description: This bit is used to choose slow_clk or ref_tick for low speed
+ timer2. 1'b1:slow_clk 0:ref_tick*/
+#define LEDC_TICK_SEL_LSTIMER2 (BIT(25))
+#define LEDC_TICK_SEL_LSTIMER2_M (BIT(25))
+#define LEDC_TICK_SEL_LSTIMER2_V 0x1
+#define LEDC_TICK_SEL_LSTIMER2_S 25
+/* LEDC_LSTIMER2_RST : R/W ;bitpos:[24] ;default: 1'b1 ; */
+/*description: This bit is used to reset low speed timer2 the counter will be 0 after reset.*/
+#define LEDC_LSTIMER2_RST (BIT(24))
+#define LEDC_LSTIMER2_RST_M (BIT(24))
+#define LEDC_LSTIMER2_RST_V 0x1
+#define LEDC_LSTIMER2_RST_S 24
+/* LEDC_LSTIMER2_PAUSE : R/W ;bitpos:[23] ;default: 1'b0 ; */
+/*description: This bit is used to pause the counter in low speed timer2.*/
+#define LEDC_LSTIMER2_PAUSE (BIT(23))
+#define LEDC_LSTIMER2_PAUSE_M (BIT(23))
+#define LEDC_LSTIMER2_PAUSE_V 0x1
+#define LEDC_LSTIMER2_PAUSE_S 23
+/* LEDC_DIV_NUM_LSTIMER2 : R/W ;bitpos:[22:5] ;default: 18'h0 ; */
+/*description: This register is used to configure parameter for divider in low
+ speed timer2 the least significant eight bits represent the decimal part.*/
+#define LEDC_DIV_NUM_LSTIMER2 0x0003FFFF
+#define LEDC_DIV_NUM_LSTIMER2_M ((LEDC_DIV_NUM_LSTIMER2_V)<<(LEDC_DIV_NUM_LSTIMER2_S))
+#define LEDC_DIV_NUM_LSTIMER2_V 0x3FFFF
+#define LEDC_DIV_NUM_LSTIMER2_S 5
+/* LEDC_LSTIMER2_LIM : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: This register controls the range of the counter in low speed
+ timer2. the counter range is [0 2**reg_lstimer2_lim] the max bit width for counter is 20.*/
+#define LEDC_LSTIMER2_LIM 0x0000001F
+#define LEDC_LSTIMER2_LIM_M ((LEDC_LSTIMER2_LIM_V)<<(LEDC_LSTIMER2_LIM_S))
+#define LEDC_LSTIMER2_LIM_V 0x1F
+#define LEDC_LSTIMER2_LIM_S 0
+
+#define LEDC_LSTIMER2_VALUE_REG (DR_REG_LEDC_BASE + 0x0174)
+/* LEDC_LSTIMER2_CNT : RO ;bitpos:[19:0] ;default: 20'b0 ; */
+/*description: software can read this register to get the current counter value
+ in low speed timer2.*/
+#define LEDC_LSTIMER2_CNT 0x000FFFFF
+#define LEDC_LSTIMER2_CNT_M ((LEDC_LSTIMER2_CNT_V)<<(LEDC_LSTIMER2_CNT_S))
+#define LEDC_LSTIMER2_CNT_V 0xFFFFF
+#define LEDC_LSTIMER2_CNT_S 0
+
+#define LEDC_LSTIMER3_CONF_REG (DR_REG_LEDC_BASE + 0x0178)
+/* LEDC_LSTIMER3_PARA_UP : R/W ;bitpos:[26] ;default: 1'h0 ; */
+/*description: Set this bit to update reg_div_num_lstime3 and reg_lstimer3_lim.*/
+#define LEDC_LSTIMER3_PARA_UP (BIT(26))
+#define LEDC_LSTIMER3_PARA_UP_M (BIT(26))
+#define LEDC_LSTIMER3_PARA_UP_V 0x1
+#define LEDC_LSTIMER3_PARA_UP_S 26
+/* LEDC_TICK_SEL_LSTIMER3 : R/W ;bitpos:[25] ;default: 1'b0 ; */
+/*description: This bit is used to choose slow_clk or ref_tick for low speed
+ timer3. 1'b1:slow_clk 0:ref_tick*/
+#define LEDC_TICK_SEL_LSTIMER3 (BIT(25))
+#define LEDC_TICK_SEL_LSTIMER3_M (BIT(25))
+#define LEDC_TICK_SEL_LSTIMER3_V 0x1
+#define LEDC_TICK_SEL_LSTIMER3_S 25
+/* LEDC_LSTIMER3_RST : R/W ;bitpos:[24] ;default: 1'b1 ; */
+/*description: This bit is used to reset low speed timer3 the counter will be 0 after reset.*/
+#define LEDC_LSTIMER3_RST (BIT(24))
+#define LEDC_LSTIMER3_RST_M (BIT(24))
+#define LEDC_LSTIMER3_RST_V 0x1
+#define LEDC_LSTIMER3_RST_S 24
+/* LEDC_LSTIMER3_PAUSE : R/W ;bitpos:[23] ;default: 1'b0 ; */
+/*description: This bit is used to pause the counter in low speed timer3.*/
+#define LEDC_LSTIMER3_PAUSE (BIT(23))
+#define LEDC_LSTIMER3_PAUSE_M (BIT(23))
+#define LEDC_LSTIMER3_PAUSE_V 0x1
+#define LEDC_LSTIMER3_PAUSE_S 23
+/* LEDC_DIV_NUM_LSTIMER3 : R/W ;bitpos:[22:5] ;default: 18'h0 ; */
+/*description: This register is used to configure parameter for divider in low
+ speed timer3 the least significant eight bits represent the decimal part.*/
+#define LEDC_DIV_NUM_LSTIMER3 0x0003FFFF
+#define LEDC_DIV_NUM_LSTIMER3_M ((LEDC_DIV_NUM_LSTIMER3_V)<<(LEDC_DIV_NUM_LSTIMER3_S))
+#define LEDC_DIV_NUM_LSTIMER3_V 0x3FFFF
+#define LEDC_DIV_NUM_LSTIMER3_S 5
+/* LEDC_LSTIMER3_LIM : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: This register controls the range of the counter in low speed
+ timer3. the counter range is [0 2**reg_lstimer3_lim] the max bit width for counter is 20.*/
+#define LEDC_LSTIMER3_LIM 0x0000001F
+#define LEDC_LSTIMER3_LIM_M ((LEDC_LSTIMER3_LIM_V)<<(LEDC_LSTIMER3_LIM_S))
+#define LEDC_LSTIMER3_LIM_V 0x1F
+#define LEDC_LSTIMER3_LIM_S 0
+
+#define LEDC_LSTIMER3_VALUE_REG (DR_REG_LEDC_BASE + 0x017C)
+/* LEDC_LSTIMER3_CNT : RO ;bitpos:[19:0] ;default: 20'b0 ; */
+/*description: software can read this register to get the current counter value
+ in low speed timer3.*/
+#define LEDC_LSTIMER3_CNT 0x000FFFFF
+#define LEDC_LSTIMER3_CNT_M ((LEDC_LSTIMER3_CNT_V)<<(LEDC_LSTIMER3_CNT_S))
+#define LEDC_LSTIMER3_CNT_V 0xFFFFF
+#define LEDC_LSTIMER3_CNT_S 0
+
+#define LEDC_INT_RAW_REG (DR_REG_LEDC_BASE + 0x0180)
+/* LEDC_DUTY_CHNG_END_LSCH7_INT_RAW : RO ;bitpos:[23] ;default: 1'b0 ; */
+/*description: The interrupt raw bit for low speed channel 7 duty change done.*/
+#define LEDC_DUTY_CHNG_END_LSCH7_INT_RAW (BIT(23))
+#define LEDC_DUTY_CHNG_END_LSCH7_INT_RAW_M (BIT(23))
+#define LEDC_DUTY_CHNG_END_LSCH7_INT_RAW_V 0x1
+#define LEDC_DUTY_CHNG_END_LSCH7_INT_RAW_S 23
+/* LEDC_DUTY_CHNG_END_LSCH6_INT_RAW : RO ;bitpos:[22] ;default: 1'b0 ; */
+/*description: The interrupt raw bit for low speed channel 6 duty change done.*/
+#define LEDC_DUTY_CHNG_END_LSCH6_INT_RAW (BIT(22))
+#define LEDC_DUTY_CHNG_END_LSCH6_INT_RAW_M (BIT(22))
+#define LEDC_DUTY_CHNG_END_LSCH6_INT_RAW_V 0x1
+#define LEDC_DUTY_CHNG_END_LSCH6_INT_RAW_S 22
+/* LEDC_DUTY_CHNG_END_LSCH5_INT_RAW : RO ;bitpos:[21] ;default: 1'b0 ; */
+/*description: The interrupt raw bit for low speed channel 5 duty change done.*/
+#define LEDC_DUTY_CHNG_END_LSCH5_INT_RAW (BIT(21))
+#define LEDC_DUTY_CHNG_END_LSCH5_INT_RAW_M (BIT(21))
+#define LEDC_DUTY_CHNG_END_LSCH5_INT_RAW_V 0x1
+#define LEDC_DUTY_CHNG_END_LSCH5_INT_RAW_S 21
+/* LEDC_DUTY_CHNG_END_LSCH4_INT_RAW : RO ;bitpos:[20] ;default: 1'b0 ; */
+/*description: The interrupt raw bit for low speed channel 4 duty change done.*/
+#define LEDC_DUTY_CHNG_END_LSCH4_INT_RAW (BIT(20))
+#define LEDC_DUTY_CHNG_END_LSCH4_INT_RAW_M (BIT(20))
+#define LEDC_DUTY_CHNG_END_LSCH4_INT_RAW_V 0x1
+#define LEDC_DUTY_CHNG_END_LSCH4_INT_RAW_S 20
+/* LEDC_DUTY_CHNG_END_LSCH3_INT_RAW : RO ;bitpos:[19] ;default: 1'b0 ; */
+/*description: The interrupt raw bit for low speed channel 3 duty change done.*/
+#define LEDC_DUTY_CHNG_END_LSCH3_INT_RAW (BIT(19))
+#define LEDC_DUTY_CHNG_END_LSCH3_INT_RAW_M (BIT(19))
+#define LEDC_DUTY_CHNG_END_LSCH3_INT_RAW_V 0x1
+#define LEDC_DUTY_CHNG_END_LSCH3_INT_RAW_S 19
+/* LEDC_DUTY_CHNG_END_LSCH2_INT_RAW : RO ;bitpos:[18] ;default: 1'b0 ; */
+/*description: The interrupt raw bit for low speed channel 2 duty change done.*/
+#define LEDC_DUTY_CHNG_END_LSCH2_INT_RAW (BIT(18))
+#define LEDC_DUTY_CHNG_END_LSCH2_INT_RAW_M (BIT(18))
+#define LEDC_DUTY_CHNG_END_LSCH2_INT_RAW_V 0x1
+#define LEDC_DUTY_CHNG_END_LSCH2_INT_RAW_S 18
+/* LEDC_DUTY_CHNG_END_LSCH1_INT_RAW : RO ;bitpos:[17] ;default: 1'b0 ; */
+/*description: The interrupt raw bit for low speed channel 1 duty change done.*/
+#define LEDC_DUTY_CHNG_END_LSCH1_INT_RAW (BIT(17))
+#define LEDC_DUTY_CHNG_END_LSCH1_INT_RAW_M (BIT(17))
+#define LEDC_DUTY_CHNG_END_LSCH1_INT_RAW_V 0x1
+#define LEDC_DUTY_CHNG_END_LSCH1_INT_RAW_S 17
+/* LEDC_DUTY_CHNG_END_LSCH0_INT_RAW : RO ;bitpos:[16] ;default: 1'b0 ; */
+/*description: The interrupt raw bit for low speed channel 0 duty change done.*/
+#define LEDC_DUTY_CHNG_END_LSCH0_INT_RAW (BIT(16))
+#define LEDC_DUTY_CHNG_END_LSCH0_INT_RAW_M (BIT(16))
+#define LEDC_DUTY_CHNG_END_LSCH0_INT_RAW_V 0x1
+#define LEDC_DUTY_CHNG_END_LSCH0_INT_RAW_S 16
+/* LEDC_DUTY_CHNG_END_HSCH7_INT_RAW : RO ;bitpos:[15] ;default: 1'b0 ; */
+/*description: The interrupt raw bit for high speed channel 7 duty change done.*/
+#define LEDC_DUTY_CHNG_END_HSCH7_INT_RAW (BIT(15))
+#define LEDC_DUTY_CHNG_END_HSCH7_INT_RAW_M (BIT(15))
+#define LEDC_DUTY_CHNG_END_HSCH7_INT_RAW_V 0x1
+#define LEDC_DUTY_CHNG_END_HSCH7_INT_RAW_S 15
+/* LEDC_DUTY_CHNG_END_HSCH6_INT_RAW : RO ;bitpos:[14] ;default: 1'b0 ; */
+/*description: The interrupt raw bit for high speed channel 6 duty change done.*/
+#define LEDC_DUTY_CHNG_END_HSCH6_INT_RAW (BIT(14))
+#define LEDC_DUTY_CHNG_END_HSCH6_INT_RAW_M (BIT(14))
+#define LEDC_DUTY_CHNG_END_HSCH6_INT_RAW_V 0x1
+#define LEDC_DUTY_CHNG_END_HSCH6_INT_RAW_S 14
+/* LEDC_DUTY_CHNG_END_HSCH5_INT_RAW : RO ;bitpos:[13] ;default: 1'b0 ; */
+/*description: The interrupt raw bit for high speed channel 5 duty change done.*/
+#define LEDC_DUTY_CHNG_END_HSCH5_INT_RAW (BIT(13))
+#define LEDC_DUTY_CHNG_END_HSCH5_INT_RAW_M (BIT(13))
+#define LEDC_DUTY_CHNG_END_HSCH5_INT_RAW_V 0x1
+#define LEDC_DUTY_CHNG_END_HSCH5_INT_RAW_S 13
+/* LEDC_DUTY_CHNG_END_HSCH4_INT_RAW : RO ;bitpos:[12] ;default: 1'b0 ; */
+/*description: The interrupt raw bit for high speed channel 4 duty change done.*/
+#define LEDC_DUTY_CHNG_END_HSCH4_INT_RAW (BIT(12))
+#define LEDC_DUTY_CHNG_END_HSCH4_INT_RAW_M (BIT(12))
+#define LEDC_DUTY_CHNG_END_HSCH4_INT_RAW_V 0x1
+#define LEDC_DUTY_CHNG_END_HSCH4_INT_RAW_S 12
+/* LEDC_DUTY_CHNG_END_HSCH3_INT_RAW : RO ;bitpos:[11] ;default: 1'b0 ; */
+/*description: The interrupt raw bit for high speed channel 3 duty change done.*/
+#define LEDC_DUTY_CHNG_END_HSCH3_INT_RAW (BIT(11))
+#define LEDC_DUTY_CHNG_END_HSCH3_INT_RAW_M (BIT(11))
+#define LEDC_DUTY_CHNG_END_HSCH3_INT_RAW_V 0x1
+#define LEDC_DUTY_CHNG_END_HSCH3_INT_RAW_S 11
+/* LEDC_DUTY_CHNG_END_HSCH2_INT_RAW : RO ;bitpos:[10] ;default: 1'b0 ; */
+/*description: The interrupt raw bit for high speed channel 2 duty change done.*/
+#define LEDC_DUTY_CHNG_END_HSCH2_INT_RAW (BIT(10))
+#define LEDC_DUTY_CHNG_END_HSCH2_INT_RAW_M (BIT(10))
+#define LEDC_DUTY_CHNG_END_HSCH2_INT_RAW_V 0x1
+#define LEDC_DUTY_CHNG_END_HSCH2_INT_RAW_S 10
+/* LEDC_DUTY_CHNG_END_HSCH1_INT_RAW : RO ;bitpos:[9] ;default: 1'b0 ; */
+/*description: The interrupt raw bit for high speed channel 1 duty change done.*/
+#define LEDC_DUTY_CHNG_END_HSCH1_INT_RAW (BIT(9))
+#define LEDC_DUTY_CHNG_END_HSCH1_INT_RAW_M (BIT(9))
+#define LEDC_DUTY_CHNG_END_HSCH1_INT_RAW_V 0x1
+#define LEDC_DUTY_CHNG_END_HSCH1_INT_RAW_S 9
+/* LEDC_DUTY_CHNG_END_HSCH0_INT_RAW : RO ;bitpos:[8] ;default: 1'b0 ; */
+/*description: The interrupt raw bit for high speed channel 0 duty change done.*/
+#define LEDC_DUTY_CHNG_END_HSCH0_INT_RAW (BIT(8))
+#define LEDC_DUTY_CHNG_END_HSCH0_INT_RAW_M (BIT(8))
+#define LEDC_DUTY_CHNG_END_HSCH0_INT_RAW_V 0x1
+#define LEDC_DUTY_CHNG_END_HSCH0_INT_RAW_S 8
+/* LEDC_LSTIMER3_OVF_INT_RAW : RO ;bitpos:[7] ;default: 1'b0 ; */
+/*description: The interrupt raw bit for low speed channel3 counter overflow.*/
+#define LEDC_LSTIMER3_OVF_INT_RAW (BIT(7))
+#define LEDC_LSTIMER3_OVF_INT_RAW_M (BIT(7))
+#define LEDC_LSTIMER3_OVF_INT_RAW_V 0x1
+#define LEDC_LSTIMER3_OVF_INT_RAW_S 7
+/* LEDC_LSTIMER2_OVF_INT_RAW : RO ;bitpos:[6] ;default: 1'b0 ; */
+/*description: The interrupt raw bit for low speed channel2 counter overflow.*/
+#define LEDC_LSTIMER2_OVF_INT_RAW (BIT(6))
+#define LEDC_LSTIMER2_OVF_INT_RAW_M (BIT(6))
+#define LEDC_LSTIMER2_OVF_INT_RAW_V 0x1
+#define LEDC_LSTIMER2_OVF_INT_RAW_S 6
+/* LEDC_LSTIMER1_OVF_INT_RAW : RO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: The interrupt raw bit for low speed channel1 counter overflow.*/
+#define LEDC_LSTIMER1_OVF_INT_RAW (BIT(5))
+#define LEDC_LSTIMER1_OVF_INT_RAW_M (BIT(5))
+#define LEDC_LSTIMER1_OVF_INT_RAW_V 0x1
+#define LEDC_LSTIMER1_OVF_INT_RAW_S 5
+/* LEDC_LSTIMER0_OVF_INT_RAW : RO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: The interrupt raw bit for low speed channel0 counter overflow.*/
+#define LEDC_LSTIMER0_OVF_INT_RAW (BIT(4))
+#define LEDC_LSTIMER0_OVF_INT_RAW_M (BIT(4))
+#define LEDC_LSTIMER0_OVF_INT_RAW_V 0x1
+#define LEDC_LSTIMER0_OVF_INT_RAW_S 4
+/* LEDC_HSTIMER3_OVF_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: The interrupt raw bit for high speed channel3 counter overflow.*/
+#define LEDC_HSTIMER3_OVF_INT_RAW (BIT(3))
+#define LEDC_HSTIMER3_OVF_INT_RAW_M (BIT(3))
+#define LEDC_HSTIMER3_OVF_INT_RAW_V 0x1
+#define LEDC_HSTIMER3_OVF_INT_RAW_S 3
+/* LEDC_HSTIMER2_OVF_INT_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */
+/*description: The interrupt raw bit for high speed channel2 counter overflow.*/
+#define LEDC_HSTIMER2_OVF_INT_RAW (BIT(2))
+#define LEDC_HSTIMER2_OVF_INT_RAW_M (BIT(2))
+#define LEDC_HSTIMER2_OVF_INT_RAW_V 0x1
+#define LEDC_HSTIMER2_OVF_INT_RAW_S 2
+/* LEDC_HSTIMER1_OVF_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: The interrupt raw bit for high speed channel1 counter overflow.*/
+#define LEDC_HSTIMER1_OVF_INT_RAW (BIT(1))
+#define LEDC_HSTIMER1_OVF_INT_RAW_M (BIT(1))
+#define LEDC_HSTIMER1_OVF_INT_RAW_V 0x1
+#define LEDC_HSTIMER1_OVF_INT_RAW_S 1
+/* LEDC_HSTIMER0_OVF_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: The interrupt raw bit for high speed channel0 counter overflow.*/
+#define LEDC_HSTIMER0_OVF_INT_RAW (BIT(0))
+#define LEDC_HSTIMER0_OVF_INT_RAW_M (BIT(0))
+#define LEDC_HSTIMER0_OVF_INT_RAW_V 0x1
+#define LEDC_HSTIMER0_OVF_INT_RAW_S 0
+
+#define LEDC_INT_ST_REG (DR_REG_LEDC_BASE + 0x0184)
+/* LEDC_DUTY_CHNG_END_LSCH7_INT_ST : RO ;bitpos:[23] ;default: 1'h0 ; */
+/*description: The interrupt status bit for low speed channel 7 duty change done event*/
+#define LEDC_DUTY_CHNG_END_LSCH7_INT_ST (BIT(23))
+#define LEDC_DUTY_CHNG_END_LSCH7_INT_ST_M (BIT(23))
+#define LEDC_DUTY_CHNG_END_LSCH7_INT_ST_V 0x1
+#define LEDC_DUTY_CHNG_END_LSCH7_INT_ST_S 23
+/* LEDC_DUTY_CHNG_END_LSCH6_INT_ST : RO ;bitpos:[22] ;default: 1'b0 ; */
+/*description: The interrupt status bit for low speed channel 6 duty change done event.*/
+#define LEDC_DUTY_CHNG_END_LSCH6_INT_ST (BIT(22))
+#define LEDC_DUTY_CHNG_END_LSCH6_INT_ST_M (BIT(22))
+#define LEDC_DUTY_CHNG_END_LSCH6_INT_ST_V 0x1
+#define LEDC_DUTY_CHNG_END_LSCH6_INT_ST_S 22
+/* LEDC_DUTY_CHNG_END_LSCH5_INT_ST : RO ;bitpos:[21] ;default: 1'b0 ; */
+/*description: The interrupt status bit for low speed channel 5 duty change done event.*/
+#define LEDC_DUTY_CHNG_END_LSCH5_INT_ST (BIT(21))
+#define LEDC_DUTY_CHNG_END_LSCH5_INT_ST_M (BIT(21))
+#define LEDC_DUTY_CHNG_END_LSCH5_INT_ST_V 0x1
+#define LEDC_DUTY_CHNG_END_LSCH5_INT_ST_S 21
+/* LEDC_DUTY_CHNG_END_LSCH4_INT_ST : RO ;bitpos:[20] ;default: 1'b0 ; */
+/*description: The interrupt status bit for low speed channel 4 duty change done event.*/
+#define LEDC_DUTY_CHNG_END_LSCH4_INT_ST (BIT(20))
+#define LEDC_DUTY_CHNG_END_LSCH4_INT_ST_M (BIT(20))
+#define LEDC_DUTY_CHNG_END_LSCH4_INT_ST_V 0x1
+#define LEDC_DUTY_CHNG_END_LSCH4_INT_ST_S 20
+/* LEDC_DUTY_CHNG_END_LSCH3_INT_ST : RO ;bitpos:[19] ;default: 1'b0 ; */
+/*description: The interrupt status bit for low speed channel 3 duty change done event.*/
+#define LEDC_DUTY_CHNG_END_LSCH3_INT_ST (BIT(19))
+#define LEDC_DUTY_CHNG_END_LSCH3_INT_ST_M (BIT(19))
+#define LEDC_DUTY_CHNG_END_LSCH3_INT_ST_V 0x1
+#define LEDC_DUTY_CHNG_END_LSCH3_INT_ST_S 19
+/* LEDC_DUTY_CHNG_END_LSCH2_INT_ST : RO ;bitpos:[18] ;default: 1'b0 ; */
+/*description: The interrupt status bit for low speed channel 2 duty change done event.*/
+#define LEDC_DUTY_CHNG_END_LSCH2_INT_ST (BIT(18))
+#define LEDC_DUTY_CHNG_END_LSCH2_INT_ST_M (BIT(18))
+#define LEDC_DUTY_CHNG_END_LSCH2_INT_ST_V 0x1
+#define LEDC_DUTY_CHNG_END_LSCH2_INT_ST_S 18
+/* LEDC_DUTY_CHNG_END_LSCH1_INT_ST : RO ;bitpos:[17] ;default: 1'b0 ; */
+/*description: The interrupt status bit for low speed channel 1 duty change done event.*/
+#define LEDC_DUTY_CHNG_END_LSCH1_INT_ST (BIT(17))
+#define LEDC_DUTY_CHNG_END_LSCH1_INT_ST_M (BIT(17))
+#define LEDC_DUTY_CHNG_END_LSCH1_INT_ST_V 0x1
+#define LEDC_DUTY_CHNG_END_LSCH1_INT_ST_S 17
+/* LEDC_DUTY_CHNG_END_LSCH0_INT_ST : RO ;bitpos:[16] ;default: 1'b0 ; */
+/*description: The interrupt status bit for low speed channel 0 duty change done event.*/
+#define LEDC_DUTY_CHNG_END_LSCH0_INT_ST (BIT(16))
+#define LEDC_DUTY_CHNG_END_LSCH0_INT_ST_M (BIT(16))
+#define LEDC_DUTY_CHNG_END_LSCH0_INT_ST_V 0x1
+#define LEDC_DUTY_CHNG_END_LSCH0_INT_ST_S 16
+/* LEDC_DUTY_CHNG_END_HSCH7_INT_ST : RO ;bitpos:[15] ;default: 1'b0 ; */
+/*description: The interrupt status bit for high speed channel 7 duty change done event.*/
+#define LEDC_DUTY_CHNG_END_HSCH7_INT_ST (BIT(15))
+#define LEDC_DUTY_CHNG_END_HSCH7_INT_ST_M (BIT(15))
+#define LEDC_DUTY_CHNG_END_HSCH7_INT_ST_V 0x1
+#define LEDC_DUTY_CHNG_END_HSCH7_INT_ST_S 15
+/* LEDC_DUTY_CHNG_END_HSCH6_INT_ST : RO ;bitpos:[14] ;default: 1'b0 ; */
+/*description: The interrupt status bit for high speed channel 6 duty change done event.*/
+#define LEDC_DUTY_CHNG_END_HSCH6_INT_ST (BIT(14))
+#define LEDC_DUTY_CHNG_END_HSCH6_INT_ST_M (BIT(14))
+#define LEDC_DUTY_CHNG_END_HSCH6_INT_ST_V 0x1
+#define LEDC_DUTY_CHNG_END_HSCH6_INT_ST_S 14
+/* LEDC_DUTY_CHNG_END_HSCH5_INT_ST : RO ;bitpos:[13] ;default: 1'b0 ; */
+/*description: The interrupt status bit for high speed channel 5 duty change done event.*/
+#define LEDC_DUTY_CHNG_END_HSCH5_INT_ST (BIT(13))
+#define LEDC_DUTY_CHNG_END_HSCH5_INT_ST_M (BIT(13))
+#define LEDC_DUTY_CHNG_END_HSCH5_INT_ST_V 0x1
+#define LEDC_DUTY_CHNG_END_HSCH5_INT_ST_S 13
+/* LEDC_DUTY_CHNG_END_HSCH4_INT_ST : RO ;bitpos:[12] ;default: 1'b0 ; */
+/*description: The interrupt status bit for high speed channel 4 duty change done event.*/
+#define LEDC_DUTY_CHNG_END_HSCH4_INT_ST (BIT(12))
+#define LEDC_DUTY_CHNG_END_HSCH4_INT_ST_M (BIT(12))
+#define LEDC_DUTY_CHNG_END_HSCH4_INT_ST_V 0x1
+#define LEDC_DUTY_CHNG_END_HSCH4_INT_ST_S 12
+/* LEDC_DUTY_CHNG_END_HSCH3_INT_ST : RO ;bitpos:[11] ;default: 1'b0 ; */
+/*description: The interrupt status bit for high speed channel 3 duty change done event.*/
+#define LEDC_DUTY_CHNG_END_HSCH3_INT_ST (BIT(11))
+#define LEDC_DUTY_CHNG_END_HSCH3_INT_ST_M (BIT(11))
+#define LEDC_DUTY_CHNG_END_HSCH3_INT_ST_V 0x1
+#define LEDC_DUTY_CHNG_END_HSCH3_INT_ST_S 11
+/* LEDC_DUTY_CHNG_END_HSCH2_INT_ST : RO ;bitpos:[10] ;default: 1'b0 ; */
+/*description: The interrupt status bit for high speed channel 2 duty change done event.*/
+#define LEDC_DUTY_CHNG_END_HSCH2_INT_ST (BIT(10))
+#define LEDC_DUTY_CHNG_END_HSCH2_INT_ST_M (BIT(10))
+#define LEDC_DUTY_CHNG_END_HSCH2_INT_ST_V 0x1
+#define LEDC_DUTY_CHNG_END_HSCH2_INT_ST_S 10
+/* LEDC_DUTY_CHNG_END_HSCH1_INT_ST : RO ;bitpos:[9] ;default: 1'b0 ; */
+/*description: The interrupt status bit for high speed channel 1 duty change done event.*/
+#define LEDC_DUTY_CHNG_END_HSCH1_INT_ST (BIT(9))
+#define LEDC_DUTY_CHNG_END_HSCH1_INT_ST_M (BIT(9))
+#define LEDC_DUTY_CHNG_END_HSCH1_INT_ST_V 0x1
+#define LEDC_DUTY_CHNG_END_HSCH1_INT_ST_S 9
+/* LEDC_DUTY_CHNG_END_HSCH0_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */
+/*description: The interrupt status bit for high speed channel 0 duty change done event.*/
+#define LEDC_DUTY_CHNG_END_HSCH0_INT_ST (BIT(8))
+#define LEDC_DUTY_CHNG_END_HSCH0_INT_ST_M (BIT(8))
+#define LEDC_DUTY_CHNG_END_HSCH0_INT_ST_V 0x1
+#define LEDC_DUTY_CHNG_END_HSCH0_INT_ST_S 8
+/* LEDC_LSTIMER3_OVF_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */
+/*description: The interrupt status bit for low speed channel3 counter overflow event.*/
+#define LEDC_LSTIMER3_OVF_INT_ST (BIT(7))
+#define LEDC_LSTIMER3_OVF_INT_ST_M (BIT(7))
+#define LEDC_LSTIMER3_OVF_INT_ST_V 0x1
+#define LEDC_LSTIMER3_OVF_INT_ST_S 7
+/* LEDC_LSTIMER2_OVF_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */
+/*description: The interrupt status bit for low speed channel2 counter overflow event.*/
+#define LEDC_LSTIMER2_OVF_INT_ST (BIT(6))
+#define LEDC_LSTIMER2_OVF_INT_ST_M (BIT(6))
+#define LEDC_LSTIMER2_OVF_INT_ST_V 0x1
+#define LEDC_LSTIMER2_OVF_INT_ST_S 6
+/* LEDC_LSTIMER1_OVF_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: The interrupt status bit for low speed channel1 counter overflow event.*/
+#define LEDC_LSTIMER1_OVF_INT_ST (BIT(5))
+#define LEDC_LSTIMER1_OVF_INT_ST_M (BIT(5))
+#define LEDC_LSTIMER1_OVF_INT_ST_V 0x1
+#define LEDC_LSTIMER1_OVF_INT_ST_S 5
+/* LEDC_LSTIMER0_OVF_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: The interrupt status bit for low speed channel0 counter overflow event.*/
+#define LEDC_LSTIMER0_OVF_INT_ST (BIT(4))
+#define LEDC_LSTIMER0_OVF_INT_ST_M (BIT(4))
+#define LEDC_LSTIMER0_OVF_INT_ST_V 0x1
+#define LEDC_LSTIMER0_OVF_INT_ST_S 4
+/* LEDC_HSTIMER3_OVF_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: The interrupt status bit for high speed channel3 counter overflow event.*/
+#define LEDC_HSTIMER3_OVF_INT_ST (BIT(3))
+#define LEDC_HSTIMER3_OVF_INT_ST_M (BIT(3))
+#define LEDC_HSTIMER3_OVF_INT_ST_V 0x1
+#define LEDC_HSTIMER3_OVF_INT_ST_S 3
+/* LEDC_HSTIMER2_OVF_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */
+/*description: The interrupt status bit for high speed channel2 counter overflow event.*/
+#define LEDC_HSTIMER2_OVF_INT_ST (BIT(2))
+#define LEDC_HSTIMER2_OVF_INT_ST_M (BIT(2))
+#define LEDC_HSTIMER2_OVF_INT_ST_V 0x1
+#define LEDC_HSTIMER2_OVF_INT_ST_S 2
+/* LEDC_HSTIMER1_OVF_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: The interrupt status bit for high speed channel1 counter overflow event.*/
+#define LEDC_HSTIMER1_OVF_INT_ST (BIT(1))
+#define LEDC_HSTIMER1_OVF_INT_ST_M (BIT(1))
+#define LEDC_HSTIMER1_OVF_INT_ST_V 0x1
+#define LEDC_HSTIMER1_OVF_INT_ST_S 1
+/* LEDC_HSTIMER0_OVF_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: The interrupt status bit for high speed channel0 counter overflow event.*/
+#define LEDC_HSTIMER0_OVF_INT_ST (BIT(0))
+#define LEDC_HSTIMER0_OVF_INT_ST_M (BIT(0))
+#define LEDC_HSTIMER0_OVF_INT_ST_V 0x1
+#define LEDC_HSTIMER0_OVF_INT_ST_S 0
+
+#define LEDC_INT_ENA_REG (DR_REG_LEDC_BASE + 0x0188)
+/* LEDC_DUTY_CHNG_END_LSCH7_INT_ENA : R/W ;bitpos:[23] ;default: 1'h0 ; */
+/*description: The interrupt enable bit for low speed channel 7 duty change done interrupt.*/
+#define LEDC_DUTY_CHNG_END_LSCH7_INT_ENA (BIT(23))
+#define LEDC_DUTY_CHNG_END_LSCH7_INT_ENA_M (BIT(23))
+#define LEDC_DUTY_CHNG_END_LSCH7_INT_ENA_V 0x1
+#define LEDC_DUTY_CHNG_END_LSCH7_INT_ENA_S 23
+/* LEDC_DUTY_CHNG_END_LSCH6_INT_ENA : R/W ;bitpos:[22] ;default: 1'b0 ; */
+/*description: The interrupt enable bit for low speed channel 6 duty change done interrupt.*/
+#define LEDC_DUTY_CHNG_END_LSCH6_INT_ENA (BIT(22))
+#define LEDC_DUTY_CHNG_END_LSCH6_INT_ENA_M (BIT(22))
+#define LEDC_DUTY_CHNG_END_LSCH6_INT_ENA_V 0x1
+#define LEDC_DUTY_CHNG_END_LSCH6_INT_ENA_S 22
+/* LEDC_DUTY_CHNG_END_LSCH5_INT_ENA : R/W ;bitpos:[21] ;default: 1'b0 ; */
+/*description: The interrupt enable bit for low speed channel 5 duty change done interrupt.*/
+#define LEDC_DUTY_CHNG_END_LSCH5_INT_ENA (BIT(21))
+#define LEDC_DUTY_CHNG_END_LSCH5_INT_ENA_M (BIT(21))
+#define LEDC_DUTY_CHNG_END_LSCH5_INT_ENA_V 0x1
+#define LEDC_DUTY_CHNG_END_LSCH5_INT_ENA_S 21
+/* LEDC_DUTY_CHNG_END_LSCH4_INT_ENA : R/W ;bitpos:[20] ;default: 1'b0 ; */
+/*description: The interrupt enable bit for low speed channel 4 duty change done interrupt.*/
+#define LEDC_DUTY_CHNG_END_LSCH4_INT_ENA (BIT(20))
+#define LEDC_DUTY_CHNG_END_LSCH4_INT_ENA_M (BIT(20))
+#define LEDC_DUTY_CHNG_END_LSCH4_INT_ENA_V 0x1
+#define LEDC_DUTY_CHNG_END_LSCH4_INT_ENA_S 20
+/* LEDC_DUTY_CHNG_END_LSCH3_INT_ENA : R/W ;bitpos:[19] ;default: 1'b0 ; */
+/*description: The interrupt enable bit for low speed channel 3 duty change done interrupt.*/
+#define LEDC_DUTY_CHNG_END_LSCH3_INT_ENA (BIT(19))
+#define LEDC_DUTY_CHNG_END_LSCH3_INT_ENA_M (BIT(19))
+#define LEDC_DUTY_CHNG_END_LSCH3_INT_ENA_V 0x1
+#define LEDC_DUTY_CHNG_END_LSCH3_INT_ENA_S 19
+/* LEDC_DUTY_CHNG_END_LSCH2_INT_ENA : R/W ;bitpos:[18] ;default: 1'b0 ; */
+/*description: The interrupt enable bit for low speed channel 2 duty change done interrupt.*/
+#define LEDC_DUTY_CHNG_END_LSCH2_INT_ENA (BIT(18))
+#define LEDC_DUTY_CHNG_END_LSCH2_INT_ENA_M (BIT(18))
+#define LEDC_DUTY_CHNG_END_LSCH2_INT_ENA_V 0x1
+#define LEDC_DUTY_CHNG_END_LSCH2_INT_ENA_S 18
+/* LEDC_DUTY_CHNG_END_LSCH1_INT_ENA : R/W ;bitpos:[17] ;default: 1'b0 ; */
+/*description: The interrupt enable bit for low speed channel 1 duty change done interrupt.*/
+#define LEDC_DUTY_CHNG_END_LSCH1_INT_ENA (BIT(17))
+#define LEDC_DUTY_CHNG_END_LSCH1_INT_ENA_M (BIT(17))
+#define LEDC_DUTY_CHNG_END_LSCH1_INT_ENA_V 0x1
+#define LEDC_DUTY_CHNG_END_LSCH1_INT_ENA_S 17
+/* LEDC_DUTY_CHNG_END_LSCH0_INT_ENA : R/W ;bitpos:[16] ;default: 1'b0 ; */
+/*description: The interrupt enable bit for low speed channel 0 duty change done interrupt.*/
+#define LEDC_DUTY_CHNG_END_LSCH0_INT_ENA (BIT(16))
+#define LEDC_DUTY_CHNG_END_LSCH0_INT_ENA_M (BIT(16))
+#define LEDC_DUTY_CHNG_END_LSCH0_INT_ENA_V 0x1
+#define LEDC_DUTY_CHNG_END_LSCH0_INT_ENA_S 16
+/* LEDC_DUTY_CHNG_END_HSCH7_INT_ENA : R/W ;bitpos:[15] ;default: 1'b0 ; */
+/*description: The interrupt enable bit for high speed channel 7 duty change done interrupt.*/
+#define LEDC_DUTY_CHNG_END_HSCH7_INT_ENA (BIT(15))
+#define LEDC_DUTY_CHNG_END_HSCH7_INT_ENA_M (BIT(15))
+#define LEDC_DUTY_CHNG_END_HSCH7_INT_ENA_V 0x1
+#define LEDC_DUTY_CHNG_END_HSCH7_INT_ENA_S 15
+/* LEDC_DUTY_CHNG_END_HSCH6_INT_ENA : R/W ;bitpos:[14] ;default: 1'b0 ; */
+/*description: The interrupt enable bit for high speed channel 6 duty change done interrupt.*/
+#define LEDC_DUTY_CHNG_END_HSCH6_INT_ENA (BIT(14))
+#define LEDC_DUTY_CHNG_END_HSCH6_INT_ENA_M (BIT(14))
+#define LEDC_DUTY_CHNG_END_HSCH6_INT_ENA_V 0x1
+#define LEDC_DUTY_CHNG_END_HSCH6_INT_ENA_S 14
+/* LEDC_DUTY_CHNG_END_HSCH5_INT_ENA : R/W ;bitpos:[13] ;default: 1'b0 ; */
+/*description: The interrupt enable bit for high speed channel 5 duty change done interrupt.*/
+#define LEDC_DUTY_CHNG_END_HSCH5_INT_ENA (BIT(13))
+#define LEDC_DUTY_CHNG_END_HSCH5_INT_ENA_M (BIT(13))
+#define LEDC_DUTY_CHNG_END_HSCH5_INT_ENA_V 0x1
+#define LEDC_DUTY_CHNG_END_HSCH5_INT_ENA_S 13
+/* LEDC_DUTY_CHNG_END_HSCH4_INT_ENA : R/W ;bitpos:[12] ;default: 1'b0 ; */
+/*description: The interrupt enable bit for high speed channel 4 duty change done interrupt.*/
+#define LEDC_DUTY_CHNG_END_HSCH4_INT_ENA (BIT(12))
+#define LEDC_DUTY_CHNG_END_HSCH4_INT_ENA_M (BIT(12))
+#define LEDC_DUTY_CHNG_END_HSCH4_INT_ENA_V 0x1
+#define LEDC_DUTY_CHNG_END_HSCH4_INT_ENA_S 12
+/* LEDC_DUTY_CHNG_END_HSCH3_INT_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */
+/*description: The interrupt enable bit for high speed channel 3 duty change done interrupt.*/
+#define LEDC_DUTY_CHNG_END_HSCH3_INT_ENA (BIT(11))
+#define LEDC_DUTY_CHNG_END_HSCH3_INT_ENA_M (BIT(11))
+#define LEDC_DUTY_CHNG_END_HSCH3_INT_ENA_V 0x1
+#define LEDC_DUTY_CHNG_END_HSCH3_INT_ENA_S 11
+/* LEDC_DUTY_CHNG_END_HSCH2_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */
+/*description: The interrupt enable bit for high speed channel 2 duty change done interrupt.*/
+#define LEDC_DUTY_CHNG_END_HSCH2_INT_ENA (BIT(10))
+#define LEDC_DUTY_CHNG_END_HSCH2_INT_ENA_M (BIT(10))
+#define LEDC_DUTY_CHNG_END_HSCH2_INT_ENA_V 0x1
+#define LEDC_DUTY_CHNG_END_HSCH2_INT_ENA_S 10
+/* LEDC_DUTY_CHNG_END_HSCH1_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */
+/*description: The interrupt enable bit for high speed channel 1 duty change done interrupt.*/
+#define LEDC_DUTY_CHNG_END_HSCH1_INT_ENA (BIT(9))
+#define LEDC_DUTY_CHNG_END_HSCH1_INT_ENA_M (BIT(9))
+#define LEDC_DUTY_CHNG_END_HSCH1_INT_ENA_V 0x1
+#define LEDC_DUTY_CHNG_END_HSCH1_INT_ENA_S 9
+/* LEDC_DUTY_CHNG_END_HSCH0_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */
+/*description: The interrupt enable bit for high speed channel 0 duty change done interrupt.*/
+#define LEDC_DUTY_CHNG_END_HSCH0_INT_ENA (BIT(8))
+#define LEDC_DUTY_CHNG_END_HSCH0_INT_ENA_M (BIT(8))
+#define LEDC_DUTY_CHNG_END_HSCH0_INT_ENA_V 0x1
+#define LEDC_DUTY_CHNG_END_HSCH0_INT_ENA_S 8
+/* LEDC_LSTIMER3_OVF_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: The interrupt enable bit for low speed channel3 counter overflow interrupt.*/
+#define LEDC_LSTIMER3_OVF_INT_ENA (BIT(7))
+#define LEDC_LSTIMER3_OVF_INT_ENA_M (BIT(7))
+#define LEDC_LSTIMER3_OVF_INT_ENA_V 0x1
+#define LEDC_LSTIMER3_OVF_INT_ENA_S 7
+/* LEDC_LSTIMER2_OVF_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: The interrupt enable bit for low speed channel2 counter overflow interrupt.*/
+#define LEDC_LSTIMER2_OVF_INT_ENA (BIT(6))
+#define LEDC_LSTIMER2_OVF_INT_ENA_M (BIT(6))
+#define LEDC_LSTIMER2_OVF_INT_ENA_V 0x1
+#define LEDC_LSTIMER2_OVF_INT_ENA_S 6
+/* LEDC_LSTIMER1_OVF_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: The interrupt enable bit for low speed channel1 counter overflow interrupt.*/
+#define LEDC_LSTIMER1_OVF_INT_ENA (BIT(5))
+#define LEDC_LSTIMER1_OVF_INT_ENA_M (BIT(5))
+#define LEDC_LSTIMER1_OVF_INT_ENA_V 0x1
+#define LEDC_LSTIMER1_OVF_INT_ENA_S 5
+/* LEDC_LSTIMER0_OVF_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: The interrupt enable bit for low speed channel0 counter overflow interrupt.*/
+#define LEDC_LSTIMER0_OVF_INT_ENA (BIT(4))
+#define LEDC_LSTIMER0_OVF_INT_ENA_M (BIT(4))
+#define LEDC_LSTIMER0_OVF_INT_ENA_V 0x1
+#define LEDC_LSTIMER0_OVF_INT_ENA_S 4
+/* LEDC_HSTIMER3_OVF_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: The interrupt enable bit for high speed channel3 counter overflow interrupt.*/
+#define LEDC_HSTIMER3_OVF_INT_ENA (BIT(3))
+#define LEDC_HSTIMER3_OVF_INT_ENA_M (BIT(3))
+#define LEDC_HSTIMER3_OVF_INT_ENA_V 0x1
+#define LEDC_HSTIMER3_OVF_INT_ENA_S 3
+/* LEDC_HSTIMER2_OVF_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: The interrupt enable bit for high speed channel2 counter overflow interrupt.*/
+#define LEDC_HSTIMER2_OVF_INT_ENA (BIT(2))
+#define LEDC_HSTIMER2_OVF_INT_ENA_M (BIT(2))
+#define LEDC_HSTIMER2_OVF_INT_ENA_V 0x1
+#define LEDC_HSTIMER2_OVF_INT_ENA_S 2
+/* LEDC_HSTIMER1_OVF_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: The interrupt enable bit for high speed channel1 counter overflow interrupt.*/
+#define LEDC_HSTIMER1_OVF_INT_ENA (BIT(1))
+#define LEDC_HSTIMER1_OVF_INT_ENA_M (BIT(1))
+#define LEDC_HSTIMER1_OVF_INT_ENA_V 0x1
+#define LEDC_HSTIMER1_OVF_INT_ENA_S 1
+/* LEDC_HSTIMER0_OVF_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: The interrupt enable bit for high speed channel0 counter overflow interrupt.*/
+#define LEDC_HSTIMER0_OVF_INT_ENA (BIT(0))
+#define LEDC_HSTIMER0_OVF_INT_ENA_M (BIT(0))
+#define LEDC_HSTIMER0_OVF_INT_ENA_V 0x1
+#define LEDC_HSTIMER0_OVF_INT_ENA_S 0
+
+#define LEDC_INT_CLR_REG (DR_REG_LEDC_BASE + 0x018C)
+/* LEDC_DUTY_CHNG_END_LSCH7_INT_CLR : WO ;bitpos:[23] ;default: 1'h0 ; */
+/*description: Set this bit to clear low speed channel 7 duty change done interrupt.*/
+#define LEDC_DUTY_CHNG_END_LSCH7_INT_CLR (BIT(23))
+#define LEDC_DUTY_CHNG_END_LSCH7_INT_CLR_M (BIT(23))
+#define LEDC_DUTY_CHNG_END_LSCH7_INT_CLR_V 0x1
+#define LEDC_DUTY_CHNG_END_LSCH7_INT_CLR_S 23
+/* LEDC_DUTY_CHNG_END_LSCH6_INT_CLR : WO ;bitpos:[22] ;default: 1'b0 ; */
+/*description: Set this bit to clear low speed channel 6 duty change done interrupt.*/
+#define LEDC_DUTY_CHNG_END_LSCH6_INT_CLR (BIT(22))
+#define LEDC_DUTY_CHNG_END_LSCH6_INT_CLR_M (BIT(22))
+#define LEDC_DUTY_CHNG_END_LSCH6_INT_CLR_V 0x1
+#define LEDC_DUTY_CHNG_END_LSCH6_INT_CLR_S 22
+/* LEDC_DUTY_CHNG_END_LSCH5_INT_CLR : WO ;bitpos:[21] ;default: 1'b0 ; */
+/*description: Set this bit to clear low speed channel 5 duty change done interrupt.*/
+#define LEDC_DUTY_CHNG_END_LSCH5_INT_CLR (BIT(21))
+#define LEDC_DUTY_CHNG_END_LSCH5_INT_CLR_M (BIT(21))
+#define LEDC_DUTY_CHNG_END_LSCH5_INT_CLR_V 0x1
+#define LEDC_DUTY_CHNG_END_LSCH5_INT_CLR_S 21
+/* LEDC_DUTY_CHNG_END_LSCH4_INT_CLR : WO ;bitpos:[20] ;default: 1'b0 ; */
+/*description: Set this bit to clear low speed channel 4 duty change done interrupt.*/
+#define LEDC_DUTY_CHNG_END_LSCH4_INT_CLR (BIT(20))
+#define LEDC_DUTY_CHNG_END_LSCH4_INT_CLR_M (BIT(20))
+#define LEDC_DUTY_CHNG_END_LSCH4_INT_CLR_V 0x1
+#define LEDC_DUTY_CHNG_END_LSCH4_INT_CLR_S 20
+/* LEDC_DUTY_CHNG_END_LSCH3_INT_CLR : WO ;bitpos:[19] ;default: 1'b0 ; */
+/*description: Set this bit to clear low speed channel 3 duty change done interrupt.*/
+#define LEDC_DUTY_CHNG_END_LSCH3_INT_CLR (BIT(19))
+#define LEDC_DUTY_CHNG_END_LSCH3_INT_CLR_M (BIT(19))
+#define LEDC_DUTY_CHNG_END_LSCH3_INT_CLR_V 0x1
+#define LEDC_DUTY_CHNG_END_LSCH3_INT_CLR_S 19
+/* LEDC_DUTY_CHNG_END_LSCH2_INT_CLR : WO ;bitpos:[18] ;default: 1'b0 ; */
+/*description: Set this bit to clear low speed channel 2 duty change done interrupt.*/
+#define LEDC_DUTY_CHNG_END_LSCH2_INT_CLR (BIT(18))
+#define LEDC_DUTY_CHNG_END_LSCH2_INT_CLR_M (BIT(18))
+#define LEDC_DUTY_CHNG_END_LSCH2_INT_CLR_V 0x1
+#define LEDC_DUTY_CHNG_END_LSCH2_INT_CLR_S 18
+/* LEDC_DUTY_CHNG_END_LSCH1_INT_CLR : WO ;bitpos:[17] ;default: 1'b0 ; */
+/*description: Set this bit to clear low speed channel 1 duty change done interrupt.*/
+#define LEDC_DUTY_CHNG_END_LSCH1_INT_CLR (BIT(17))
+#define LEDC_DUTY_CHNG_END_LSCH1_INT_CLR_M (BIT(17))
+#define LEDC_DUTY_CHNG_END_LSCH1_INT_CLR_V 0x1
+#define LEDC_DUTY_CHNG_END_LSCH1_INT_CLR_S 17
+/* LEDC_DUTY_CHNG_END_LSCH0_INT_CLR : WO ;bitpos:[16] ;default: 1'b0 ; */
+/*description: Set this bit to clear low speed channel 0 duty change done interrupt.*/
+#define LEDC_DUTY_CHNG_END_LSCH0_INT_CLR (BIT(16))
+#define LEDC_DUTY_CHNG_END_LSCH0_INT_CLR_M (BIT(16))
+#define LEDC_DUTY_CHNG_END_LSCH0_INT_CLR_V 0x1
+#define LEDC_DUTY_CHNG_END_LSCH0_INT_CLR_S 16
+/* LEDC_DUTY_CHNG_END_HSCH7_INT_CLR : WO ;bitpos:[15] ;default: 1'b0 ; */
+/*description: Set this bit to clear high speed channel 7 duty change done interrupt.*/
+#define LEDC_DUTY_CHNG_END_HSCH7_INT_CLR (BIT(15))
+#define LEDC_DUTY_CHNG_END_HSCH7_INT_CLR_M (BIT(15))
+#define LEDC_DUTY_CHNG_END_HSCH7_INT_CLR_V 0x1
+#define LEDC_DUTY_CHNG_END_HSCH7_INT_CLR_S 15
+/* LEDC_DUTY_CHNG_END_HSCH6_INT_CLR : WO ;bitpos:[14] ;default: 1'b0 ; */
+/*description: Set this bit to clear high speed channel 6 duty change done interrupt.*/
+#define LEDC_DUTY_CHNG_END_HSCH6_INT_CLR (BIT(14))
+#define LEDC_DUTY_CHNG_END_HSCH6_INT_CLR_M (BIT(14))
+#define LEDC_DUTY_CHNG_END_HSCH6_INT_CLR_V 0x1
+#define LEDC_DUTY_CHNG_END_HSCH6_INT_CLR_S 14
+/* LEDC_DUTY_CHNG_END_HSCH5_INT_CLR : WO ;bitpos:[13] ;default: 1'b0 ; */
+/*description: Set this bit to clear high speed channel 5 duty change done interrupt.*/
+#define LEDC_DUTY_CHNG_END_HSCH5_INT_CLR (BIT(13))
+#define LEDC_DUTY_CHNG_END_HSCH5_INT_CLR_M (BIT(13))
+#define LEDC_DUTY_CHNG_END_HSCH5_INT_CLR_V 0x1
+#define LEDC_DUTY_CHNG_END_HSCH5_INT_CLR_S 13
+/* LEDC_DUTY_CHNG_END_HSCH4_INT_CLR : WO ;bitpos:[12] ;default: 1'b0 ; */
+/*description: Set this bit to clear high speed channel 4 duty change done interrupt.*/
+#define LEDC_DUTY_CHNG_END_HSCH4_INT_CLR (BIT(12))
+#define LEDC_DUTY_CHNG_END_HSCH4_INT_CLR_M (BIT(12))
+#define LEDC_DUTY_CHNG_END_HSCH4_INT_CLR_V 0x1
+#define LEDC_DUTY_CHNG_END_HSCH4_INT_CLR_S 12
+/* LEDC_DUTY_CHNG_END_HSCH3_INT_CLR : WO ;bitpos:[11] ;default: 1'b0 ; */
+/*description: Set this bit to clear high speed channel 3 duty change done interrupt.*/
+#define LEDC_DUTY_CHNG_END_HSCH3_INT_CLR (BIT(11))
+#define LEDC_DUTY_CHNG_END_HSCH3_INT_CLR_M (BIT(11))
+#define LEDC_DUTY_CHNG_END_HSCH3_INT_CLR_V 0x1
+#define LEDC_DUTY_CHNG_END_HSCH3_INT_CLR_S 11
+/* LEDC_DUTY_CHNG_END_HSCH2_INT_CLR : WO ;bitpos:[10] ;default: 1'b0 ; */
+/*description: Set this bit to clear high speed channel 2 duty change done interrupt.*/
+#define LEDC_DUTY_CHNG_END_HSCH2_INT_CLR (BIT(10))
+#define LEDC_DUTY_CHNG_END_HSCH2_INT_CLR_M (BIT(10))
+#define LEDC_DUTY_CHNG_END_HSCH2_INT_CLR_V 0x1
+#define LEDC_DUTY_CHNG_END_HSCH2_INT_CLR_S 10
+/* LEDC_DUTY_CHNG_END_HSCH1_INT_CLR : WO ;bitpos:[9] ;default: 1'b0 ; */
+/*description: Set this bit to clear high speed channel 1 duty change done interrupt.*/
+#define LEDC_DUTY_CHNG_END_HSCH1_INT_CLR (BIT(9))
+#define LEDC_DUTY_CHNG_END_HSCH1_INT_CLR_M (BIT(9))
+#define LEDC_DUTY_CHNG_END_HSCH1_INT_CLR_V 0x1
+#define LEDC_DUTY_CHNG_END_HSCH1_INT_CLR_S 9
+/* LEDC_DUTY_CHNG_END_HSCH0_INT_CLR : WO ;bitpos:[8] ;default: 1'b0 ; */
+/*description: Set this bit to clear high speed channel 0 duty change done interrupt.*/
+#define LEDC_DUTY_CHNG_END_HSCH0_INT_CLR (BIT(8))
+#define LEDC_DUTY_CHNG_END_HSCH0_INT_CLR_M (BIT(8))
+#define LEDC_DUTY_CHNG_END_HSCH0_INT_CLR_V 0x1
+#define LEDC_DUTY_CHNG_END_HSCH0_INT_CLR_S 8
+/* LEDC_LSTIMER3_OVF_INT_CLR : WO ;bitpos:[7] ;default: 1'b0 ; */
+/*description: Set this bit to clear low speed channel3 counter overflow interrupt.*/
+#define LEDC_LSTIMER3_OVF_INT_CLR (BIT(7))
+#define LEDC_LSTIMER3_OVF_INT_CLR_M (BIT(7))
+#define LEDC_LSTIMER3_OVF_INT_CLR_V 0x1
+#define LEDC_LSTIMER3_OVF_INT_CLR_S 7
+/* LEDC_LSTIMER2_OVF_INT_CLR : WO ;bitpos:[6] ;default: 1'b0 ; */
+/*description: Set this bit to clear low speed channel2 counter overflow interrupt.*/
+#define LEDC_LSTIMER2_OVF_INT_CLR (BIT(6))
+#define LEDC_LSTIMER2_OVF_INT_CLR_M (BIT(6))
+#define LEDC_LSTIMER2_OVF_INT_CLR_V 0x1
+#define LEDC_LSTIMER2_OVF_INT_CLR_S 6
+/* LEDC_LSTIMER1_OVF_INT_CLR : WO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: Set this bit to clear low speed channel1 counter overflow interrupt.*/
+#define LEDC_LSTIMER1_OVF_INT_CLR (BIT(5))
+#define LEDC_LSTIMER1_OVF_INT_CLR_M (BIT(5))
+#define LEDC_LSTIMER1_OVF_INT_CLR_V 0x1
+#define LEDC_LSTIMER1_OVF_INT_CLR_S 5
+/* LEDC_LSTIMER0_OVF_INT_CLR : WO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: Set this bit to clear low speed channel0 counter overflow interrupt.*/
+#define LEDC_LSTIMER0_OVF_INT_CLR (BIT(4))
+#define LEDC_LSTIMER0_OVF_INT_CLR_M (BIT(4))
+#define LEDC_LSTIMER0_OVF_INT_CLR_V 0x1
+#define LEDC_LSTIMER0_OVF_INT_CLR_S 4
+/* LEDC_HSTIMER3_OVF_INT_CLR : WO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: Set this bit to clear high speed channel3 counter overflow interrupt.*/
+#define LEDC_HSTIMER3_OVF_INT_CLR (BIT(3))
+#define LEDC_HSTIMER3_OVF_INT_CLR_M (BIT(3))
+#define LEDC_HSTIMER3_OVF_INT_CLR_V 0x1
+#define LEDC_HSTIMER3_OVF_INT_CLR_S 3
+/* LEDC_HSTIMER2_OVF_INT_CLR : WO ;bitpos:[2] ;default: 1'b0 ; */
+/*description: Set this bit to clear high speed channel2 counter overflow interrupt.*/
+#define LEDC_HSTIMER2_OVF_INT_CLR (BIT(2))
+#define LEDC_HSTIMER2_OVF_INT_CLR_M (BIT(2))
+#define LEDC_HSTIMER2_OVF_INT_CLR_V 0x1
+#define LEDC_HSTIMER2_OVF_INT_CLR_S 2
+/* LEDC_HSTIMER1_OVF_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: Set this bit to clear high speed channel1 counter overflow interrupt.*/
+#define LEDC_HSTIMER1_OVF_INT_CLR (BIT(1))
+#define LEDC_HSTIMER1_OVF_INT_CLR_M (BIT(1))
+#define LEDC_HSTIMER1_OVF_INT_CLR_V 0x1
+#define LEDC_HSTIMER1_OVF_INT_CLR_S 1
+/* LEDC_HSTIMER0_OVF_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: Set this bit to clear high speed channel0 counter overflow interrupt.*/
+#define LEDC_HSTIMER0_OVF_INT_CLR (BIT(0))
+#define LEDC_HSTIMER0_OVF_INT_CLR_M (BIT(0))
+#define LEDC_HSTIMER0_OVF_INT_CLR_V 0x1
+#define LEDC_HSTIMER0_OVF_INT_CLR_S 0
+
+#define LEDC_CONF_REG (DR_REG_LEDC_BASE + 0x0190)
+/* LEDC_APB_CLK_SEL : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: This bit is used to set the frequency of slow_clk. 1'b1:80mhz 1'b0:8mhz*/
+#define LEDC_APB_CLK_SEL (BIT(0))
+#define LEDC_APB_CLK_SEL_M (BIT(0))
+#define LEDC_APB_CLK_SEL_V 0x1
+#define LEDC_APB_CLK_SEL_S 0
+
+#define LEDC_DATE_REG (DR_REG_LEDC_BASE + 0x01FC)
+/* LEDC_DATE : R/W ;bitpos:[31:0] ;default: 32'h16031700 ; */
+/*description: This register represents the version .*/
+#define LEDC_DATE 0xFFFFFFFF
+#define LEDC_DATE_M ((LEDC_DATE_V)<<(LEDC_DATE_S))
+#define LEDC_DATE_V 0xFFFFFFFF
+#define LEDC_DATE_S 0
+
+
+
+
+#endif /*_SOC_LEDC_REG_H_ */
+
+
-// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD\r
-//\r
-// Licensed under the Apache License, Version 2.0 (the "License");\r
-// you may not use this file except in compliance with the License.\r
-// You may obtain a copy of the License at\r
-\r
-// http://www.apache.org/licenses/LICENSE-2.0\r
-//\r
-// Unless required by applicable law or agreed to in writing, software\r
-// distributed under the License is distributed on an "AS IS" BASIS,\r
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
-// See the License for the specific language governing permissions and\r
-// limitations under the License.\r
-#ifndef _SOC_PCNT_REG_H_\r
-#define _SOC_PCNT_REG_H_\r
-\r
-\r
-#include "soc.h"\r
-#define PCNT_U0_CONF0_REG (DR_REG_PCNT_BASE + 0x0000)\r
-/* PCNT_CH1_LCTRL_MODE_U0 : R/W ;bitpos:[31:30] ;default: 2'd0 ; */\r
-/*description: This register is used to control the mode of channel1's low control\r
- signal for unit0. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/\r
-#define PCNT_CH1_LCTRL_MODE_U0 0x00000003\r
-#define PCNT_CH1_LCTRL_MODE_U0_M ((PCNT_CH1_LCTRL_MODE_U0_V)<<(PCNT_CH1_LCTRL_MODE_U0_S))\r
-#define PCNT_CH1_LCTRL_MODE_U0_V 0x3\r
-#define PCNT_CH1_LCTRL_MODE_U0_S 30\r
-/* PCNT_CH1_HCTRL_MODE_U0 : R/W ;bitpos:[29:28] ;default: 2'd0 ; */\r
-/*description: This register is used to control the mode of channel1's high\r
- control signal for unit0. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/\r
-#define PCNT_CH1_HCTRL_MODE_U0 0x00000003\r
-#define PCNT_CH1_HCTRL_MODE_U0_M ((PCNT_CH1_HCTRL_MODE_U0_V)<<(PCNT_CH1_HCTRL_MODE_U0_S))\r
-#define PCNT_CH1_HCTRL_MODE_U0_V 0x3\r
-#define PCNT_CH1_HCTRL_MODE_U0_S 28\r
-/* PCNT_CH1_POS_MODE_U0 : R/W ;bitpos:[27:26] ;default: 2'd0 ; */\r
-/*description: This register is used to control the mode of channel1's input\r
- posedge signal for unit0. 2'd1: increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden*/\r
-#define PCNT_CH1_POS_MODE_U0 0x00000003\r
-#define PCNT_CH1_POS_MODE_U0_M ((PCNT_CH1_POS_MODE_U0_V)<<(PCNT_CH1_POS_MODE_U0_S))\r
-#define PCNT_CH1_POS_MODE_U0_V 0x3\r
-#define PCNT_CH1_POS_MODE_U0_S 26\r
-/* PCNT_CH1_NEG_MODE_U0 : R/W ;bitpos:[25:24] ;default: 2'd0 ; */\r
-/*description: This register is used to control the mode of channel1's input\r
- negedge signal for unit0. 2'd1: increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden*/\r
-#define PCNT_CH1_NEG_MODE_U0 0x00000003\r
-#define PCNT_CH1_NEG_MODE_U0_M ((PCNT_CH1_NEG_MODE_U0_V)<<(PCNT_CH1_NEG_MODE_U0_S))\r
-#define PCNT_CH1_NEG_MODE_U0_V 0x3\r
-#define PCNT_CH1_NEG_MODE_U0_S 24\r
-/* PCNT_CH0_LCTRL_MODE_U0 : R/W ;bitpos:[23:22] ;default: 2'd0 ; */\r
-/*description: This register is used to control the mode of channel0's low control\r
- signal for unit0. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/\r
-#define PCNT_CH0_LCTRL_MODE_U0 0x00000003\r
-#define PCNT_CH0_LCTRL_MODE_U0_M ((PCNT_CH0_LCTRL_MODE_U0_V)<<(PCNT_CH0_LCTRL_MODE_U0_S))\r
-#define PCNT_CH0_LCTRL_MODE_U0_V 0x3\r
-#define PCNT_CH0_LCTRL_MODE_U0_S 22\r
-/* PCNT_CH0_HCTRL_MODE_U0 : R/W ;bitpos:[21:20] ;default: 2'd0 ; */\r
-/*description: This register is used to control the mode of channel0's high\r
- control signal for unit0. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/\r
-#define PCNT_CH0_HCTRL_MODE_U0 0x00000003\r
-#define PCNT_CH0_HCTRL_MODE_U0_M ((PCNT_CH0_HCTRL_MODE_U0_V)<<(PCNT_CH0_HCTRL_MODE_U0_S))\r
-#define PCNT_CH0_HCTRL_MODE_U0_V 0x3\r
-#define PCNT_CH0_HCTRL_MODE_U0_S 20\r
-/* PCNT_CH0_POS_MODE_U0 : R/W ;bitpos:[19:18] ;default: 2'd0 ; */\r
-/*description: This register is used to control the mode of channel0's input\r
- posedge signal for unit0. 2'd1: increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden*/\r
-#define PCNT_CH0_POS_MODE_U0 0x00000003\r
-#define PCNT_CH0_POS_MODE_U0_M ((PCNT_CH0_POS_MODE_U0_V)<<(PCNT_CH0_POS_MODE_U0_S))\r
-#define PCNT_CH0_POS_MODE_U0_V 0x3\r
-#define PCNT_CH0_POS_MODE_U0_S 18\r
-/* PCNT_CH0_NEG_MODE_U0 : R/W ;bitpos:[17:16] ;default: 2'd0 ; */\r
-/*description: This register is used to control the mode of channel0's input\r
- negedge signal for unit0. 2'd1: increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden*/\r
-#define PCNT_CH0_NEG_MODE_U0 0x00000003\r
-#define PCNT_CH0_NEG_MODE_U0_M ((PCNT_CH0_NEG_MODE_U0_V)<<(PCNT_CH0_NEG_MODE_U0_S))\r
-#define PCNT_CH0_NEG_MODE_U0_V 0x3\r
-#define PCNT_CH0_NEG_MODE_U0_S 16\r
-/* PCNT_THR_THRES1_EN_U0 : R/W ;bitpos:[15] ;default: 1'b0 ; */\r
-/*description: This is the enable bit for comparing unit0's count with thres1 value .*/\r
-#define PCNT_THR_THRES1_EN_U0 (BIT(15))\r
-#define PCNT_THR_THRES1_EN_U0_M (BIT(15))\r
-#define PCNT_THR_THRES1_EN_U0_V 0x1\r
-#define PCNT_THR_THRES1_EN_U0_S 15\r
-/* PCNT_THR_THRES0_EN_U0 : R/W ;bitpos:[14] ;default: 1'b0 ; */\r
-/*description: This is the enable bit for comparing unit0's count with thres0 value.*/\r
-#define PCNT_THR_THRES0_EN_U0 (BIT(14))\r
-#define PCNT_THR_THRES0_EN_U0_M (BIT(14))\r
-#define PCNT_THR_THRES0_EN_U0_V 0x1\r
-#define PCNT_THR_THRES0_EN_U0_S 14\r
-/* PCNT_THR_L_LIM_EN_U0 : R/W ;bitpos:[13] ;default: 1'b1 ; */\r
-/*description: This is the enable bit for comparing unit0's count with thr_l_lim value.*/\r
-#define PCNT_THR_L_LIM_EN_U0 (BIT(13))\r
-#define PCNT_THR_L_LIM_EN_U0_M (BIT(13))\r
-#define PCNT_THR_L_LIM_EN_U0_V 0x1\r
-#define PCNT_THR_L_LIM_EN_U0_S 13\r
-/* PCNT_THR_H_LIM_EN_U0 : R/W ;bitpos:[12] ;default: 1'b1 ; */\r
-/*description: This is the enable bit for comparing unit0's count with thr_h_lim value.*/\r
-#define PCNT_THR_H_LIM_EN_U0 (BIT(12))\r
-#define PCNT_THR_H_LIM_EN_U0_M (BIT(12))\r
-#define PCNT_THR_H_LIM_EN_U0_V 0x1\r
-#define PCNT_THR_H_LIM_EN_U0_S 12\r
-/* PCNT_THR_ZERO_EN_U0 : R/W ;bitpos:[11] ;default: 1'b1 ; */\r
-/*description: This is the enable bit for comparing unit0's count with 0 value.*/\r
-#define PCNT_THR_ZERO_EN_U0 (BIT(11))\r
-#define PCNT_THR_ZERO_EN_U0_M (BIT(11))\r
-#define PCNT_THR_ZERO_EN_U0_V 0x1\r
-#define PCNT_THR_ZERO_EN_U0_S 11\r
-/* PCNT_FILTER_EN_U0 : R/W ;bitpos:[10] ;default: 1'b1 ; */\r
-/*description: This is the enable bit for filtering input signals for unit0.*/\r
-#define PCNT_FILTER_EN_U0 (BIT(10))\r
-#define PCNT_FILTER_EN_U0_M (BIT(10))\r
-#define PCNT_FILTER_EN_U0_V 0x1\r
-#define PCNT_FILTER_EN_U0_S 10\r
-/* PCNT_FILTER_THRES_U0 : R/W ;bitpos:[9:0] ;default: 10'h10 ; */\r
-/*description: This register is used to filter pluse whose width is smaller\r
- than this value for unit0.*/\r
-#define PCNT_FILTER_THRES_U0 0x000003FF\r
-#define PCNT_FILTER_THRES_U0_M ((PCNT_FILTER_THRES_U0_V)<<(PCNT_FILTER_THRES_U0_S))\r
-#define PCNT_FILTER_THRES_U0_V 0x3FF\r
-#define PCNT_FILTER_THRES_U0_S 0\r
-\r
-#define PCNT_U0_CONF1_REG (DR_REG_PCNT_BASE + 0x0004)\r
-/* PCNT_CNT_THRES1_U0 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */\r
-/*description: This register is used to configure thres1 value for unit0.*/\r
-#define PCNT_CNT_THRES1_U0 0x0000FFFF\r
-#define PCNT_CNT_THRES1_U0_M ((PCNT_CNT_THRES1_U0_V)<<(PCNT_CNT_THRES1_U0_S))\r
-#define PCNT_CNT_THRES1_U0_V 0xFFFF\r
-#define PCNT_CNT_THRES1_U0_S 16\r
-/* PCNT_CNT_THRES0_U0 : R/W ;bitpos:[15:0] ;default: 10'h0 ; */\r
-/*description: This register is used to configure thres0 value for unit0.*/\r
-#define PCNT_CNT_THRES0_U0 0x0000FFFF\r
-#define PCNT_CNT_THRES0_U0_M ((PCNT_CNT_THRES0_U0_V)<<(PCNT_CNT_THRES0_U0_S))\r
-#define PCNT_CNT_THRES0_U0_V 0xFFFF\r
-#define PCNT_CNT_THRES0_U0_S 0\r
-\r
-#define PCNT_U0_CONF2_REG (DR_REG_PCNT_BASE + 0x0008)\r
-/* PCNT_CNT_L_LIM_U0 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */\r
-/*description: This register is used to confiugre thr_l_lim value for unit0.*/\r
-#define PCNT_CNT_L_LIM_U0 0x0000FFFF\r
-#define PCNT_CNT_L_LIM_U0_M ((PCNT_CNT_L_LIM_U0_V)<<(PCNT_CNT_L_LIM_U0_S))\r
-#define PCNT_CNT_L_LIM_U0_V 0xFFFF\r
-#define PCNT_CNT_L_LIM_U0_S 16\r
-/* PCNT_CNT_H_LIM_U0 : R/W ;bitpos:[15:0] ;default: 10'h0 ; */\r
-/*description: This register is used to configure thr_h_lim value for unit0.*/\r
-#define PCNT_CNT_H_LIM_U0 0x0000FFFF\r
-#define PCNT_CNT_H_LIM_U0_M ((PCNT_CNT_H_LIM_U0_V)<<(PCNT_CNT_H_LIM_U0_S))\r
-#define PCNT_CNT_H_LIM_U0_V 0xFFFF\r
-#define PCNT_CNT_H_LIM_U0_S 0\r
-\r
-#define PCNT_U1_CONF0_REG (DR_REG_PCNT_BASE + 0x000c)\r
-/* PCNT_CH1_LCTRL_MODE_U1 : R/W ;bitpos:[31:30] ;default: 2'd0 ; */\r
-/*description: This register is used to control the mode of channel1's low control\r
- signal for unit1. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/\r
-#define PCNT_CH1_LCTRL_MODE_U1 0x00000003\r
-#define PCNT_CH1_LCTRL_MODE_U1_M ((PCNT_CH1_LCTRL_MODE_U1_V)<<(PCNT_CH1_LCTRL_MODE_U1_S))\r
-#define PCNT_CH1_LCTRL_MODE_U1_V 0x3\r
-#define PCNT_CH1_LCTRL_MODE_U1_S 30\r
-/* PCNT_CH1_HCTRL_MODE_U1 : R/W ;bitpos:[29:28] ;default: 2'd0 ; */\r
-/*description: This register is used to control the mode of channel1's high\r
- control signal for unit1. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/\r
-#define PCNT_CH1_HCTRL_MODE_U1 0x00000003\r
-#define PCNT_CH1_HCTRL_MODE_U1_M ((PCNT_CH1_HCTRL_MODE_U1_V)<<(PCNT_CH1_HCTRL_MODE_U1_S))\r
-#define PCNT_CH1_HCTRL_MODE_U1_V 0x3\r
-#define PCNT_CH1_HCTRL_MODE_U1_S 28\r
-/* PCNT_CH1_POS_MODE_U1 : R/W ;bitpos:[27:26] ;default: 2'd0 ; */\r
-/*description: This register is used to control the mode of channel1's input\r
- posedge signal for unit1. 2'd1: increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden*/\r
-#define PCNT_CH1_POS_MODE_U1 0x00000003\r
-#define PCNT_CH1_POS_MODE_U1_M ((PCNT_CH1_POS_MODE_U1_V)<<(PCNT_CH1_POS_MODE_U1_S))\r
-#define PCNT_CH1_POS_MODE_U1_V 0x3\r
-#define PCNT_CH1_POS_MODE_U1_S 26\r
-/* PCNT_CH1_NEG_MODE_U1 : R/W ;bitpos:[25:24] ;default: 2'd0 ; */\r
-/*description: This register is used to control the mode of channel1's input\r
- negedge signal for unit1. 2'd1: increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden*/\r
-#define PCNT_CH1_NEG_MODE_U1 0x00000003\r
-#define PCNT_CH1_NEG_MODE_U1_M ((PCNT_CH1_NEG_MODE_U1_V)<<(PCNT_CH1_NEG_MODE_U1_S))\r
-#define PCNT_CH1_NEG_MODE_U1_V 0x3\r
-#define PCNT_CH1_NEG_MODE_U1_S 24\r
-/* PCNT_CH0_LCTRL_MODE_U1 : R/W ;bitpos:[23:22] ;default: 2'd0 ; */\r
-/*description: This register is used to control the mode of channel0's low control\r
- signal for unit1. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/\r
-#define PCNT_CH0_LCTRL_MODE_U1 0x00000003\r
-#define PCNT_CH0_LCTRL_MODE_U1_M ((PCNT_CH0_LCTRL_MODE_U1_V)<<(PCNT_CH0_LCTRL_MODE_U1_S))\r
-#define PCNT_CH0_LCTRL_MODE_U1_V 0x3\r
-#define PCNT_CH0_LCTRL_MODE_U1_S 22\r
-/* PCNT_CH0_HCTRL_MODE_U1 : R/W ;bitpos:[21:20] ;default: 2'd0 ; */\r
-/*description: This register is used to control the mode of channel0's high\r
- control signal for unit1. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/\r
-#define PCNT_CH0_HCTRL_MODE_U1 0x00000003\r
-#define PCNT_CH0_HCTRL_MODE_U1_M ((PCNT_CH0_HCTRL_MODE_U1_V)<<(PCNT_CH0_HCTRL_MODE_U1_S))\r
-#define PCNT_CH0_HCTRL_MODE_U1_V 0x3\r
-#define PCNT_CH0_HCTRL_MODE_U1_S 20\r
-/* PCNT_CH0_POS_MODE_U1 : R/W ;bitpos:[19:18] ;default: 2'd0 ; */\r
-/*description: This register is used to control the mode of channel0's input\r
- posedge signal for unit1. 2'd1: increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden*/\r
-#define PCNT_CH0_POS_MODE_U1 0x00000003\r
-#define PCNT_CH0_POS_MODE_U1_M ((PCNT_CH0_POS_MODE_U1_V)<<(PCNT_CH0_POS_MODE_U1_S))\r
-#define PCNT_CH0_POS_MODE_U1_V 0x3\r
-#define PCNT_CH0_POS_MODE_U1_S 18\r
-/* PCNT_CH0_NEG_MODE_U1 : R/W ;bitpos:[17:16] ;default: 2'd0 ; */\r
-/*description: This register is used to control the mode of channel0's input\r
- negedge signal for unit1. 2'd1: increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden*/\r
-#define PCNT_CH0_NEG_MODE_U1 0x00000003\r
-#define PCNT_CH0_NEG_MODE_U1_M ((PCNT_CH0_NEG_MODE_U1_V)<<(PCNT_CH0_NEG_MODE_U1_S))\r
-#define PCNT_CH0_NEG_MODE_U1_V 0x3\r
-#define PCNT_CH0_NEG_MODE_U1_S 16\r
-/* PCNT_THR_THRES1_EN_U1 : R/W ;bitpos:[15] ;default: 1'b0 ; */\r
-/*description: This is the enable bit for comparing unit1's count with thres1 value .*/\r
-#define PCNT_THR_THRES1_EN_U1 (BIT(15))\r
-#define PCNT_THR_THRES1_EN_U1_M (BIT(15))\r
-#define PCNT_THR_THRES1_EN_U1_V 0x1\r
-#define PCNT_THR_THRES1_EN_U1_S 15\r
-/* PCNT_THR_THRES0_EN_U1 : R/W ;bitpos:[14] ;default: 1'b0 ; */\r
-/*description: This is the enable bit for comparing unit1's count with thres0 value.*/\r
-#define PCNT_THR_THRES0_EN_U1 (BIT(14))\r
-#define PCNT_THR_THRES0_EN_U1_M (BIT(14))\r
-#define PCNT_THR_THRES0_EN_U1_V 0x1\r
-#define PCNT_THR_THRES0_EN_U1_S 14\r
-/* PCNT_THR_L_LIM_EN_U1 : R/W ;bitpos:[13] ;default: 1'b1 ; */\r
-/*description: This is the enable bit for comparing unit1's count with thr_l_lim value.*/\r
-#define PCNT_THR_L_LIM_EN_U1 (BIT(13))\r
-#define PCNT_THR_L_LIM_EN_U1_M (BIT(13))\r
-#define PCNT_THR_L_LIM_EN_U1_V 0x1\r
-#define PCNT_THR_L_LIM_EN_U1_S 13\r
-/* PCNT_THR_H_LIM_EN_U1 : R/W ;bitpos:[12] ;default: 1'b1 ; */\r
-/*description: This is the enable bit for comparing unit1's count with thr_h_lim value.*/\r
-#define PCNT_THR_H_LIM_EN_U1 (BIT(12))\r
-#define PCNT_THR_H_LIM_EN_U1_M (BIT(12))\r
-#define PCNT_THR_H_LIM_EN_U1_V 0x1\r
-#define PCNT_THR_H_LIM_EN_U1_S 12\r
-/* PCNT_THR_ZERO_EN_U1 : R/W ;bitpos:[11] ;default: 1'b1 ; */\r
-/*description: This is the enable bit for comparing unit1's count with 0 value.*/\r
-#define PCNT_THR_ZERO_EN_U1 (BIT(11))\r
-#define PCNT_THR_ZERO_EN_U1_M (BIT(11))\r
-#define PCNT_THR_ZERO_EN_U1_V 0x1\r
-#define PCNT_THR_ZERO_EN_U1_S 11\r
-/* PCNT_FILTER_EN_U1 : R/W ;bitpos:[10] ;default: 1'b1 ; */\r
-/*description: This is the enable bit for filtering input signals for unit1.*/\r
-#define PCNT_FILTER_EN_U1 (BIT(10))\r
-#define PCNT_FILTER_EN_U1_M (BIT(10))\r
-#define PCNT_FILTER_EN_U1_V 0x1\r
-#define PCNT_FILTER_EN_U1_S 10\r
-/* PCNT_FILTER_THRES_U1 : R/W ;bitpos:[9:0] ;default: 10'h10 ; */\r
-/*description: This register is used to filter pluse whose width is smaller\r
- than this value for unit1.*/\r
-#define PCNT_FILTER_THRES_U1 0x000003FF\r
-#define PCNT_FILTER_THRES_U1_M ((PCNT_FILTER_THRES_U1_V)<<(PCNT_FILTER_THRES_U1_S))\r
-#define PCNT_FILTER_THRES_U1_V 0x3FF\r
-#define PCNT_FILTER_THRES_U1_S 0\r
-\r
-#define PCNT_U1_CONF1_REG (DR_REG_PCNT_BASE + 0x0010)\r
-/* PCNT_CNT_THRES1_U1 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */\r
-/*description: This register is used to configure thres1 value for unit1.*/\r
-#define PCNT_CNT_THRES1_U1 0x0000FFFF\r
-#define PCNT_CNT_THRES1_U1_M ((PCNT_CNT_THRES1_U1_V)<<(PCNT_CNT_THRES1_U1_S))\r
-#define PCNT_CNT_THRES1_U1_V 0xFFFF\r
-#define PCNT_CNT_THRES1_U1_S 16\r
-/* PCNT_CNT_THRES0_U1 : R/W ;bitpos:[15:0] ;default: 10'h0 ; */\r
-/*description: This register is used to configure thres0 value for unit1.*/\r
-#define PCNT_CNT_THRES0_U1 0x0000FFFF\r
-#define PCNT_CNT_THRES0_U1_M ((PCNT_CNT_THRES0_U1_V)<<(PCNT_CNT_THRES0_U1_S))\r
-#define PCNT_CNT_THRES0_U1_V 0xFFFF\r
-#define PCNT_CNT_THRES0_U1_S 0\r
-\r
-#define PCNT_U1_CONF2_REG (DR_REG_PCNT_BASE + 0x0014)\r
-/* PCNT_CNT_L_LIM_U1 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */\r
-/*description: This register is used to confiugre thr_l_lim value for unit1.*/\r
-#define PCNT_CNT_L_LIM_U1 0x0000FFFF\r
-#define PCNT_CNT_L_LIM_U1_M ((PCNT_CNT_L_LIM_U1_V)<<(PCNT_CNT_L_LIM_U1_S))\r
-#define PCNT_CNT_L_LIM_U1_V 0xFFFF\r
-#define PCNT_CNT_L_LIM_U1_S 16\r
-/* PCNT_CNT_H_LIM_U1 : R/W ;bitpos:[15:0] ;default: 10'h0 ; */\r
-/*description: This register is used to configure thr_h_lim value for unit1.*/\r
-#define PCNT_CNT_H_LIM_U1 0x0000FFFF\r
-#define PCNT_CNT_H_LIM_U1_M ((PCNT_CNT_H_LIM_U1_V)<<(PCNT_CNT_H_LIM_U1_S))\r
-#define PCNT_CNT_H_LIM_U1_V 0xFFFF\r
-#define PCNT_CNT_H_LIM_U1_S 0\r
-\r
-#define PCNT_U2_CONF0_REG (DR_REG_PCNT_BASE + 0x0018)\r
-/* PCNT_CH1_LCTRL_MODE_U2 : R/W ;bitpos:[31:30] ;default: 2'd0 ; */\r
-/*description: This register is used to control the mode of channel1's low control\r
- signal for unit2. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/\r
-#define PCNT_CH1_LCTRL_MODE_U2 0x00000003\r
-#define PCNT_CH1_LCTRL_MODE_U2_M ((PCNT_CH1_LCTRL_MODE_U2_V)<<(PCNT_CH1_LCTRL_MODE_U2_S))\r
-#define PCNT_CH1_LCTRL_MODE_U2_V 0x3\r
-#define PCNT_CH1_LCTRL_MODE_U2_S 30\r
-/* PCNT_CH1_HCTRL_MODE_U2 : R/W ;bitpos:[29:28] ;default: 2'd0 ; */\r
-/*description: This register is used to control the mode of channel1's high\r
- control signal for unit2. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/\r
-#define PCNT_CH1_HCTRL_MODE_U2 0x00000003\r
-#define PCNT_CH1_HCTRL_MODE_U2_M ((PCNT_CH1_HCTRL_MODE_U2_V)<<(PCNT_CH1_HCTRL_MODE_U2_S))\r
-#define PCNT_CH1_HCTRL_MODE_U2_V 0x3\r
-#define PCNT_CH1_HCTRL_MODE_U2_S 28\r
-/* PCNT_CH1_POS_MODE_U2 : R/W ;bitpos:[27:26] ;default: 2'd0 ; */\r
-/*description: This register is used to control the mode of channel1's input\r
- posedge signal for unit2. 2'd1: increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden*/\r
-#define PCNT_CH1_POS_MODE_U2 0x00000003\r
-#define PCNT_CH1_POS_MODE_U2_M ((PCNT_CH1_POS_MODE_U2_V)<<(PCNT_CH1_POS_MODE_U2_S))\r
-#define PCNT_CH1_POS_MODE_U2_V 0x3\r
-#define PCNT_CH1_POS_MODE_U2_S 26\r
-/* PCNT_CH1_NEG_MODE_U2 : R/W ;bitpos:[25:24] ;default: 2'd0 ; */\r
-/*description: This register is used to control the mode of channel1's input\r
- negedge signal for unit2. 2'd1: increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden*/\r
-#define PCNT_CH1_NEG_MODE_U2 0x00000003\r
-#define PCNT_CH1_NEG_MODE_U2_M ((PCNT_CH1_NEG_MODE_U2_V)<<(PCNT_CH1_NEG_MODE_U2_S))\r
-#define PCNT_CH1_NEG_MODE_U2_V 0x3\r
-#define PCNT_CH1_NEG_MODE_U2_S 24\r
-/* PCNT_CH0_LCTRL_MODE_U2 : R/W ;bitpos:[23:22] ;default: 2'd0 ; */\r
-/*description: This register is used to control the mode of channel0's low control\r
- signal for unit2. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/\r
-#define PCNT_CH0_LCTRL_MODE_U2 0x00000003\r
-#define PCNT_CH0_LCTRL_MODE_U2_M ((PCNT_CH0_LCTRL_MODE_U2_V)<<(PCNT_CH0_LCTRL_MODE_U2_S))\r
-#define PCNT_CH0_LCTRL_MODE_U2_V 0x3\r
-#define PCNT_CH0_LCTRL_MODE_U2_S 22\r
-/* PCNT_CH0_HCTRL_MODE_U2 : R/W ;bitpos:[21:20] ;default: 2'd0 ; */\r
-/*description: This register is used to control the mode of channel0's high\r
- control signal for unit2. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/\r
-#define PCNT_CH0_HCTRL_MODE_U2 0x00000003\r
-#define PCNT_CH0_HCTRL_MODE_U2_M ((PCNT_CH0_HCTRL_MODE_U2_V)<<(PCNT_CH0_HCTRL_MODE_U2_S))\r
-#define PCNT_CH0_HCTRL_MODE_U2_V 0x3\r
-#define PCNT_CH0_HCTRL_MODE_U2_S 20\r
-/* PCNT_CH0_POS_MODE_U2 : R/W ;bitpos:[19:18] ;default: 2'd0 ; */\r
-/*description: This register is used to control the mode of channel0's input\r
- posedge signal for unit2. 2'd1: increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden*/\r
-#define PCNT_CH0_POS_MODE_U2 0x00000003\r
-#define PCNT_CH0_POS_MODE_U2_M ((PCNT_CH0_POS_MODE_U2_V)<<(PCNT_CH0_POS_MODE_U2_S))\r
-#define PCNT_CH0_POS_MODE_U2_V 0x3\r
-#define PCNT_CH0_POS_MODE_U2_S 18\r
-/* PCNT_CH0_NEG_MODE_U2 : R/W ;bitpos:[17:16] ;default: 2'd0 ; */\r
-/*description: This register is used to control the mode of channel0's input\r
- negedge signal for unit2. 2'd1: increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden*/\r
-#define PCNT_CH0_NEG_MODE_U2 0x00000003\r
-#define PCNT_CH0_NEG_MODE_U2_M ((PCNT_CH0_NEG_MODE_U2_V)<<(PCNT_CH0_NEG_MODE_U2_S))\r
-#define PCNT_CH0_NEG_MODE_U2_V 0x3\r
-#define PCNT_CH0_NEG_MODE_U2_S 16\r
-/* PCNT_THR_THRES1_EN_U2 : R/W ;bitpos:[15] ;default: 1'b0 ; */\r
-/*description: This is the enable bit for comparing unit2's count with thres1 value .*/\r
-#define PCNT_THR_THRES1_EN_U2 (BIT(15))\r
-#define PCNT_THR_THRES1_EN_U2_M (BIT(15))\r
-#define PCNT_THR_THRES1_EN_U2_V 0x1\r
-#define PCNT_THR_THRES1_EN_U2_S 15\r
-/* PCNT_THR_THRES0_EN_U2 : R/W ;bitpos:[14] ;default: 1'b0 ; */\r
-/*description: This is the enable bit for comparing unit2's count with thres0 value.*/\r
-#define PCNT_THR_THRES0_EN_U2 (BIT(14))\r
-#define PCNT_THR_THRES0_EN_U2_M (BIT(14))\r
-#define PCNT_THR_THRES0_EN_U2_V 0x1\r
-#define PCNT_THR_THRES0_EN_U2_S 14\r
-/* PCNT_THR_L_LIM_EN_U2 : R/W ;bitpos:[13] ;default: 1'b1 ; */\r
-/*description: This is the enable bit for comparing unit2's count with thr_l_lim value.*/\r
-#define PCNT_THR_L_LIM_EN_U2 (BIT(13))\r
-#define PCNT_THR_L_LIM_EN_U2_M (BIT(13))\r
-#define PCNT_THR_L_LIM_EN_U2_V 0x1\r
-#define PCNT_THR_L_LIM_EN_U2_S 13\r
-/* PCNT_THR_H_LIM_EN_U2 : R/W ;bitpos:[12] ;default: 1'b1 ; */\r
-/*description: This is the enable bit for comparing unit2's count with thr_h_lim value.*/\r
-#define PCNT_THR_H_LIM_EN_U2 (BIT(12))\r
-#define PCNT_THR_H_LIM_EN_U2_M (BIT(12))\r
-#define PCNT_THR_H_LIM_EN_U2_V 0x1\r
-#define PCNT_THR_H_LIM_EN_U2_S 12\r
-/* PCNT_THR_ZERO_EN_U2 : R/W ;bitpos:[11] ;default: 1'b1 ; */\r
-/*description: This is the enable bit for comparing unit2's count with 0 value.*/\r
-#define PCNT_THR_ZERO_EN_U2 (BIT(11))\r
-#define PCNT_THR_ZERO_EN_U2_M (BIT(11))\r
-#define PCNT_THR_ZERO_EN_U2_V 0x1\r
-#define PCNT_THR_ZERO_EN_U2_S 11\r
-/* PCNT_FILTER_EN_U2 : R/W ;bitpos:[10] ;default: 1'b1 ; */\r
-/*description: This is the enable bit for filtering input signals for unit2.*/\r
-#define PCNT_FILTER_EN_U2 (BIT(10))\r
-#define PCNT_FILTER_EN_U2_M (BIT(10))\r
-#define PCNT_FILTER_EN_U2_V 0x1\r
-#define PCNT_FILTER_EN_U2_S 10\r
-/* PCNT_FILTER_THRES_U2 : R/W ;bitpos:[9:0] ;default: 10'h10 ; */\r
-/*description: This register is used to filter pluse whose width is smaller\r
- than this value for unit2.*/\r
-#define PCNT_FILTER_THRES_U2 0x000003FF\r
-#define PCNT_FILTER_THRES_U2_M ((PCNT_FILTER_THRES_U2_V)<<(PCNT_FILTER_THRES_U2_S))\r
-#define PCNT_FILTER_THRES_U2_V 0x3FF\r
-#define PCNT_FILTER_THRES_U2_S 0\r
-\r
-#define PCNT_U2_CONF1_REG (DR_REG_PCNT_BASE + 0x001c)\r
-/* PCNT_CNT_THRES1_U2 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */\r
-/*description: This register is used to configure thres1 value for unit2.*/\r
-#define PCNT_CNT_THRES1_U2 0x0000FFFF\r
-#define PCNT_CNT_THRES1_U2_M ((PCNT_CNT_THRES1_U2_V)<<(PCNT_CNT_THRES1_U2_S))\r
-#define PCNT_CNT_THRES1_U2_V 0xFFFF\r
-#define PCNT_CNT_THRES1_U2_S 16\r
-/* PCNT_CNT_THRES0_U2 : R/W ;bitpos:[15:0] ;default: 10'h0 ; */\r
-/*description: This register is used to configure thres0 value for unit2.*/\r
-#define PCNT_CNT_THRES0_U2 0x0000FFFF\r
-#define PCNT_CNT_THRES0_U2_M ((PCNT_CNT_THRES0_U2_V)<<(PCNT_CNT_THRES0_U2_S))\r
-#define PCNT_CNT_THRES0_U2_V 0xFFFF\r
-#define PCNT_CNT_THRES0_U2_S 0\r
-\r
-#define PCNT_U2_CONF2_REG (DR_REG_PCNT_BASE + 0x0020)\r
-/* PCNT_CNT_L_LIM_U2 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */\r
-/*description: This register is used to confiugre thr_l_lim value for unit2.*/\r
-#define PCNT_CNT_L_LIM_U2 0x0000FFFF\r
-#define PCNT_CNT_L_LIM_U2_M ((PCNT_CNT_L_LIM_U2_V)<<(PCNT_CNT_L_LIM_U2_S))\r
-#define PCNT_CNT_L_LIM_U2_V 0xFFFF\r
-#define PCNT_CNT_L_LIM_U2_S 16\r
-/* PCNT_CNT_H_LIM_U2 : R/W ;bitpos:[15:0] ;default: 10'h0 ; */\r
-/*description: This register is used to configure thr_h_lim value for unit2.*/\r
-#define PCNT_CNT_H_LIM_U2 0x0000FFFF\r
-#define PCNT_CNT_H_LIM_U2_M ((PCNT_CNT_H_LIM_U2_V)<<(PCNT_CNT_H_LIM_U2_S))\r
-#define PCNT_CNT_H_LIM_U2_V 0xFFFF\r
-#define PCNT_CNT_H_LIM_U2_S 0\r
-\r
-#define PCNT_U3_CONF0_REG (DR_REG_PCNT_BASE + 0x0024)\r
-/* PCNT_CH1_LCTRL_MODE_U3 : R/W ;bitpos:[31:30] ;default: 2'd0 ; */\r
-/*description: This register is used to control the mode of channel1's low control\r
- signal for unit3. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/\r
-#define PCNT_CH1_LCTRL_MODE_U3 0x00000003\r
-#define PCNT_CH1_LCTRL_MODE_U3_M ((PCNT_CH1_LCTRL_MODE_U3_V)<<(PCNT_CH1_LCTRL_MODE_U3_S))\r
-#define PCNT_CH1_LCTRL_MODE_U3_V 0x3\r
-#define PCNT_CH1_LCTRL_MODE_U3_S 30\r
-/* PCNT_CH1_HCTRL_MODE_U3 : R/W ;bitpos:[29:28] ;default: 2'd0 ; */\r
-/*description: This register is used to control the mode of channel1's high\r
- control signal for unit3. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/\r
-#define PCNT_CH1_HCTRL_MODE_U3 0x00000003\r
-#define PCNT_CH1_HCTRL_MODE_U3_M ((PCNT_CH1_HCTRL_MODE_U3_V)<<(PCNT_CH1_HCTRL_MODE_U3_S))\r
-#define PCNT_CH1_HCTRL_MODE_U3_V 0x3\r
-#define PCNT_CH1_HCTRL_MODE_U3_S 28\r
-/* PCNT_CH1_POS_MODE_U3 : R/W ;bitpos:[27:26] ;default: 2'd0 ; */\r
-/*description: This register is used to control the mode of channel1's input\r
- posedge signal for unit3. 2'd1: increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden*/\r
-#define PCNT_CH1_POS_MODE_U3 0x00000003\r
-#define PCNT_CH1_POS_MODE_U3_M ((PCNT_CH1_POS_MODE_U3_V)<<(PCNT_CH1_POS_MODE_U3_S))\r
-#define PCNT_CH1_POS_MODE_U3_V 0x3\r
-#define PCNT_CH1_POS_MODE_U3_S 26\r
-/* PCNT_CH1_NEG_MODE_U3 : R/W ;bitpos:[25:24] ;default: 2'd0 ; */\r
-/*description: This register is used to control the mode of channel1's input\r
- negedge signal for unit3. 2'd1: increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden*/\r
-#define PCNT_CH1_NEG_MODE_U3 0x00000003\r
-#define PCNT_CH1_NEG_MODE_U3_M ((PCNT_CH1_NEG_MODE_U3_V)<<(PCNT_CH1_NEG_MODE_U3_S))\r
-#define PCNT_CH1_NEG_MODE_U3_V 0x3\r
-#define PCNT_CH1_NEG_MODE_U3_S 24\r
-/* PCNT_CH0_LCTRL_MODE_U3 : R/W ;bitpos:[23:22] ;default: 2'd0 ; */\r
-/*description: This register is used to control the mode of channel0's low control\r
- signal for unit3. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/\r
-#define PCNT_CH0_LCTRL_MODE_U3 0x00000003\r
-#define PCNT_CH0_LCTRL_MODE_U3_M ((PCNT_CH0_LCTRL_MODE_U3_V)<<(PCNT_CH0_LCTRL_MODE_U3_S))\r
-#define PCNT_CH0_LCTRL_MODE_U3_V 0x3\r
-#define PCNT_CH0_LCTRL_MODE_U3_S 22\r
-/* PCNT_CH0_HCTRL_MODE_U3 : R/W ;bitpos:[21:20] ;default: 2'd0 ; */\r
-/*description: This register is used to control the mode of channel0's high\r
- control signal for unit3. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/\r
-#define PCNT_CH0_HCTRL_MODE_U3 0x00000003\r
-#define PCNT_CH0_HCTRL_MODE_U3_M ((PCNT_CH0_HCTRL_MODE_U3_V)<<(PCNT_CH0_HCTRL_MODE_U3_S))\r
-#define PCNT_CH0_HCTRL_MODE_U3_V 0x3\r
-#define PCNT_CH0_HCTRL_MODE_U3_S 20\r
-/* PCNT_CH0_POS_MODE_U3 : R/W ;bitpos:[19:18] ;default: 2'd0 ; */\r
-/*description: This register is used to control the mode of channel0's input\r
- posedge signal for unit3. 2'd1: increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden*/\r
-#define PCNT_CH0_POS_MODE_U3 0x00000003\r
-#define PCNT_CH0_POS_MODE_U3_M ((PCNT_CH0_POS_MODE_U3_V)<<(PCNT_CH0_POS_MODE_U3_S))\r
-#define PCNT_CH0_POS_MODE_U3_V 0x3\r
-#define PCNT_CH0_POS_MODE_U3_S 18\r
-/* PCNT_CH0_NEG_MODE_U3 : R/W ;bitpos:[17:16] ;default: 2'd0 ; */\r
-/*description: This register is used to control the mode of channel0's input\r
- negedge signal for unit3. 2'd1: increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden*/\r
-#define PCNT_CH0_NEG_MODE_U3 0x00000003\r
-#define PCNT_CH0_NEG_MODE_U3_M ((PCNT_CH0_NEG_MODE_U3_V)<<(PCNT_CH0_NEG_MODE_U3_S))\r
-#define PCNT_CH0_NEG_MODE_U3_V 0x3\r
-#define PCNT_CH0_NEG_MODE_U3_S 16\r
-/* PCNT_THR_THRES1_EN_U3 : R/W ;bitpos:[15] ;default: 1'b0 ; */\r
-/*description: This is the enable bit for comparing unit3's count with thres1 value .*/\r
-#define PCNT_THR_THRES1_EN_U3 (BIT(15))\r
-#define PCNT_THR_THRES1_EN_U3_M (BIT(15))\r
-#define PCNT_THR_THRES1_EN_U3_V 0x1\r
-#define PCNT_THR_THRES1_EN_U3_S 15\r
-/* PCNT_THR_THRES0_EN_U3 : R/W ;bitpos:[14] ;default: 1'b0 ; */\r
-/*description: This is the enable bit for comparing unit3's count with thres0 value.*/\r
-#define PCNT_THR_THRES0_EN_U3 (BIT(14))\r
-#define PCNT_THR_THRES0_EN_U3_M (BIT(14))\r
-#define PCNT_THR_THRES0_EN_U3_V 0x1\r
-#define PCNT_THR_THRES0_EN_U3_S 14\r
-/* PCNT_THR_L_LIM_EN_U3 : R/W ;bitpos:[13] ;default: 1'b1 ; */\r
-/*description: This is the enable bit for comparing unit3's count with thr_l_lim value.*/\r
-#define PCNT_THR_L_LIM_EN_U3 (BIT(13))\r
-#define PCNT_THR_L_LIM_EN_U3_M (BIT(13))\r
-#define PCNT_THR_L_LIM_EN_U3_V 0x1\r
-#define PCNT_THR_L_LIM_EN_U3_S 13\r
-/* PCNT_THR_H_LIM_EN_U3 : R/W ;bitpos:[12] ;default: 1'b1 ; */\r
-/*description: This is the enable bit for comparing unit3's count with thr_h_lim value.*/\r
-#define PCNT_THR_H_LIM_EN_U3 (BIT(12))\r
-#define PCNT_THR_H_LIM_EN_U3_M (BIT(12))\r
-#define PCNT_THR_H_LIM_EN_U3_V 0x1\r
-#define PCNT_THR_H_LIM_EN_U3_S 12\r
-/* PCNT_THR_ZERO_EN_U3 : R/W ;bitpos:[11] ;default: 1'b1 ; */\r
-/*description: This is the enable bit for comparing unit3's count with 0 value.*/\r
-#define PCNT_THR_ZERO_EN_U3 (BIT(11))\r
-#define PCNT_THR_ZERO_EN_U3_M (BIT(11))\r
-#define PCNT_THR_ZERO_EN_U3_V 0x1\r
-#define PCNT_THR_ZERO_EN_U3_S 11\r
-/* PCNT_FILTER_EN_U3 : R/W ;bitpos:[10] ;default: 1'b1 ; */\r
-/*description: This is the enable bit for filtering input signals for unit3.*/\r
-#define PCNT_FILTER_EN_U3 (BIT(10))\r
-#define PCNT_FILTER_EN_U3_M (BIT(10))\r
-#define PCNT_FILTER_EN_U3_V 0x1\r
-#define PCNT_FILTER_EN_U3_S 10\r
-/* PCNT_FILTER_THRES_U3 : R/W ;bitpos:[9:0] ;default: 10'h10 ; */\r
-/*description: This register is used to filter pluse whose width is smaller\r
- than this value for unit3.*/\r
-#define PCNT_FILTER_THRES_U3 0x000003FF\r
-#define PCNT_FILTER_THRES_U3_M ((PCNT_FILTER_THRES_U3_V)<<(PCNT_FILTER_THRES_U3_S))\r
-#define PCNT_FILTER_THRES_U3_V 0x3FF\r
-#define PCNT_FILTER_THRES_U3_S 0\r
-\r
-#define PCNT_U3_CONF1_REG (DR_REG_PCNT_BASE + 0x0028)\r
-/* PCNT_CNT_THRES1_U3 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */\r
-/*description: This register is used to configure thres1 value for unit3.*/\r
-#define PCNT_CNT_THRES1_U3 0x0000FFFF\r
-#define PCNT_CNT_THRES1_U3_M ((PCNT_CNT_THRES1_U3_V)<<(PCNT_CNT_THRES1_U3_S))\r
-#define PCNT_CNT_THRES1_U3_V 0xFFFF\r
-#define PCNT_CNT_THRES1_U3_S 16\r
-/* PCNT_CNT_THRES0_U3 : R/W ;bitpos:[15:0] ;default: 10'h0 ; */\r
-/*description: This register is used to configure thres0 value for unit3.*/\r
-#define PCNT_CNT_THRES0_U3 0x0000FFFF\r
-#define PCNT_CNT_THRES0_U3_M ((PCNT_CNT_THRES0_U3_V)<<(PCNT_CNT_THRES0_U3_S))\r
-#define PCNT_CNT_THRES0_U3_V 0xFFFF\r
-#define PCNT_CNT_THRES0_U3_S 0\r
-\r
-#define PCNT_U3_CONF2_REG (DR_REG_PCNT_BASE + 0x002c)\r
-/* PCNT_CNT_L_LIM_U3 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */\r
-/*description: This register is used to confiugre thr_l_lim value for unit3.*/\r
-#define PCNT_CNT_L_LIM_U3 0x0000FFFF\r
-#define PCNT_CNT_L_LIM_U3_M ((PCNT_CNT_L_LIM_U3_V)<<(PCNT_CNT_L_LIM_U3_S))\r
-#define PCNT_CNT_L_LIM_U3_V 0xFFFF\r
-#define PCNT_CNT_L_LIM_U3_S 16\r
-/* PCNT_CNT_H_LIM_U3 : R/W ;bitpos:[15:0] ;default: 10'h0 ; */\r
-/*description: This register is used to configure thr_h_lim value for unit3.*/\r
-#define PCNT_CNT_H_LIM_U3 0x0000FFFF\r
-#define PCNT_CNT_H_LIM_U3_M ((PCNT_CNT_H_LIM_U3_V)<<(PCNT_CNT_H_LIM_U3_S))\r
-#define PCNT_CNT_H_LIM_U3_V 0xFFFF\r
-#define PCNT_CNT_H_LIM_U3_S 0\r
-\r
-#define PCNT_U4_CONF0_REG (DR_REG_PCNT_BASE + 0x0030)\r
-/* PCNT_CH1_LCTRL_MODE_U4 : R/W ;bitpos:[31:30] ;default: 2'd0 ; */\r
-/*description: This register is used to control the mode of channel1's low control\r
- signal for unit4. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/\r
-#define PCNT_CH1_LCTRL_MODE_U4 0x00000003\r
-#define PCNT_CH1_LCTRL_MODE_U4_M ((PCNT_CH1_LCTRL_MODE_U4_V)<<(PCNT_CH1_LCTRL_MODE_U4_S))\r
-#define PCNT_CH1_LCTRL_MODE_U4_V 0x3\r
-#define PCNT_CH1_LCTRL_MODE_U4_S 30\r
-/* PCNT_CH1_HCTRL_MODE_U4 : R/W ;bitpos:[29:28] ;default: 2'd0 ; */\r
-/*description: This register is used to control the mode of channel1's high\r
- control signal for unit4. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/\r
-#define PCNT_CH1_HCTRL_MODE_U4 0x00000003\r
-#define PCNT_CH1_HCTRL_MODE_U4_M ((PCNT_CH1_HCTRL_MODE_U4_V)<<(PCNT_CH1_HCTRL_MODE_U4_S))\r
-#define PCNT_CH1_HCTRL_MODE_U4_V 0x3\r
-#define PCNT_CH1_HCTRL_MODE_U4_S 28\r
-/* PCNT_CH1_POS_MODE_U4 : R/W ;bitpos:[27:26] ;default: 2'd0 ; */\r
-/*description: This register is used to control the mode of channel1's input\r
- posedge signal for unit4. 2'd1: increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden*/\r
-#define PCNT_CH1_POS_MODE_U4 0x00000003\r
-#define PCNT_CH1_POS_MODE_U4_M ((PCNT_CH1_POS_MODE_U4_V)<<(PCNT_CH1_POS_MODE_U4_S))\r
-#define PCNT_CH1_POS_MODE_U4_V 0x3\r
-#define PCNT_CH1_POS_MODE_U4_S 26\r
-/* PCNT_CH1_NEG_MODE_U4 : R/W ;bitpos:[25:24] ;default: 2'd0 ; */\r
-/*description: This register is used to control the mode of channel1's input\r
- negedge signal for unit4. 2'd1: increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden*/\r
-#define PCNT_CH1_NEG_MODE_U4 0x00000003\r
-#define PCNT_CH1_NEG_MODE_U4_M ((PCNT_CH1_NEG_MODE_U4_V)<<(PCNT_CH1_NEG_MODE_U4_S))\r
-#define PCNT_CH1_NEG_MODE_U4_V 0x3\r
-#define PCNT_CH1_NEG_MODE_U4_S 24\r
-/* PCNT_CH0_LCTRL_MODE_U4 : R/W ;bitpos:[23:22] ;default: 2'd0 ; */\r
-/*description: This register is used to control the mode of channel0's low control\r
- signal for unit4. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/\r
-#define PCNT_CH0_LCTRL_MODE_U4 0x00000003\r
-#define PCNT_CH0_LCTRL_MODE_U4_M ((PCNT_CH0_LCTRL_MODE_U4_V)<<(PCNT_CH0_LCTRL_MODE_U4_S))\r
-#define PCNT_CH0_LCTRL_MODE_U4_V 0x3\r
-#define PCNT_CH0_LCTRL_MODE_U4_S 22\r
-/* PCNT_CH0_HCTRL_MODE_U4 : R/W ;bitpos:[21:20] ;default: 2'd0 ; */\r
-/*description: This register is used to control the mode of channel0's high\r
- control signal for unit4. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/\r
-#define PCNT_CH0_HCTRL_MODE_U4 0x00000003\r
-#define PCNT_CH0_HCTRL_MODE_U4_M ((PCNT_CH0_HCTRL_MODE_U4_V)<<(PCNT_CH0_HCTRL_MODE_U4_S))\r
-#define PCNT_CH0_HCTRL_MODE_U4_V 0x3\r
-#define PCNT_CH0_HCTRL_MODE_U4_S 20\r
-/* PCNT_CH0_POS_MODE_U4 : R/W ;bitpos:[19:18] ;default: 2'd0 ; */\r
-/*description: This register is used to control the mode of channel0's input\r
- posedge signal for unit4. 2'd1: increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden*/\r
-#define PCNT_CH0_POS_MODE_U4 0x00000003\r
-#define PCNT_CH0_POS_MODE_U4_M ((PCNT_CH0_POS_MODE_U4_V)<<(PCNT_CH0_POS_MODE_U4_S))\r
-#define PCNT_CH0_POS_MODE_U4_V 0x3\r
-#define PCNT_CH0_POS_MODE_U4_S 18\r
-/* PCNT_CH0_NEG_MODE_U4 : R/W ;bitpos:[17:16] ;default: 2'd0 ; */\r
-/*description: This register is used to control the mode of channel0's input\r
- negedge signal for unit4. 2'd1: increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden*/\r
-#define PCNT_CH0_NEG_MODE_U4 0x00000003\r
-#define PCNT_CH0_NEG_MODE_U4_M ((PCNT_CH0_NEG_MODE_U4_V)<<(PCNT_CH0_NEG_MODE_U4_S))\r
-#define PCNT_CH0_NEG_MODE_U4_V 0x3\r
-#define PCNT_CH0_NEG_MODE_U4_S 16\r
-/* PCNT_THR_THRES1_EN_U4 : R/W ;bitpos:[15] ;default: 1'b0 ; */\r
-/*description: This is the enable bit for comparing unit4's count with thres1 value .*/\r
-#define PCNT_THR_THRES1_EN_U4 (BIT(15))\r
-#define PCNT_THR_THRES1_EN_U4_M (BIT(15))\r
-#define PCNT_THR_THRES1_EN_U4_V 0x1\r
-#define PCNT_THR_THRES1_EN_U4_S 15\r
-/* PCNT_THR_THRES0_EN_U4 : R/W ;bitpos:[14] ;default: 1'b0 ; */\r
-/*description: This is the enable bit for comparing unit4's count with thres0 value.*/\r
-#define PCNT_THR_THRES0_EN_U4 (BIT(14))\r
-#define PCNT_THR_THRES0_EN_U4_M (BIT(14))\r
-#define PCNT_THR_THRES0_EN_U4_V 0x1\r
-#define PCNT_THR_THRES0_EN_U4_S 14\r
-/* PCNT_THR_L_LIM_EN_U4 : R/W ;bitpos:[13] ;default: 1'b1 ; */\r
-/*description: This is the enable bit for comparing unit4's count with thr_l_lim value.*/\r
-#define PCNT_THR_L_LIM_EN_U4 (BIT(13))\r
-#define PCNT_THR_L_LIM_EN_U4_M (BIT(13))\r
-#define PCNT_THR_L_LIM_EN_U4_V 0x1\r
-#define PCNT_THR_L_LIM_EN_U4_S 13\r
-/* PCNT_THR_H_LIM_EN_U4 : R/W ;bitpos:[12] ;default: 1'b1 ; */\r
-/*description: This is the enable bit for comparing unit4's count with thr_h_lim value.*/\r
-#define PCNT_THR_H_LIM_EN_U4 (BIT(12))\r
-#define PCNT_THR_H_LIM_EN_U4_M (BIT(12))\r
-#define PCNT_THR_H_LIM_EN_U4_V 0x1\r
-#define PCNT_THR_H_LIM_EN_U4_S 12\r
-/* PCNT_THR_ZERO_EN_U4 : R/W ;bitpos:[11] ;default: 1'b1 ; */\r
-/*description: This is the enable bit for comparing unit4's count with 0 value.*/\r
-#define PCNT_THR_ZERO_EN_U4 (BIT(11))\r
-#define PCNT_THR_ZERO_EN_U4_M (BIT(11))\r
-#define PCNT_THR_ZERO_EN_U4_V 0x1\r
-#define PCNT_THR_ZERO_EN_U4_S 11\r
-/* PCNT_FILTER_EN_U4 : R/W ;bitpos:[10] ;default: 1'b1 ; */\r
-/*description: This is the enable bit for filtering input signals for unit4.*/\r
-#define PCNT_FILTER_EN_U4 (BIT(10))\r
-#define PCNT_FILTER_EN_U4_M (BIT(10))\r
-#define PCNT_FILTER_EN_U4_V 0x1\r
-#define PCNT_FILTER_EN_U4_S 10\r
-/* PCNT_FILTER_THRES_U4 : R/W ;bitpos:[9:0] ;default: 10'h10 ; */\r
-/*description: This register is used to filter pluse whose width is smaller\r
- than this value for unit4.*/\r
-#define PCNT_FILTER_THRES_U4 0x000003FF\r
-#define PCNT_FILTER_THRES_U4_M ((PCNT_FILTER_THRES_U4_V)<<(PCNT_FILTER_THRES_U4_S))\r
-#define PCNT_FILTER_THRES_U4_V 0x3FF\r
-#define PCNT_FILTER_THRES_U4_S 0\r
-\r
-#define PCNT_U4_CONF1_REG (DR_REG_PCNT_BASE + 0x0034)\r
-/* PCNT_CNT_THRES1_U4 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */\r
-/*description: This register is used to configure thres1 value for unit4.*/\r
-#define PCNT_CNT_THRES1_U4 0x0000FFFF\r
-#define PCNT_CNT_THRES1_U4_M ((PCNT_CNT_THRES1_U4_V)<<(PCNT_CNT_THRES1_U4_S))\r
-#define PCNT_CNT_THRES1_U4_V 0xFFFF\r
-#define PCNT_CNT_THRES1_U4_S 16\r
-/* PCNT_CNT_THRES0_U4 : R/W ;bitpos:[15:0] ;default: 10'h0 ; */\r
-/*description: This register is used to configure thres0 value for unit4.*/\r
-#define PCNT_CNT_THRES0_U4 0x0000FFFF\r
-#define PCNT_CNT_THRES0_U4_M ((PCNT_CNT_THRES0_U4_V)<<(PCNT_CNT_THRES0_U4_S))\r
-#define PCNT_CNT_THRES0_U4_V 0xFFFF\r
-#define PCNT_CNT_THRES0_U4_S 0\r
-\r
-#define PCNT_U4_CONF2_REG (DR_REG_PCNT_BASE + 0x0038)\r
-/* PCNT_CNT_L_LIM_U4 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */\r
-/*description: This register is used to confiugre thr_l_lim value for unit4.*/\r
-#define PCNT_CNT_L_LIM_U4 0x0000FFFF\r
-#define PCNT_CNT_L_LIM_U4_M ((PCNT_CNT_L_LIM_U4_V)<<(PCNT_CNT_L_LIM_U4_S))\r
-#define PCNT_CNT_L_LIM_U4_V 0xFFFF\r
-#define PCNT_CNT_L_LIM_U4_S 16\r
-/* PCNT_CNT_H_LIM_U4 : R/W ;bitpos:[15:0] ;default: 10'h0 ; */\r
-/*description: This register is used to configure thr_h_lim value for unit4.*/\r
-#define PCNT_CNT_H_LIM_U4 0x0000FFFF\r
-#define PCNT_CNT_H_LIM_U4_M ((PCNT_CNT_H_LIM_U4_V)<<(PCNT_CNT_H_LIM_U4_S))\r
-#define PCNT_CNT_H_LIM_U4_V 0xFFFF\r
-#define PCNT_CNT_H_LIM_U4_S 0\r
-\r
-#define PCNT_U5_CONF0_REG (DR_REG_PCNT_BASE + 0x003c)\r
-/* PCNT_CH1_LCTRL_MODE_U5 : R/W ;bitpos:[31:30] ;default: 2'd0 ; */\r
-/*description: This register is used to control the mode of channel1's low control\r
- signal for unit5. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/\r
-#define PCNT_CH1_LCTRL_MODE_U5 0x00000003\r
-#define PCNT_CH1_LCTRL_MODE_U5_M ((PCNT_CH1_LCTRL_MODE_U5_V)<<(PCNT_CH1_LCTRL_MODE_U5_S))\r
-#define PCNT_CH1_LCTRL_MODE_U5_V 0x3\r
-#define PCNT_CH1_LCTRL_MODE_U5_S 30\r
-/* PCNT_CH1_HCTRL_MODE_U5 : R/W ;bitpos:[29:28] ;default: 2'd0 ; */\r
-/*description: This register is used to control the mode of channel1's high\r
- control signal for unit5. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/\r
-#define PCNT_CH1_HCTRL_MODE_U5 0x00000003\r
-#define PCNT_CH1_HCTRL_MODE_U5_M ((PCNT_CH1_HCTRL_MODE_U5_V)<<(PCNT_CH1_HCTRL_MODE_U5_S))\r
-#define PCNT_CH1_HCTRL_MODE_U5_V 0x3\r
-#define PCNT_CH1_HCTRL_MODE_U5_S 28\r
-/* PCNT_CH1_POS_MODE_U5 : R/W ;bitpos:[27:26] ;default: 2'd0 ; */\r
-/*description: This register is used to control the mode of channel1's input\r
- posedge signal for unit5. 2'd1: increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden*/\r
-#define PCNT_CH1_POS_MODE_U5 0x00000003\r
-#define PCNT_CH1_POS_MODE_U5_M ((PCNT_CH1_POS_MODE_U5_V)<<(PCNT_CH1_POS_MODE_U5_S))\r
-#define PCNT_CH1_POS_MODE_U5_V 0x3\r
-#define PCNT_CH1_POS_MODE_U5_S 26\r
-/* PCNT_CH1_NEG_MODE_U5 : R/W ;bitpos:[25:24] ;default: 2'd0 ; */\r
-/*description: This register is used to control the mode of channel1's input\r
- negedge signal for unit5. 2'd1: increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden*/\r
-#define PCNT_CH1_NEG_MODE_U5 0x00000003\r
-#define PCNT_CH1_NEG_MODE_U5_M ((PCNT_CH1_NEG_MODE_U5_V)<<(PCNT_CH1_NEG_MODE_U5_S))\r
-#define PCNT_CH1_NEG_MODE_U5_V 0x3\r
-#define PCNT_CH1_NEG_MODE_U5_S 24\r
-/* PCNT_CH0_LCTRL_MODE_U5 : R/W ;bitpos:[23:22] ;default: 2'd0 ; */\r
-/*description: This register is used to control the mode of channel0's low control\r
- signal for unit5. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/\r
-#define PCNT_CH0_LCTRL_MODE_U5 0x00000003\r
-#define PCNT_CH0_LCTRL_MODE_U5_M ((PCNT_CH0_LCTRL_MODE_U5_V)<<(PCNT_CH0_LCTRL_MODE_U5_S))\r
-#define PCNT_CH0_LCTRL_MODE_U5_V 0x3\r
-#define PCNT_CH0_LCTRL_MODE_U5_S 22\r
-/* PCNT_CH0_HCTRL_MODE_U5 : R/W ;bitpos:[21:20] ;default: 2'd0 ; */\r
-/*description: This register is used to control the mode of channel0's high\r
- control signal for unit5. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/\r
-#define PCNT_CH0_HCTRL_MODE_U5 0x00000003\r
-#define PCNT_CH0_HCTRL_MODE_U5_M ((PCNT_CH0_HCTRL_MODE_U5_V)<<(PCNT_CH0_HCTRL_MODE_U5_S))\r
-#define PCNT_CH0_HCTRL_MODE_U5_V 0x3\r
-#define PCNT_CH0_HCTRL_MODE_U5_S 20\r
-/* PCNT_CH0_POS_MODE_U5 : R/W ;bitpos:[19:18] ;default: 2'd0 ; */\r
-/*description: This register is used to control the mode of channel0's input\r
- posedge signal for unit5. 2'd1: increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden*/\r
-#define PCNT_CH0_POS_MODE_U5 0x00000003\r
-#define PCNT_CH0_POS_MODE_U5_M ((PCNT_CH0_POS_MODE_U5_V)<<(PCNT_CH0_POS_MODE_U5_S))\r
-#define PCNT_CH0_POS_MODE_U5_V 0x3\r
-#define PCNT_CH0_POS_MODE_U5_S 18\r
-/* PCNT_CH0_NEG_MODE_U5 : R/W ;bitpos:[17:16] ;default: 2'd0 ; */\r
-/*description: This register is used to control the mode of channel0's input\r
- negedge signal for unit5. 2'd1: increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden*/\r
-#define PCNT_CH0_NEG_MODE_U5 0x00000003\r
-#define PCNT_CH0_NEG_MODE_U5_M ((PCNT_CH0_NEG_MODE_U5_V)<<(PCNT_CH0_NEG_MODE_U5_S))\r
-#define PCNT_CH0_NEG_MODE_U5_V 0x3\r
-#define PCNT_CH0_NEG_MODE_U5_S 16\r
-/* PCNT_THR_THRES1_EN_U5 : R/W ;bitpos:[15] ;default: 1'b0 ; */\r
-/*description: This is the enable bit for comparing unit5's count with thres1 value .*/\r
-#define PCNT_THR_THRES1_EN_U5 (BIT(15))\r
-#define PCNT_THR_THRES1_EN_U5_M (BIT(15))\r
-#define PCNT_THR_THRES1_EN_U5_V 0x1\r
-#define PCNT_THR_THRES1_EN_U5_S 15\r
-/* PCNT_THR_THRES0_EN_U5 : R/W ;bitpos:[14] ;default: 1'b0 ; */\r
-/*description: This is the enable bit for comparing unit5's count with thres0 value.*/\r
-#define PCNT_THR_THRES0_EN_U5 (BIT(14))\r
-#define PCNT_THR_THRES0_EN_U5_M (BIT(14))\r
-#define PCNT_THR_THRES0_EN_U5_V 0x1\r
-#define PCNT_THR_THRES0_EN_U5_S 14\r
-/* PCNT_THR_L_LIM_EN_U5 : R/W ;bitpos:[13] ;default: 1'b1 ; */\r
-/*description: This is the enable bit for comparing unit5's count with thr_l_lim value.*/\r
-#define PCNT_THR_L_LIM_EN_U5 (BIT(13))\r
-#define PCNT_THR_L_LIM_EN_U5_M (BIT(13))\r
-#define PCNT_THR_L_LIM_EN_U5_V 0x1\r
-#define PCNT_THR_L_LIM_EN_U5_S 13\r
-/* PCNT_THR_H_LIM_EN_U5 : R/W ;bitpos:[12] ;default: 1'b1 ; */\r
-/*description: This is the enable bit for comparing unit5's count with thr_h_lim value.*/\r
-#define PCNT_THR_H_LIM_EN_U5 (BIT(12))\r
-#define PCNT_THR_H_LIM_EN_U5_M (BIT(12))\r
-#define PCNT_THR_H_LIM_EN_U5_V 0x1\r
-#define PCNT_THR_H_LIM_EN_U5_S 12\r
-/* PCNT_THR_ZERO_EN_U5 : R/W ;bitpos:[11] ;default: 1'b1 ; */\r
-/*description: This is the enable bit for comparing unit5's count with 0 value.*/\r
-#define PCNT_THR_ZERO_EN_U5 (BIT(11))\r
-#define PCNT_THR_ZERO_EN_U5_M (BIT(11))\r
-#define PCNT_THR_ZERO_EN_U5_V 0x1\r
-#define PCNT_THR_ZERO_EN_U5_S 11\r
-/* PCNT_FILTER_EN_U5 : R/W ;bitpos:[10] ;default: 1'b1 ; */\r
-/*description: This is the enable bit for filtering input signals for unit5.*/\r
-#define PCNT_FILTER_EN_U5 (BIT(10))\r
-#define PCNT_FILTER_EN_U5_M (BIT(10))\r
-#define PCNT_FILTER_EN_U5_V 0x1\r
-#define PCNT_FILTER_EN_U5_S 10\r
-/* PCNT_FILTER_THRES_U5 : R/W ;bitpos:[9:0] ;default: 10'h10 ; */\r
-/*description: This register is used to filter pluse whose width is smaller\r
- than this value for unit5.*/\r
-#define PCNT_FILTER_THRES_U5 0x000003FF\r
-#define PCNT_FILTER_THRES_U5_M ((PCNT_FILTER_THRES_U5_V)<<(PCNT_FILTER_THRES_U5_S))\r
-#define PCNT_FILTER_THRES_U5_V 0x3FF\r
-#define PCNT_FILTER_THRES_U5_S 0\r
-\r
-#define PCNT_U5_CONF1_REG (DR_REG_PCNT_BASE + 0x0040)\r
-/* PCNT_CNT_THRES1_U5 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */\r
-/*description: This register is used to configure thres1 value for unit5.*/\r
-#define PCNT_CNT_THRES1_U5 0x0000FFFF\r
-#define PCNT_CNT_THRES1_U5_M ((PCNT_CNT_THRES1_U5_V)<<(PCNT_CNT_THRES1_U5_S))\r
-#define PCNT_CNT_THRES1_U5_V 0xFFFF\r
-#define PCNT_CNT_THRES1_U5_S 16\r
-/* PCNT_CNT_THRES0_U5 : R/W ;bitpos:[15:0] ;default: 10'h0 ; */\r
-/*description: This register is used to configure thres0 value for unit5.*/\r
-#define PCNT_CNT_THRES0_U5 0x0000FFFF\r
-#define PCNT_CNT_THRES0_U5_M ((PCNT_CNT_THRES0_U5_V)<<(PCNT_CNT_THRES0_U5_S))\r
-#define PCNT_CNT_THRES0_U5_V 0xFFFF\r
-#define PCNT_CNT_THRES0_U5_S 0\r
-\r
-#define PCNT_U5_CONF2_REG (DR_REG_PCNT_BASE + 0x0044)\r
-/* PCNT_CNT_L_LIM_U5 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */\r
-/*description: This register is used to confiugre thr_l_lim value for unit5.*/\r
-#define PCNT_CNT_L_LIM_U5 0x0000FFFF\r
-#define PCNT_CNT_L_LIM_U5_M ((PCNT_CNT_L_LIM_U5_V)<<(PCNT_CNT_L_LIM_U5_S))\r
-#define PCNT_CNT_L_LIM_U5_V 0xFFFF\r
-#define PCNT_CNT_L_LIM_U5_S 16\r
-/* PCNT_CNT_H_LIM_U5 : R/W ;bitpos:[15:0] ;default: 10'h0 ; */\r
-/*description: This register is used to configure thr_h_lim value for unit5.*/\r
-#define PCNT_CNT_H_LIM_U5 0x0000FFFF\r
-#define PCNT_CNT_H_LIM_U5_M ((PCNT_CNT_H_LIM_U5_V)<<(PCNT_CNT_H_LIM_U5_S))\r
-#define PCNT_CNT_H_LIM_U5_V 0xFFFF\r
-#define PCNT_CNT_H_LIM_U5_S 0\r
-\r
-#define PCNT_U6_CONF0_REG (DR_REG_PCNT_BASE + 0x0048)\r
-/* PCNT_CH1_LCTRL_MODE_U6 : R/W ;bitpos:[31:30] ;default: 2'd0 ; */\r
-/*description: This register is used to control the mode of channel1's low control\r
- signal for unit6. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/\r
-#define PCNT_CH1_LCTRL_MODE_U6 0x00000003\r
-#define PCNT_CH1_LCTRL_MODE_U6_M ((PCNT_CH1_LCTRL_MODE_U6_V)<<(PCNT_CH1_LCTRL_MODE_U6_S))\r
-#define PCNT_CH1_LCTRL_MODE_U6_V 0x3\r
-#define PCNT_CH1_LCTRL_MODE_U6_S 30\r
-/* PCNT_CH1_HCTRL_MODE_U6 : R/W ;bitpos:[29:28] ;default: 2'd0 ; */\r
-/*description: This register is used to control the mode of channel1's high\r
- control signal for unit6. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/\r
-#define PCNT_CH1_HCTRL_MODE_U6 0x00000003\r
-#define PCNT_CH1_HCTRL_MODE_U6_M ((PCNT_CH1_HCTRL_MODE_U6_V)<<(PCNT_CH1_HCTRL_MODE_U6_S))\r
-#define PCNT_CH1_HCTRL_MODE_U6_V 0x3\r
-#define PCNT_CH1_HCTRL_MODE_U6_S 28\r
-/* PCNT_CH1_POS_MODE_U6 : R/W ;bitpos:[27:26] ;default: 2'd0 ; */\r
-/*description: This register is used to control the mode of channel1's input\r
- posedge signal for unit6. 2'd1: increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden*/\r
-#define PCNT_CH1_POS_MODE_U6 0x00000003\r
-#define PCNT_CH1_POS_MODE_U6_M ((PCNT_CH1_POS_MODE_U6_V)<<(PCNT_CH1_POS_MODE_U6_S))\r
-#define PCNT_CH1_POS_MODE_U6_V 0x3\r
-#define PCNT_CH1_POS_MODE_U6_S 26\r
-/* PCNT_CH1_NEG_MODE_U6 : R/W ;bitpos:[25:24] ;default: 2'd0 ; */\r
-/*description: This register is used to control the mode of channel1's input\r
- negedge signal for unit6. 2'd1: increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden*/\r
-#define PCNT_CH1_NEG_MODE_U6 0x00000003\r
-#define PCNT_CH1_NEG_MODE_U6_M ((PCNT_CH1_NEG_MODE_U6_V)<<(PCNT_CH1_NEG_MODE_U6_S))\r
-#define PCNT_CH1_NEG_MODE_U6_V 0x3\r
-#define PCNT_CH1_NEG_MODE_U6_S 24\r
-/* PCNT_CH0_LCTRL_MODE_U6 : R/W ;bitpos:[23:22] ;default: 2'd0 ; */\r
-/*description: This register is used to control the mode of channel0's low control\r
- signal for unit6. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/\r
-#define PCNT_CH0_LCTRL_MODE_U6 0x00000003\r
-#define PCNT_CH0_LCTRL_MODE_U6_M ((PCNT_CH0_LCTRL_MODE_U6_V)<<(PCNT_CH0_LCTRL_MODE_U6_S))\r
-#define PCNT_CH0_LCTRL_MODE_U6_V 0x3\r
-#define PCNT_CH0_LCTRL_MODE_U6_S 22\r
-/* PCNT_CH0_HCTRL_MODE_U6 : R/W ;bitpos:[21:20] ;default: 2'd0 ; */\r
-/*description: This register is used to control the mode of channel0's high\r
- control signal for unit6. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/\r
-#define PCNT_CH0_HCTRL_MODE_U6 0x00000003\r
-#define PCNT_CH0_HCTRL_MODE_U6_M ((PCNT_CH0_HCTRL_MODE_U6_V)<<(PCNT_CH0_HCTRL_MODE_U6_S))\r
-#define PCNT_CH0_HCTRL_MODE_U6_V 0x3\r
-#define PCNT_CH0_HCTRL_MODE_U6_S 20\r
-/* PCNT_CH0_POS_MODE_U6 : R/W ;bitpos:[19:18] ;default: 2'd0 ; */\r
-/*description: This register is used to control the mode of channel0's input\r
- posedge signal for unit6. 2'd1: increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden*/\r
-#define PCNT_CH0_POS_MODE_U6 0x00000003\r
-#define PCNT_CH0_POS_MODE_U6_M ((PCNT_CH0_POS_MODE_U6_V)<<(PCNT_CH0_POS_MODE_U6_S))\r
-#define PCNT_CH0_POS_MODE_U6_V 0x3\r
-#define PCNT_CH0_POS_MODE_U6_S 18\r
-/* PCNT_CH0_NEG_MODE_U6 : R/W ;bitpos:[17:16] ;default: 2'd0 ; */\r
-/*description: This register is used to control the mode of channel0's input\r
- negedge signal for unit6. 2'd1: increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden*/\r
-#define PCNT_CH0_NEG_MODE_U6 0x00000003\r
-#define PCNT_CH0_NEG_MODE_U6_M ((PCNT_CH0_NEG_MODE_U6_V)<<(PCNT_CH0_NEG_MODE_U6_S))\r
-#define PCNT_CH0_NEG_MODE_U6_V 0x3\r
-#define PCNT_CH0_NEG_MODE_U6_S 16\r
-/* PCNT_THR_THRES1_EN_U6 : R/W ;bitpos:[15] ;default: 1'b0 ; */\r
-/*description: This is the enable bit for comparing unit6's count with thres1 value .*/\r
-#define PCNT_THR_THRES1_EN_U6 (BIT(15))\r
-#define PCNT_THR_THRES1_EN_U6_M (BIT(15))\r
-#define PCNT_THR_THRES1_EN_U6_V 0x1\r
-#define PCNT_THR_THRES1_EN_U6_S 15\r
-/* PCNT_THR_THRES0_EN_U6 : R/W ;bitpos:[14] ;default: 1'b0 ; */\r
-/*description: This is the enable bit for comparing unit6's count with thres0 value.*/\r
-#define PCNT_THR_THRES0_EN_U6 (BIT(14))\r
-#define PCNT_THR_THRES0_EN_U6_M (BIT(14))\r
-#define PCNT_THR_THRES0_EN_U6_V 0x1\r
-#define PCNT_THR_THRES0_EN_U6_S 14\r
-/* PCNT_THR_L_LIM_EN_U6 : R/W ;bitpos:[13] ;default: 1'b1 ; */\r
-/*description: This is the enable bit for comparing unit6's count with thr_l_lim value.*/\r
-#define PCNT_THR_L_LIM_EN_U6 (BIT(13))\r
-#define PCNT_THR_L_LIM_EN_U6_M (BIT(13))\r
-#define PCNT_THR_L_LIM_EN_U6_V 0x1\r
-#define PCNT_THR_L_LIM_EN_U6_S 13\r
-/* PCNT_THR_H_LIM_EN_U6 : R/W ;bitpos:[12] ;default: 1'b1 ; */\r
-/*description: This is the enable bit for comparing unit6's count with thr_h_lim value.*/\r
-#define PCNT_THR_H_LIM_EN_U6 (BIT(12))\r
-#define PCNT_THR_H_LIM_EN_U6_M (BIT(12))\r
-#define PCNT_THR_H_LIM_EN_U6_V 0x1\r
-#define PCNT_THR_H_LIM_EN_U6_S 12\r
-/* PCNT_THR_ZERO_EN_U6 : R/W ;bitpos:[11] ;default: 1'b1 ; */\r
-/*description: This is the enable bit for comparing unit6's count with 0 value.*/\r
-#define PCNT_THR_ZERO_EN_U6 (BIT(11))\r
-#define PCNT_THR_ZERO_EN_U6_M (BIT(11))\r
-#define PCNT_THR_ZERO_EN_U6_V 0x1\r
-#define PCNT_THR_ZERO_EN_U6_S 11\r
-/* PCNT_FILTER_EN_U6 : R/W ;bitpos:[10] ;default: 1'b1 ; */\r
-/*description: This is the enable bit for filtering input signals for unit6.*/\r
-#define PCNT_FILTER_EN_U6 (BIT(10))\r
-#define PCNT_FILTER_EN_U6_M (BIT(10))\r
-#define PCNT_FILTER_EN_U6_V 0x1\r
-#define PCNT_FILTER_EN_U6_S 10\r
-/* PCNT_FILTER_THRES_U6 : R/W ;bitpos:[9:0] ;default: 10'h10 ; */\r
-/*description: This register is used to filter pluse whose width is smaller\r
- than this value for unit6.*/\r
-#define PCNT_FILTER_THRES_U6 0x000003FF\r
-#define PCNT_FILTER_THRES_U6_M ((PCNT_FILTER_THRES_U6_V)<<(PCNT_FILTER_THRES_U6_S))\r
-#define PCNT_FILTER_THRES_U6_V 0x3FF\r
-#define PCNT_FILTER_THRES_U6_S 0\r
-\r
-#define PCNT_U6_CONF1_REG (DR_REG_PCNT_BASE + 0x004c)\r
-/* PCNT_CNT_THRES1_U6 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */\r
-/*description: This register is used to configure thres1 value for unit6.*/\r
-#define PCNT_CNT_THRES1_U6 0x0000FFFF\r
-#define PCNT_CNT_THRES1_U6_M ((PCNT_CNT_THRES1_U6_V)<<(PCNT_CNT_THRES1_U6_S))\r
-#define PCNT_CNT_THRES1_U6_V 0xFFFF\r
-#define PCNT_CNT_THRES1_U6_S 16\r
-/* PCNT_CNT_THRES0_U6 : R/W ;bitpos:[15:0] ;default: 10'h0 ; */\r
-/*description: This register is used to configure thres0 value for unit6.*/\r
-#define PCNT_CNT_THRES0_U6 0x0000FFFF\r
-#define PCNT_CNT_THRES0_U6_M ((PCNT_CNT_THRES0_U6_V)<<(PCNT_CNT_THRES0_U6_S))\r
-#define PCNT_CNT_THRES0_U6_V 0xFFFF\r
-#define PCNT_CNT_THRES0_U6_S 0\r
-\r
-#define PCNT_U6_CONF2_REG (DR_REG_PCNT_BASE + 0x0050)\r
-/* PCNT_CNT_L_LIM_U6 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */\r
-/*description: This register is used to confiugre thr_l_lim value for unit6.*/\r
-#define PCNT_CNT_L_LIM_U6 0x0000FFFF\r
-#define PCNT_CNT_L_LIM_U6_M ((PCNT_CNT_L_LIM_U6_V)<<(PCNT_CNT_L_LIM_U6_S))\r
-#define PCNT_CNT_L_LIM_U6_V 0xFFFF\r
-#define PCNT_CNT_L_LIM_U6_S 16\r
-/* PCNT_CNT_H_LIM_U6 : R/W ;bitpos:[15:0] ;default: 10'h0 ; */\r
-/*description: This register is used to configure thr_h_lim value for unit6.*/\r
-#define PCNT_CNT_H_LIM_U6 0x0000FFFF\r
-#define PCNT_CNT_H_LIM_U6_M ((PCNT_CNT_H_LIM_U6_V)<<(PCNT_CNT_H_LIM_U6_S))\r
-#define PCNT_CNT_H_LIM_U6_V 0xFFFF\r
-#define PCNT_CNT_H_LIM_U6_S 0\r
-\r
-#define PCNT_U7_CONF0_REG (DR_REG_PCNT_BASE + 0x0054)\r
-/* PCNT_CH1_LCTRL_MODE_U7 : R/W ;bitpos:[31:30] ;default: 2'd0 ; */\r
-/*description: This register is used to control the mode of channel1's low control\r
- signal for unit7. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/\r
-#define PCNT_CH1_LCTRL_MODE_U7 0x00000003\r
-#define PCNT_CH1_LCTRL_MODE_U7_M ((PCNT_CH1_LCTRL_MODE_U7_V)<<(PCNT_CH1_LCTRL_MODE_U7_S))\r
-#define PCNT_CH1_LCTRL_MODE_U7_V 0x3\r
-#define PCNT_CH1_LCTRL_MODE_U7_S 30\r
-/* PCNT_CH1_HCTRL_MODE_U7 : R/W ;bitpos:[29:28] ;default: 2'd0 ; */\r
-/*description: This register is used to control the mode of channel1's high\r
- control signal for unit7. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/\r
-#define PCNT_CH1_HCTRL_MODE_U7 0x00000003\r
-#define PCNT_CH1_HCTRL_MODE_U7_M ((PCNT_CH1_HCTRL_MODE_U7_V)<<(PCNT_CH1_HCTRL_MODE_U7_S))\r
-#define PCNT_CH1_HCTRL_MODE_U7_V 0x3\r
-#define PCNT_CH1_HCTRL_MODE_U7_S 28\r
-/* PCNT_CH1_POS_MODE_U7 : R/W ;bitpos:[27:26] ;default: 2'd0 ; */\r
-/*description: This register is used to control the mode of channel1's input\r
- posedge signal for unit7. 2'd1: increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden*/\r
-#define PCNT_CH1_POS_MODE_U7 0x00000003\r
-#define PCNT_CH1_POS_MODE_U7_M ((PCNT_CH1_POS_MODE_U7_V)<<(PCNT_CH1_POS_MODE_U7_S))\r
-#define PCNT_CH1_POS_MODE_U7_V 0x3\r
-#define PCNT_CH1_POS_MODE_U7_S 26\r
-/* PCNT_CH1_NEG_MODE_U7 : R/W ;bitpos:[25:24] ;default: 2'd0 ; */\r
-/*description: This register is used to control the mode of channel1's input\r
- negedge signal for unit7. 2'd1: increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden*/\r
-#define PCNT_CH1_NEG_MODE_U7 0x00000003\r
-#define PCNT_CH1_NEG_MODE_U7_M ((PCNT_CH1_NEG_MODE_U7_V)<<(PCNT_CH1_NEG_MODE_U7_S))\r
-#define PCNT_CH1_NEG_MODE_U7_V 0x3\r
-#define PCNT_CH1_NEG_MODE_U7_S 24\r
-/* PCNT_CH0_LCTRL_MODE_U7 : R/W ;bitpos:[23:22] ;default: 2'd0 ; */\r
-/*description: This register is used to control the mode of channel0's low control\r
- signal for unit7. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/\r
-#define PCNT_CH0_LCTRL_MODE_U7 0x00000003\r
-#define PCNT_CH0_LCTRL_MODE_U7_M ((PCNT_CH0_LCTRL_MODE_U7_V)<<(PCNT_CH0_LCTRL_MODE_U7_S))\r
-#define PCNT_CH0_LCTRL_MODE_U7_V 0x3\r
-#define PCNT_CH0_LCTRL_MODE_U7_S 22\r
-/* PCNT_CH0_HCTRL_MODE_U7 : R/W ;bitpos:[21:20] ;default: 2'd0 ; */\r
-/*description: This register is used to control the mode of channel0's high\r
- control signal for unit7. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/\r
-#define PCNT_CH0_HCTRL_MODE_U7 0x00000003\r
-#define PCNT_CH0_HCTRL_MODE_U7_M ((PCNT_CH0_HCTRL_MODE_U7_V)<<(PCNT_CH0_HCTRL_MODE_U7_S))\r
-#define PCNT_CH0_HCTRL_MODE_U7_V 0x3\r
-#define PCNT_CH0_HCTRL_MODE_U7_S 20\r
-/* PCNT_CH0_POS_MODE_U7 : R/W ;bitpos:[19:18] ;default: 2'd0 ; */\r
-/*description: This register is used to control the mode of channel0's input\r
- posedge signal for unit7. 2'd1: increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden*/\r
-#define PCNT_CH0_POS_MODE_U7 0x00000003\r
-#define PCNT_CH0_POS_MODE_U7_M ((PCNT_CH0_POS_MODE_U7_V)<<(PCNT_CH0_POS_MODE_U7_S))\r
-#define PCNT_CH0_POS_MODE_U7_V 0x3\r
-#define PCNT_CH0_POS_MODE_U7_S 18\r
-/* PCNT_CH0_NEG_MODE_U7 : R/W ;bitpos:[17:16] ;default: 2'd0 ; */\r
-/*description: This register is used to control the mode of channel0's input\r
- negedge signal for unit7. 2'd1: increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden*/\r
-#define PCNT_CH0_NEG_MODE_U7 0x00000003\r
-#define PCNT_CH0_NEG_MODE_U7_M ((PCNT_CH0_NEG_MODE_U7_V)<<(PCNT_CH0_NEG_MODE_U7_S))\r
-#define PCNT_CH0_NEG_MODE_U7_V 0x3\r
-#define PCNT_CH0_NEG_MODE_U7_S 16\r
-/* PCNT_THR_THRES1_EN_U7 : R/W ;bitpos:[15] ;default: 1'b0 ; */\r
-/*description: This is the enable bit for comparing unit7's count with thres1 value .*/\r
-#define PCNT_THR_THRES1_EN_U7 (BIT(15))\r
-#define PCNT_THR_THRES1_EN_U7_M (BIT(15))\r
-#define PCNT_THR_THRES1_EN_U7_V 0x1\r
-#define PCNT_THR_THRES1_EN_U7_S 15\r
-/* PCNT_THR_THRES0_EN_U7 : R/W ;bitpos:[14] ;default: 1'b0 ; */\r
-/*description: This is the enable bit for comparing unit7's count with thres0 value.*/\r
-#define PCNT_THR_THRES0_EN_U7 (BIT(14))\r
-#define PCNT_THR_THRES0_EN_U7_M (BIT(14))\r
-#define PCNT_THR_THRES0_EN_U7_V 0x1\r
-#define PCNT_THR_THRES0_EN_U7_S 14\r
-/* PCNT_THR_L_LIM_EN_U7 : R/W ;bitpos:[13] ;default: 1'b1 ; */\r
-/*description: This is the enable bit for comparing unit7's count with thr_l_lim value.*/\r
-#define PCNT_THR_L_LIM_EN_U7 (BIT(13))\r
-#define PCNT_THR_L_LIM_EN_U7_M (BIT(13))\r
-#define PCNT_THR_L_LIM_EN_U7_V 0x1\r
-#define PCNT_THR_L_LIM_EN_U7_S 13\r
-/* PCNT_THR_H_LIM_EN_U7 : R/W ;bitpos:[12] ;default: 1'b1 ; */\r
-/*description: This is the enable bit for comparing unit7's count with thr_h_lim value.*/\r
-#define PCNT_THR_H_LIM_EN_U7 (BIT(12))\r
-#define PCNT_THR_H_LIM_EN_U7_M (BIT(12))\r
-#define PCNT_THR_H_LIM_EN_U7_V 0x1\r
-#define PCNT_THR_H_LIM_EN_U7_S 12\r
-/* PCNT_THR_ZERO_EN_U7 : R/W ;bitpos:[11] ;default: 1'b1 ; */\r
-/*description: This is the enable bit for comparing unit7's count with 0 value.*/\r
-#define PCNT_THR_ZERO_EN_U7 (BIT(11))\r
-#define PCNT_THR_ZERO_EN_U7_M (BIT(11))\r
-#define PCNT_THR_ZERO_EN_U7_V 0x1\r
-#define PCNT_THR_ZERO_EN_U7_S 11\r
-/* PCNT_FILTER_EN_U7 : R/W ;bitpos:[10] ;default: 1'b1 ; */\r
-/*description: This is the enable bit for filtering input signals for unit7.*/\r
-#define PCNT_FILTER_EN_U7 (BIT(10))\r
-#define PCNT_FILTER_EN_U7_M (BIT(10))\r
-#define PCNT_FILTER_EN_U7_V 0x1\r
-#define PCNT_FILTER_EN_U7_S 10\r
-/* PCNT_FILTER_THRES_U7 : R/W ;bitpos:[9:0] ;default: 10'h10 ; */\r
-/*description: This register is used to filter pluse whose width is smaller\r
- than this value for unit7.*/\r
-#define PCNT_FILTER_THRES_U7 0x000003FF\r
-#define PCNT_FILTER_THRES_U7_M ((PCNT_FILTER_THRES_U7_V)<<(PCNT_FILTER_THRES_U7_S))\r
-#define PCNT_FILTER_THRES_U7_V 0x3FF\r
-#define PCNT_FILTER_THRES_U7_S 0\r
-\r
-#define PCNT_U7_CONF1_REG (DR_REG_PCNT_BASE + 0x0058)\r
-/* PCNT_CNT_THRES1_U7 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */\r
-/*description: This register is used to configure thres1 value for unit7.*/\r
-#define PCNT_CNT_THRES1_U7 0x0000FFFF\r
-#define PCNT_CNT_THRES1_U7_M ((PCNT_CNT_THRES1_U7_V)<<(PCNT_CNT_THRES1_U7_S))\r
-#define PCNT_CNT_THRES1_U7_V 0xFFFF\r
-#define PCNT_CNT_THRES1_U7_S 16\r
-/* PCNT_CNT_THRES0_U7 : R/W ;bitpos:[15:0] ;default: 10'h0 ; */\r
-/*description: This register is used to configure thres0 value for unit7.*/\r
-#define PCNT_CNT_THRES0_U7 0x0000FFFF\r
-#define PCNT_CNT_THRES0_U7_M ((PCNT_CNT_THRES0_U7_V)<<(PCNT_CNT_THRES0_U7_S))\r
-#define PCNT_CNT_THRES0_U7_V 0xFFFF\r
-#define PCNT_CNT_THRES0_U7_S 0\r
-\r
-#define PCNT_U7_CONF2_REG (DR_REG_PCNT_BASE + 0x005c)\r
-/* PCNT_CNT_L_LIM_U7 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */\r
-/*description: This register is used to confiugre thr_l_lim value for unit7.*/\r
-#define PCNT_CNT_L_LIM_U7 0x0000FFFF\r
-#define PCNT_CNT_L_LIM_U7_M ((PCNT_CNT_L_LIM_U7_V)<<(PCNT_CNT_L_LIM_U7_S))\r
-#define PCNT_CNT_L_LIM_U7_V 0xFFFF\r
-#define PCNT_CNT_L_LIM_U7_S 16\r
-/* PCNT_CNT_H_LIM_U7 : R/W ;bitpos:[15:0] ;default: 10'h0 ; */\r
-/*description: This register is used to configure thr_h_lim value for unit7.*/\r
-#define PCNT_CNT_H_LIM_U7 0x0000FFFF\r
-#define PCNT_CNT_H_LIM_U7_M ((PCNT_CNT_H_LIM_U7_V)<<(PCNT_CNT_H_LIM_U7_S))\r
-#define PCNT_CNT_H_LIM_U7_V 0xFFFF\r
-#define PCNT_CNT_H_LIM_U7_S 0\r
-\r
-#define PCNT_U0_CNT_REG (DR_REG_PCNT_BASE + 0x0060)\r
-/* PCNT_PLUS_CNT_U0 : RO ;bitpos:[15:0] ;default: 16'h0 ; */\r
-/*description: This register stores the current pulse count value for unit0.*/\r
-#define PCNT_PLUS_CNT_U0 0x0000FFFF\r
-#define PCNT_PLUS_CNT_U0_M ((PCNT_PLUS_CNT_U0_V)<<(PCNT_PLUS_CNT_U0_S))\r
-#define PCNT_PLUS_CNT_U0_V 0xFFFF\r
-#define PCNT_PLUS_CNT_U0_S 0\r
-\r
-#define PCNT_U1_CNT_REG (DR_REG_PCNT_BASE + 0x0064)\r
-/* PCNT_PLUS_CNT_U1 : RO ;bitpos:[15:0] ;default: 16'h0 ; */\r
-/*description: This register stores the current pulse count value for unit1.*/\r
-#define PCNT_PLUS_CNT_U1 0x0000FFFF\r
-#define PCNT_PLUS_CNT_U1_M ((PCNT_PLUS_CNT_U1_V)<<(PCNT_PLUS_CNT_U1_S))\r
-#define PCNT_PLUS_CNT_U1_V 0xFFFF\r
-#define PCNT_PLUS_CNT_U1_S 0\r
-\r
-#define PCNT_U2_CNT_REG (DR_REG_PCNT_BASE + 0x0068)\r
-/* PCNT_PLUS_CNT_U2 : RO ;bitpos:[15:0] ;default: 16'h0 ; */\r
-/*description: This register stores the current pulse count value for unit2.*/\r
-#define PCNT_PLUS_CNT_U2 0x0000FFFF\r
-#define PCNT_PLUS_CNT_U2_M ((PCNT_PLUS_CNT_U2_V)<<(PCNT_PLUS_CNT_U2_S))\r
-#define PCNT_PLUS_CNT_U2_V 0xFFFF\r
-#define PCNT_PLUS_CNT_U2_S 0\r
-\r
-#define PCNT_U3_CNT_REG (DR_REG_PCNT_BASE + 0x006c)\r
-/* PCNT_PLUS_CNT_U3 : RO ;bitpos:[15:0] ;default: 16'h0 ; */\r
-/*description: This register stores the current pulse count value for unit3.*/\r
-#define PCNT_PLUS_CNT_U3 0x0000FFFF\r
-#define PCNT_PLUS_CNT_U3_M ((PCNT_PLUS_CNT_U3_V)<<(PCNT_PLUS_CNT_U3_S))\r
-#define PCNT_PLUS_CNT_U3_V 0xFFFF\r
-#define PCNT_PLUS_CNT_U3_S 0\r
-\r
-#define PCNT_U4_CNT_REG (DR_REG_PCNT_BASE + 0x0070)\r
-/* PCNT_PLUS_CNT_U4 : RO ;bitpos:[15:0] ;default: 16'h0 ; */\r
-/*description: This register stores the current pulse count value for unit4.*/\r
-#define PCNT_PLUS_CNT_U4 0x0000FFFF\r
-#define PCNT_PLUS_CNT_U4_M ((PCNT_PLUS_CNT_U4_V)<<(PCNT_PLUS_CNT_U4_S))\r
-#define PCNT_PLUS_CNT_U4_V 0xFFFF\r
-#define PCNT_PLUS_CNT_U4_S 0\r
-\r
-#define PCNT_U5_CNT_REG (DR_REG_PCNT_BASE + 0x0074)\r
-/* PCNT_PLUS_CNT_U5 : RO ;bitpos:[15:0] ;default: 16'h0 ; */\r
-/*description: This register stores the current pulse count value for unit5.*/\r
-#define PCNT_PLUS_CNT_U5 0x0000FFFF\r
-#define PCNT_PLUS_CNT_U5_M ((PCNT_PLUS_CNT_U5_V)<<(PCNT_PLUS_CNT_U5_S))\r
-#define PCNT_PLUS_CNT_U5_V 0xFFFF\r
-#define PCNT_PLUS_CNT_U5_S 0\r
-\r
-#define PCNT_U6_CNT_REG (DR_REG_PCNT_BASE + 0x0078)\r
-/* PCNT_PLUS_CNT_U6 : RO ;bitpos:[15:0] ;default: 16'h0 ; */\r
-/*description: This register stores the current pulse count value for unit6.*/\r
-#define PCNT_PLUS_CNT_U6 0x0000FFFF\r
-#define PCNT_PLUS_CNT_U6_M ((PCNT_PLUS_CNT_U6_V)<<(PCNT_PLUS_CNT_U6_S))\r
-#define PCNT_PLUS_CNT_U6_V 0xFFFF\r
-#define PCNT_PLUS_CNT_U6_S 0\r
-\r
-#define PCNT_U7_CNT_REG (DR_REG_PCNT_BASE + 0x007c)\r
-/* PCNT_PLUS_CNT_U7 : RO ;bitpos:[15:0] ;default: 16'h0 ; */\r
-/*description: This register stores the current pulse count value for unit7.*/\r
-#define PCNT_PLUS_CNT_U7 0x0000FFFF\r
-#define PCNT_PLUS_CNT_U7_M ((PCNT_PLUS_CNT_U7_V)<<(PCNT_PLUS_CNT_U7_S))\r
-#define PCNT_PLUS_CNT_U7_V 0xFFFF\r
-#define PCNT_PLUS_CNT_U7_S 0\r
-\r
-#define PCNT_INT_RAW_REG (DR_REG_PCNT_BASE + 0x0080)\r
-/* PCNT_CNT_THR_EVENT_U7_INT_RAW : RO ;bitpos:[7] ;default: 1'b0 ; */\r
-/*description: This is the interrupt raw bit for channel7 event.*/\r
-#define PCNT_CNT_THR_EVENT_U7_INT_RAW (BIT(7))\r
-#define PCNT_CNT_THR_EVENT_U7_INT_RAW_M (BIT(7))\r
-#define PCNT_CNT_THR_EVENT_U7_INT_RAW_V 0x1\r
-#define PCNT_CNT_THR_EVENT_U7_INT_RAW_S 7\r
-/* PCNT_CNT_THR_EVENT_U6_INT_RAW : RO ;bitpos:[6] ;default: 1'b0 ; */\r
-/*description: This is the interrupt raw bit for channel6 event.*/\r
-#define PCNT_CNT_THR_EVENT_U6_INT_RAW (BIT(6))\r
-#define PCNT_CNT_THR_EVENT_U6_INT_RAW_M (BIT(6))\r
-#define PCNT_CNT_THR_EVENT_U6_INT_RAW_V 0x1\r
-#define PCNT_CNT_THR_EVENT_U6_INT_RAW_S 6\r
-/* PCNT_CNT_THR_EVENT_U5_INT_RAW : RO ;bitpos:[5] ;default: 1'b0 ; */\r
-/*description: This is the interrupt raw bit for channel5 event.*/\r
-#define PCNT_CNT_THR_EVENT_U5_INT_RAW (BIT(5))\r
-#define PCNT_CNT_THR_EVENT_U5_INT_RAW_M (BIT(5))\r
-#define PCNT_CNT_THR_EVENT_U5_INT_RAW_V 0x1\r
-#define PCNT_CNT_THR_EVENT_U5_INT_RAW_S 5\r
-/* PCNT_CNT_THR_EVENT_U4_INT_RAW : RO ;bitpos:[4] ;default: 1'b0 ; */\r
-/*description: This is the interrupt raw bit for channel4 event.*/\r
-#define PCNT_CNT_THR_EVENT_U4_INT_RAW (BIT(4))\r
-#define PCNT_CNT_THR_EVENT_U4_INT_RAW_M (BIT(4))\r
-#define PCNT_CNT_THR_EVENT_U4_INT_RAW_V 0x1\r
-#define PCNT_CNT_THR_EVENT_U4_INT_RAW_S 4\r
-/* PCNT_CNT_THR_EVENT_U3_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */\r
-/*description: This is the interrupt raw bit for channel3 event.*/\r
-#define PCNT_CNT_THR_EVENT_U3_INT_RAW (BIT(3))\r
-#define PCNT_CNT_THR_EVENT_U3_INT_RAW_M (BIT(3))\r
-#define PCNT_CNT_THR_EVENT_U3_INT_RAW_V 0x1\r
-#define PCNT_CNT_THR_EVENT_U3_INT_RAW_S 3\r
-/* PCNT_CNT_THR_EVENT_U2_INT_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */\r
-/*description: This is the interrupt raw bit for channel2 event.*/\r
-#define PCNT_CNT_THR_EVENT_U2_INT_RAW (BIT(2))\r
-#define PCNT_CNT_THR_EVENT_U2_INT_RAW_M (BIT(2))\r
-#define PCNT_CNT_THR_EVENT_U2_INT_RAW_V 0x1\r
-#define PCNT_CNT_THR_EVENT_U2_INT_RAW_S 2\r
-/* PCNT_CNT_THR_EVENT_U1_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */\r
-/*description: This is the interrupt raw bit for channel1 event.*/\r
-#define PCNT_CNT_THR_EVENT_U1_INT_RAW (BIT(1))\r
-#define PCNT_CNT_THR_EVENT_U1_INT_RAW_M (BIT(1))\r
-#define PCNT_CNT_THR_EVENT_U1_INT_RAW_V 0x1\r
-#define PCNT_CNT_THR_EVENT_U1_INT_RAW_S 1\r
-/* PCNT_CNT_THR_EVENT_U0_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */\r
-/*description: This is the interrupt raw bit for channel0 event.*/\r
-#define PCNT_CNT_THR_EVENT_U0_INT_RAW (BIT(0))\r
-#define PCNT_CNT_THR_EVENT_U0_INT_RAW_M (BIT(0))\r
-#define PCNT_CNT_THR_EVENT_U0_INT_RAW_V 0x1\r
-#define PCNT_CNT_THR_EVENT_U0_INT_RAW_S 0\r
-\r
-#define PCNT_INT_ST_REG (DR_REG_PCNT_BASE + 0x0084)\r
-/* PCNT_CNT_THR_EVENT_U7_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */\r
-/*description: This is the interrupt status bit for channel7 event.*/\r
-#define PCNT_CNT_THR_EVENT_U7_INT_ST (BIT(7))\r
-#define PCNT_CNT_THR_EVENT_U7_INT_ST_M (BIT(7))\r
-#define PCNT_CNT_THR_EVENT_U7_INT_ST_V 0x1\r
-#define PCNT_CNT_THR_EVENT_U7_INT_ST_S 7\r
-/* PCNT_CNT_THR_EVENT_U6_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */\r
-/*description: This is the interrupt status bit for channel6 event.*/\r
-#define PCNT_CNT_THR_EVENT_U6_INT_ST (BIT(6))\r
-#define PCNT_CNT_THR_EVENT_U6_INT_ST_M (BIT(6))\r
-#define PCNT_CNT_THR_EVENT_U6_INT_ST_V 0x1\r
-#define PCNT_CNT_THR_EVENT_U6_INT_ST_S 6\r
-/* PCNT_CNT_THR_EVENT_U5_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */\r
-/*description: This is the interrupt status bit for channel5 event.*/\r
-#define PCNT_CNT_THR_EVENT_U5_INT_ST (BIT(5))\r
-#define PCNT_CNT_THR_EVENT_U5_INT_ST_M (BIT(5))\r
-#define PCNT_CNT_THR_EVENT_U5_INT_ST_V 0x1\r
-#define PCNT_CNT_THR_EVENT_U5_INT_ST_S 5\r
-/* PCNT_CNT_THR_EVENT_U4_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */\r
-/*description: This is the interrupt status bit for channel4 event.*/\r
-#define PCNT_CNT_THR_EVENT_U4_INT_ST (BIT(4))\r
-#define PCNT_CNT_THR_EVENT_U4_INT_ST_M (BIT(4))\r
-#define PCNT_CNT_THR_EVENT_U4_INT_ST_V 0x1\r
-#define PCNT_CNT_THR_EVENT_U4_INT_ST_S 4\r
-/* PCNT_CNT_THR_EVENT_U3_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */\r
-/*description: This is the interrupt status bit for channel3 event.*/\r
-#define PCNT_CNT_THR_EVENT_U3_INT_ST (BIT(3))\r
-#define PCNT_CNT_THR_EVENT_U3_INT_ST_M (BIT(3))\r
-#define PCNT_CNT_THR_EVENT_U3_INT_ST_V 0x1\r
-#define PCNT_CNT_THR_EVENT_U3_INT_ST_S 3\r
-/* PCNT_CNT_THR_EVENT_U2_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */\r
-/*description: This is the interrupt status bit for channel2 event.*/\r
-#define PCNT_CNT_THR_EVENT_U2_INT_ST (BIT(2))\r
-#define PCNT_CNT_THR_EVENT_U2_INT_ST_M (BIT(2))\r
-#define PCNT_CNT_THR_EVENT_U2_INT_ST_V 0x1\r
-#define PCNT_CNT_THR_EVENT_U2_INT_ST_S 2\r
-/* PCNT_CNT_THR_EVENT_U1_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */\r
-/*description: This is the interrupt status bit for channel1 event.*/\r
-#define PCNT_CNT_THR_EVENT_U1_INT_ST (BIT(1))\r
-#define PCNT_CNT_THR_EVENT_U1_INT_ST_M (BIT(1))\r
-#define PCNT_CNT_THR_EVENT_U1_INT_ST_V 0x1\r
-#define PCNT_CNT_THR_EVENT_U1_INT_ST_S 1\r
-/* PCNT_CNT_THR_EVENT_U0_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */\r
-/*description: This is the interrupt status bit for channel0 event.*/\r
-#define PCNT_CNT_THR_EVENT_U0_INT_ST (BIT(0))\r
-#define PCNT_CNT_THR_EVENT_U0_INT_ST_M (BIT(0))\r
-#define PCNT_CNT_THR_EVENT_U0_INT_ST_V 0x1\r
-#define PCNT_CNT_THR_EVENT_U0_INT_ST_S 0\r
-\r
-#define PCNT_INT_ENA_REG (DR_REG_PCNT_BASE + 0x0088)\r
-/* PCNT_CNT_THR_EVENT_U7_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */\r
-/*description: This is the interrupt enable bit for channel7 event.*/\r
-#define PCNT_CNT_THR_EVENT_U7_INT_ENA (BIT(7))\r
-#define PCNT_CNT_THR_EVENT_U7_INT_ENA_M (BIT(7))\r
-#define PCNT_CNT_THR_EVENT_U7_INT_ENA_V 0x1\r
-#define PCNT_CNT_THR_EVENT_U7_INT_ENA_S 7\r
-/* PCNT_CNT_THR_EVENT_U6_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */\r
-/*description: This is the interrupt enable bit for channel6 event.*/\r
-#define PCNT_CNT_THR_EVENT_U6_INT_ENA (BIT(6))\r
-#define PCNT_CNT_THR_EVENT_U6_INT_ENA_M (BIT(6))\r
-#define PCNT_CNT_THR_EVENT_U6_INT_ENA_V 0x1\r
-#define PCNT_CNT_THR_EVENT_U6_INT_ENA_S 6\r
-/* PCNT_CNT_THR_EVENT_U5_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */\r
-/*description: This is the interrupt enable bit for channel5 event.*/\r
-#define PCNT_CNT_THR_EVENT_U5_INT_ENA (BIT(5))\r
-#define PCNT_CNT_THR_EVENT_U5_INT_ENA_M (BIT(5))\r
-#define PCNT_CNT_THR_EVENT_U5_INT_ENA_V 0x1\r
-#define PCNT_CNT_THR_EVENT_U5_INT_ENA_S 5\r
-/* PCNT_CNT_THR_EVENT_U4_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */\r
-/*description: This is the interrupt enable bit for channel4 event.*/\r
-#define PCNT_CNT_THR_EVENT_U4_INT_ENA (BIT(4))\r
-#define PCNT_CNT_THR_EVENT_U4_INT_ENA_M (BIT(4))\r
-#define PCNT_CNT_THR_EVENT_U4_INT_ENA_V 0x1\r
-#define PCNT_CNT_THR_EVENT_U4_INT_ENA_S 4\r
-/* PCNT_CNT_THR_EVENT_U3_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */\r
-/*description: This is the interrupt enable bit for channel3 event.*/\r
-#define PCNT_CNT_THR_EVENT_U3_INT_ENA (BIT(3))\r
-#define PCNT_CNT_THR_EVENT_U3_INT_ENA_M (BIT(3))\r
-#define PCNT_CNT_THR_EVENT_U3_INT_ENA_V 0x1\r
-#define PCNT_CNT_THR_EVENT_U3_INT_ENA_S 3\r
-/* PCNT_CNT_THR_EVENT_U2_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */\r
-/*description: This is the interrupt enable bit for channel2 event.*/\r
-#define PCNT_CNT_THR_EVENT_U2_INT_ENA (BIT(2))\r
-#define PCNT_CNT_THR_EVENT_U2_INT_ENA_M (BIT(2))\r
-#define PCNT_CNT_THR_EVENT_U2_INT_ENA_V 0x1\r
-#define PCNT_CNT_THR_EVENT_U2_INT_ENA_S 2\r
-/* PCNT_CNT_THR_EVENT_U1_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */\r
-/*description: This is the interrupt enable bit for channel1 event.*/\r
-#define PCNT_CNT_THR_EVENT_U1_INT_ENA (BIT(1))\r
-#define PCNT_CNT_THR_EVENT_U1_INT_ENA_M (BIT(1))\r
-#define PCNT_CNT_THR_EVENT_U1_INT_ENA_V 0x1\r
-#define PCNT_CNT_THR_EVENT_U1_INT_ENA_S 1\r
-/* PCNT_CNT_THR_EVENT_U0_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */\r
-/*description: This is the interrupt enable bit for channel0 event.*/\r
-#define PCNT_CNT_THR_EVENT_U0_INT_ENA (BIT(0))\r
-#define PCNT_CNT_THR_EVENT_U0_INT_ENA_M (BIT(0))\r
-#define PCNT_CNT_THR_EVENT_U0_INT_ENA_V 0x1\r
-#define PCNT_CNT_THR_EVENT_U0_INT_ENA_S 0\r
-\r
-#define PCNT_INT_CLR_REG (DR_REG_PCNT_BASE + 0x008c)\r
-/* PCNT_CNT_THR_EVENT_U7_INT_CLR : WO ;bitpos:[7] ;default: 1'b0 ; */\r
-/*description: Set this bit to clear channel7 event interrupt.*/\r
-#define PCNT_CNT_THR_EVENT_U7_INT_CLR (BIT(7))\r
-#define PCNT_CNT_THR_EVENT_U7_INT_CLR_M (BIT(7))\r
-#define PCNT_CNT_THR_EVENT_U7_INT_CLR_V 0x1\r
-#define PCNT_CNT_THR_EVENT_U7_INT_CLR_S 7\r
-/* PCNT_CNT_THR_EVENT_U6_INT_CLR : WO ;bitpos:[6] ;default: 1'b0 ; */\r
-/*description: Set this bit to clear channel6 event interrupt.*/\r
-#define PCNT_CNT_THR_EVENT_U6_INT_CLR (BIT(6))\r
-#define PCNT_CNT_THR_EVENT_U6_INT_CLR_M (BIT(6))\r
-#define PCNT_CNT_THR_EVENT_U6_INT_CLR_V 0x1\r
-#define PCNT_CNT_THR_EVENT_U6_INT_CLR_S 6\r
-/* PCNT_CNT_THR_EVENT_U5_INT_CLR : WO ;bitpos:[5] ;default: 1'b0 ; */\r
-/*description: Set this bit to clear channel5 event interrupt.*/\r
-#define PCNT_CNT_THR_EVENT_U5_INT_CLR (BIT(5))\r
-#define PCNT_CNT_THR_EVENT_U5_INT_CLR_M (BIT(5))\r
-#define PCNT_CNT_THR_EVENT_U5_INT_CLR_V 0x1\r
-#define PCNT_CNT_THR_EVENT_U5_INT_CLR_S 5\r
-/* PCNT_CNT_THR_EVENT_U4_INT_CLR : WO ;bitpos:[4] ;default: 1'b0 ; */\r
-/*description: Set this bit to clear channel4 event interrupt.*/\r
-#define PCNT_CNT_THR_EVENT_U4_INT_CLR (BIT(4))\r
-#define PCNT_CNT_THR_EVENT_U4_INT_CLR_M (BIT(4))\r
-#define PCNT_CNT_THR_EVENT_U4_INT_CLR_V 0x1\r
-#define PCNT_CNT_THR_EVENT_U4_INT_CLR_S 4\r
-/* PCNT_CNT_THR_EVENT_U3_INT_CLR : WO ;bitpos:[3] ;default: 1'b0 ; */\r
-/*description: Set this bit to clear channel3 event interrupt.*/\r
-#define PCNT_CNT_THR_EVENT_U3_INT_CLR (BIT(3))\r
-#define PCNT_CNT_THR_EVENT_U3_INT_CLR_M (BIT(3))\r
-#define PCNT_CNT_THR_EVENT_U3_INT_CLR_V 0x1\r
-#define PCNT_CNT_THR_EVENT_U3_INT_CLR_S 3\r
-/* PCNT_CNT_THR_EVENT_U2_INT_CLR : WO ;bitpos:[2] ;default: 1'b0 ; */\r
-/*description: Set this bit to clear channel2 event interrupt.*/\r
-#define PCNT_CNT_THR_EVENT_U2_INT_CLR (BIT(2))\r
-#define PCNT_CNT_THR_EVENT_U2_INT_CLR_M (BIT(2))\r
-#define PCNT_CNT_THR_EVENT_U2_INT_CLR_V 0x1\r
-#define PCNT_CNT_THR_EVENT_U2_INT_CLR_S 2\r
-/* PCNT_CNT_THR_EVENT_U1_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */\r
-/*description: Set this bit to clear channel1 event interrupt.*/\r
-#define PCNT_CNT_THR_EVENT_U1_INT_CLR (BIT(1))\r
-#define PCNT_CNT_THR_EVENT_U1_INT_CLR_M (BIT(1))\r
-#define PCNT_CNT_THR_EVENT_U1_INT_CLR_V 0x1\r
-#define PCNT_CNT_THR_EVENT_U1_INT_CLR_S 1\r
-/* PCNT_CNT_THR_EVENT_U0_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */\r
-/*description: Set this bit to clear channel0 event interrupt.*/\r
-#define PCNT_CNT_THR_EVENT_U0_INT_CLR (BIT(0))\r
-#define PCNT_CNT_THR_EVENT_U0_INT_CLR_M (BIT(0))\r
-#define PCNT_CNT_THR_EVENT_U0_INT_CLR_V 0x1\r
-#define PCNT_CNT_THR_EVENT_U0_INT_CLR_S 0\r
-\r
-#define PCNT_U0_STATUS_REG (DR_REG_PCNT_BASE + 0x0090)\r
-/* PCNT_CORE_STATUS_U0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */\r
-/*description: */\r
-#define PCNT_CORE_STATUS_U0 0xFFFFFFFF\r
-#define PCNT_CORE_STATUS_U0_M ((PCNT_CORE_STATUS_U0_V)<<(PCNT_CORE_STATUS_U0_S))\r
-#define PCNT_CORE_STATUS_U0_V 0xFFFFFFFF\r
-#define PCNT_CORE_STATUS_U0_S 0\r
-/*0: positive value to zero; 1: negative value to zero; 2: counter value negative ; 3: counter value positive*/\r
-#define PCNT_STATUS_CNT_MODE 0x3\r
-#define PCNT_STATUS_CNT_MODE_M ((PCNT_STATUS_CNT_MODE_V)<<(PCNT_STATUS_CNT_MODE_S))\r
-#define PCNT_STATUS_CNT_MODE_V 0x3\r
-#define PCNT_STATUS_CNT_MODE_S 0\r
-/* counter value equals to thresh1*/\r
-#define PCNT_STATUS_THRES1 BIT(2)\r
-#define PCNT_STATUS_THRES1_M BIT(2)\r
-#define PCNT_STATUS_THRES1_V 0x1\r
-#define PCNT_STATUS_THRES1_S 2\r
-/* counter value equals to thresh0*/\r
-#define PCNT_STATUS_THRES0 BIT(3)\r
-#define PCNT_STATUS_THRES0_M BIT(3)\r
-#define PCNT_STATUS_THRES0_V 0x1\r
-#define PCNT_STATUS_THRES0_S 3\r
-/* counter value reaches h_lim*/\r
-#define PCNT_STATUS_L_LIM BIT(4)\r
-#define PCNT_STATUS_L_LIM_M BIT(4)\r
-#define PCNT_STATUS_L_LIM_V 0x1\r
-#define PCNT_STATUS_L_LIM_S 4\r
-/* counter value reaches l_lim*/\r
-#define PCNT_STATUS_H_LIM BIT(5)\r
-#define PCNT_STATUS_H_LIM_M BIT(5)\r
-#define PCNT_STATUS_H_LIM_V 0x1\r
-#define PCNT_STATUS_H_LIM_S 5\r
-/* counter value equals to zero*/\r
-#define PCNT_STATUS_ZERO BIT(6)\r
-#define PCNT_STATUS_ZERO_M BIT(6)\r
-#define PCNT_STATUS_ZERO_V 0x1\r
-#define PCNT_STATUS_ZERO_S 6\r
-\r
-#define PCNT_U1_STATUS_REG (DR_REG_PCNT_BASE + 0x0094)\r
-/* PCNT_CORE_STATUS_U1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */\r
-/*description: */\r
-#define PCNT_CORE_STATUS_U1 0xFFFFFFFF\r
-#define PCNT_CORE_STATUS_U1_M ((PCNT_CORE_STATUS_U1_V)<<(PCNT_CORE_STATUS_U1_S))\r
-#define PCNT_CORE_STATUS_U1_V 0xFFFFFFFF\r
-#define PCNT_CORE_STATUS_U1_S 0\r
-\r
-#define PCNT_U2_STATUS_REG (DR_REG_PCNT_BASE + 0x0098)\r
-/* PCNT_CORE_STATUS_U2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */\r
-/*description: */\r
-#define PCNT_CORE_STATUS_U2 0xFFFFFFFF\r
-#define PCNT_CORE_STATUS_U2_M ((PCNT_CORE_STATUS_U2_V)<<(PCNT_CORE_STATUS_U2_S))\r
-#define PCNT_CORE_STATUS_U2_V 0xFFFFFFFF\r
-#define PCNT_CORE_STATUS_U2_S 0\r
-\r
-#define PCNT_U3_STATUS_REG (DR_REG_PCNT_BASE + 0x009c)\r
-/* PCNT_CORE_STATUS_U3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */\r
-/*description: */\r
-#define PCNT_CORE_STATUS_U3 0xFFFFFFFF\r
-#define PCNT_CORE_STATUS_U3_M ((PCNT_CORE_STATUS_U3_V)<<(PCNT_CORE_STATUS_U3_S))\r
-#define PCNT_CORE_STATUS_U3_V 0xFFFFFFFF\r
-#define PCNT_CORE_STATUS_U3_S 0\r
-\r
-#define PCNT_U4_STATUS_REG (DR_REG_PCNT_BASE + 0x00a0)\r
-/* PCNT_CORE_STATUS_U4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */\r
-/*description: */\r
-#define PCNT_CORE_STATUS_U4 0xFFFFFFFF\r
-#define PCNT_CORE_STATUS_U4_M ((PCNT_CORE_STATUS_U4_V)<<(PCNT_CORE_STATUS_U4_S))\r
-#define PCNT_CORE_STATUS_U4_V 0xFFFFFFFF\r
-#define PCNT_CORE_STATUS_U4_S 0\r
-\r
-#define PCNT_U5_STATUS_REG (DR_REG_PCNT_BASE + 0x00a4)\r
-/* PCNT_CORE_STATUS_U5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */\r
-/*description: */\r
-#define PCNT_CORE_STATUS_U5 0xFFFFFFFF\r
-#define PCNT_CORE_STATUS_U5_M ((PCNT_CORE_STATUS_U5_V)<<(PCNT_CORE_STATUS_U5_S))\r
-#define PCNT_CORE_STATUS_U5_V 0xFFFFFFFF\r
-#define PCNT_CORE_STATUS_U5_S 0\r
-\r
-#define PCNT_U6_STATUS_REG (DR_REG_PCNT_BASE + 0x00a8)\r
-/* PCNT_CORE_STATUS_U6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */\r
-/*description: */\r
-#define PCNT_CORE_STATUS_U6 0xFFFFFFFF\r
-#define PCNT_CORE_STATUS_U6_M ((PCNT_CORE_STATUS_U6_V)<<(PCNT_CORE_STATUS_U6_S))\r
-#define PCNT_CORE_STATUS_U6_V 0xFFFFFFFF\r
-#define PCNT_CORE_STATUS_U6_S 0\r
-\r
-#define PCNT_U7_STATUS_REG (DR_REG_PCNT_BASE + 0x00ac)\r
-/* PCNT_CORE_STATUS_U7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */\r
-/*description: */\r
-#define PCNT_CORE_STATUS_U7 0xFFFFFFFF\r
-#define PCNT_CORE_STATUS_U7_M ((PCNT_CORE_STATUS_U7_V)<<(PCNT_CORE_STATUS_U7_S))\r
-#define PCNT_CORE_STATUS_U7_V 0xFFFFFFFF\r
-#define PCNT_CORE_STATUS_U7_S 0\r
-\r
-#define PCNT_CTRL_REG (DR_REG_PCNT_BASE + 0x00b0)\r
-/* PCNT_CLK_EN : R/W ;bitpos:[16] ;default: 1'b0 ; */\r
-/*description: */\r
-#define PCNT_CLK_EN (BIT(16))\r
-#define PCNT_CLK_EN_M (BIT(16))\r
-#define PCNT_CLK_EN_V 0x1\r
-#define PCNT_CLK_EN_S 16\r
-/* PCNT_CNT_PAUSE_U7 : R/W ;bitpos:[15] ;default: 1'b0 ; */\r
-/*description: Set this bit to pause unit7's counter.*/\r
-#define PCNT_CNT_PAUSE_U7 (BIT(15))\r
-#define PCNT_CNT_PAUSE_U7_M (BIT(15))\r
-#define PCNT_CNT_PAUSE_U7_V 0x1\r
-#define PCNT_CNT_PAUSE_U7_S 15\r
-/* PCNT_PLUS_CNT_RST_U7 : R/W ;bitpos:[14] ;default: 1'b1 ; */\r
-/*description: Set this bit to clear unit7's counter.*/\r
-#define PCNT_PLUS_CNT_RST_U7 (BIT(14))\r
-#define PCNT_PLUS_CNT_RST_U7_M (BIT(14))\r
-#define PCNT_PLUS_CNT_RST_U7_V 0x1\r
-#define PCNT_PLUS_CNT_RST_U7_S 14\r
-/* PCNT_CNT_PAUSE_U6 : R/W ;bitpos:[13] ;default: 1'b0 ; */\r
-/*description: Set this bit to pause unit6's counter.*/\r
-#define PCNT_CNT_PAUSE_U6 (BIT(13))\r
-#define PCNT_CNT_PAUSE_U6_M (BIT(13))\r
-#define PCNT_CNT_PAUSE_U6_V 0x1\r
-#define PCNT_CNT_PAUSE_U6_S 13\r
-/* PCNT_PLUS_CNT_RST_U6 : R/W ;bitpos:[12] ;default: 1'b1 ; */\r
-/*description: Set this bit to clear unit6's counter.*/\r
-#define PCNT_PLUS_CNT_RST_U6 (BIT(12))\r
-#define PCNT_PLUS_CNT_RST_U6_M (BIT(12))\r
-#define PCNT_PLUS_CNT_RST_U6_V 0x1\r
-#define PCNT_PLUS_CNT_RST_U6_S 12\r
-/* PCNT_CNT_PAUSE_U5 : R/W ;bitpos:[11] ;default: 1'b0 ; */\r
-/*description: Set this bit to pause unit5's counter.*/\r
-#define PCNT_CNT_PAUSE_U5 (BIT(11))\r
-#define PCNT_CNT_PAUSE_U5_M (BIT(11))\r
-#define PCNT_CNT_PAUSE_U5_V 0x1\r
-#define PCNT_CNT_PAUSE_U5_S 11\r
-/* PCNT_PLUS_CNT_RST_U5 : R/W ;bitpos:[10] ;default: 1'b1 ; */\r
-/*description: Set this bit to clear unit5's counter.*/\r
-#define PCNT_PLUS_CNT_RST_U5 (BIT(10))\r
-#define PCNT_PLUS_CNT_RST_U5_M (BIT(10))\r
-#define PCNT_PLUS_CNT_RST_U5_V 0x1\r
-#define PCNT_PLUS_CNT_RST_U5_S 10\r
-/* PCNT_CNT_PAUSE_U4 : R/W ;bitpos:[9] ;default: 1'b0 ; */\r
-/*description: Set this bit to pause unit4's counter.*/\r
-#define PCNT_CNT_PAUSE_U4 (BIT(9))\r
-#define PCNT_CNT_PAUSE_U4_M (BIT(9))\r
-#define PCNT_CNT_PAUSE_U4_V 0x1\r
-#define PCNT_CNT_PAUSE_U4_S 9\r
-/* PCNT_PLUS_CNT_RST_U4 : R/W ;bitpos:[8] ;default: 1'b1 ; */\r
-/*description: Set this bit to clear unit4's counter.*/\r
-#define PCNT_PLUS_CNT_RST_U4 (BIT(8))\r
-#define PCNT_PLUS_CNT_RST_U4_M (BIT(8))\r
-#define PCNT_PLUS_CNT_RST_U4_V 0x1\r
-#define PCNT_PLUS_CNT_RST_U4_S 8\r
-/* PCNT_CNT_PAUSE_U3 : R/W ;bitpos:[7] ;default: 1'b0 ; */\r
-/*description: Set this bit to pause unit3's counter.*/\r
-#define PCNT_CNT_PAUSE_U3 (BIT(7))\r
-#define PCNT_CNT_PAUSE_U3_M (BIT(7))\r
-#define PCNT_CNT_PAUSE_U3_V 0x1\r
-#define PCNT_CNT_PAUSE_U3_S 7\r
-/* PCNT_PLUS_CNT_RST_U3 : R/W ;bitpos:[6] ;default: 1'b1 ; */\r
-/*description: Set this bit to clear unit3's counter.*/\r
-#define PCNT_PLUS_CNT_RST_U3 (BIT(6))\r
-#define PCNT_PLUS_CNT_RST_U3_M (BIT(6))\r
-#define PCNT_PLUS_CNT_RST_U3_V 0x1\r
-#define PCNT_PLUS_CNT_RST_U3_S 6\r
-/* PCNT_CNT_PAUSE_U2 : R/W ;bitpos:[5] ;default: 1'b0 ; */\r
-/*description: Set this bit to pause unit2's counter.*/\r
-#define PCNT_CNT_PAUSE_U2 (BIT(5))\r
-#define PCNT_CNT_PAUSE_U2_M (BIT(5))\r
-#define PCNT_CNT_PAUSE_U2_V 0x1\r
-#define PCNT_CNT_PAUSE_U2_S 5\r
-/* PCNT_PLUS_CNT_RST_U2 : R/W ;bitpos:[4] ;default: 1'b1 ; */\r
-/*description: Set this bit to clear unit2's counter.*/\r
-#define PCNT_PLUS_CNT_RST_U2 (BIT(4))\r
-#define PCNT_PLUS_CNT_RST_U2_M (BIT(4))\r
-#define PCNT_PLUS_CNT_RST_U2_V 0x1\r
-#define PCNT_PLUS_CNT_RST_U2_S 4\r
-/* PCNT_CNT_PAUSE_U1 : R/W ;bitpos:[3] ;default: 1'b0 ; */\r
-/*description: Set this bit to pause unit1's counter.*/\r
-#define PCNT_CNT_PAUSE_U1 (BIT(3))\r
-#define PCNT_CNT_PAUSE_U1_M (BIT(3))\r
-#define PCNT_CNT_PAUSE_U1_V 0x1\r
-#define PCNT_CNT_PAUSE_U1_S 3\r
-/* PCNT_PLUS_CNT_RST_U1 : R/W ;bitpos:[2] ;default: 1'b1 ; */\r
-/*description: Set this bit to clear unit1's counter.*/\r
-#define PCNT_PLUS_CNT_RST_U1 (BIT(2))\r
-#define PCNT_PLUS_CNT_RST_U1_M (BIT(2))\r
-#define PCNT_PLUS_CNT_RST_U1_V 0x1\r
-#define PCNT_PLUS_CNT_RST_U1_S 2\r
-/* PCNT_CNT_PAUSE_U0 : R/W ;bitpos:[1] ;default: 1'b0 ; */\r
-/*description: Set this bit to pause unit0's counter.*/\r
-#define PCNT_CNT_PAUSE_U0 (BIT(1))\r
-#define PCNT_CNT_PAUSE_U0_M (BIT(1))\r
-#define PCNT_CNT_PAUSE_U0_V 0x1\r
-#define PCNT_CNT_PAUSE_U0_S 1\r
-/* PCNT_PLUS_CNT_RST_U0 : R/W ;bitpos:[0] ;default: 1'b1 ; */\r
-/*description: Set this bit to clear unit0's counter.*/\r
-#define PCNT_PLUS_CNT_RST_U0 (BIT(0))\r
-#define PCNT_PLUS_CNT_RST_U0_M (BIT(0))\r
-#define PCNT_PLUS_CNT_RST_U0_V 0x1\r
-#define PCNT_PLUS_CNT_RST_U0_S 0\r
-\r
-#define PCNT_DATE_REG (DR_REG_PCNT_BASE + 0x00fc)\r
-/* PCNT_DATE : R/W ;bitpos:[31:0] ;default: 32'h14122600 ; */\r
-/*description: */\r
-#define PCNT_DATE 0xFFFFFFFF\r
-#define PCNT_DATE_M ((PCNT_DATE_V)<<(PCNT_DATE_S))\r
-#define PCNT_DATE_V 0xFFFFFFFF\r
-#define PCNT_DATE_S 0\r
-\r
-\r
-\r
-\r
-#endif /*_SOC_PCNT_REG_H_ */\r
-\r
-\r
+// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+#ifndef _SOC_PCNT_REG_H_
+#define _SOC_PCNT_REG_H_
+
+
+#include "soc.h"
+#define PCNT_U0_CONF0_REG (DR_REG_PCNT_BASE + 0x0000)
+/* PCNT_CH1_LCTRL_MODE_U0 : R/W ;bitpos:[31:30] ;default: 2'd0 ; */
+/*description: This register is used to control the mode of channel1's low control
+ signal for unit0. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/
+#define PCNT_CH1_LCTRL_MODE_U0 0x00000003
+#define PCNT_CH1_LCTRL_MODE_U0_M ((PCNT_CH1_LCTRL_MODE_U0_V)<<(PCNT_CH1_LCTRL_MODE_U0_S))
+#define PCNT_CH1_LCTRL_MODE_U0_V 0x3
+#define PCNT_CH1_LCTRL_MODE_U0_S 30
+/* PCNT_CH1_HCTRL_MODE_U0 : R/W ;bitpos:[29:28] ;default: 2'd0 ; */
+/*description: This register is used to control the mode of channel1's high
+ control signal for unit0. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/
+#define PCNT_CH1_HCTRL_MODE_U0 0x00000003
+#define PCNT_CH1_HCTRL_MODE_U0_M ((PCNT_CH1_HCTRL_MODE_U0_V)<<(PCNT_CH1_HCTRL_MODE_U0_S))
+#define PCNT_CH1_HCTRL_MODE_U0_V 0x3
+#define PCNT_CH1_HCTRL_MODE_U0_S 28
+/* PCNT_CH1_POS_MODE_U0 : R/W ;bitpos:[27:26] ;default: 2'd0 ; */
+/*description: This register is used to control the mode of channel1's input
+ posedge signal for unit0. 2'd1: increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden*/
+#define PCNT_CH1_POS_MODE_U0 0x00000003
+#define PCNT_CH1_POS_MODE_U0_M ((PCNT_CH1_POS_MODE_U0_V)<<(PCNT_CH1_POS_MODE_U0_S))
+#define PCNT_CH1_POS_MODE_U0_V 0x3
+#define PCNT_CH1_POS_MODE_U0_S 26
+/* PCNT_CH1_NEG_MODE_U0 : R/W ;bitpos:[25:24] ;default: 2'd0 ; */
+/*description: This register is used to control the mode of channel1's input
+ negedge signal for unit0. 2'd1: increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden*/
+#define PCNT_CH1_NEG_MODE_U0 0x00000003
+#define PCNT_CH1_NEG_MODE_U0_M ((PCNT_CH1_NEG_MODE_U0_V)<<(PCNT_CH1_NEG_MODE_U0_S))
+#define PCNT_CH1_NEG_MODE_U0_V 0x3
+#define PCNT_CH1_NEG_MODE_U0_S 24
+/* PCNT_CH0_LCTRL_MODE_U0 : R/W ;bitpos:[23:22] ;default: 2'd0 ; */
+/*description: This register is used to control the mode of channel0's low control
+ signal for unit0. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/
+#define PCNT_CH0_LCTRL_MODE_U0 0x00000003
+#define PCNT_CH0_LCTRL_MODE_U0_M ((PCNT_CH0_LCTRL_MODE_U0_V)<<(PCNT_CH0_LCTRL_MODE_U0_S))
+#define PCNT_CH0_LCTRL_MODE_U0_V 0x3
+#define PCNT_CH0_LCTRL_MODE_U0_S 22
+/* PCNT_CH0_HCTRL_MODE_U0 : R/W ;bitpos:[21:20] ;default: 2'd0 ; */
+/*description: This register is used to control the mode of channel0's high
+ control signal for unit0. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/
+#define PCNT_CH0_HCTRL_MODE_U0 0x00000003
+#define PCNT_CH0_HCTRL_MODE_U0_M ((PCNT_CH0_HCTRL_MODE_U0_V)<<(PCNT_CH0_HCTRL_MODE_U0_S))
+#define PCNT_CH0_HCTRL_MODE_U0_V 0x3
+#define PCNT_CH0_HCTRL_MODE_U0_S 20
+/* PCNT_CH0_POS_MODE_U0 : R/W ;bitpos:[19:18] ;default: 2'd0 ; */
+/*description: This register is used to control the mode of channel0's input
+ posedge signal for unit0. 2'd1: increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden*/
+#define PCNT_CH0_POS_MODE_U0 0x00000003
+#define PCNT_CH0_POS_MODE_U0_M ((PCNT_CH0_POS_MODE_U0_V)<<(PCNT_CH0_POS_MODE_U0_S))
+#define PCNT_CH0_POS_MODE_U0_V 0x3
+#define PCNT_CH0_POS_MODE_U0_S 18
+/* PCNT_CH0_NEG_MODE_U0 : R/W ;bitpos:[17:16] ;default: 2'd0 ; */
+/*description: This register is used to control the mode of channel0's input
+ negedge signal for unit0. 2'd1: increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden*/
+#define PCNT_CH0_NEG_MODE_U0 0x00000003
+#define PCNT_CH0_NEG_MODE_U0_M ((PCNT_CH0_NEG_MODE_U0_V)<<(PCNT_CH0_NEG_MODE_U0_S))
+#define PCNT_CH0_NEG_MODE_U0_V 0x3
+#define PCNT_CH0_NEG_MODE_U0_S 16
+/* PCNT_THR_THRES1_EN_U0 : R/W ;bitpos:[15] ;default: 1'b0 ; */
+/*description: This is the enable bit for comparing unit0's count with thres1 value .*/
+#define PCNT_THR_THRES1_EN_U0 (BIT(15))
+#define PCNT_THR_THRES1_EN_U0_M (BIT(15))
+#define PCNT_THR_THRES1_EN_U0_V 0x1
+#define PCNT_THR_THRES1_EN_U0_S 15
+/* PCNT_THR_THRES0_EN_U0 : R/W ;bitpos:[14] ;default: 1'b0 ; */
+/*description: This is the enable bit for comparing unit0's count with thres0 value.*/
+#define PCNT_THR_THRES0_EN_U0 (BIT(14))
+#define PCNT_THR_THRES0_EN_U0_M (BIT(14))
+#define PCNT_THR_THRES0_EN_U0_V 0x1
+#define PCNT_THR_THRES0_EN_U0_S 14
+/* PCNT_THR_L_LIM_EN_U0 : R/W ;bitpos:[13] ;default: 1'b1 ; */
+/*description: This is the enable bit for comparing unit0's count with thr_l_lim value.*/
+#define PCNT_THR_L_LIM_EN_U0 (BIT(13))
+#define PCNT_THR_L_LIM_EN_U0_M (BIT(13))
+#define PCNT_THR_L_LIM_EN_U0_V 0x1
+#define PCNT_THR_L_LIM_EN_U0_S 13
+/* PCNT_THR_H_LIM_EN_U0 : R/W ;bitpos:[12] ;default: 1'b1 ; */
+/*description: This is the enable bit for comparing unit0's count with thr_h_lim value.*/
+#define PCNT_THR_H_LIM_EN_U0 (BIT(12))
+#define PCNT_THR_H_LIM_EN_U0_M (BIT(12))
+#define PCNT_THR_H_LIM_EN_U0_V 0x1
+#define PCNT_THR_H_LIM_EN_U0_S 12
+/* PCNT_THR_ZERO_EN_U0 : R/W ;bitpos:[11] ;default: 1'b1 ; */
+/*description: This is the enable bit for comparing unit0's count with 0 value.*/
+#define PCNT_THR_ZERO_EN_U0 (BIT(11))
+#define PCNT_THR_ZERO_EN_U0_M (BIT(11))
+#define PCNT_THR_ZERO_EN_U0_V 0x1
+#define PCNT_THR_ZERO_EN_U0_S 11
+/* PCNT_FILTER_EN_U0 : R/W ;bitpos:[10] ;default: 1'b1 ; */
+/*description: This is the enable bit for filtering input signals for unit0.*/
+#define PCNT_FILTER_EN_U0 (BIT(10))
+#define PCNT_FILTER_EN_U0_M (BIT(10))
+#define PCNT_FILTER_EN_U0_V 0x1
+#define PCNT_FILTER_EN_U0_S 10
+/* PCNT_FILTER_THRES_U0 : R/W ;bitpos:[9:0] ;default: 10'h10 ; */
+/*description: This register is used to filter pluse whose width is smaller
+ than this value for unit0.*/
+#define PCNT_FILTER_THRES_U0 0x000003FF
+#define PCNT_FILTER_THRES_U0_M ((PCNT_FILTER_THRES_U0_V)<<(PCNT_FILTER_THRES_U0_S))
+#define PCNT_FILTER_THRES_U0_V 0x3FF
+#define PCNT_FILTER_THRES_U0_S 0
+
+#define PCNT_U0_CONF1_REG (DR_REG_PCNT_BASE + 0x0004)
+/* PCNT_CNT_THRES1_U0 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */
+/*description: This register is used to configure thres1 value for unit0.*/
+#define PCNT_CNT_THRES1_U0 0x0000FFFF
+#define PCNT_CNT_THRES1_U0_M ((PCNT_CNT_THRES1_U0_V)<<(PCNT_CNT_THRES1_U0_S))
+#define PCNT_CNT_THRES1_U0_V 0xFFFF
+#define PCNT_CNT_THRES1_U0_S 16
+/* PCNT_CNT_THRES0_U0 : R/W ;bitpos:[15:0] ;default: 10'h0 ; */
+/*description: This register is used to configure thres0 value for unit0.*/
+#define PCNT_CNT_THRES0_U0 0x0000FFFF
+#define PCNT_CNT_THRES0_U0_M ((PCNT_CNT_THRES0_U0_V)<<(PCNT_CNT_THRES0_U0_S))
+#define PCNT_CNT_THRES0_U0_V 0xFFFF
+#define PCNT_CNT_THRES0_U0_S 0
+
+#define PCNT_U0_CONF2_REG (DR_REG_PCNT_BASE + 0x0008)
+/* PCNT_CNT_L_LIM_U0 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */
+/*description: This register is used to confiugre thr_l_lim value for unit0.*/
+#define PCNT_CNT_L_LIM_U0 0x0000FFFF
+#define PCNT_CNT_L_LIM_U0_M ((PCNT_CNT_L_LIM_U0_V)<<(PCNT_CNT_L_LIM_U0_S))
+#define PCNT_CNT_L_LIM_U0_V 0xFFFF
+#define PCNT_CNT_L_LIM_U0_S 16
+/* PCNT_CNT_H_LIM_U0 : R/W ;bitpos:[15:0] ;default: 10'h0 ; */
+/*description: This register is used to configure thr_h_lim value for unit0.*/
+#define PCNT_CNT_H_LIM_U0 0x0000FFFF
+#define PCNT_CNT_H_LIM_U0_M ((PCNT_CNT_H_LIM_U0_V)<<(PCNT_CNT_H_LIM_U0_S))
+#define PCNT_CNT_H_LIM_U0_V 0xFFFF
+#define PCNT_CNT_H_LIM_U0_S 0
+
+#define PCNT_U1_CONF0_REG (DR_REG_PCNT_BASE + 0x000c)
+/* PCNT_CH1_LCTRL_MODE_U1 : R/W ;bitpos:[31:30] ;default: 2'd0 ; */
+/*description: This register is used to control the mode of channel1's low control
+ signal for unit1. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/
+#define PCNT_CH1_LCTRL_MODE_U1 0x00000003
+#define PCNT_CH1_LCTRL_MODE_U1_M ((PCNT_CH1_LCTRL_MODE_U1_V)<<(PCNT_CH1_LCTRL_MODE_U1_S))
+#define PCNT_CH1_LCTRL_MODE_U1_V 0x3
+#define PCNT_CH1_LCTRL_MODE_U1_S 30
+/* PCNT_CH1_HCTRL_MODE_U1 : R/W ;bitpos:[29:28] ;default: 2'd0 ; */
+/*description: This register is used to control the mode of channel1's high
+ control signal for unit1. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/
+#define PCNT_CH1_HCTRL_MODE_U1 0x00000003
+#define PCNT_CH1_HCTRL_MODE_U1_M ((PCNT_CH1_HCTRL_MODE_U1_V)<<(PCNT_CH1_HCTRL_MODE_U1_S))
+#define PCNT_CH1_HCTRL_MODE_U1_V 0x3
+#define PCNT_CH1_HCTRL_MODE_U1_S 28
+/* PCNT_CH1_POS_MODE_U1 : R/W ;bitpos:[27:26] ;default: 2'd0 ; */
+/*description: This register is used to control the mode of channel1's input
+ posedge signal for unit1. 2'd1: increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden*/
+#define PCNT_CH1_POS_MODE_U1 0x00000003
+#define PCNT_CH1_POS_MODE_U1_M ((PCNT_CH1_POS_MODE_U1_V)<<(PCNT_CH1_POS_MODE_U1_S))
+#define PCNT_CH1_POS_MODE_U1_V 0x3
+#define PCNT_CH1_POS_MODE_U1_S 26
+/* PCNT_CH1_NEG_MODE_U1 : R/W ;bitpos:[25:24] ;default: 2'd0 ; */
+/*description: This register is used to control the mode of channel1's input
+ negedge signal for unit1. 2'd1: increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden*/
+#define PCNT_CH1_NEG_MODE_U1 0x00000003
+#define PCNT_CH1_NEG_MODE_U1_M ((PCNT_CH1_NEG_MODE_U1_V)<<(PCNT_CH1_NEG_MODE_U1_S))
+#define PCNT_CH1_NEG_MODE_U1_V 0x3
+#define PCNT_CH1_NEG_MODE_U1_S 24
+/* PCNT_CH0_LCTRL_MODE_U1 : R/W ;bitpos:[23:22] ;default: 2'd0 ; */
+/*description: This register is used to control the mode of channel0's low control
+ signal for unit1. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/
+#define PCNT_CH0_LCTRL_MODE_U1 0x00000003
+#define PCNT_CH0_LCTRL_MODE_U1_M ((PCNT_CH0_LCTRL_MODE_U1_V)<<(PCNT_CH0_LCTRL_MODE_U1_S))
+#define PCNT_CH0_LCTRL_MODE_U1_V 0x3
+#define PCNT_CH0_LCTRL_MODE_U1_S 22
+/* PCNT_CH0_HCTRL_MODE_U1 : R/W ;bitpos:[21:20] ;default: 2'd0 ; */
+/*description: This register is used to control the mode of channel0's high
+ control signal for unit1. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/
+#define PCNT_CH0_HCTRL_MODE_U1 0x00000003
+#define PCNT_CH0_HCTRL_MODE_U1_M ((PCNT_CH0_HCTRL_MODE_U1_V)<<(PCNT_CH0_HCTRL_MODE_U1_S))
+#define PCNT_CH0_HCTRL_MODE_U1_V 0x3
+#define PCNT_CH0_HCTRL_MODE_U1_S 20
+/* PCNT_CH0_POS_MODE_U1 : R/W ;bitpos:[19:18] ;default: 2'd0 ; */
+/*description: This register is used to control the mode of channel0's input
+ posedge signal for unit1. 2'd1: increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden*/
+#define PCNT_CH0_POS_MODE_U1 0x00000003
+#define PCNT_CH0_POS_MODE_U1_M ((PCNT_CH0_POS_MODE_U1_V)<<(PCNT_CH0_POS_MODE_U1_S))
+#define PCNT_CH0_POS_MODE_U1_V 0x3
+#define PCNT_CH0_POS_MODE_U1_S 18
+/* PCNT_CH0_NEG_MODE_U1 : R/W ;bitpos:[17:16] ;default: 2'd0 ; */
+/*description: This register is used to control the mode of channel0's input
+ negedge signal for unit1. 2'd1: increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden*/
+#define PCNT_CH0_NEG_MODE_U1 0x00000003
+#define PCNT_CH0_NEG_MODE_U1_M ((PCNT_CH0_NEG_MODE_U1_V)<<(PCNT_CH0_NEG_MODE_U1_S))
+#define PCNT_CH0_NEG_MODE_U1_V 0x3
+#define PCNT_CH0_NEG_MODE_U1_S 16
+/* PCNT_THR_THRES1_EN_U1 : R/W ;bitpos:[15] ;default: 1'b0 ; */
+/*description: This is the enable bit for comparing unit1's count with thres1 value .*/
+#define PCNT_THR_THRES1_EN_U1 (BIT(15))
+#define PCNT_THR_THRES1_EN_U1_M (BIT(15))
+#define PCNT_THR_THRES1_EN_U1_V 0x1
+#define PCNT_THR_THRES1_EN_U1_S 15
+/* PCNT_THR_THRES0_EN_U1 : R/W ;bitpos:[14] ;default: 1'b0 ; */
+/*description: This is the enable bit for comparing unit1's count with thres0 value.*/
+#define PCNT_THR_THRES0_EN_U1 (BIT(14))
+#define PCNT_THR_THRES0_EN_U1_M (BIT(14))
+#define PCNT_THR_THRES0_EN_U1_V 0x1
+#define PCNT_THR_THRES0_EN_U1_S 14
+/* PCNT_THR_L_LIM_EN_U1 : R/W ;bitpos:[13] ;default: 1'b1 ; */
+/*description: This is the enable bit for comparing unit1's count with thr_l_lim value.*/
+#define PCNT_THR_L_LIM_EN_U1 (BIT(13))
+#define PCNT_THR_L_LIM_EN_U1_M (BIT(13))
+#define PCNT_THR_L_LIM_EN_U1_V 0x1
+#define PCNT_THR_L_LIM_EN_U1_S 13
+/* PCNT_THR_H_LIM_EN_U1 : R/W ;bitpos:[12] ;default: 1'b1 ; */
+/*description: This is the enable bit for comparing unit1's count with thr_h_lim value.*/
+#define PCNT_THR_H_LIM_EN_U1 (BIT(12))
+#define PCNT_THR_H_LIM_EN_U1_M (BIT(12))
+#define PCNT_THR_H_LIM_EN_U1_V 0x1
+#define PCNT_THR_H_LIM_EN_U1_S 12
+/* PCNT_THR_ZERO_EN_U1 : R/W ;bitpos:[11] ;default: 1'b1 ; */
+/*description: This is the enable bit for comparing unit1's count with 0 value.*/
+#define PCNT_THR_ZERO_EN_U1 (BIT(11))
+#define PCNT_THR_ZERO_EN_U1_M (BIT(11))
+#define PCNT_THR_ZERO_EN_U1_V 0x1
+#define PCNT_THR_ZERO_EN_U1_S 11
+/* PCNT_FILTER_EN_U1 : R/W ;bitpos:[10] ;default: 1'b1 ; */
+/*description: This is the enable bit for filtering input signals for unit1.*/
+#define PCNT_FILTER_EN_U1 (BIT(10))
+#define PCNT_FILTER_EN_U1_M (BIT(10))
+#define PCNT_FILTER_EN_U1_V 0x1
+#define PCNT_FILTER_EN_U1_S 10
+/* PCNT_FILTER_THRES_U1 : R/W ;bitpos:[9:0] ;default: 10'h10 ; */
+/*description: This register is used to filter pluse whose width is smaller
+ than this value for unit1.*/
+#define PCNT_FILTER_THRES_U1 0x000003FF
+#define PCNT_FILTER_THRES_U1_M ((PCNT_FILTER_THRES_U1_V)<<(PCNT_FILTER_THRES_U1_S))
+#define PCNT_FILTER_THRES_U1_V 0x3FF
+#define PCNT_FILTER_THRES_U1_S 0
+
+#define PCNT_U1_CONF1_REG (DR_REG_PCNT_BASE + 0x0010)
+/* PCNT_CNT_THRES1_U1 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */
+/*description: This register is used to configure thres1 value for unit1.*/
+#define PCNT_CNT_THRES1_U1 0x0000FFFF
+#define PCNT_CNT_THRES1_U1_M ((PCNT_CNT_THRES1_U1_V)<<(PCNT_CNT_THRES1_U1_S))
+#define PCNT_CNT_THRES1_U1_V 0xFFFF
+#define PCNT_CNT_THRES1_U1_S 16
+/* PCNT_CNT_THRES0_U1 : R/W ;bitpos:[15:0] ;default: 10'h0 ; */
+/*description: This register is used to configure thres0 value for unit1.*/
+#define PCNT_CNT_THRES0_U1 0x0000FFFF
+#define PCNT_CNT_THRES0_U1_M ((PCNT_CNT_THRES0_U1_V)<<(PCNT_CNT_THRES0_U1_S))
+#define PCNT_CNT_THRES0_U1_V 0xFFFF
+#define PCNT_CNT_THRES0_U1_S 0
+
+#define PCNT_U1_CONF2_REG (DR_REG_PCNT_BASE + 0x0014)
+/* PCNT_CNT_L_LIM_U1 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */
+/*description: This register is used to confiugre thr_l_lim value for unit1.*/
+#define PCNT_CNT_L_LIM_U1 0x0000FFFF
+#define PCNT_CNT_L_LIM_U1_M ((PCNT_CNT_L_LIM_U1_V)<<(PCNT_CNT_L_LIM_U1_S))
+#define PCNT_CNT_L_LIM_U1_V 0xFFFF
+#define PCNT_CNT_L_LIM_U1_S 16
+/* PCNT_CNT_H_LIM_U1 : R/W ;bitpos:[15:0] ;default: 10'h0 ; */
+/*description: This register is used to configure thr_h_lim value for unit1.*/
+#define PCNT_CNT_H_LIM_U1 0x0000FFFF
+#define PCNT_CNT_H_LIM_U1_M ((PCNT_CNT_H_LIM_U1_V)<<(PCNT_CNT_H_LIM_U1_S))
+#define PCNT_CNT_H_LIM_U1_V 0xFFFF
+#define PCNT_CNT_H_LIM_U1_S 0
+
+#define PCNT_U2_CONF0_REG (DR_REG_PCNT_BASE + 0x0018)
+/* PCNT_CH1_LCTRL_MODE_U2 : R/W ;bitpos:[31:30] ;default: 2'd0 ; */
+/*description: This register is used to control the mode of channel1's low control
+ signal for unit2. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/
+#define PCNT_CH1_LCTRL_MODE_U2 0x00000003
+#define PCNT_CH1_LCTRL_MODE_U2_M ((PCNT_CH1_LCTRL_MODE_U2_V)<<(PCNT_CH1_LCTRL_MODE_U2_S))
+#define PCNT_CH1_LCTRL_MODE_U2_V 0x3
+#define PCNT_CH1_LCTRL_MODE_U2_S 30
+/* PCNT_CH1_HCTRL_MODE_U2 : R/W ;bitpos:[29:28] ;default: 2'd0 ; */
+/*description: This register is used to control the mode of channel1's high
+ control signal for unit2. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/
+#define PCNT_CH1_HCTRL_MODE_U2 0x00000003
+#define PCNT_CH1_HCTRL_MODE_U2_M ((PCNT_CH1_HCTRL_MODE_U2_V)<<(PCNT_CH1_HCTRL_MODE_U2_S))
+#define PCNT_CH1_HCTRL_MODE_U2_V 0x3
+#define PCNT_CH1_HCTRL_MODE_U2_S 28
+/* PCNT_CH1_POS_MODE_U2 : R/W ;bitpos:[27:26] ;default: 2'd0 ; */
+/*description: This register is used to control the mode of channel1's input
+ posedge signal for unit2. 2'd1: increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden*/
+#define PCNT_CH1_POS_MODE_U2 0x00000003
+#define PCNT_CH1_POS_MODE_U2_M ((PCNT_CH1_POS_MODE_U2_V)<<(PCNT_CH1_POS_MODE_U2_S))
+#define PCNT_CH1_POS_MODE_U2_V 0x3
+#define PCNT_CH1_POS_MODE_U2_S 26
+/* PCNT_CH1_NEG_MODE_U2 : R/W ;bitpos:[25:24] ;default: 2'd0 ; */
+/*description: This register is used to control the mode of channel1's input
+ negedge signal for unit2. 2'd1: increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden*/
+#define PCNT_CH1_NEG_MODE_U2 0x00000003
+#define PCNT_CH1_NEG_MODE_U2_M ((PCNT_CH1_NEG_MODE_U2_V)<<(PCNT_CH1_NEG_MODE_U2_S))
+#define PCNT_CH1_NEG_MODE_U2_V 0x3
+#define PCNT_CH1_NEG_MODE_U2_S 24
+/* PCNT_CH0_LCTRL_MODE_U2 : R/W ;bitpos:[23:22] ;default: 2'd0 ; */
+/*description: This register is used to control the mode of channel0's low control
+ signal for unit2. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/
+#define PCNT_CH0_LCTRL_MODE_U2 0x00000003
+#define PCNT_CH0_LCTRL_MODE_U2_M ((PCNT_CH0_LCTRL_MODE_U2_V)<<(PCNT_CH0_LCTRL_MODE_U2_S))
+#define PCNT_CH0_LCTRL_MODE_U2_V 0x3
+#define PCNT_CH0_LCTRL_MODE_U2_S 22
+/* PCNT_CH0_HCTRL_MODE_U2 : R/W ;bitpos:[21:20] ;default: 2'd0 ; */
+/*description: This register is used to control the mode of channel0's high
+ control signal for unit2. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/
+#define PCNT_CH0_HCTRL_MODE_U2 0x00000003
+#define PCNT_CH0_HCTRL_MODE_U2_M ((PCNT_CH0_HCTRL_MODE_U2_V)<<(PCNT_CH0_HCTRL_MODE_U2_S))
+#define PCNT_CH0_HCTRL_MODE_U2_V 0x3
+#define PCNT_CH0_HCTRL_MODE_U2_S 20
+/* PCNT_CH0_POS_MODE_U2 : R/W ;bitpos:[19:18] ;default: 2'd0 ; */
+/*description: This register is used to control the mode of channel0's input
+ posedge signal for unit2. 2'd1: increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden*/
+#define PCNT_CH0_POS_MODE_U2 0x00000003
+#define PCNT_CH0_POS_MODE_U2_M ((PCNT_CH0_POS_MODE_U2_V)<<(PCNT_CH0_POS_MODE_U2_S))
+#define PCNT_CH0_POS_MODE_U2_V 0x3
+#define PCNT_CH0_POS_MODE_U2_S 18
+/* PCNT_CH0_NEG_MODE_U2 : R/W ;bitpos:[17:16] ;default: 2'd0 ; */
+/*description: This register is used to control the mode of channel0's input
+ negedge signal for unit2. 2'd1: increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden*/
+#define PCNT_CH0_NEG_MODE_U2 0x00000003
+#define PCNT_CH0_NEG_MODE_U2_M ((PCNT_CH0_NEG_MODE_U2_V)<<(PCNT_CH0_NEG_MODE_U2_S))
+#define PCNT_CH0_NEG_MODE_U2_V 0x3
+#define PCNT_CH0_NEG_MODE_U2_S 16
+/* PCNT_THR_THRES1_EN_U2 : R/W ;bitpos:[15] ;default: 1'b0 ; */
+/*description: This is the enable bit for comparing unit2's count with thres1 value .*/
+#define PCNT_THR_THRES1_EN_U2 (BIT(15))
+#define PCNT_THR_THRES1_EN_U2_M (BIT(15))
+#define PCNT_THR_THRES1_EN_U2_V 0x1
+#define PCNT_THR_THRES1_EN_U2_S 15
+/* PCNT_THR_THRES0_EN_U2 : R/W ;bitpos:[14] ;default: 1'b0 ; */
+/*description: This is the enable bit for comparing unit2's count with thres0 value.*/
+#define PCNT_THR_THRES0_EN_U2 (BIT(14))
+#define PCNT_THR_THRES0_EN_U2_M (BIT(14))
+#define PCNT_THR_THRES0_EN_U2_V 0x1
+#define PCNT_THR_THRES0_EN_U2_S 14
+/* PCNT_THR_L_LIM_EN_U2 : R/W ;bitpos:[13] ;default: 1'b1 ; */
+/*description: This is the enable bit for comparing unit2's count with thr_l_lim value.*/
+#define PCNT_THR_L_LIM_EN_U2 (BIT(13))
+#define PCNT_THR_L_LIM_EN_U2_M (BIT(13))
+#define PCNT_THR_L_LIM_EN_U2_V 0x1
+#define PCNT_THR_L_LIM_EN_U2_S 13
+/* PCNT_THR_H_LIM_EN_U2 : R/W ;bitpos:[12] ;default: 1'b1 ; */
+/*description: This is the enable bit for comparing unit2's count with thr_h_lim value.*/
+#define PCNT_THR_H_LIM_EN_U2 (BIT(12))
+#define PCNT_THR_H_LIM_EN_U2_M (BIT(12))
+#define PCNT_THR_H_LIM_EN_U2_V 0x1
+#define PCNT_THR_H_LIM_EN_U2_S 12
+/* PCNT_THR_ZERO_EN_U2 : R/W ;bitpos:[11] ;default: 1'b1 ; */
+/*description: This is the enable bit for comparing unit2's count with 0 value.*/
+#define PCNT_THR_ZERO_EN_U2 (BIT(11))
+#define PCNT_THR_ZERO_EN_U2_M (BIT(11))
+#define PCNT_THR_ZERO_EN_U2_V 0x1
+#define PCNT_THR_ZERO_EN_U2_S 11
+/* PCNT_FILTER_EN_U2 : R/W ;bitpos:[10] ;default: 1'b1 ; */
+/*description: This is the enable bit for filtering input signals for unit2.*/
+#define PCNT_FILTER_EN_U2 (BIT(10))
+#define PCNT_FILTER_EN_U2_M (BIT(10))
+#define PCNT_FILTER_EN_U2_V 0x1
+#define PCNT_FILTER_EN_U2_S 10
+/* PCNT_FILTER_THRES_U2 : R/W ;bitpos:[9:0] ;default: 10'h10 ; */
+/*description: This register is used to filter pluse whose width is smaller
+ than this value for unit2.*/
+#define PCNT_FILTER_THRES_U2 0x000003FF
+#define PCNT_FILTER_THRES_U2_M ((PCNT_FILTER_THRES_U2_V)<<(PCNT_FILTER_THRES_U2_S))
+#define PCNT_FILTER_THRES_U2_V 0x3FF
+#define PCNT_FILTER_THRES_U2_S 0
+
+#define PCNT_U2_CONF1_REG (DR_REG_PCNT_BASE + 0x001c)
+/* PCNT_CNT_THRES1_U2 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */
+/*description: This register is used to configure thres1 value for unit2.*/
+#define PCNT_CNT_THRES1_U2 0x0000FFFF
+#define PCNT_CNT_THRES1_U2_M ((PCNT_CNT_THRES1_U2_V)<<(PCNT_CNT_THRES1_U2_S))
+#define PCNT_CNT_THRES1_U2_V 0xFFFF
+#define PCNT_CNT_THRES1_U2_S 16
+/* PCNT_CNT_THRES0_U2 : R/W ;bitpos:[15:0] ;default: 10'h0 ; */
+/*description: This register is used to configure thres0 value for unit2.*/
+#define PCNT_CNT_THRES0_U2 0x0000FFFF
+#define PCNT_CNT_THRES0_U2_M ((PCNT_CNT_THRES0_U2_V)<<(PCNT_CNT_THRES0_U2_S))
+#define PCNT_CNT_THRES0_U2_V 0xFFFF
+#define PCNT_CNT_THRES0_U2_S 0
+
+#define PCNT_U2_CONF2_REG (DR_REG_PCNT_BASE + 0x0020)
+/* PCNT_CNT_L_LIM_U2 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */
+/*description: This register is used to confiugre thr_l_lim value for unit2.*/
+#define PCNT_CNT_L_LIM_U2 0x0000FFFF
+#define PCNT_CNT_L_LIM_U2_M ((PCNT_CNT_L_LIM_U2_V)<<(PCNT_CNT_L_LIM_U2_S))
+#define PCNT_CNT_L_LIM_U2_V 0xFFFF
+#define PCNT_CNT_L_LIM_U2_S 16
+/* PCNT_CNT_H_LIM_U2 : R/W ;bitpos:[15:0] ;default: 10'h0 ; */
+/*description: This register is used to configure thr_h_lim value for unit2.*/
+#define PCNT_CNT_H_LIM_U2 0x0000FFFF
+#define PCNT_CNT_H_LIM_U2_M ((PCNT_CNT_H_LIM_U2_V)<<(PCNT_CNT_H_LIM_U2_S))
+#define PCNT_CNT_H_LIM_U2_V 0xFFFF
+#define PCNT_CNT_H_LIM_U2_S 0
+
+#define PCNT_U3_CONF0_REG (DR_REG_PCNT_BASE + 0x0024)
+/* PCNT_CH1_LCTRL_MODE_U3 : R/W ;bitpos:[31:30] ;default: 2'd0 ; */
+/*description: This register is used to control the mode of channel1's low control
+ signal for unit3. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/
+#define PCNT_CH1_LCTRL_MODE_U3 0x00000003
+#define PCNT_CH1_LCTRL_MODE_U3_M ((PCNT_CH1_LCTRL_MODE_U3_V)<<(PCNT_CH1_LCTRL_MODE_U3_S))
+#define PCNT_CH1_LCTRL_MODE_U3_V 0x3
+#define PCNT_CH1_LCTRL_MODE_U3_S 30
+/* PCNT_CH1_HCTRL_MODE_U3 : R/W ;bitpos:[29:28] ;default: 2'd0 ; */
+/*description: This register is used to control the mode of channel1's high
+ control signal for unit3. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/
+#define PCNT_CH1_HCTRL_MODE_U3 0x00000003
+#define PCNT_CH1_HCTRL_MODE_U3_M ((PCNT_CH1_HCTRL_MODE_U3_V)<<(PCNT_CH1_HCTRL_MODE_U3_S))
+#define PCNT_CH1_HCTRL_MODE_U3_V 0x3
+#define PCNT_CH1_HCTRL_MODE_U3_S 28
+/* PCNT_CH1_POS_MODE_U3 : R/W ;bitpos:[27:26] ;default: 2'd0 ; */
+/*description: This register is used to control the mode of channel1's input
+ posedge signal for unit3. 2'd1: increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden*/
+#define PCNT_CH1_POS_MODE_U3 0x00000003
+#define PCNT_CH1_POS_MODE_U3_M ((PCNT_CH1_POS_MODE_U3_V)<<(PCNT_CH1_POS_MODE_U3_S))
+#define PCNT_CH1_POS_MODE_U3_V 0x3
+#define PCNT_CH1_POS_MODE_U3_S 26
+/* PCNT_CH1_NEG_MODE_U3 : R/W ;bitpos:[25:24] ;default: 2'd0 ; */
+/*description: This register is used to control the mode of channel1's input
+ negedge signal for unit3. 2'd1: increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden*/
+#define PCNT_CH1_NEG_MODE_U3 0x00000003
+#define PCNT_CH1_NEG_MODE_U3_M ((PCNT_CH1_NEG_MODE_U3_V)<<(PCNT_CH1_NEG_MODE_U3_S))
+#define PCNT_CH1_NEG_MODE_U3_V 0x3
+#define PCNT_CH1_NEG_MODE_U3_S 24
+/* PCNT_CH0_LCTRL_MODE_U3 : R/W ;bitpos:[23:22] ;default: 2'd0 ; */
+/*description: This register is used to control the mode of channel0's low control
+ signal for unit3. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/
+#define PCNT_CH0_LCTRL_MODE_U3 0x00000003
+#define PCNT_CH0_LCTRL_MODE_U3_M ((PCNT_CH0_LCTRL_MODE_U3_V)<<(PCNT_CH0_LCTRL_MODE_U3_S))
+#define PCNT_CH0_LCTRL_MODE_U3_V 0x3
+#define PCNT_CH0_LCTRL_MODE_U3_S 22
+/* PCNT_CH0_HCTRL_MODE_U3 : R/W ;bitpos:[21:20] ;default: 2'd0 ; */
+/*description: This register is used to control the mode of channel0's high
+ control signal for unit3. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/
+#define PCNT_CH0_HCTRL_MODE_U3 0x00000003
+#define PCNT_CH0_HCTRL_MODE_U3_M ((PCNT_CH0_HCTRL_MODE_U3_V)<<(PCNT_CH0_HCTRL_MODE_U3_S))
+#define PCNT_CH0_HCTRL_MODE_U3_V 0x3
+#define PCNT_CH0_HCTRL_MODE_U3_S 20
+/* PCNT_CH0_POS_MODE_U3 : R/W ;bitpos:[19:18] ;default: 2'd0 ; */
+/*description: This register is used to control the mode of channel0's input
+ posedge signal for unit3. 2'd1: increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden*/
+#define PCNT_CH0_POS_MODE_U3 0x00000003
+#define PCNT_CH0_POS_MODE_U3_M ((PCNT_CH0_POS_MODE_U3_V)<<(PCNT_CH0_POS_MODE_U3_S))
+#define PCNT_CH0_POS_MODE_U3_V 0x3
+#define PCNT_CH0_POS_MODE_U3_S 18
+/* PCNT_CH0_NEG_MODE_U3 : R/W ;bitpos:[17:16] ;default: 2'd0 ; */
+/*description: This register is used to control the mode of channel0's input
+ negedge signal for unit3. 2'd1: increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden*/
+#define PCNT_CH0_NEG_MODE_U3 0x00000003
+#define PCNT_CH0_NEG_MODE_U3_M ((PCNT_CH0_NEG_MODE_U3_V)<<(PCNT_CH0_NEG_MODE_U3_S))
+#define PCNT_CH0_NEG_MODE_U3_V 0x3
+#define PCNT_CH0_NEG_MODE_U3_S 16
+/* PCNT_THR_THRES1_EN_U3 : R/W ;bitpos:[15] ;default: 1'b0 ; */
+/*description: This is the enable bit for comparing unit3's count with thres1 value .*/
+#define PCNT_THR_THRES1_EN_U3 (BIT(15))
+#define PCNT_THR_THRES1_EN_U3_M (BIT(15))
+#define PCNT_THR_THRES1_EN_U3_V 0x1
+#define PCNT_THR_THRES1_EN_U3_S 15
+/* PCNT_THR_THRES0_EN_U3 : R/W ;bitpos:[14] ;default: 1'b0 ; */
+/*description: This is the enable bit for comparing unit3's count with thres0 value.*/
+#define PCNT_THR_THRES0_EN_U3 (BIT(14))
+#define PCNT_THR_THRES0_EN_U3_M (BIT(14))
+#define PCNT_THR_THRES0_EN_U3_V 0x1
+#define PCNT_THR_THRES0_EN_U3_S 14
+/* PCNT_THR_L_LIM_EN_U3 : R/W ;bitpos:[13] ;default: 1'b1 ; */
+/*description: This is the enable bit for comparing unit3's count with thr_l_lim value.*/
+#define PCNT_THR_L_LIM_EN_U3 (BIT(13))
+#define PCNT_THR_L_LIM_EN_U3_M (BIT(13))
+#define PCNT_THR_L_LIM_EN_U3_V 0x1
+#define PCNT_THR_L_LIM_EN_U3_S 13
+/* PCNT_THR_H_LIM_EN_U3 : R/W ;bitpos:[12] ;default: 1'b1 ; */
+/*description: This is the enable bit for comparing unit3's count with thr_h_lim value.*/
+#define PCNT_THR_H_LIM_EN_U3 (BIT(12))
+#define PCNT_THR_H_LIM_EN_U3_M (BIT(12))
+#define PCNT_THR_H_LIM_EN_U3_V 0x1
+#define PCNT_THR_H_LIM_EN_U3_S 12
+/* PCNT_THR_ZERO_EN_U3 : R/W ;bitpos:[11] ;default: 1'b1 ; */
+/*description: This is the enable bit for comparing unit3's count with 0 value.*/
+#define PCNT_THR_ZERO_EN_U3 (BIT(11))
+#define PCNT_THR_ZERO_EN_U3_M (BIT(11))
+#define PCNT_THR_ZERO_EN_U3_V 0x1
+#define PCNT_THR_ZERO_EN_U3_S 11
+/* PCNT_FILTER_EN_U3 : R/W ;bitpos:[10] ;default: 1'b1 ; */
+/*description: This is the enable bit for filtering input signals for unit3.*/
+#define PCNT_FILTER_EN_U3 (BIT(10))
+#define PCNT_FILTER_EN_U3_M (BIT(10))
+#define PCNT_FILTER_EN_U3_V 0x1
+#define PCNT_FILTER_EN_U3_S 10
+/* PCNT_FILTER_THRES_U3 : R/W ;bitpos:[9:0] ;default: 10'h10 ; */
+/*description: This register is used to filter pluse whose width is smaller
+ than this value for unit3.*/
+#define PCNT_FILTER_THRES_U3 0x000003FF
+#define PCNT_FILTER_THRES_U3_M ((PCNT_FILTER_THRES_U3_V)<<(PCNT_FILTER_THRES_U3_S))
+#define PCNT_FILTER_THRES_U3_V 0x3FF
+#define PCNT_FILTER_THRES_U3_S 0
+
+#define PCNT_U3_CONF1_REG (DR_REG_PCNT_BASE + 0x0028)
+/* PCNT_CNT_THRES1_U3 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */
+/*description: This register is used to configure thres1 value for unit3.*/
+#define PCNT_CNT_THRES1_U3 0x0000FFFF
+#define PCNT_CNT_THRES1_U3_M ((PCNT_CNT_THRES1_U3_V)<<(PCNT_CNT_THRES1_U3_S))
+#define PCNT_CNT_THRES1_U3_V 0xFFFF
+#define PCNT_CNT_THRES1_U3_S 16
+/* PCNT_CNT_THRES0_U3 : R/W ;bitpos:[15:0] ;default: 10'h0 ; */
+/*description: This register is used to configure thres0 value for unit3.*/
+#define PCNT_CNT_THRES0_U3 0x0000FFFF
+#define PCNT_CNT_THRES0_U3_M ((PCNT_CNT_THRES0_U3_V)<<(PCNT_CNT_THRES0_U3_S))
+#define PCNT_CNT_THRES0_U3_V 0xFFFF
+#define PCNT_CNT_THRES0_U3_S 0
+
+#define PCNT_U3_CONF2_REG (DR_REG_PCNT_BASE + 0x002c)
+/* PCNT_CNT_L_LIM_U3 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */
+/*description: This register is used to confiugre thr_l_lim value for unit3.*/
+#define PCNT_CNT_L_LIM_U3 0x0000FFFF
+#define PCNT_CNT_L_LIM_U3_M ((PCNT_CNT_L_LIM_U3_V)<<(PCNT_CNT_L_LIM_U3_S))
+#define PCNT_CNT_L_LIM_U3_V 0xFFFF
+#define PCNT_CNT_L_LIM_U3_S 16
+/* PCNT_CNT_H_LIM_U3 : R/W ;bitpos:[15:0] ;default: 10'h0 ; */
+/*description: This register is used to configure thr_h_lim value for unit3.*/
+#define PCNT_CNT_H_LIM_U3 0x0000FFFF
+#define PCNT_CNT_H_LIM_U3_M ((PCNT_CNT_H_LIM_U3_V)<<(PCNT_CNT_H_LIM_U3_S))
+#define PCNT_CNT_H_LIM_U3_V 0xFFFF
+#define PCNT_CNT_H_LIM_U3_S 0
+
+#define PCNT_U4_CONF0_REG (DR_REG_PCNT_BASE + 0x0030)
+/* PCNT_CH1_LCTRL_MODE_U4 : R/W ;bitpos:[31:30] ;default: 2'd0 ; */
+/*description: This register is used to control the mode of channel1's low control
+ signal for unit4. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/
+#define PCNT_CH1_LCTRL_MODE_U4 0x00000003
+#define PCNT_CH1_LCTRL_MODE_U4_M ((PCNT_CH1_LCTRL_MODE_U4_V)<<(PCNT_CH1_LCTRL_MODE_U4_S))
+#define PCNT_CH1_LCTRL_MODE_U4_V 0x3
+#define PCNT_CH1_LCTRL_MODE_U4_S 30
+/* PCNT_CH1_HCTRL_MODE_U4 : R/W ;bitpos:[29:28] ;default: 2'd0 ; */
+/*description: This register is used to control the mode of channel1's high
+ control signal for unit4. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/
+#define PCNT_CH1_HCTRL_MODE_U4 0x00000003
+#define PCNT_CH1_HCTRL_MODE_U4_M ((PCNT_CH1_HCTRL_MODE_U4_V)<<(PCNT_CH1_HCTRL_MODE_U4_S))
+#define PCNT_CH1_HCTRL_MODE_U4_V 0x3
+#define PCNT_CH1_HCTRL_MODE_U4_S 28
+/* PCNT_CH1_POS_MODE_U4 : R/W ;bitpos:[27:26] ;default: 2'd0 ; */
+/*description: This register is used to control the mode of channel1's input
+ posedge signal for unit4. 2'd1: increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden*/
+#define PCNT_CH1_POS_MODE_U4 0x00000003
+#define PCNT_CH1_POS_MODE_U4_M ((PCNT_CH1_POS_MODE_U4_V)<<(PCNT_CH1_POS_MODE_U4_S))
+#define PCNT_CH1_POS_MODE_U4_V 0x3
+#define PCNT_CH1_POS_MODE_U4_S 26
+/* PCNT_CH1_NEG_MODE_U4 : R/W ;bitpos:[25:24] ;default: 2'd0 ; */
+/*description: This register is used to control the mode of channel1's input
+ negedge signal for unit4. 2'd1: increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden*/
+#define PCNT_CH1_NEG_MODE_U4 0x00000003
+#define PCNT_CH1_NEG_MODE_U4_M ((PCNT_CH1_NEG_MODE_U4_V)<<(PCNT_CH1_NEG_MODE_U4_S))
+#define PCNT_CH1_NEG_MODE_U4_V 0x3
+#define PCNT_CH1_NEG_MODE_U4_S 24
+/* PCNT_CH0_LCTRL_MODE_U4 : R/W ;bitpos:[23:22] ;default: 2'd0 ; */
+/*description: This register is used to control the mode of channel0's low control
+ signal for unit4. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/
+#define PCNT_CH0_LCTRL_MODE_U4 0x00000003
+#define PCNT_CH0_LCTRL_MODE_U4_M ((PCNT_CH0_LCTRL_MODE_U4_V)<<(PCNT_CH0_LCTRL_MODE_U4_S))
+#define PCNT_CH0_LCTRL_MODE_U4_V 0x3
+#define PCNT_CH0_LCTRL_MODE_U4_S 22
+/* PCNT_CH0_HCTRL_MODE_U4 : R/W ;bitpos:[21:20] ;default: 2'd0 ; */
+/*description: This register is used to control the mode of channel0's high
+ control signal for unit4. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/
+#define PCNT_CH0_HCTRL_MODE_U4 0x00000003
+#define PCNT_CH0_HCTRL_MODE_U4_M ((PCNT_CH0_HCTRL_MODE_U4_V)<<(PCNT_CH0_HCTRL_MODE_U4_S))
+#define PCNT_CH0_HCTRL_MODE_U4_V 0x3
+#define PCNT_CH0_HCTRL_MODE_U4_S 20
+/* PCNT_CH0_POS_MODE_U4 : R/W ;bitpos:[19:18] ;default: 2'd0 ; */
+/*description: This register is used to control the mode of channel0's input
+ posedge signal for unit4. 2'd1: increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden*/
+#define PCNT_CH0_POS_MODE_U4 0x00000003
+#define PCNT_CH0_POS_MODE_U4_M ((PCNT_CH0_POS_MODE_U4_V)<<(PCNT_CH0_POS_MODE_U4_S))
+#define PCNT_CH0_POS_MODE_U4_V 0x3
+#define PCNT_CH0_POS_MODE_U4_S 18
+/* PCNT_CH0_NEG_MODE_U4 : R/W ;bitpos:[17:16] ;default: 2'd0 ; */
+/*description: This register is used to control the mode of channel0's input
+ negedge signal for unit4. 2'd1: increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden*/
+#define PCNT_CH0_NEG_MODE_U4 0x00000003
+#define PCNT_CH0_NEG_MODE_U4_M ((PCNT_CH0_NEG_MODE_U4_V)<<(PCNT_CH0_NEG_MODE_U4_S))
+#define PCNT_CH0_NEG_MODE_U4_V 0x3
+#define PCNT_CH0_NEG_MODE_U4_S 16
+/* PCNT_THR_THRES1_EN_U4 : R/W ;bitpos:[15] ;default: 1'b0 ; */
+/*description: This is the enable bit for comparing unit4's count with thres1 value .*/
+#define PCNT_THR_THRES1_EN_U4 (BIT(15))
+#define PCNT_THR_THRES1_EN_U4_M (BIT(15))
+#define PCNT_THR_THRES1_EN_U4_V 0x1
+#define PCNT_THR_THRES1_EN_U4_S 15
+/* PCNT_THR_THRES0_EN_U4 : R/W ;bitpos:[14] ;default: 1'b0 ; */
+/*description: This is the enable bit for comparing unit4's count with thres0 value.*/
+#define PCNT_THR_THRES0_EN_U4 (BIT(14))
+#define PCNT_THR_THRES0_EN_U4_M (BIT(14))
+#define PCNT_THR_THRES0_EN_U4_V 0x1
+#define PCNT_THR_THRES0_EN_U4_S 14
+/* PCNT_THR_L_LIM_EN_U4 : R/W ;bitpos:[13] ;default: 1'b1 ; */
+/*description: This is the enable bit for comparing unit4's count with thr_l_lim value.*/
+#define PCNT_THR_L_LIM_EN_U4 (BIT(13))
+#define PCNT_THR_L_LIM_EN_U4_M (BIT(13))
+#define PCNT_THR_L_LIM_EN_U4_V 0x1
+#define PCNT_THR_L_LIM_EN_U4_S 13
+/* PCNT_THR_H_LIM_EN_U4 : R/W ;bitpos:[12] ;default: 1'b1 ; */
+/*description: This is the enable bit for comparing unit4's count with thr_h_lim value.*/
+#define PCNT_THR_H_LIM_EN_U4 (BIT(12))
+#define PCNT_THR_H_LIM_EN_U4_M (BIT(12))
+#define PCNT_THR_H_LIM_EN_U4_V 0x1
+#define PCNT_THR_H_LIM_EN_U4_S 12
+/* PCNT_THR_ZERO_EN_U4 : R/W ;bitpos:[11] ;default: 1'b1 ; */
+/*description: This is the enable bit for comparing unit4's count with 0 value.*/
+#define PCNT_THR_ZERO_EN_U4 (BIT(11))
+#define PCNT_THR_ZERO_EN_U4_M (BIT(11))
+#define PCNT_THR_ZERO_EN_U4_V 0x1
+#define PCNT_THR_ZERO_EN_U4_S 11
+/* PCNT_FILTER_EN_U4 : R/W ;bitpos:[10] ;default: 1'b1 ; */
+/*description: This is the enable bit for filtering input signals for unit4.*/
+#define PCNT_FILTER_EN_U4 (BIT(10))
+#define PCNT_FILTER_EN_U4_M (BIT(10))
+#define PCNT_FILTER_EN_U4_V 0x1
+#define PCNT_FILTER_EN_U4_S 10
+/* PCNT_FILTER_THRES_U4 : R/W ;bitpos:[9:0] ;default: 10'h10 ; */
+/*description: This register is used to filter pluse whose width is smaller
+ than this value for unit4.*/
+#define PCNT_FILTER_THRES_U4 0x000003FF
+#define PCNT_FILTER_THRES_U4_M ((PCNT_FILTER_THRES_U4_V)<<(PCNT_FILTER_THRES_U4_S))
+#define PCNT_FILTER_THRES_U4_V 0x3FF
+#define PCNT_FILTER_THRES_U4_S 0
+
+#define PCNT_U4_CONF1_REG (DR_REG_PCNT_BASE + 0x0034)
+/* PCNT_CNT_THRES1_U4 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */
+/*description: This register is used to configure thres1 value for unit4.*/
+#define PCNT_CNT_THRES1_U4 0x0000FFFF
+#define PCNT_CNT_THRES1_U4_M ((PCNT_CNT_THRES1_U4_V)<<(PCNT_CNT_THRES1_U4_S))
+#define PCNT_CNT_THRES1_U4_V 0xFFFF
+#define PCNT_CNT_THRES1_U4_S 16
+/* PCNT_CNT_THRES0_U4 : R/W ;bitpos:[15:0] ;default: 10'h0 ; */
+/*description: This register is used to configure thres0 value for unit4.*/
+#define PCNT_CNT_THRES0_U4 0x0000FFFF
+#define PCNT_CNT_THRES0_U4_M ((PCNT_CNT_THRES0_U4_V)<<(PCNT_CNT_THRES0_U4_S))
+#define PCNT_CNT_THRES0_U4_V 0xFFFF
+#define PCNT_CNT_THRES0_U4_S 0
+
+#define PCNT_U4_CONF2_REG (DR_REG_PCNT_BASE + 0x0038)
+/* PCNT_CNT_L_LIM_U4 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */
+/*description: This register is used to confiugre thr_l_lim value for unit4.*/
+#define PCNT_CNT_L_LIM_U4 0x0000FFFF
+#define PCNT_CNT_L_LIM_U4_M ((PCNT_CNT_L_LIM_U4_V)<<(PCNT_CNT_L_LIM_U4_S))
+#define PCNT_CNT_L_LIM_U4_V 0xFFFF
+#define PCNT_CNT_L_LIM_U4_S 16
+/* PCNT_CNT_H_LIM_U4 : R/W ;bitpos:[15:0] ;default: 10'h0 ; */
+/*description: This register is used to configure thr_h_lim value for unit4.*/
+#define PCNT_CNT_H_LIM_U4 0x0000FFFF
+#define PCNT_CNT_H_LIM_U4_M ((PCNT_CNT_H_LIM_U4_V)<<(PCNT_CNT_H_LIM_U4_S))
+#define PCNT_CNT_H_LIM_U4_V 0xFFFF
+#define PCNT_CNT_H_LIM_U4_S 0
+
+#define PCNT_U5_CONF0_REG (DR_REG_PCNT_BASE + 0x003c)
+/* PCNT_CH1_LCTRL_MODE_U5 : R/W ;bitpos:[31:30] ;default: 2'd0 ; */
+/*description: This register is used to control the mode of channel1's low control
+ signal for unit5. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/
+#define PCNT_CH1_LCTRL_MODE_U5 0x00000003
+#define PCNT_CH1_LCTRL_MODE_U5_M ((PCNT_CH1_LCTRL_MODE_U5_V)<<(PCNT_CH1_LCTRL_MODE_U5_S))
+#define PCNT_CH1_LCTRL_MODE_U5_V 0x3
+#define PCNT_CH1_LCTRL_MODE_U5_S 30
+/* PCNT_CH1_HCTRL_MODE_U5 : R/W ;bitpos:[29:28] ;default: 2'd0 ; */
+/*description: This register is used to control the mode of channel1's high
+ control signal for unit5. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/
+#define PCNT_CH1_HCTRL_MODE_U5 0x00000003
+#define PCNT_CH1_HCTRL_MODE_U5_M ((PCNT_CH1_HCTRL_MODE_U5_V)<<(PCNT_CH1_HCTRL_MODE_U5_S))
+#define PCNT_CH1_HCTRL_MODE_U5_V 0x3
+#define PCNT_CH1_HCTRL_MODE_U5_S 28
+/* PCNT_CH1_POS_MODE_U5 : R/W ;bitpos:[27:26] ;default: 2'd0 ; */
+/*description: This register is used to control the mode of channel1's input
+ posedge signal for unit5. 2'd1: increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden*/
+#define PCNT_CH1_POS_MODE_U5 0x00000003
+#define PCNT_CH1_POS_MODE_U5_M ((PCNT_CH1_POS_MODE_U5_V)<<(PCNT_CH1_POS_MODE_U5_S))
+#define PCNT_CH1_POS_MODE_U5_V 0x3
+#define PCNT_CH1_POS_MODE_U5_S 26
+/* PCNT_CH1_NEG_MODE_U5 : R/W ;bitpos:[25:24] ;default: 2'd0 ; */
+/*description: This register is used to control the mode of channel1's input
+ negedge signal for unit5. 2'd1: increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden*/
+#define PCNT_CH1_NEG_MODE_U5 0x00000003
+#define PCNT_CH1_NEG_MODE_U5_M ((PCNT_CH1_NEG_MODE_U5_V)<<(PCNT_CH1_NEG_MODE_U5_S))
+#define PCNT_CH1_NEG_MODE_U5_V 0x3
+#define PCNT_CH1_NEG_MODE_U5_S 24
+/* PCNT_CH0_LCTRL_MODE_U5 : R/W ;bitpos:[23:22] ;default: 2'd0 ; */
+/*description: This register is used to control the mode of channel0's low control
+ signal for unit5. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/
+#define PCNT_CH0_LCTRL_MODE_U5 0x00000003
+#define PCNT_CH0_LCTRL_MODE_U5_M ((PCNT_CH0_LCTRL_MODE_U5_V)<<(PCNT_CH0_LCTRL_MODE_U5_S))
+#define PCNT_CH0_LCTRL_MODE_U5_V 0x3
+#define PCNT_CH0_LCTRL_MODE_U5_S 22
+/* PCNT_CH0_HCTRL_MODE_U5 : R/W ;bitpos:[21:20] ;default: 2'd0 ; */
+/*description: This register is used to control the mode of channel0's high
+ control signal for unit5. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/
+#define PCNT_CH0_HCTRL_MODE_U5 0x00000003
+#define PCNT_CH0_HCTRL_MODE_U5_M ((PCNT_CH0_HCTRL_MODE_U5_V)<<(PCNT_CH0_HCTRL_MODE_U5_S))
+#define PCNT_CH0_HCTRL_MODE_U5_V 0x3
+#define PCNT_CH0_HCTRL_MODE_U5_S 20
+/* PCNT_CH0_POS_MODE_U5 : R/W ;bitpos:[19:18] ;default: 2'd0 ; */
+/*description: This register is used to control the mode of channel0's input
+ posedge signal for unit5. 2'd1: increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden*/
+#define PCNT_CH0_POS_MODE_U5 0x00000003
+#define PCNT_CH0_POS_MODE_U5_M ((PCNT_CH0_POS_MODE_U5_V)<<(PCNT_CH0_POS_MODE_U5_S))
+#define PCNT_CH0_POS_MODE_U5_V 0x3
+#define PCNT_CH0_POS_MODE_U5_S 18
+/* PCNT_CH0_NEG_MODE_U5 : R/W ;bitpos:[17:16] ;default: 2'd0 ; */
+/*description: This register is used to control the mode of channel0's input
+ negedge signal for unit5. 2'd1: increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden*/
+#define PCNT_CH0_NEG_MODE_U5 0x00000003
+#define PCNT_CH0_NEG_MODE_U5_M ((PCNT_CH0_NEG_MODE_U5_V)<<(PCNT_CH0_NEG_MODE_U5_S))
+#define PCNT_CH0_NEG_MODE_U5_V 0x3
+#define PCNT_CH0_NEG_MODE_U5_S 16
+/* PCNT_THR_THRES1_EN_U5 : R/W ;bitpos:[15] ;default: 1'b0 ; */
+/*description: This is the enable bit for comparing unit5's count with thres1 value .*/
+#define PCNT_THR_THRES1_EN_U5 (BIT(15))
+#define PCNT_THR_THRES1_EN_U5_M (BIT(15))
+#define PCNT_THR_THRES1_EN_U5_V 0x1
+#define PCNT_THR_THRES1_EN_U5_S 15
+/* PCNT_THR_THRES0_EN_U5 : R/W ;bitpos:[14] ;default: 1'b0 ; */
+/*description: This is the enable bit for comparing unit5's count with thres0 value.*/
+#define PCNT_THR_THRES0_EN_U5 (BIT(14))
+#define PCNT_THR_THRES0_EN_U5_M (BIT(14))
+#define PCNT_THR_THRES0_EN_U5_V 0x1
+#define PCNT_THR_THRES0_EN_U5_S 14
+/* PCNT_THR_L_LIM_EN_U5 : R/W ;bitpos:[13] ;default: 1'b1 ; */
+/*description: This is the enable bit for comparing unit5's count with thr_l_lim value.*/
+#define PCNT_THR_L_LIM_EN_U5 (BIT(13))
+#define PCNT_THR_L_LIM_EN_U5_M (BIT(13))
+#define PCNT_THR_L_LIM_EN_U5_V 0x1
+#define PCNT_THR_L_LIM_EN_U5_S 13
+/* PCNT_THR_H_LIM_EN_U5 : R/W ;bitpos:[12] ;default: 1'b1 ; */
+/*description: This is the enable bit for comparing unit5's count with thr_h_lim value.*/
+#define PCNT_THR_H_LIM_EN_U5 (BIT(12))
+#define PCNT_THR_H_LIM_EN_U5_M (BIT(12))
+#define PCNT_THR_H_LIM_EN_U5_V 0x1
+#define PCNT_THR_H_LIM_EN_U5_S 12
+/* PCNT_THR_ZERO_EN_U5 : R/W ;bitpos:[11] ;default: 1'b1 ; */
+/*description: This is the enable bit for comparing unit5's count with 0 value.*/
+#define PCNT_THR_ZERO_EN_U5 (BIT(11))
+#define PCNT_THR_ZERO_EN_U5_M (BIT(11))
+#define PCNT_THR_ZERO_EN_U5_V 0x1
+#define PCNT_THR_ZERO_EN_U5_S 11
+/* PCNT_FILTER_EN_U5 : R/W ;bitpos:[10] ;default: 1'b1 ; */
+/*description: This is the enable bit for filtering input signals for unit5.*/
+#define PCNT_FILTER_EN_U5 (BIT(10))
+#define PCNT_FILTER_EN_U5_M (BIT(10))
+#define PCNT_FILTER_EN_U5_V 0x1
+#define PCNT_FILTER_EN_U5_S 10
+/* PCNT_FILTER_THRES_U5 : R/W ;bitpos:[9:0] ;default: 10'h10 ; */
+/*description: This register is used to filter pluse whose width is smaller
+ than this value for unit5.*/
+#define PCNT_FILTER_THRES_U5 0x000003FF
+#define PCNT_FILTER_THRES_U5_M ((PCNT_FILTER_THRES_U5_V)<<(PCNT_FILTER_THRES_U5_S))
+#define PCNT_FILTER_THRES_U5_V 0x3FF
+#define PCNT_FILTER_THRES_U5_S 0
+
+#define PCNT_U5_CONF1_REG (DR_REG_PCNT_BASE + 0x0040)
+/* PCNT_CNT_THRES1_U5 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */
+/*description: This register is used to configure thres1 value for unit5.*/
+#define PCNT_CNT_THRES1_U5 0x0000FFFF
+#define PCNT_CNT_THRES1_U5_M ((PCNT_CNT_THRES1_U5_V)<<(PCNT_CNT_THRES1_U5_S))
+#define PCNT_CNT_THRES1_U5_V 0xFFFF
+#define PCNT_CNT_THRES1_U5_S 16
+/* PCNT_CNT_THRES0_U5 : R/W ;bitpos:[15:0] ;default: 10'h0 ; */
+/*description: This register is used to configure thres0 value for unit5.*/
+#define PCNT_CNT_THRES0_U5 0x0000FFFF
+#define PCNT_CNT_THRES0_U5_M ((PCNT_CNT_THRES0_U5_V)<<(PCNT_CNT_THRES0_U5_S))
+#define PCNT_CNT_THRES0_U5_V 0xFFFF
+#define PCNT_CNT_THRES0_U5_S 0
+
+#define PCNT_U5_CONF2_REG (DR_REG_PCNT_BASE + 0x0044)
+/* PCNT_CNT_L_LIM_U5 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */
+/*description: This register is used to confiugre thr_l_lim value for unit5.*/
+#define PCNT_CNT_L_LIM_U5 0x0000FFFF
+#define PCNT_CNT_L_LIM_U5_M ((PCNT_CNT_L_LIM_U5_V)<<(PCNT_CNT_L_LIM_U5_S))
+#define PCNT_CNT_L_LIM_U5_V 0xFFFF
+#define PCNT_CNT_L_LIM_U5_S 16
+/* PCNT_CNT_H_LIM_U5 : R/W ;bitpos:[15:0] ;default: 10'h0 ; */
+/*description: This register is used to configure thr_h_lim value for unit5.*/
+#define PCNT_CNT_H_LIM_U5 0x0000FFFF
+#define PCNT_CNT_H_LIM_U5_M ((PCNT_CNT_H_LIM_U5_V)<<(PCNT_CNT_H_LIM_U5_S))
+#define PCNT_CNT_H_LIM_U5_V 0xFFFF
+#define PCNT_CNT_H_LIM_U5_S 0
+
+#define PCNT_U6_CONF0_REG (DR_REG_PCNT_BASE + 0x0048)
+/* PCNT_CH1_LCTRL_MODE_U6 : R/W ;bitpos:[31:30] ;default: 2'd0 ; */
+/*description: This register is used to control the mode of channel1's low control
+ signal for unit6. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/
+#define PCNT_CH1_LCTRL_MODE_U6 0x00000003
+#define PCNT_CH1_LCTRL_MODE_U6_M ((PCNT_CH1_LCTRL_MODE_U6_V)<<(PCNT_CH1_LCTRL_MODE_U6_S))
+#define PCNT_CH1_LCTRL_MODE_U6_V 0x3
+#define PCNT_CH1_LCTRL_MODE_U6_S 30
+/* PCNT_CH1_HCTRL_MODE_U6 : R/W ;bitpos:[29:28] ;default: 2'd0 ; */
+/*description: This register is used to control the mode of channel1's high
+ control signal for unit6. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/
+#define PCNT_CH1_HCTRL_MODE_U6 0x00000003
+#define PCNT_CH1_HCTRL_MODE_U6_M ((PCNT_CH1_HCTRL_MODE_U6_V)<<(PCNT_CH1_HCTRL_MODE_U6_S))
+#define PCNT_CH1_HCTRL_MODE_U6_V 0x3
+#define PCNT_CH1_HCTRL_MODE_U6_S 28
+/* PCNT_CH1_POS_MODE_U6 : R/W ;bitpos:[27:26] ;default: 2'd0 ; */
+/*description: This register is used to control the mode of channel1's input
+ posedge signal for unit6. 2'd1: increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden*/
+#define PCNT_CH1_POS_MODE_U6 0x00000003
+#define PCNT_CH1_POS_MODE_U6_M ((PCNT_CH1_POS_MODE_U6_V)<<(PCNT_CH1_POS_MODE_U6_S))
+#define PCNT_CH1_POS_MODE_U6_V 0x3
+#define PCNT_CH1_POS_MODE_U6_S 26
+/* PCNT_CH1_NEG_MODE_U6 : R/W ;bitpos:[25:24] ;default: 2'd0 ; */
+/*description: This register is used to control the mode of channel1's input
+ negedge signal for unit6. 2'd1: increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden*/
+#define PCNT_CH1_NEG_MODE_U6 0x00000003
+#define PCNT_CH1_NEG_MODE_U6_M ((PCNT_CH1_NEG_MODE_U6_V)<<(PCNT_CH1_NEG_MODE_U6_S))
+#define PCNT_CH1_NEG_MODE_U6_V 0x3
+#define PCNT_CH1_NEG_MODE_U6_S 24
+/* PCNT_CH0_LCTRL_MODE_U6 : R/W ;bitpos:[23:22] ;default: 2'd0 ; */
+/*description: This register is used to control the mode of channel0's low control
+ signal for unit6. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/
+#define PCNT_CH0_LCTRL_MODE_U6 0x00000003
+#define PCNT_CH0_LCTRL_MODE_U6_M ((PCNT_CH0_LCTRL_MODE_U6_V)<<(PCNT_CH0_LCTRL_MODE_U6_S))
+#define PCNT_CH0_LCTRL_MODE_U6_V 0x3
+#define PCNT_CH0_LCTRL_MODE_U6_S 22
+/* PCNT_CH0_HCTRL_MODE_U6 : R/W ;bitpos:[21:20] ;default: 2'd0 ; */
+/*description: This register is used to control the mode of channel0's high
+ control signal for unit6. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/
+#define PCNT_CH0_HCTRL_MODE_U6 0x00000003
+#define PCNT_CH0_HCTRL_MODE_U6_M ((PCNT_CH0_HCTRL_MODE_U6_V)<<(PCNT_CH0_HCTRL_MODE_U6_S))
+#define PCNT_CH0_HCTRL_MODE_U6_V 0x3
+#define PCNT_CH0_HCTRL_MODE_U6_S 20
+/* PCNT_CH0_POS_MODE_U6 : R/W ;bitpos:[19:18] ;default: 2'd0 ; */
+/*description: This register is used to control the mode of channel0's input
+ posedge signal for unit6. 2'd1: increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden*/
+#define PCNT_CH0_POS_MODE_U6 0x00000003
+#define PCNT_CH0_POS_MODE_U6_M ((PCNT_CH0_POS_MODE_U6_V)<<(PCNT_CH0_POS_MODE_U6_S))
+#define PCNT_CH0_POS_MODE_U6_V 0x3
+#define PCNT_CH0_POS_MODE_U6_S 18
+/* PCNT_CH0_NEG_MODE_U6 : R/W ;bitpos:[17:16] ;default: 2'd0 ; */
+/*description: This register is used to control the mode of channel0's input
+ negedge signal for unit6. 2'd1: increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden*/
+#define PCNT_CH0_NEG_MODE_U6 0x00000003
+#define PCNT_CH0_NEG_MODE_U6_M ((PCNT_CH0_NEG_MODE_U6_V)<<(PCNT_CH0_NEG_MODE_U6_S))
+#define PCNT_CH0_NEG_MODE_U6_V 0x3
+#define PCNT_CH0_NEG_MODE_U6_S 16
+/* PCNT_THR_THRES1_EN_U6 : R/W ;bitpos:[15] ;default: 1'b0 ; */
+/*description: This is the enable bit for comparing unit6's count with thres1 value .*/
+#define PCNT_THR_THRES1_EN_U6 (BIT(15))
+#define PCNT_THR_THRES1_EN_U6_M (BIT(15))
+#define PCNT_THR_THRES1_EN_U6_V 0x1
+#define PCNT_THR_THRES1_EN_U6_S 15
+/* PCNT_THR_THRES0_EN_U6 : R/W ;bitpos:[14] ;default: 1'b0 ; */
+/*description: This is the enable bit for comparing unit6's count with thres0 value.*/
+#define PCNT_THR_THRES0_EN_U6 (BIT(14))
+#define PCNT_THR_THRES0_EN_U6_M (BIT(14))
+#define PCNT_THR_THRES0_EN_U6_V 0x1
+#define PCNT_THR_THRES0_EN_U6_S 14
+/* PCNT_THR_L_LIM_EN_U6 : R/W ;bitpos:[13] ;default: 1'b1 ; */
+/*description: This is the enable bit for comparing unit6's count with thr_l_lim value.*/
+#define PCNT_THR_L_LIM_EN_U6 (BIT(13))
+#define PCNT_THR_L_LIM_EN_U6_M (BIT(13))
+#define PCNT_THR_L_LIM_EN_U6_V 0x1
+#define PCNT_THR_L_LIM_EN_U6_S 13
+/* PCNT_THR_H_LIM_EN_U6 : R/W ;bitpos:[12] ;default: 1'b1 ; */
+/*description: This is the enable bit for comparing unit6's count with thr_h_lim value.*/
+#define PCNT_THR_H_LIM_EN_U6 (BIT(12))
+#define PCNT_THR_H_LIM_EN_U6_M (BIT(12))
+#define PCNT_THR_H_LIM_EN_U6_V 0x1
+#define PCNT_THR_H_LIM_EN_U6_S 12
+/* PCNT_THR_ZERO_EN_U6 : R/W ;bitpos:[11] ;default: 1'b1 ; */
+/*description: This is the enable bit for comparing unit6's count with 0 value.*/
+#define PCNT_THR_ZERO_EN_U6 (BIT(11))
+#define PCNT_THR_ZERO_EN_U6_M (BIT(11))
+#define PCNT_THR_ZERO_EN_U6_V 0x1
+#define PCNT_THR_ZERO_EN_U6_S 11
+/* PCNT_FILTER_EN_U6 : R/W ;bitpos:[10] ;default: 1'b1 ; */
+/*description: This is the enable bit for filtering input signals for unit6.*/
+#define PCNT_FILTER_EN_U6 (BIT(10))
+#define PCNT_FILTER_EN_U6_M (BIT(10))
+#define PCNT_FILTER_EN_U6_V 0x1
+#define PCNT_FILTER_EN_U6_S 10
+/* PCNT_FILTER_THRES_U6 : R/W ;bitpos:[9:0] ;default: 10'h10 ; */
+/*description: This register is used to filter pluse whose width is smaller
+ than this value for unit6.*/
+#define PCNT_FILTER_THRES_U6 0x000003FF
+#define PCNT_FILTER_THRES_U6_M ((PCNT_FILTER_THRES_U6_V)<<(PCNT_FILTER_THRES_U6_S))
+#define PCNT_FILTER_THRES_U6_V 0x3FF
+#define PCNT_FILTER_THRES_U6_S 0
+
+#define PCNT_U6_CONF1_REG (DR_REG_PCNT_BASE + 0x004c)
+/* PCNT_CNT_THRES1_U6 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */
+/*description: This register is used to configure thres1 value for unit6.*/
+#define PCNT_CNT_THRES1_U6 0x0000FFFF
+#define PCNT_CNT_THRES1_U6_M ((PCNT_CNT_THRES1_U6_V)<<(PCNT_CNT_THRES1_U6_S))
+#define PCNT_CNT_THRES1_U6_V 0xFFFF
+#define PCNT_CNT_THRES1_U6_S 16
+/* PCNT_CNT_THRES0_U6 : R/W ;bitpos:[15:0] ;default: 10'h0 ; */
+/*description: This register is used to configure thres0 value for unit6.*/
+#define PCNT_CNT_THRES0_U6 0x0000FFFF
+#define PCNT_CNT_THRES0_U6_M ((PCNT_CNT_THRES0_U6_V)<<(PCNT_CNT_THRES0_U6_S))
+#define PCNT_CNT_THRES0_U6_V 0xFFFF
+#define PCNT_CNT_THRES0_U6_S 0
+
+#define PCNT_U6_CONF2_REG (DR_REG_PCNT_BASE + 0x0050)
+/* PCNT_CNT_L_LIM_U6 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */
+/*description: This register is used to confiugre thr_l_lim value for unit6.*/
+#define PCNT_CNT_L_LIM_U6 0x0000FFFF
+#define PCNT_CNT_L_LIM_U6_M ((PCNT_CNT_L_LIM_U6_V)<<(PCNT_CNT_L_LIM_U6_S))
+#define PCNT_CNT_L_LIM_U6_V 0xFFFF
+#define PCNT_CNT_L_LIM_U6_S 16
+/* PCNT_CNT_H_LIM_U6 : R/W ;bitpos:[15:0] ;default: 10'h0 ; */
+/*description: This register is used to configure thr_h_lim value for unit6.*/
+#define PCNT_CNT_H_LIM_U6 0x0000FFFF
+#define PCNT_CNT_H_LIM_U6_M ((PCNT_CNT_H_LIM_U6_V)<<(PCNT_CNT_H_LIM_U6_S))
+#define PCNT_CNT_H_LIM_U6_V 0xFFFF
+#define PCNT_CNT_H_LIM_U6_S 0
+
+#define PCNT_U7_CONF0_REG (DR_REG_PCNT_BASE + 0x0054)
+/* PCNT_CH1_LCTRL_MODE_U7 : R/W ;bitpos:[31:30] ;default: 2'd0 ; */
+/*description: This register is used to control the mode of channel1's low control
+ signal for unit7. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/
+#define PCNT_CH1_LCTRL_MODE_U7 0x00000003
+#define PCNT_CH1_LCTRL_MODE_U7_M ((PCNT_CH1_LCTRL_MODE_U7_V)<<(PCNT_CH1_LCTRL_MODE_U7_S))
+#define PCNT_CH1_LCTRL_MODE_U7_V 0x3
+#define PCNT_CH1_LCTRL_MODE_U7_S 30
+/* PCNT_CH1_HCTRL_MODE_U7 : R/W ;bitpos:[29:28] ;default: 2'd0 ; */
+/*description: This register is used to control the mode of channel1's high
+ control signal for unit7. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/
+#define PCNT_CH1_HCTRL_MODE_U7 0x00000003
+#define PCNT_CH1_HCTRL_MODE_U7_M ((PCNT_CH1_HCTRL_MODE_U7_V)<<(PCNT_CH1_HCTRL_MODE_U7_S))
+#define PCNT_CH1_HCTRL_MODE_U7_V 0x3
+#define PCNT_CH1_HCTRL_MODE_U7_S 28
+/* PCNT_CH1_POS_MODE_U7 : R/W ;bitpos:[27:26] ;default: 2'd0 ; */
+/*description: This register is used to control the mode of channel1's input
+ posedge signal for unit7. 2'd1: increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden*/
+#define PCNT_CH1_POS_MODE_U7 0x00000003
+#define PCNT_CH1_POS_MODE_U7_M ((PCNT_CH1_POS_MODE_U7_V)<<(PCNT_CH1_POS_MODE_U7_S))
+#define PCNT_CH1_POS_MODE_U7_V 0x3
+#define PCNT_CH1_POS_MODE_U7_S 26
+/* PCNT_CH1_NEG_MODE_U7 : R/W ;bitpos:[25:24] ;default: 2'd0 ; */
+/*description: This register is used to control the mode of channel1's input
+ negedge signal for unit7. 2'd1: increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden*/
+#define PCNT_CH1_NEG_MODE_U7 0x00000003
+#define PCNT_CH1_NEG_MODE_U7_M ((PCNT_CH1_NEG_MODE_U7_V)<<(PCNT_CH1_NEG_MODE_U7_S))
+#define PCNT_CH1_NEG_MODE_U7_V 0x3
+#define PCNT_CH1_NEG_MODE_U7_S 24
+/* PCNT_CH0_LCTRL_MODE_U7 : R/W ;bitpos:[23:22] ;default: 2'd0 ; */
+/*description: This register is used to control the mode of channel0's low control
+ signal for unit7. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/
+#define PCNT_CH0_LCTRL_MODE_U7 0x00000003
+#define PCNT_CH0_LCTRL_MODE_U7_M ((PCNT_CH0_LCTRL_MODE_U7_V)<<(PCNT_CH0_LCTRL_MODE_U7_S))
+#define PCNT_CH0_LCTRL_MODE_U7_V 0x3
+#define PCNT_CH0_LCTRL_MODE_U7_S 22
+/* PCNT_CH0_HCTRL_MODE_U7 : R/W ;bitpos:[21:20] ;default: 2'd0 ; */
+/*description: This register is used to control the mode of channel0's high
+ control signal for unit7. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/
+#define PCNT_CH0_HCTRL_MODE_U7 0x00000003
+#define PCNT_CH0_HCTRL_MODE_U7_M ((PCNT_CH0_HCTRL_MODE_U7_V)<<(PCNT_CH0_HCTRL_MODE_U7_S))
+#define PCNT_CH0_HCTRL_MODE_U7_V 0x3
+#define PCNT_CH0_HCTRL_MODE_U7_S 20
+/* PCNT_CH0_POS_MODE_U7 : R/W ;bitpos:[19:18] ;default: 2'd0 ; */
+/*description: This register is used to control the mode of channel0's input
+ posedge signal for unit7. 2'd1: increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden*/
+#define PCNT_CH0_POS_MODE_U7 0x00000003
+#define PCNT_CH0_POS_MODE_U7_M ((PCNT_CH0_POS_MODE_U7_V)<<(PCNT_CH0_POS_MODE_U7_S))
+#define PCNT_CH0_POS_MODE_U7_V 0x3
+#define PCNT_CH0_POS_MODE_U7_S 18
+/* PCNT_CH0_NEG_MODE_U7 : R/W ;bitpos:[17:16] ;default: 2'd0 ; */
+/*description: This register is used to control the mode of channel0's input
+ negedge signal for unit7. 2'd1: increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden*/
+#define PCNT_CH0_NEG_MODE_U7 0x00000003
+#define PCNT_CH0_NEG_MODE_U7_M ((PCNT_CH0_NEG_MODE_U7_V)<<(PCNT_CH0_NEG_MODE_U7_S))
+#define PCNT_CH0_NEG_MODE_U7_V 0x3
+#define PCNT_CH0_NEG_MODE_U7_S 16
+/* PCNT_THR_THRES1_EN_U7 : R/W ;bitpos:[15] ;default: 1'b0 ; */
+/*description: This is the enable bit for comparing unit7's count with thres1 value .*/
+#define PCNT_THR_THRES1_EN_U7 (BIT(15))
+#define PCNT_THR_THRES1_EN_U7_M (BIT(15))
+#define PCNT_THR_THRES1_EN_U7_V 0x1
+#define PCNT_THR_THRES1_EN_U7_S 15
+/* PCNT_THR_THRES0_EN_U7 : R/W ;bitpos:[14] ;default: 1'b0 ; */
+/*description: This is the enable bit for comparing unit7's count with thres0 value.*/
+#define PCNT_THR_THRES0_EN_U7 (BIT(14))
+#define PCNT_THR_THRES0_EN_U7_M (BIT(14))
+#define PCNT_THR_THRES0_EN_U7_V 0x1
+#define PCNT_THR_THRES0_EN_U7_S 14
+/* PCNT_THR_L_LIM_EN_U7 : R/W ;bitpos:[13] ;default: 1'b1 ; */
+/*description: This is the enable bit for comparing unit7's count with thr_l_lim value.*/
+#define PCNT_THR_L_LIM_EN_U7 (BIT(13))
+#define PCNT_THR_L_LIM_EN_U7_M (BIT(13))
+#define PCNT_THR_L_LIM_EN_U7_V 0x1
+#define PCNT_THR_L_LIM_EN_U7_S 13
+/* PCNT_THR_H_LIM_EN_U7 : R/W ;bitpos:[12] ;default: 1'b1 ; */
+/*description: This is the enable bit for comparing unit7's count with thr_h_lim value.*/
+#define PCNT_THR_H_LIM_EN_U7 (BIT(12))
+#define PCNT_THR_H_LIM_EN_U7_M (BIT(12))
+#define PCNT_THR_H_LIM_EN_U7_V 0x1
+#define PCNT_THR_H_LIM_EN_U7_S 12
+/* PCNT_THR_ZERO_EN_U7 : R/W ;bitpos:[11] ;default: 1'b1 ; */
+/*description: This is the enable bit for comparing unit7's count with 0 value.*/
+#define PCNT_THR_ZERO_EN_U7 (BIT(11))
+#define PCNT_THR_ZERO_EN_U7_M (BIT(11))
+#define PCNT_THR_ZERO_EN_U7_V 0x1
+#define PCNT_THR_ZERO_EN_U7_S 11
+/* PCNT_FILTER_EN_U7 : R/W ;bitpos:[10] ;default: 1'b1 ; */
+/*description: This is the enable bit for filtering input signals for unit7.*/
+#define PCNT_FILTER_EN_U7 (BIT(10))
+#define PCNT_FILTER_EN_U7_M (BIT(10))
+#define PCNT_FILTER_EN_U7_V 0x1
+#define PCNT_FILTER_EN_U7_S 10
+/* PCNT_FILTER_THRES_U7 : R/W ;bitpos:[9:0] ;default: 10'h10 ; */
+/*description: This register is used to filter pluse whose width is smaller
+ than this value for unit7.*/
+#define PCNT_FILTER_THRES_U7 0x000003FF
+#define PCNT_FILTER_THRES_U7_M ((PCNT_FILTER_THRES_U7_V)<<(PCNT_FILTER_THRES_U7_S))
+#define PCNT_FILTER_THRES_U7_V 0x3FF
+#define PCNT_FILTER_THRES_U7_S 0
+
+#define PCNT_U7_CONF1_REG (DR_REG_PCNT_BASE + 0x0058)
+/* PCNT_CNT_THRES1_U7 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */
+/*description: This register is used to configure thres1 value for unit7.*/
+#define PCNT_CNT_THRES1_U7 0x0000FFFF
+#define PCNT_CNT_THRES1_U7_M ((PCNT_CNT_THRES1_U7_V)<<(PCNT_CNT_THRES1_U7_S))
+#define PCNT_CNT_THRES1_U7_V 0xFFFF
+#define PCNT_CNT_THRES1_U7_S 16
+/* PCNT_CNT_THRES0_U7 : R/W ;bitpos:[15:0] ;default: 10'h0 ; */
+/*description: This register is used to configure thres0 value for unit7.*/
+#define PCNT_CNT_THRES0_U7 0x0000FFFF
+#define PCNT_CNT_THRES0_U7_M ((PCNT_CNT_THRES0_U7_V)<<(PCNT_CNT_THRES0_U7_S))
+#define PCNT_CNT_THRES0_U7_V 0xFFFF
+#define PCNT_CNT_THRES0_U7_S 0
+
+#define PCNT_U7_CONF2_REG (DR_REG_PCNT_BASE + 0x005c)
+/* PCNT_CNT_L_LIM_U7 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */
+/*description: This register is used to confiugre thr_l_lim value for unit7.*/
+#define PCNT_CNT_L_LIM_U7 0x0000FFFF
+#define PCNT_CNT_L_LIM_U7_M ((PCNT_CNT_L_LIM_U7_V)<<(PCNT_CNT_L_LIM_U7_S))
+#define PCNT_CNT_L_LIM_U7_V 0xFFFF
+#define PCNT_CNT_L_LIM_U7_S 16
+/* PCNT_CNT_H_LIM_U7 : R/W ;bitpos:[15:0] ;default: 10'h0 ; */
+/*description: This register is used to configure thr_h_lim value for unit7.*/
+#define PCNT_CNT_H_LIM_U7 0x0000FFFF
+#define PCNT_CNT_H_LIM_U7_M ((PCNT_CNT_H_LIM_U7_V)<<(PCNT_CNT_H_LIM_U7_S))
+#define PCNT_CNT_H_LIM_U7_V 0xFFFF
+#define PCNT_CNT_H_LIM_U7_S 0
+
+#define PCNT_U0_CNT_REG (DR_REG_PCNT_BASE + 0x0060)
+/* PCNT_PLUS_CNT_U0 : RO ;bitpos:[15:0] ;default: 16'h0 ; */
+/*description: This register stores the current pulse count value for unit0.*/
+#define PCNT_PLUS_CNT_U0 0x0000FFFF
+#define PCNT_PLUS_CNT_U0_M ((PCNT_PLUS_CNT_U0_V)<<(PCNT_PLUS_CNT_U0_S))
+#define PCNT_PLUS_CNT_U0_V 0xFFFF
+#define PCNT_PLUS_CNT_U0_S 0
+
+#define PCNT_U1_CNT_REG (DR_REG_PCNT_BASE + 0x0064)
+/* PCNT_PLUS_CNT_U1 : RO ;bitpos:[15:0] ;default: 16'h0 ; */
+/*description: This register stores the current pulse count value for unit1.*/
+#define PCNT_PLUS_CNT_U1 0x0000FFFF
+#define PCNT_PLUS_CNT_U1_M ((PCNT_PLUS_CNT_U1_V)<<(PCNT_PLUS_CNT_U1_S))
+#define PCNT_PLUS_CNT_U1_V 0xFFFF
+#define PCNT_PLUS_CNT_U1_S 0
+
+#define PCNT_U2_CNT_REG (DR_REG_PCNT_BASE + 0x0068)
+/* PCNT_PLUS_CNT_U2 : RO ;bitpos:[15:0] ;default: 16'h0 ; */
+/*description: This register stores the current pulse count value for unit2.*/
+#define PCNT_PLUS_CNT_U2 0x0000FFFF
+#define PCNT_PLUS_CNT_U2_M ((PCNT_PLUS_CNT_U2_V)<<(PCNT_PLUS_CNT_U2_S))
+#define PCNT_PLUS_CNT_U2_V 0xFFFF
+#define PCNT_PLUS_CNT_U2_S 0
+
+#define PCNT_U3_CNT_REG (DR_REG_PCNT_BASE + 0x006c)
+/* PCNT_PLUS_CNT_U3 : RO ;bitpos:[15:0] ;default: 16'h0 ; */
+/*description: This register stores the current pulse count value for unit3.*/
+#define PCNT_PLUS_CNT_U3 0x0000FFFF
+#define PCNT_PLUS_CNT_U3_M ((PCNT_PLUS_CNT_U3_V)<<(PCNT_PLUS_CNT_U3_S))
+#define PCNT_PLUS_CNT_U3_V 0xFFFF
+#define PCNT_PLUS_CNT_U3_S 0
+
+#define PCNT_U4_CNT_REG (DR_REG_PCNT_BASE + 0x0070)
+/* PCNT_PLUS_CNT_U4 : RO ;bitpos:[15:0] ;default: 16'h0 ; */
+/*description: This register stores the current pulse count value for unit4.*/
+#define PCNT_PLUS_CNT_U4 0x0000FFFF
+#define PCNT_PLUS_CNT_U4_M ((PCNT_PLUS_CNT_U4_V)<<(PCNT_PLUS_CNT_U4_S))
+#define PCNT_PLUS_CNT_U4_V 0xFFFF
+#define PCNT_PLUS_CNT_U4_S 0
+
+#define PCNT_U5_CNT_REG (DR_REG_PCNT_BASE + 0x0074)
+/* PCNT_PLUS_CNT_U5 : RO ;bitpos:[15:0] ;default: 16'h0 ; */
+/*description: This register stores the current pulse count value for unit5.*/
+#define PCNT_PLUS_CNT_U5 0x0000FFFF
+#define PCNT_PLUS_CNT_U5_M ((PCNT_PLUS_CNT_U5_V)<<(PCNT_PLUS_CNT_U5_S))
+#define PCNT_PLUS_CNT_U5_V 0xFFFF
+#define PCNT_PLUS_CNT_U5_S 0
+
+#define PCNT_U6_CNT_REG (DR_REG_PCNT_BASE + 0x0078)
+/* PCNT_PLUS_CNT_U6 : RO ;bitpos:[15:0] ;default: 16'h0 ; */
+/*description: This register stores the current pulse count value for unit6.*/
+#define PCNT_PLUS_CNT_U6 0x0000FFFF
+#define PCNT_PLUS_CNT_U6_M ((PCNT_PLUS_CNT_U6_V)<<(PCNT_PLUS_CNT_U6_S))
+#define PCNT_PLUS_CNT_U6_V 0xFFFF
+#define PCNT_PLUS_CNT_U6_S 0
+
+#define PCNT_U7_CNT_REG (DR_REG_PCNT_BASE + 0x007c)
+/* PCNT_PLUS_CNT_U7 : RO ;bitpos:[15:0] ;default: 16'h0 ; */
+/*description: This register stores the current pulse count value for unit7.*/
+#define PCNT_PLUS_CNT_U7 0x0000FFFF
+#define PCNT_PLUS_CNT_U7_M ((PCNT_PLUS_CNT_U7_V)<<(PCNT_PLUS_CNT_U7_S))
+#define PCNT_PLUS_CNT_U7_V 0xFFFF
+#define PCNT_PLUS_CNT_U7_S 0
+
+#define PCNT_INT_RAW_REG (DR_REG_PCNT_BASE + 0x0080)
+/* PCNT_CNT_THR_EVENT_U7_INT_RAW : RO ;bitpos:[7] ;default: 1'b0 ; */
+/*description: This is the interrupt raw bit for channel7 event.*/
+#define PCNT_CNT_THR_EVENT_U7_INT_RAW (BIT(7))
+#define PCNT_CNT_THR_EVENT_U7_INT_RAW_M (BIT(7))
+#define PCNT_CNT_THR_EVENT_U7_INT_RAW_V 0x1
+#define PCNT_CNT_THR_EVENT_U7_INT_RAW_S 7
+/* PCNT_CNT_THR_EVENT_U6_INT_RAW : RO ;bitpos:[6] ;default: 1'b0 ; */
+/*description: This is the interrupt raw bit for channel6 event.*/
+#define PCNT_CNT_THR_EVENT_U6_INT_RAW (BIT(6))
+#define PCNT_CNT_THR_EVENT_U6_INT_RAW_M (BIT(6))
+#define PCNT_CNT_THR_EVENT_U6_INT_RAW_V 0x1
+#define PCNT_CNT_THR_EVENT_U6_INT_RAW_S 6
+/* PCNT_CNT_THR_EVENT_U5_INT_RAW : RO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: This is the interrupt raw bit for channel5 event.*/
+#define PCNT_CNT_THR_EVENT_U5_INT_RAW (BIT(5))
+#define PCNT_CNT_THR_EVENT_U5_INT_RAW_M (BIT(5))
+#define PCNT_CNT_THR_EVENT_U5_INT_RAW_V 0x1
+#define PCNT_CNT_THR_EVENT_U5_INT_RAW_S 5
+/* PCNT_CNT_THR_EVENT_U4_INT_RAW : RO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: This is the interrupt raw bit for channel4 event.*/
+#define PCNT_CNT_THR_EVENT_U4_INT_RAW (BIT(4))
+#define PCNT_CNT_THR_EVENT_U4_INT_RAW_M (BIT(4))
+#define PCNT_CNT_THR_EVENT_U4_INT_RAW_V 0x1
+#define PCNT_CNT_THR_EVENT_U4_INT_RAW_S 4
+/* PCNT_CNT_THR_EVENT_U3_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: This is the interrupt raw bit for channel3 event.*/
+#define PCNT_CNT_THR_EVENT_U3_INT_RAW (BIT(3))
+#define PCNT_CNT_THR_EVENT_U3_INT_RAW_M (BIT(3))
+#define PCNT_CNT_THR_EVENT_U3_INT_RAW_V 0x1
+#define PCNT_CNT_THR_EVENT_U3_INT_RAW_S 3
+/* PCNT_CNT_THR_EVENT_U2_INT_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */
+/*description: This is the interrupt raw bit for channel2 event.*/
+#define PCNT_CNT_THR_EVENT_U2_INT_RAW (BIT(2))
+#define PCNT_CNT_THR_EVENT_U2_INT_RAW_M (BIT(2))
+#define PCNT_CNT_THR_EVENT_U2_INT_RAW_V 0x1
+#define PCNT_CNT_THR_EVENT_U2_INT_RAW_S 2
+/* PCNT_CNT_THR_EVENT_U1_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: This is the interrupt raw bit for channel1 event.*/
+#define PCNT_CNT_THR_EVENT_U1_INT_RAW (BIT(1))
+#define PCNT_CNT_THR_EVENT_U1_INT_RAW_M (BIT(1))
+#define PCNT_CNT_THR_EVENT_U1_INT_RAW_V 0x1
+#define PCNT_CNT_THR_EVENT_U1_INT_RAW_S 1
+/* PCNT_CNT_THR_EVENT_U0_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: This is the interrupt raw bit for channel0 event.*/
+#define PCNT_CNT_THR_EVENT_U0_INT_RAW (BIT(0))
+#define PCNT_CNT_THR_EVENT_U0_INT_RAW_M (BIT(0))
+#define PCNT_CNT_THR_EVENT_U0_INT_RAW_V 0x1
+#define PCNT_CNT_THR_EVENT_U0_INT_RAW_S 0
+
+#define PCNT_INT_ST_REG (DR_REG_PCNT_BASE + 0x0084)
+/* PCNT_CNT_THR_EVENT_U7_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */
+/*description: This is the interrupt status bit for channel7 event.*/
+#define PCNT_CNT_THR_EVENT_U7_INT_ST (BIT(7))
+#define PCNT_CNT_THR_EVENT_U7_INT_ST_M (BIT(7))
+#define PCNT_CNT_THR_EVENT_U7_INT_ST_V 0x1
+#define PCNT_CNT_THR_EVENT_U7_INT_ST_S 7
+/* PCNT_CNT_THR_EVENT_U6_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */
+/*description: This is the interrupt status bit for channel6 event.*/
+#define PCNT_CNT_THR_EVENT_U6_INT_ST (BIT(6))
+#define PCNT_CNT_THR_EVENT_U6_INT_ST_M (BIT(6))
+#define PCNT_CNT_THR_EVENT_U6_INT_ST_V 0x1
+#define PCNT_CNT_THR_EVENT_U6_INT_ST_S 6
+/* PCNT_CNT_THR_EVENT_U5_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: This is the interrupt status bit for channel5 event.*/
+#define PCNT_CNT_THR_EVENT_U5_INT_ST (BIT(5))
+#define PCNT_CNT_THR_EVENT_U5_INT_ST_M (BIT(5))
+#define PCNT_CNT_THR_EVENT_U5_INT_ST_V 0x1
+#define PCNT_CNT_THR_EVENT_U5_INT_ST_S 5
+/* PCNT_CNT_THR_EVENT_U4_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: This is the interrupt status bit for channel4 event.*/
+#define PCNT_CNT_THR_EVENT_U4_INT_ST (BIT(4))
+#define PCNT_CNT_THR_EVENT_U4_INT_ST_M (BIT(4))
+#define PCNT_CNT_THR_EVENT_U4_INT_ST_V 0x1
+#define PCNT_CNT_THR_EVENT_U4_INT_ST_S 4
+/* PCNT_CNT_THR_EVENT_U3_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: This is the interrupt status bit for channel3 event.*/
+#define PCNT_CNT_THR_EVENT_U3_INT_ST (BIT(3))
+#define PCNT_CNT_THR_EVENT_U3_INT_ST_M (BIT(3))
+#define PCNT_CNT_THR_EVENT_U3_INT_ST_V 0x1
+#define PCNT_CNT_THR_EVENT_U3_INT_ST_S 3
+/* PCNT_CNT_THR_EVENT_U2_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */
+/*description: This is the interrupt status bit for channel2 event.*/
+#define PCNT_CNT_THR_EVENT_U2_INT_ST (BIT(2))
+#define PCNT_CNT_THR_EVENT_U2_INT_ST_M (BIT(2))
+#define PCNT_CNT_THR_EVENT_U2_INT_ST_V 0x1
+#define PCNT_CNT_THR_EVENT_U2_INT_ST_S 2
+/* PCNT_CNT_THR_EVENT_U1_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: This is the interrupt status bit for channel1 event.*/
+#define PCNT_CNT_THR_EVENT_U1_INT_ST (BIT(1))
+#define PCNT_CNT_THR_EVENT_U1_INT_ST_M (BIT(1))
+#define PCNT_CNT_THR_EVENT_U1_INT_ST_V 0x1
+#define PCNT_CNT_THR_EVENT_U1_INT_ST_S 1
+/* PCNT_CNT_THR_EVENT_U0_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: This is the interrupt status bit for channel0 event.*/
+#define PCNT_CNT_THR_EVENT_U0_INT_ST (BIT(0))
+#define PCNT_CNT_THR_EVENT_U0_INT_ST_M (BIT(0))
+#define PCNT_CNT_THR_EVENT_U0_INT_ST_V 0x1
+#define PCNT_CNT_THR_EVENT_U0_INT_ST_S 0
+
+#define PCNT_INT_ENA_REG (DR_REG_PCNT_BASE + 0x0088)
+/* PCNT_CNT_THR_EVENT_U7_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: This is the interrupt enable bit for channel7 event.*/
+#define PCNT_CNT_THR_EVENT_U7_INT_ENA (BIT(7))
+#define PCNT_CNT_THR_EVENT_U7_INT_ENA_M (BIT(7))
+#define PCNT_CNT_THR_EVENT_U7_INT_ENA_V 0x1
+#define PCNT_CNT_THR_EVENT_U7_INT_ENA_S 7
+/* PCNT_CNT_THR_EVENT_U6_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: This is the interrupt enable bit for channel6 event.*/
+#define PCNT_CNT_THR_EVENT_U6_INT_ENA (BIT(6))
+#define PCNT_CNT_THR_EVENT_U6_INT_ENA_M (BIT(6))
+#define PCNT_CNT_THR_EVENT_U6_INT_ENA_V 0x1
+#define PCNT_CNT_THR_EVENT_U6_INT_ENA_S 6
+/* PCNT_CNT_THR_EVENT_U5_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: This is the interrupt enable bit for channel5 event.*/
+#define PCNT_CNT_THR_EVENT_U5_INT_ENA (BIT(5))
+#define PCNT_CNT_THR_EVENT_U5_INT_ENA_M (BIT(5))
+#define PCNT_CNT_THR_EVENT_U5_INT_ENA_V 0x1
+#define PCNT_CNT_THR_EVENT_U5_INT_ENA_S 5
+/* PCNT_CNT_THR_EVENT_U4_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: This is the interrupt enable bit for channel4 event.*/
+#define PCNT_CNT_THR_EVENT_U4_INT_ENA (BIT(4))
+#define PCNT_CNT_THR_EVENT_U4_INT_ENA_M (BIT(4))
+#define PCNT_CNT_THR_EVENT_U4_INT_ENA_V 0x1
+#define PCNT_CNT_THR_EVENT_U4_INT_ENA_S 4
+/* PCNT_CNT_THR_EVENT_U3_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: This is the interrupt enable bit for channel3 event.*/
+#define PCNT_CNT_THR_EVENT_U3_INT_ENA (BIT(3))
+#define PCNT_CNT_THR_EVENT_U3_INT_ENA_M (BIT(3))
+#define PCNT_CNT_THR_EVENT_U3_INT_ENA_V 0x1
+#define PCNT_CNT_THR_EVENT_U3_INT_ENA_S 3
+/* PCNT_CNT_THR_EVENT_U2_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: This is the interrupt enable bit for channel2 event.*/
+#define PCNT_CNT_THR_EVENT_U2_INT_ENA (BIT(2))
+#define PCNT_CNT_THR_EVENT_U2_INT_ENA_M (BIT(2))
+#define PCNT_CNT_THR_EVENT_U2_INT_ENA_V 0x1
+#define PCNT_CNT_THR_EVENT_U2_INT_ENA_S 2
+/* PCNT_CNT_THR_EVENT_U1_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: This is the interrupt enable bit for channel1 event.*/
+#define PCNT_CNT_THR_EVENT_U1_INT_ENA (BIT(1))
+#define PCNT_CNT_THR_EVENT_U1_INT_ENA_M (BIT(1))
+#define PCNT_CNT_THR_EVENT_U1_INT_ENA_V 0x1
+#define PCNT_CNT_THR_EVENT_U1_INT_ENA_S 1
+/* PCNT_CNT_THR_EVENT_U0_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: This is the interrupt enable bit for channel0 event.*/
+#define PCNT_CNT_THR_EVENT_U0_INT_ENA (BIT(0))
+#define PCNT_CNT_THR_EVENT_U0_INT_ENA_M (BIT(0))
+#define PCNT_CNT_THR_EVENT_U0_INT_ENA_V 0x1
+#define PCNT_CNT_THR_EVENT_U0_INT_ENA_S 0
+
+#define PCNT_INT_CLR_REG (DR_REG_PCNT_BASE + 0x008c)
+/* PCNT_CNT_THR_EVENT_U7_INT_CLR : WO ;bitpos:[7] ;default: 1'b0 ; */
+/*description: Set this bit to clear channel7 event interrupt.*/
+#define PCNT_CNT_THR_EVENT_U7_INT_CLR (BIT(7))
+#define PCNT_CNT_THR_EVENT_U7_INT_CLR_M (BIT(7))
+#define PCNT_CNT_THR_EVENT_U7_INT_CLR_V 0x1
+#define PCNT_CNT_THR_EVENT_U7_INT_CLR_S 7
+/* PCNT_CNT_THR_EVENT_U6_INT_CLR : WO ;bitpos:[6] ;default: 1'b0 ; */
+/*description: Set this bit to clear channel6 event interrupt.*/
+#define PCNT_CNT_THR_EVENT_U6_INT_CLR (BIT(6))
+#define PCNT_CNT_THR_EVENT_U6_INT_CLR_M (BIT(6))
+#define PCNT_CNT_THR_EVENT_U6_INT_CLR_V 0x1
+#define PCNT_CNT_THR_EVENT_U6_INT_CLR_S 6
+/* PCNT_CNT_THR_EVENT_U5_INT_CLR : WO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: Set this bit to clear channel5 event interrupt.*/
+#define PCNT_CNT_THR_EVENT_U5_INT_CLR (BIT(5))
+#define PCNT_CNT_THR_EVENT_U5_INT_CLR_M (BIT(5))
+#define PCNT_CNT_THR_EVENT_U5_INT_CLR_V 0x1
+#define PCNT_CNT_THR_EVENT_U5_INT_CLR_S 5
+/* PCNT_CNT_THR_EVENT_U4_INT_CLR : WO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: Set this bit to clear channel4 event interrupt.*/
+#define PCNT_CNT_THR_EVENT_U4_INT_CLR (BIT(4))
+#define PCNT_CNT_THR_EVENT_U4_INT_CLR_M (BIT(4))
+#define PCNT_CNT_THR_EVENT_U4_INT_CLR_V 0x1
+#define PCNT_CNT_THR_EVENT_U4_INT_CLR_S 4
+/* PCNT_CNT_THR_EVENT_U3_INT_CLR : WO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: Set this bit to clear channel3 event interrupt.*/
+#define PCNT_CNT_THR_EVENT_U3_INT_CLR (BIT(3))
+#define PCNT_CNT_THR_EVENT_U3_INT_CLR_M (BIT(3))
+#define PCNT_CNT_THR_EVENT_U3_INT_CLR_V 0x1
+#define PCNT_CNT_THR_EVENT_U3_INT_CLR_S 3
+/* PCNT_CNT_THR_EVENT_U2_INT_CLR : WO ;bitpos:[2] ;default: 1'b0 ; */
+/*description: Set this bit to clear channel2 event interrupt.*/
+#define PCNT_CNT_THR_EVENT_U2_INT_CLR (BIT(2))
+#define PCNT_CNT_THR_EVENT_U2_INT_CLR_M (BIT(2))
+#define PCNT_CNT_THR_EVENT_U2_INT_CLR_V 0x1
+#define PCNT_CNT_THR_EVENT_U2_INT_CLR_S 2
+/* PCNT_CNT_THR_EVENT_U1_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: Set this bit to clear channel1 event interrupt.*/
+#define PCNT_CNT_THR_EVENT_U1_INT_CLR (BIT(1))
+#define PCNT_CNT_THR_EVENT_U1_INT_CLR_M (BIT(1))
+#define PCNT_CNT_THR_EVENT_U1_INT_CLR_V 0x1
+#define PCNT_CNT_THR_EVENT_U1_INT_CLR_S 1
+/* PCNT_CNT_THR_EVENT_U0_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: Set this bit to clear channel0 event interrupt.*/
+#define PCNT_CNT_THR_EVENT_U0_INT_CLR (BIT(0))
+#define PCNT_CNT_THR_EVENT_U0_INT_CLR_M (BIT(0))
+#define PCNT_CNT_THR_EVENT_U0_INT_CLR_V 0x1
+#define PCNT_CNT_THR_EVENT_U0_INT_CLR_S 0
+
+#define PCNT_U0_STATUS_REG (DR_REG_PCNT_BASE + 0x0090)
+/* PCNT_CORE_STATUS_U0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define PCNT_CORE_STATUS_U0 0xFFFFFFFF
+#define PCNT_CORE_STATUS_U0_M ((PCNT_CORE_STATUS_U0_V)<<(PCNT_CORE_STATUS_U0_S))
+#define PCNT_CORE_STATUS_U0_V 0xFFFFFFFF
+#define PCNT_CORE_STATUS_U0_S 0
+/*0: positive value to zero; 1: negative value to zero; 2: counter value negative ; 3: counter value positive*/
+#define PCNT_STATUS_CNT_MODE 0x3
+#define PCNT_STATUS_CNT_MODE_M ((PCNT_STATUS_CNT_MODE_V)<<(PCNT_STATUS_CNT_MODE_S))
+#define PCNT_STATUS_CNT_MODE_V 0x3
+#define PCNT_STATUS_CNT_MODE_S 0
+/* counter value equals to thresh1*/
+#define PCNT_STATUS_THRES1 BIT(2)
+#define PCNT_STATUS_THRES1_M BIT(2)
+#define PCNT_STATUS_THRES1_V 0x1
+#define PCNT_STATUS_THRES1_S 2
+/* counter value equals to thresh0*/
+#define PCNT_STATUS_THRES0 BIT(3)
+#define PCNT_STATUS_THRES0_M BIT(3)
+#define PCNT_STATUS_THRES0_V 0x1
+#define PCNT_STATUS_THRES0_S 3
+/* counter value reaches h_lim*/
+#define PCNT_STATUS_L_LIM BIT(4)
+#define PCNT_STATUS_L_LIM_M BIT(4)
+#define PCNT_STATUS_L_LIM_V 0x1
+#define PCNT_STATUS_L_LIM_S 4
+/* counter value reaches l_lim*/
+#define PCNT_STATUS_H_LIM BIT(5)
+#define PCNT_STATUS_H_LIM_M BIT(5)
+#define PCNT_STATUS_H_LIM_V 0x1
+#define PCNT_STATUS_H_LIM_S 5
+/* counter value equals to zero*/
+#define PCNT_STATUS_ZERO BIT(6)
+#define PCNT_STATUS_ZERO_M BIT(6)
+#define PCNT_STATUS_ZERO_V 0x1
+#define PCNT_STATUS_ZERO_S 6
+
+#define PCNT_U1_STATUS_REG (DR_REG_PCNT_BASE + 0x0094)
+/* PCNT_CORE_STATUS_U1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define PCNT_CORE_STATUS_U1 0xFFFFFFFF
+#define PCNT_CORE_STATUS_U1_M ((PCNT_CORE_STATUS_U1_V)<<(PCNT_CORE_STATUS_U1_S))
+#define PCNT_CORE_STATUS_U1_V 0xFFFFFFFF
+#define PCNT_CORE_STATUS_U1_S 0
+
+#define PCNT_U2_STATUS_REG (DR_REG_PCNT_BASE + 0x0098)
+/* PCNT_CORE_STATUS_U2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define PCNT_CORE_STATUS_U2 0xFFFFFFFF
+#define PCNT_CORE_STATUS_U2_M ((PCNT_CORE_STATUS_U2_V)<<(PCNT_CORE_STATUS_U2_S))
+#define PCNT_CORE_STATUS_U2_V 0xFFFFFFFF
+#define PCNT_CORE_STATUS_U2_S 0
+
+#define PCNT_U3_STATUS_REG (DR_REG_PCNT_BASE + 0x009c)
+/* PCNT_CORE_STATUS_U3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define PCNT_CORE_STATUS_U3 0xFFFFFFFF
+#define PCNT_CORE_STATUS_U3_M ((PCNT_CORE_STATUS_U3_V)<<(PCNT_CORE_STATUS_U3_S))
+#define PCNT_CORE_STATUS_U3_V 0xFFFFFFFF
+#define PCNT_CORE_STATUS_U3_S 0
+
+#define PCNT_U4_STATUS_REG (DR_REG_PCNT_BASE + 0x00a0)
+/* PCNT_CORE_STATUS_U4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define PCNT_CORE_STATUS_U4 0xFFFFFFFF
+#define PCNT_CORE_STATUS_U4_M ((PCNT_CORE_STATUS_U4_V)<<(PCNT_CORE_STATUS_U4_S))
+#define PCNT_CORE_STATUS_U4_V 0xFFFFFFFF
+#define PCNT_CORE_STATUS_U4_S 0
+
+#define PCNT_U5_STATUS_REG (DR_REG_PCNT_BASE + 0x00a4)
+/* PCNT_CORE_STATUS_U5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define PCNT_CORE_STATUS_U5 0xFFFFFFFF
+#define PCNT_CORE_STATUS_U5_M ((PCNT_CORE_STATUS_U5_V)<<(PCNT_CORE_STATUS_U5_S))
+#define PCNT_CORE_STATUS_U5_V 0xFFFFFFFF
+#define PCNT_CORE_STATUS_U5_S 0
+
+#define PCNT_U6_STATUS_REG (DR_REG_PCNT_BASE + 0x00a8)
+/* PCNT_CORE_STATUS_U6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define PCNT_CORE_STATUS_U6 0xFFFFFFFF
+#define PCNT_CORE_STATUS_U6_M ((PCNT_CORE_STATUS_U6_V)<<(PCNT_CORE_STATUS_U6_S))
+#define PCNT_CORE_STATUS_U6_V 0xFFFFFFFF
+#define PCNT_CORE_STATUS_U6_S 0
+
+#define PCNT_U7_STATUS_REG (DR_REG_PCNT_BASE + 0x00ac)
+/* PCNT_CORE_STATUS_U7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define PCNT_CORE_STATUS_U7 0xFFFFFFFF
+#define PCNT_CORE_STATUS_U7_M ((PCNT_CORE_STATUS_U7_V)<<(PCNT_CORE_STATUS_U7_S))
+#define PCNT_CORE_STATUS_U7_V 0xFFFFFFFF
+#define PCNT_CORE_STATUS_U7_S 0
+
+#define PCNT_CTRL_REG (DR_REG_PCNT_BASE + 0x00b0)
+/* PCNT_CLK_EN : R/W ;bitpos:[16] ;default: 1'b0 ; */
+/*description: */
+#define PCNT_CLK_EN (BIT(16))
+#define PCNT_CLK_EN_M (BIT(16))
+#define PCNT_CLK_EN_V 0x1
+#define PCNT_CLK_EN_S 16
+/* PCNT_CNT_PAUSE_U7 : R/W ;bitpos:[15] ;default: 1'b0 ; */
+/*description: Set this bit to pause unit7's counter.*/
+#define PCNT_CNT_PAUSE_U7 (BIT(15))
+#define PCNT_CNT_PAUSE_U7_M (BIT(15))
+#define PCNT_CNT_PAUSE_U7_V 0x1
+#define PCNT_CNT_PAUSE_U7_S 15
+/* PCNT_PLUS_CNT_RST_U7 : R/W ;bitpos:[14] ;default: 1'b1 ; */
+/*description: Set this bit to clear unit7's counter.*/
+#define PCNT_PLUS_CNT_RST_U7 (BIT(14))
+#define PCNT_PLUS_CNT_RST_U7_M (BIT(14))
+#define PCNT_PLUS_CNT_RST_U7_V 0x1
+#define PCNT_PLUS_CNT_RST_U7_S 14
+/* PCNT_CNT_PAUSE_U6 : R/W ;bitpos:[13] ;default: 1'b0 ; */
+/*description: Set this bit to pause unit6's counter.*/
+#define PCNT_CNT_PAUSE_U6 (BIT(13))
+#define PCNT_CNT_PAUSE_U6_M (BIT(13))
+#define PCNT_CNT_PAUSE_U6_V 0x1
+#define PCNT_CNT_PAUSE_U6_S 13
+/* PCNT_PLUS_CNT_RST_U6 : R/W ;bitpos:[12] ;default: 1'b1 ; */
+/*description: Set this bit to clear unit6's counter.*/
+#define PCNT_PLUS_CNT_RST_U6 (BIT(12))
+#define PCNT_PLUS_CNT_RST_U6_M (BIT(12))
+#define PCNT_PLUS_CNT_RST_U6_V 0x1
+#define PCNT_PLUS_CNT_RST_U6_S 12
+/* PCNT_CNT_PAUSE_U5 : R/W ;bitpos:[11] ;default: 1'b0 ; */
+/*description: Set this bit to pause unit5's counter.*/
+#define PCNT_CNT_PAUSE_U5 (BIT(11))
+#define PCNT_CNT_PAUSE_U5_M (BIT(11))
+#define PCNT_CNT_PAUSE_U5_V 0x1
+#define PCNT_CNT_PAUSE_U5_S 11
+/* PCNT_PLUS_CNT_RST_U5 : R/W ;bitpos:[10] ;default: 1'b1 ; */
+/*description: Set this bit to clear unit5's counter.*/
+#define PCNT_PLUS_CNT_RST_U5 (BIT(10))
+#define PCNT_PLUS_CNT_RST_U5_M (BIT(10))
+#define PCNT_PLUS_CNT_RST_U5_V 0x1
+#define PCNT_PLUS_CNT_RST_U5_S 10
+/* PCNT_CNT_PAUSE_U4 : R/W ;bitpos:[9] ;default: 1'b0 ; */
+/*description: Set this bit to pause unit4's counter.*/
+#define PCNT_CNT_PAUSE_U4 (BIT(9))
+#define PCNT_CNT_PAUSE_U4_M (BIT(9))
+#define PCNT_CNT_PAUSE_U4_V 0x1
+#define PCNT_CNT_PAUSE_U4_S 9
+/* PCNT_PLUS_CNT_RST_U4 : R/W ;bitpos:[8] ;default: 1'b1 ; */
+/*description: Set this bit to clear unit4's counter.*/
+#define PCNT_PLUS_CNT_RST_U4 (BIT(8))
+#define PCNT_PLUS_CNT_RST_U4_M (BIT(8))
+#define PCNT_PLUS_CNT_RST_U4_V 0x1
+#define PCNT_PLUS_CNT_RST_U4_S 8
+/* PCNT_CNT_PAUSE_U3 : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: Set this bit to pause unit3's counter.*/
+#define PCNT_CNT_PAUSE_U3 (BIT(7))
+#define PCNT_CNT_PAUSE_U3_M (BIT(7))
+#define PCNT_CNT_PAUSE_U3_V 0x1
+#define PCNT_CNT_PAUSE_U3_S 7
+/* PCNT_PLUS_CNT_RST_U3 : R/W ;bitpos:[6] ;default: 1'b1 ; */
+/*description: Set this bit to clear unit3's counter.*/
+#define PCNT_PLUS_CNT_RST_U3 (BIT(6))
+#define PCNT_PLUS_CNT_RST_U3_M (BIT(6))
+#define PCNT_PLUS_CNT_RST_U3_V 0x1
+#define PCNT_PLUS_CNT_RST_U3_S 6
+/* PCNT_CNT_PAUSE_U2 : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: Set this bit to pause unit2's counter.*/
+#define PCNT_CNT_PAUSE_U2 (BIT(5))
+#define PCNT_CNT_PAUSE_U2_M (BIT(5))
+#define PCNT_CNT_PAUSE_U2_V 0x1
+#define PCNT_CNT_PAUSE_U2_S 5
+/* PCNT_PLUS_CNT_RST_U2 : R/W ;bitpos:[4] ;default: 1'b1 ; */
+/*description: Set this bit to clear unit2's counter.*/
+#define PCNT_PLUS_CNT_RST_U2 (BIT(4))
+#define PCNT_PLUS_CNT_RST_U2_M (BIT(4))
+#define PCNT_PLUS_CNT_RST_U2_V 0x1
+#define PCNT_PLUS_CNT_RST_U2_S 4
+/* PCNT_CNT_PAUSE_U1 : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: Set this bit to pause unit1's counter.*/
+#define PCNT_CNT_PAUSE_U1 (BIT(3))
+#define PCNT_CNT_PAUSE_U1_M (BIT(3))
+#define PCNT_CNT_PAUSE_U1_V 0x1
+#define PCNT_CNT_PAUSE_U1_S 3
+/* PCNT_PLUS_CNT_RST_U1 : R/W ;bitpos:[2] ;default: 1'b1 ; */
+/*description: Set this bit to clear unit1's counter.*/
+#define PCNT_PLUS_CNT_RST_U1 (BIT(2))
+#define PCNT_PLUS_CNT_RST_U1_M (BIT(2))
+#define PCNT_PLUS_CNT_RST_U1_V 0x1
+#define PCNT_PLUS_CNT_RST_U1_S 2
+/* PCNT_CNT_PAUSE_U0 : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: Set this bit to pause unit0's counter.*/
+#define PCNT_CNT_PAUSE_U0 (BIT(1))
+#define PCNT_CNT_PAUSE_U0_M (BIT(1))
+#define PCNT_CNT_PAUSE_U0_V 0x1
+#define PCNT_CNT_PAUSE_U0_S 1
+/* PCNT_PLUS_CNT_RST_U0 : R/W ;bitpos:[0] ;default: 1'b1 ; */
+/*description: Set this bit to clear unit0's counter.*/
+#define PCNT_PLUS_CNT_RST_U0 (BIT(0))
+#define PCNT_PLUS_CNT_RST_U0_M (BIT(0))
+#define PCNT_PLUS_CNT_RST_U0_V 0x1
+#define PCNT_PLUS_CNT_RST_U0_S 0
+
+#define PCNT_DATE_REG (DR_REG_PCNT_BASE + 0x00fc)
+/* PCNT_DATE : R/W ;bitpos:[31:0] ;default: 32'h14122600 ; */
+/*description: */
+#define PCNT_DATE 0xFFFFFFFF
+#define PCNT_DATE_M ((PCNT_DATE_V)<<(PCNT_DATE_S))
+#define PCNT_DATE_V 0xFFFFFFFF
+#define PCNT_DATE_S 0
+
+
+
+
+#endif /*_SOC_PCNT_REG_H_ */
+
+
-// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD\r
-//\r
-// Licensed under the Apache License, Version 2.0 (the "License");\r
-// you may not use this file except in compliance with the License.\r
-// You may obtain a copy of the License at\r
-\r
-// http://www.apache.org/licenses/LICENSE-2.0\r
-//\r
-// Unless required by applicable law or agreed to in writing, software\r
-// distributed under the License is distributed on an "AS IS" BASIS,\r
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
-// See the License for the specific language governing permissions and\r
-// limitations under the License.\r
-#ifndef _SOC_RMT_REG_H_\r
-#define _SOC_RMT_REG_H_\r
-\r
-#include "soc.h"\r
-#define RMT_CH0DATA_REG (DR_REG_RMT_BASE + 0x0000)\r
-\r
-#define RMT_CH1DATA_REG (DR_REG_RMT_BASE + 0x0004)\r
-\r
-#define RMT_CH2DATA_REG (DR_REG_RMT_BASE + 0x0008)\r
-\r
-#define RMT_CH3DATA_REG (DR_REG_RMT_BASE + 0x000c)\r
-\r
-#define RMT_CH4DATA_REG (DR_REG_RMT_BASE + 0x0010)\r
-\r
-#define RMT_CH5DATA_REG (DR_REG_RMT_BASE + 0x0014)\r
-\r
-#define RMT_CH6DATA_REG (DR_REG_RMT_BASE + 0x0018)\r
-\r
-#define RMT_CH7DATA_REG (DR_REG_RMT_BASE + 0x001c)\r
-\r
-#define RMT_CH0CONF0_REG (DR_REG_RMT_BASE + 0x0020)\r
-/* RMT_CLK_EN : R/W ;bitpos:[31] ;default: 1'h0 ; */\r
-/*description: This bit is used to control clock.when software config RMT\r
- internal registers it controls the register clock.*/\r
-#define RMT_CLK_EN (BIT(31))\r
-#define RMT_CLK_EN_M (BIT(31))\r
-#define RMT_CLK_EN_V 0x1\r
-#define RMT_CLK_EN_S 31\r
-/* RMT_MEM_PD : R/W ;bitpos:[30] ;default: 1'b0 ; */\r
-/*description: This bit is used to reduce power consumed by mem. 1:mem is in low power state.*/\r
-#define RMT_MEM_PD (BIT(30))\r
-#define RMT_MEM_PD_M (BIT(30))\r
-#define RMT_MEM_PD_V 0x1\r
-#define RMT_MEM_PD_S 30\r
-/* RMT_CARRIER_OUT_LV_CH0 : R/W ;bitpos:[29] ;default: 1'b1 ; */\r
-/*description: This bit is used to configure the way carrier wave is modulated\r
- for channel0.1'b1:transmit on low output level 1'b0:transmit on high output level.*/\r
-#define RMT_CARRIER_OUT_LV_CH0 (BIT(29))\r
-#define RMT_CARRIER_OUT_LV_CH0_M (BIT(29))\r
-#define RMT_CARRIER_OUT_LV_CH0_V 0x1\r
-#define RMT_CARRIER_OUT_LV_CH0_S 29\r
-/* RMT_CARRIER_EN_CH0 : R/W ;bitpos:[28] ;default: 1'b1 ; */\r
-/*description: This is the carrier modulation enable control bit for channel0.*/\r
-#define RMT_CARRIER_EN_CH0 (BIT(28))\r
-#define RMT_CARRIER_EN_CH0_M (BIT(28))\r
-#define RMT_CARRIER_EN_CH0_V 0x1\r
-#define RMT_CARRIER_EN_CH0_S 28\r
-/* RMT_MEM_SIZE_CH0 : R/W ;bitpos:[27:24] ;default: 4'h1 ; */\r
-/*description: This register is used to configure the the amount of memory blocks\r
- allocated to channel0.*/\r
-#define RMT_MEM_SIZE_CH0 0x0000000F\r
-#define RMT_MEM_SIZE_CH0_M ((RMT_MEM_SIZE_CH0_V)<<(RMT_MEM_SIZE_CH0_S))\r
-#define RMT_MEM_SIZE_CH0_V 0xF\r
-#define RMT_MEM_SIZE_CH0_S 24\r
-/* RMT_IDLE_THRES_CH0 : R/W ;bitpos:[23:8] ;default: 16'h1000 ; */\r
-/*description: In receive mode when no edge is detected on the input signal\r
- for longer than reg_idle_thres_ch0 then the receive process is done.*/\r
-#define RMT_IDLE_THRES_CH0 0x0000FFFF\r
-#define RMT_IDLE_THRES_CH0_M ((RMT_IDLE_THRES_CH0_V)<<(RMT_IDLE_THRES_CH0_S))\r
-#define RMT_IDLE_THRES_CH0_V 0xFFFF\r
-#define RMT_IDLE_THRES_CH0_S 8\r
-/* RMT_DIV_CNT_CH0 : R/W ;bitpos:[7:0] ;default: 8'h2 ; */\r
-/*description: This register is used to configure the frequency divider's factor in channel0.*/\r
-#define RMT_DIV_CNT_CH0 0x000000FF\r
-#define RMT_DIV_CNT_CH0_M ((RMT_DIV_CNT_CH0_V)<<(RMT_DIV_CNT_CH0_S))\r
-#define RMT_DIV_CNT_CH0_V 0xFF\r
-#define RMT_DIV_CNT_CH0_S 0\r
-\r
-#define RMT_CH0CONF1_REG (DR_REG_RMT_BASE + 0x0024)\r
-/* RMT_IDLE_OUT_EN_CH0 : R/W ;bitpos:[19] ;default: 1'b0 ; */\r
-/*description: This is the output enable control bit for channel0 in IDLE state.*/\r
-#define RMT_IDLE_OUT_EN_CH0 (BIT(19))\r
-#define RMT_IDLE_OUT_EN_CH0_M (BIT(19))\r
-#define RMT_IDLE_OUT_EN_CH0_V 0x1\r
-#define RMT_IDLE_OUT_EN_CH0_S 19\r
-/* RMT_IDLE_OUT_LV_CH0 : R/W ;bitpos:[18] ;default: 1'b0 ; */\r
-/*description: This bit configures the output signal's level for channel0 in IDLE state.*/\r
-#define RMT_IDLE_OUT_LV_CH0 (BIT(18))\r
-#define RMT_IDLE_OUT_LV_CH0_M (BIT(18))\r
-#define RMT_IDLE_OUT_LV_CH0_V 0x1\r
-#define RMT_IDLE_OUT_LV_CH0_S 18\r
-/* RMT_REF_ALWAYS_ON_CH0 : R/W ;bitpos:[17] ;default: 1'b0 ; */\r
-/*description: This bit is used to select base clock. 1'b1:clk_apb 1'b0:clk_ref*/\r
-#define RMT_REF_ALWAYS_ON_CH0 (BIT(17))\r
-#define RMT_REF_ALWAYS_ON_CH0_M (BIT(17))\r
-#define RMT_REF_ALWAYS_ON_CH0_V 0x1\r
-#define RMT_REF_ALWAYS_ON_CH0_S 17\r
-/* RMT_REF_CNT_RST_CH0 : R/W ;bitpos:[16] ;default: 1'b0 ; */\r
-/*description: This bit is used to reset divider in channel0.*/\r
-#define RMT_REF_CNT_RST_CH0 (BIT(16))\r
-#define RMT_REF_CNT_RST_CH0_M (BIT(16))\r
-#define RMT_REF_CNT_RST_CH0_V 0x1\r
-#define RMT_REF_CNT_RST_CH0_S 16\r
-/* RMT_RX_FILTER_THRES_CH0 : R/W ;bitpos:[15:8] ;default: 8'hf ; */\r
-/*description: in receive mode channel0 ignore input pulse when the pulse width\r
- is smaller then this value.*/\r
-#define RMT_RX_FILTER_THRES_CH0 0x000000FF\r
-#define RMT_RX_FILTER_THRES_CH0_M ((RMT_RX_FILTER_THRES_CH0_V)<<(RMT_RX_FILTER_THRES_CH0_S))\r
-#define RMT_RX_FILTER_THRES_CH0_V 0xFF\r
-#define RMT_RX_FILTER_THRES_CH0_S 8\r
-/* RMT_RX_FILTER_EN_CH0 : R/W ;bitpos:[7] ;default: 1'b0 ; */\r
-/*description: This is the receive filter enable bit for channel0.*/\r
-#define RMT_RX_FILTER_EN_CH0 (BIT(7))\r
-#define RMT_RX_FILTER_EN_CH0_M (BIT(7))\r
-#define RMT_RX_FILTER_EN_CH0_V 0x1\r
-#define RMT_RX_FILTER_EN_CH0_S 7\r
-/* RMT_TX_CONTI_MODE_CH0 : R/W ;bitpos:[6] ;default: 1'b0 ; */\r
-/*description: Set this bit to continue sending from the first data to the\r
- last data in channel0 again and again.*/\r
-#define RMT_TX_CONTI_MODE_CH0 (BIT(6))\r
-#define RMT_TX_CONTI_MODE_CH0_M (BIT(6))\r
-#define RMT_TX_CONTI_MODE_CH0_V 0x1\r
-#define RMT_TX_CONTI_MODE_CH0_S 6\r
-/* RMT_MEM_OWNER_CH0 : R/W ;bitpos:[5] ;default: 1'b1 ; */\r
-/*description: This is the mark of channel0's ram usage right.1'b1：receiver\r
- uses the ram 0：transmitter uses the ram*/\r
-#define RMT_MEM_OWNER_CH0 (BIT(5))\r
-#define RMT_MEM_OWNER_CH0_M (BIT(5))\r
-#define RMT_MEM_OWNER_CH0_V 0x1\r
-#define RMT_MEM_OWNER_CH0_S 5\r
-/* RMT_APB_MEM_RST_CH0 : R/W ;bitpos:[4] ;default: 1'b0 ; */\r
-/*description: Set this bit to reset W/R ram address for channel0 by apb fifo access*/\r
-#define RMT_APB_MEM_RST_CH0 (BIT(4))\r
-#define RMT_APB_MEM_RST_CH0_M (BIT(4))\r
-#define RMT_APB_MEM_RST_CH0_V 0x1\r
-#define RMT_APB_MEM_RST_CH0_S 4\r
-/* RMT_MEM_RD_RST_CH0 : R/W ;bitpos:[3] ;default: 1'b0 ; */\r
-/*description: Set this bit to reset read ram address for channel0 by transmitter access.*/\r
-#define RMT_MEM_RD_RST_CH0 (BIT(3))\r
-#define RMT_MEM_RD_RST_CH0_M (BIT(3))\r
-#define RMT_MEM_RD_RST_CH0_V 0x1\r
-#define RMT_MEM_RD_RST_CH0_S 3\r
-/* RMT_MEM_WR_RST_CH0 : R/W ;bitpos:[2] ;default: 1'h0 ; */\r
-/*description: Set this bit to reset write ram address for channel0 by receiver access.*/\r
-#define RMT_MEM_WR_RST_CH0 (BIT(2))\r
-#define RMT_MEM_WR_RST_CH0_M (BIT(2))\r
-#define RMT_MEM_WR_RST_CH0_V 0x1\r
-#define RMT_MEM_WR_RST_CH0_S 2\r
-/* RMT_RX_EN_CH0 : R/W ;bitpos:[1] ;default: 1'h0 ; */\r
-/*description: Set this bit to enbale receving data for channel0.*/\r
-#define RMT_RX_EN_CH0 (BIT(1))\r
-#define RMT_RX_EN_CH0_M (BIT(1))\r
-#define RMT_RX_EN_CH0_V 0x1\r
-#define RMT_RX_EN_CH0_S 1\r
-/* RMT_TX_START_CH0 : R/W ;bitpos:[0] ;default: 1'h0 ; */\r
-/*description: Set this bit to start sending data for channel0.*/\r
-#define RMT_TX_START_CH0 (BIT(0))\r
-#define RMT_TX_START_CH0_M (BIT(0))\r
-#define RMT_TX_START_CH0_V 0x1\r
-#define RMT_TX_START_CH0_S 0\r
-\r
-#define RMT_CH1CONF0_REG (DR_REG_RMT_BASE + 0x0028)\r
-/* RMT_CARRIER_OUT_LV_CH1 : R/W ;bitpos:[29] ;default: 1'b1 ; */\r
-/*description: This bit is used to configure the way carrier wave is modulated\r
- for channel1.1'b1:transmit on low output level 1'b0:transmit on high output level.*/\r
-#define RMT_CARRIER_OUT_LV_CH1 (BIT(29))\r
-#define RMT_CARRIER_OUT_LV_CH1_M (BIT(29))\r
-#define RMT_CARRIER_OUT_LV_CH1_V 0x1\r
-#define RMT_CARRIER_OUT_LV_CH1_S 29\r
-/* RMT_CARRIER_EN_CH1 : R/W ;bitpos:[28] ;default: 1'b1 ; */\r
-/*description: This is the carrier modulation enable control bit for channel1.*/\r
-#define RMT_CARRIER_EN_CH1 (BIT(28))\r
-#define RMT_CARRIER_EN_CH1_M (BIT(28))\r
-#define RMT_CARRIER_EN_CH1_V 0x1\r
-#define RMT_CARRIER_EN_CH1_S 28\r
-/* RMT_MEM_SIZE_CH1 : R/W ;bitpos:[27:24] ;default: 4'h1 ; */\r
-/*description: This register is used to configure the the amount of memory blocks\r
- allocated to channel1.*/\r
-#define RMT_MEM_SIZE_CH1 0x0000000F\r
-#define RMT_MEM_SIZE_CH1_M ((RMT_MEM_SIZE_CH1_V)<<(RMT_MEM_SIZE_CH1_S))\r
-#define RMT_MEM_SIZE_CH1_V 0xF\r
-#define RMT_MEM_SIZE_CH1_S 24\r
-/* RMT_IDLE_THRES_CH1 : R/W ;bitpos:[23:8] ;default: 16'h1000 ; */\r
-/*description: This register is used to configure the the amount of memory blocks\r
- allocated to channel1.*/\r
-#define RMT_IDLE_THRES_CH1 0x0000FFFF\r
-#define RMT_IDLE_THRES_CH1_M ((RMT_IDLE_THRES_CH1_V)<<(RMT_IDLE_THRES_CH1_S))\r
-#define RMT_IDLE_THRES_CH1_V 0xFFFF\r
-#define RMT_IDLE_THRES_CH1_S 8\r
-/* RMT_DIV_CNT_CH1 : R/W ;bitpos:[7:0] ;default: 8'h2 ; */\r
-/*description: This register is used to configure the frequency divider's factor in channel1.*/\r
-#define RMT_DIV_CNT_CH1 0x000000FF\r
-#define RMT_DIV_CNT_CH1_M ((RMT_DIV_CNT_CH1_V)<<(RMT_DIV_CNT_CH1_S))\r
-#define RMT_DIV_CNT_CH1_V 0xFF\r
-#define RMT_DIV_CNT_CH1_S 0\r
-\r
-#define RMT_CH1CONF1_REG (DR_REG_RMT_BASE + 0x002c)\r
-/* RMT_IDLE_OUT_EN_CH1 : R/W ;bitpos:[19] ;default: 1'b0 ; */\r
-/*description: This is the output enable control bit for channel1 in IDLE state.*/\r
-#define RMT_IDLE_OUT_EN_CH1 (BIT(19))\r
-#define RMT_IDLE_OUT_EN_CH1_M (BIT(19))\r
-#define RMT_IDLE_OUT_EN_CH1_V 0x1\r
-#define RMT_IDLE_OUT_EN_CH1_S 19\r
-/* RMT_IDLE_OUT_LV_CH1 : R/W ;bitpos:[18] ;default: 1'b0 ; */\r
-/*description: This bit configures the output signal's level for channel1 in IDLE state.*/\r
-#define RMT_IDLE_OUT_LV_CH1 (BIT(18))\r
-#define RMT_IDLE_OUT_LV_CH1_M (BIT(18))\r
-#define RMT_IDLE_OUT_LV_CH1_V 0x1\r
-#define RMT_IDLE_OUT_LV_CH1_S 18\r
-/* RMT_REF_ALWAYS_ON_CH1 : R/W ;bitpos:[17] ;default: 1'b0 ; */\r
-/*description: This bit is used to select base clock. 1'b1:clk_apb 1'b0:clk_ref*/\r
-#define RMT_REF_ALWAYS_ON_CH1 (BIT(17))\r
-#define RMT_REF_ALWAYS_ON_CH1_M (BIT(17))\r
-#define RMT_REF_ALWAYS_ON_CH1_V 0x1\r
-#define RMT_REF_ALWAYS_ON_CH1_S 17\r
-/* RMT_REF_CNT_RST_CH1 : R/W ;bitpos:[16] ;default: 1'b0 ; */\r
-/*description: This bit is used to reset divider in channel1.*/\r
-#define RMT_REF_CNT_RST_CH1 (BIT(16))\r
-#define RMT_REF_CNT_RST_CH1_M (BIT(16))\r
-#define RMT_REF_CNT_RST_CH1_V 0x1\r
-#define RMT_REF_CNT_RST_CH1_S 16\r
-/* RMT_RX_FILTER_THRES_CH1 : R/W ;bitpos:[15:8] ;default: 8'hf ; */\r
-/*description: in receive mode channel1 ignore input pulse when the pulse width\r
- is smaller then this value.*/\r
-#define RMT_RX_FILTER_THRES_CH1 0x000000FF\r
-#define RMT_RX_FILTER_THRES_CH1_M ((RMT_RX_FILTER_THRES_CH1_V)<<(RMT_RX_FILTER_THRES_CH1_S))\r
-#define RMT_RX_FILTER_THRES_CH1_V 0xFF\r
-#define RMT_RX_FILTER_THRES_CH1_S 8\r
-/* RMT_RX_FILTER_EN_CH1 : R/W ;bitpos:[7] ;default: 1'b0 ; */\r
-/*description: This is the receive filter enable bit for channel1.*/\r
-#define RMT_RX_FILTER_EN_CH1 (BIT(7))\r
-#define RMT_RX_FILTER_EN_CH1_M (BIT(7))\r
-#define RMT_RX_FILTER_EN_CH1_V 0x1\r
-#define RMT_RX_FILTER_EN_CH1_S 7\r
-/* RMT_TX_CONTI_MODE_CH1 : R/W ;bitpos:[6] ;default: 1'b0 ; */\r
-/*description: Set this bit to continue sending from the first data to the\r
- last data in channel1 again and again.*/\r
-#define RMT_TX_CONTI_MODE_CH1 (BIT(6))\r
-#define RMT_TX_CONTI_MODE_CH1_M (BIT(6))\r
-#define RMT_TX_CONTI_MODE_CH1_V 0x1\r
-#define RMT_TX_CONTI_MODE_CH1_S 6\r
-/* RMT_MEM_OWNER_CH1 : R/W ;bitpos:[5] ;default: 1'b1 ; */\r
-/*description: This is the mark of channel1's ram usage right.1'b1：receiver\r
- uses the ram 0：transmitter uses the ram*/\r
-#define RMT_MEM_OWNER_CH1 (BIT(5))\r
-#define RMT_MEM_OWNER_CH1_M (BIT(5))\r
-#define RMT_MEM_OWNER_CH1_V 0x1\r
-#define RMT_MEM_OWNER_CH1_S 5\r
-/* RMT_APB_MEM_RST_CH1 : R/W ;bitpos:[4] ;default: 1'b0 ; */\r
-/*description: Set this bit to reset W/R ram address for channel1 by apb fifo access*/\r
-#define RMT_APB_MEM_RST_CH1 (BIT(4))\r
-#define RMT_APB_MEM_RST_CH1_M (BIT(4))\r
-#define RMT_APB_MEM_RST_CH1_V 0x1\r
-#define RMT_APB_MEM_RST_CH1_S 4\r
-/* RMT_MEM_RD_RST_CH1 : R/W ;bitpos:[3] ;default: 1'b0 ; */\r
-/*description: Set this bit to reset read ram address for channel1 by transmitter access.*/\r
-#define RMT_MEM_RD_RST_CH1 (BIT(3))\r
-#define RMT_MEM_RD_RST_CH1_M (BIT(3))\r
-#define RMT_MEM_RD_RST_CH1_V 0x1\r
-#define RMT_MEM_RD_RST_CH1_S 3\r
-/* RMT_MEM_WR_RST_CH1 : R/W ;bitpos:[2] ;default: 1'h0 ; */\r
-/*description: Set this bit to reset write ram address for channel1 by receiver access.*/\r
-#define RMT_MEM_WR_RST_CH1 (BIT(2))\r
-#define RMT_MEM_WR_RST_CH1_M (BIT(2))\r
-#define RMT_MEM_WR_RST_CH1_V 0x1\r
-#define RMT_MEM_WR_RST_CH1_S 2\r
-/* RMT_RX_EN_CH1 : R/W ;bitpos:[1] ;default: 1'h0 ; */\r
-/*description: Set this bit to enbale receving data for channel1.*/\r
-#define RMT_RX_EN_CH1 (BIT(1))\r
-#define RMT_RX_EN_CH1_M (BIT(1))\r
-#define RMT_RX_EN_CH1_V 0x1\r
-#define RMT_RX_EN_CH1_S 1\r
-/* RMT_TX_START_CH1 : R/W ;bitpos:[0] ;default: 1'h0 ; */\r
-/*description: Set this bit to start sending data for channel1.*/\r
-#define RMT_TX_START_CH1 (BIT(0))\r
-#define RMT_TX_START_CH1_M (BIT(0))\r
-#define RMT_TX_START_CH1_V 0x1\r
-#define RMT_TX_START_CH1_S 0\r
-\r
-#define RMT_CH2CONF0_REG (DR_REG_RMT_BASE + 0x0030)\r
-/* RMT_CARRIER_OUT_LV_CH2 : R/W ;bitpos:[29] ;default: 1'b1 ; */\r
-/*description: This bit is used to configure carrier wave's position for channel2.1'b1:add\r
- on low level 1'b0:add on high level.*/\r
-#define RMT_CARRIER_OUT_LV_CH2 (BIT(29))\r
-#define RMT_CARRIER_OUT_LV_CH2_M (BIT(29))\r
-#define RMT_CARRIER_OUT_LV_CH2_V 0x1\r
-#define RMT_CARRIER_OUT_LV_CH2_S 29\r
-/* RMT_CARRIER_EN_CH2 : R/W ;bitpos:[28] ;default: 1'b1 ; */\r
-/*description: This is the carrier modulation enable control bit for channel2.*/\r
-#define RMT_CARRIER_EN_CH2 (BIT(28))\r
-#define RMT_CARRIER_EN_CH2_M (BIT(28))\r
-#define RMT_CARRIER_EN_CH2_V 0x1\r
-#define RMT_CARRIER_EN_CH2_S 28\r
-/* RMT_MEM_SIZE_CH2 : R/W ;bitpos:[27:24] ;default: 4'h1 ; */\r
-/*description: This register is used to configure the the amount of memory blocks\r
- allocated to channel2.*/\r
-#define RMT_MEM_SIZE_CH2 0x0000000F\r
-#define RMT_MEM_SIZE_CH2_M ((RMT_MEM_SIZE_CH2_V)<<(RMT_MEM_SIZE_CH2_S))\r
-#define RMT_MEM_SIZE_CH2_V 0xF\r
-#define RMT_MEM_SIZE_CH2_S 24\r
-/* RMT_IDLE_THRES_CH2 : R/W ;bitpos:[23:8] ;default: 16'h1000 ; */\r
-/*description: In receive mode when the counter's value is bigger than reg_idle_thres_ch2\r
- then the receive process is done.*/\r
-#define RMT_IDLE_THRES_CH2 0x0000FFFF\r
-#define RMT_IDLE_THRES_CH2_M ((RMT_IDLE_THRES_CH2_V)<<(RMT_IDLE_THRES_CH2_S))\r
-#define RMT_IDLE_THRES_CH2_V 0xFFFF\r
-#define RMT_IDLE_THRES_CH2_S 8\r
-/* RMT_DIV_CNT_CH2 : R/W ;bitpos:[7:0] ;default: 8'h2 ; */\r
-/*description: This register is used to configure the frequency divider's factor in channel2.*/\r
-#define RMT_DIV_CNT_CH2 0x000000FF\r
-#define RMT_DIV_CNT_CH2_M ((RMT_DIV_CNT_CH2_V)<<(RMT_DIV_CNT_CH2_S))\r
-#define RMT_DIV_CNT_CH2_V 0xFF\r
-#define RMT_DIV_CNT_CH2_S 0\r
-\r
-#define RMT_CH2CONF1_REG (DR_REG_RMT_BASE + 0x0034)\r
-/* RMT_IDLE_OUT_EN_CH2 : R/W ;bitpos:[19] ;default: 1'b0 ; */\r
-/*description: This is the output enable control bit for channel2 in IDLE state.*/\r
-#define RMT_IDLE_OUT_EN_CH2 (BIT(19))\r
-#define RMT_IDLE_OUT_EN_CH2_M (BIT(19))\r
-#define RMT_IDLE_OUT_EN_CH2_V 0x1\r
-#define RMT_IDLE_OUT_EN_CH2_S 19\r
-/* RMT_IDLE_OUT_LV_CH2 : R/W ;bitpos:[18] ;default: 1'b0 ; */\r
-/*description: This bit configures the output signal's level for channel2 in IDLE state.*/\r
-#define RMT_IDLE_OUT_LV_CH2 (BIT(18))\r
-#define RMT_IDLE_OUT_LV_CH2_M (BIT(18))\r
-#define RMT_IDLE_OUT_LV_CH2_V 0x1\r
-#define RMT_IDLE_OUT_LV_CH2_S 18\r
-/* RMT_REF_ALWAYS_ON_CH2 : R/W ;bitpos:[17] ;default: 1'b0 ; */\r
-/*description: This bit is used to select base clock. 1'b1:clk_apb 1'b0:clk_ref*/\r
-#define RMT_REF_ALWAYS_ON_CH2 (BIT(17))\r
-#define RMT_REF_ALWAYS_ON_CH2_M (BIT(17))\r
-#define RMT_REF_ALWAYS_ON_CH2_V 0x1\r
-#define RMT_REF_ALWAYS_ON_CH2_S 17\r
-/* RMT_REF_CNT_RST_CH2 : R/W ;bitpos:[16] ;default: 1'b0 ; */\r
-/*description: This bit is used to reset divider in channel2.*/\r
-#define RMT_REF_CNT_RST_CH2 (BIT(16))\r
-#define RMT_REF_CNT_RST_CH2_M (BIT(16))\r
-#define RMT_REF_CNT_RST_CH2_V 0x1\r
-#define RMT_REF_CNT_RST_CH2_S 16\r
-/* RMT_RX_FILTER_THRES_CH2 : R/W ;bitpos:[15:8] ;default: 8'hf ; */\r
-/*description: in receive mode channel2 ignore input pulse when the pulse width\r
- is smaller then this value.*/\r
-#define RMT_RX_FILTER_THRES_CH2 0x000000FF\r
-#define RMT_RX_FILTER_THRES_CH2_M ((RMT_RX_FILTER_THRES_CH2_V)<<(RMT_RX_FILTER_THRES_CH2_S))\r
-#define RMT_RX_FILTER_THRES_CH2_V 0xFF\r
-#define RMT_RX_FILTER_THRES_CH2_S 8\r
-/* RMT_RX_FILTER_EN_CH2 : R/W ;bitpos:[7] ;default: 1'b0 ; */\r
-/*description: This is the receive filter enable bit for channel2.*/\r
-#define RMT_RX_FILTER_EN_CH2 (BIT(7))\r
-#define RMT_RX_FILTER_EN_CH2_M (BIT(7))\r
-#define RMT_RX_FILTER_EN_CH2_V 0x1\r
-#define RMT_RX_FILTER_EN_CH2_S 7\r
-/* RMT_TX_CONTI_MODE_CH2 : R/W ;bitpos:[6] ;default: 1'b0 ; */\r
-/*description: Set this bit to continue sending from the first data to the\r
- last data in channel2.*/\r
-#define RMT_TX_CONTI_MODE_CH2 (BIT(6))\r
-#define RMT_TX_CONTI_MODE_CH2_M (BIT(6))\r
-#define RMT_TX_CONTI_MODE_CH2_V 0x1\r
-#define RMT_TX_CONTI_MODE_CH2_S 6\r
-/* RMT_MEM_OWNER_CH2 : R/W ;bitpos:[5] ;default: 1'b1 ; */\r
-/*description: This is the mark of channel2's ram usage right.1'b1：receiver\r
- uses the ram 0：transmitter uses the ram*/\r
-#define RMT_MEM_OWNER_CH2 (BIT(5))\r
-#define RMT_MEM_OWNER_CH2_M (BIT(5))\r
-#define RMT_MEM_OWNER_CH2_V 0x1\r
-#define RMT_MEM_OWNER_CH2_S 5\r
-/* RMT_APB_MEM_RST_CH2 : R/W ;bitpos:[4] ;default: 1'b0 ; */\r
-/*description: Set this bit to reset W/R ram address for channel2 by apb fifo access*/\r
-#define RMT_APB_MEM_RST_CH2 (BIT(4))\r
-#define RMT_APB_MEM_RST_CH2_M (BIT(4))\r
-#define RMT_APB_MEM_RST_CH2_V 0x1\r
-#define RMT_APB_MEM_RST_CH2_S 4\r
-/* RMT_MEM_RD_RST_CH2 : R/W ;bitpos:[3] ;default: 1'b0 ; */\r
-/*description: Set this bit to reset read ram address for channel2 by transmitter access.*/\r
-#define RMT_MEM_RD_RST_CH2 (BIT(3))\r
-#define RMT_MEM_RD_RST_CH2_M (BIT(3))\r
-#define RMT_MEM_RD_RST_CH2_V 0x1\r
-#define RMT_MEM_RD_RST_CH2_S 3\r
-/* RMT_MEM_WR_RST_CH2 : R/W ;bitpos:[2] ;default: 1'h0 ; */\r
-/*description: Set this bit to reset write ram address for channel2 by receiver access.*/\r
-#define RMT_MEM_WR_RST_CH2 (BIT(2))\r
-#define RMT_MEM_WR_RST_CH2_M (BIT(2))\r
-#define RMT_MEM_WR_RST_CH2_V 0x1\r
-#define RMT_MEM_WR_RST_CH2_S 2\r
-/* RMT_RX_EN_CH2 : R/W ;bitpos:[1] ;default: 1'h0 ; */\r
-/*description: Set this bit to enbale receving data for channel2.*/\r
-#define RMT_RX_EN_CH2 (BIT(1))\r
-#define RMT_RX_EN_CH2_M (BIT(1))\r
-#define RMT_RX_EN_CH2_V 0x1\r
-#define RMT_RX_EN_CH2_S 1\r
-/* RMT_TX_START_CH2 : R/W ;bitpos:[0] ;default: 1'h0 ; */\r
-/*description: Set this bit to start sending data for channel2.*/\r
-#define RMT_TX_START_CH2 (BIT(0))\r
-#define RMT_TX_START_CH2_M (BIT(0))\r
-#define RMT_TX_START_CH2_V 0x1\r
-#define RMT_TX_START_CH2_S 0\r
-\r
-#define RMT_CH3CONF0_REG (DR_REG_RMT_BASE + 0x0038)\r
-/* RMT_CARRIER_OUT_LV_CH3 : R/W ;bitpos:[29] ;default: 1'b1 ; */\r
-/*description: This bit is used to configure carrier wave's position for channel3.1'b1:add\r
- on low level 1'b0:add on high level.*/\r
-#define RMT_CARRIER_OUT_LV_CH3 (BIT(29))\r
-#define RMT_CARRIER_OUT_LV_CH3_M (BIT(29))\r
-#define RMT_CARRIER_OUT_LV_CH3_V 0x1\r
-#define RMT_CARRIER_OUT_LV_CH3_S 29\r
-/* RMT_CARRIER_EN_CH3 : R/W ;bitpos:[28] ;default: 1'b1 ; */\r
-/*description: This is the carrier modulation enable control bit for channel3.*/\r
-#define RMT_CARRIER_EN_CH3 (BIT(28))\r
-#define RMT_CARRIER_EN_CH3_M (BIT(28))\r
-#define RMT_CARRIER_EN_CH3_V 0x1\r
-#define RMT_CARRIER_EN_CH3_S 28\r
-/* RMT_MEM_SIZE_CH3 : R/W ;bitpos:[27:24] ;default: 4'h1 ; */\r
-/*description: This register is used to configure the the amount of memory blocks\r
- allocated to channel3.*/\r
-#define RMT_MEM_SIZE_CH3 0x0000000F\r
-#define RMT_MEM_SIZE_CH3_M ((RMT_MEM_SIZE_CH3_V)<<(RMT_MEM_SIZE_CH3_S))\r
-#define RMT_MEM_SIZE_CH3_V 0xF\r
-#define RMT_MEM_SIZE_CH3_S 24\r
-/* RMT_IDLE_THRES_CH3 : R/W ;bitpos:[23:8] ;default: 16'h1000 ; */\r
-/*description: In receive mode when the counter's value is bigger than reg_idle_thres_ch3\r
- then the receive process is done.*/\r
-#define RMT_IDLE_THRES_CH3 0x0000FFFF\r
-#define RMT_IDLE_THRES_CH3_M ((RMT_IDLE_THRES_CH3_V)<<(RMT_IDLE_THRES_CH3_S))\r
-#define RMT_IDLE_THRES_CH3_V 0xFFFF\r
-#define RMT_IDLE_THRES_CH3_S 8\r
-/* RMT_DIV_CNT_CH3 : R/W ;bitpos:[7:0] ;default: 8'h2 ; */\r
-/*description: This register is used to configure the frequency divider's factor in channel3.*/\r
-#define RMT_DIV_CNT_CH3 0x000000FF\r
-#define RMT_DIV_CNT_CH3_M ((RMT_DIV_CNT_CH3_V)<<(RMT_DIV_CNT_CH3_S))\r
-#define RMT_DIV_CNT_CH3_V 0xFF\r
-#define RMT_DIV_CNT_CH3_S 0\r
-\r
-#define RMT_CH3CONF1_REG (DR_REG_RMT_BASE + 0x003c)\r
-/* RMT_IDLE_OUT_EN_CH3 : R/W ;bitpos:[19] ;default: 1'b0 ; */\r
-/*description: This is the output enable control bit for channel3 in IDLE state.*/\r
-#define RMT_IDLE_OUT_EN_CH3 (BIT(19))\r
-#define RMT_IDLE_OUT_EN_CH3_M (BIT(19))\r
-#define RMT_IDLE_OUT_EN_CH3_V 0x1\r
-#define RMT_IDLE_OUT_EN_CH3_S 19\r
-/* RMT_IDLE_OUT_LV_CH3 : R/W ;bitpos:[18] ;default: 1'b0 ; */\r
-/*description: This bit configures the output signal's level for channel3 in IDLE state.*/\r
-#define RMT_IDLE_OUT_LV_CH3 (BIT(18))\r
-#define RMT_IDLE_OUT_LV_CH3_M (BIT(18))\r
-#define RMT_IDLE_OUT_LV_CH3_V 0x1\r
-#define RMT_IDLE_OUT_LV_CH3_S 18\r
-/* RMT_REF_ALWAYS_ON_CH3 : R/W ;bitpos:[17] ;default: 1'b0 ; */\r
-/*description: This bit is used to select base clock. 1'b1:clk_apb 1'b0:clk_ref*/\r
-#define RMT_REF_ALWAYS_ON_CH3 (BIT(17))\r
-#define RMT_REF_ALWAYS_ON_CH3_M (BIT(17))\r
-#define RMT_REF_ALWAYS_ON_CH3_V 0x1\r
-#define RMT_REF_ALWAYS_ON_CH3_S 17\r
-/* RMT_REF_CNT_RST_CH3 : R/W ;bitpos:[16] ;default: 1'b0 ; */\r
-/*description: This bit is used to reset divider in channel3.*/\r
-#define RMT_REF_CNT_RST_CH3 (BIT(16))\r
-#define RMT_REF_CNT_RST_CH3_M (BIT(16))\r
-#define RMT_REF_CNT_RST_CH3_V 0x1\r
-#define RMT_REF_CNT_RST_CH3_S 16\r
-/* RMT_RX_FILTER_THRES_CH3 : R/W ;bitpos:[15:8] ;default: 8'hf ; */\r
-/*description: in receive mode channel3 ignore input pulse when the pulse width\r
- is smaller then this value.*/\r
-#define RMT_RX_FILTER_THRES_CH3 0x000000FF\r
-#define RMT_RX_FILTER_THRES_CH3_M ((RMT_RX_FILTER_THRES_CH3_V)<<(RMT_RX_FILTER_THRES_CH3_S))\r
-#define RMT_RX_FILTER_THRES_CH3_V 0xFF\r
-#define RMT_RX_FILTER_THRES_CH3_S 8\r
-/* RMT_RX_FILTER_EN_CH3 : R/W ;bitpos:[7] ;default: 1'b0 ; */\r
-/*description: This is the receive filter enable bit for channel3.*/\r
-#define RMT_RX_FILTER_EN_CH3 (BIT(7))\r
-#define RMT_RX_FILTER_EN_CH3_M (BIT(7))\r
-#define RMT_RX_FILTER_EN_CH3_V 0x1\r
-#define RMT_RX_FILTER_EN_CH3_S 7\r
-/* RMT_TX_CONTI_MODE_CH3 : R/W ;bitpos:[6] ;default: 1'b0 ; */\r
-/*description: Set this bit to continue sending from the first data to the\r
- last data in channel3.*/\r
-#define RMT_TX_CONTI_MODE_CH3 (BIT(6))\r
-#define RMT_TX_CONTI_MODE_CH3_M (BIT(6))\r
-#define RMT_TX_CONTI_MODE_CH3_V 0x1\r
-#define RMT_TX_CONTI_MODE_CH3_S 6\r
-/* RMT_MEM_OWNER_CH3 : R/W ;bitpos:[5] ;default: 1'b1 ; */\r
-/*description: This is the mark of channel3's ram usage right.1'b1：receiver\r
- uses the ram 0：transmitter uses the ram*/\r
-#define RMT_MEM_OWNER_CH3 (BIT(5))\r
-#define RMT_MEM_OWNER_CH3_M (BIT(5))\r
-#define RMT_MEM_OWNER_CH3_V 0x1\r
-#define RMT_MEM_OWNER_CH3_S 5\r
-/* RMT_APB_MEM_RST_CH3 : R/W ;bitpos:[4] ;default: 1'b0 ; */\r
-/*description: Set this bit to reset W/R ram address for channel3 by apb fifo access*/\r
-#define RMT_APB_MEM_RST_CH3 (BIT(4))\r
-#define RMT_APB_MEM_RST_CH3_M (BIT(4))\r
-#define RMT_APB_MEM_RST_CH3_V 0x1\r
-#define RMT_APB_MEM_RST_CH3_S 4\r
-/* RMT_MEM_RD_RST_CH3 : R/W ;bitpos:[3] ;default: 1'b0 ; */\r
-/*description: Set this bit to reset read ram address for channel3 by transmitter access.*/\r
-#define RMT_MEM_RD_RST_CH3 (BIT(3))\r
-#define RMT_MEM_RD_RST_CH3_M (BIT(3))\r
-#define RMT_MEM_RD_RST_CH3_V 0x1\r
-#define RMT_MEM_RD_RST_CH3_S 3\r
-/* RMT_MEM_WR_RST_CH3 : R/W ;bitpos:[2] ;default: 1'h0 ; */\r
-/*description: Set this bit to reset write ram address for channel3 by receiver access.*/\r
-#define RMT_MEM_WR_RST_CH3 (BIT(2))\r
-#define RMT_MEM_WR_RST_CH3_M (BIT(2))\r
-#define RMT_MEM_WR_RST_CH3_V 0x1\r
-#define RMT_MEM_WR_RST_CH3_S 2\r
-/* RMT_RX_EN_CH3 : R/W ;bitpos:[1] ;default: 1'h0 ; */\r
-/*description: Set this bit to enbale receving data for channel3.*/\r
-#define RMT_RX_EN_CH3 (BIT(1))\r
-#define RMT_RX_EN_CH3_M (BIT(1))\r
-#define RMT_RX_EN_CH3_V 0x1\r
-#define RMT_RX_EN_CH3_S 1\r
-/* RMT_TX_START_CH3 : R/W ;bitpos:[0] ;default: 1'h0 ; */\r
-/*description: Set this bit to start sending data for channel3.*/\r
-#define RMT_TX_START_CH3 (BIT(0))\r
-#define RMT_TX_START_CH3_M (BIT(0))\r
-#define RMT_TX_START_CH3_V 0x1\r
-#define RMT_TX_START_CH3_S 0\r
-\r
-#define RMT_CH4CONF0_REG (DR_REG_RMT_BASE + 0x0040)\r
-/* RMT_CARRIER_OUT_LV_CH4 : R/W ;bitpos:[29] ;default: 1'b1 ; */\r
-/*description: This bit is used to configure carrier wave's position for channel4.1'b1:add\r
- on low level 1'b0:add on high level.*/\r
-#define RMT_CARRIER_OUT_LV_CH4 (BIT(29))\r
-#define RMT_CARRIER_OUT_LV_CH4_M (BIT(29))\r
-#define RMT_CARRIER_OUT_LV_CH4_V 0x1\r
-#define RMT_CARRIER_OUT_LV_CH4_S 29\r
-/* RMT_CARRIER_EN_CH4 : R/W ;bitpos:[28] ;default: 1'b1 ; */\r
-/*description: This is the carrier modulation enable control bit for channel4.*/\r
-#define RMT_CARRIER_EN_CH4 (BIT(28))\r
-#define RMT_CARRIER_EN_CH4_M (BIT(28))\r
-#define RMT_CARRIER_EN_CH4_V 0x1\r
-#define RMT_CARRIER_EN_CH4_S 28\r
-/* RMT_MEM_SIZE_CH4 : R/W ;bitpos:[27:24] ;default: 4'h1 ; */\r
-/*description: This register is used to configure the the amount of memory blocks\r
- allocated to channel4.*/\r
-#define RMT_MEM_SIZE_CH4 0x0000000F\r
-#define RMT_MEM_SIZE_CH4_M ((RMT_MEM_SIZE_CH4_V)<<(RMT_MEM_SIZE_CH4_S))\r
-#define RMT_MEM_SIZE_CH4_V 0xF\r
-#define RMT_MEM_SIZE_CH4_S 24\r
-/* RMT_IDLE_THRES_CH4 : R/W ;bitpos:[23:8] ;default: 16'h1000 ; */\r
-/*description: In receive mode when the counter's value is bigger than reg_idle_thres_ch4\r
- then the receive process is done.*/\r
-#define RMT_IDLE_THRES_CH4 0x0000FFFF\r
-#define RMT_IDLE_THRES_CH4_M ((RMT_IDLE_THRES_CH4_V)<<(RMT_IDLE_THRES_CH4_S))\r
-#define RMT_IDLE_THRES_CH4_V 0xFFFF\r
-#define RMT_IDLE_THRES_CH4_S 8\r
-/* RMT_DIV_CNT_CH4 : R/W ;bitpos:[7:0] ;default: 8'h2 ; */\r
-/*description: This register is used to configure the frequency divider's factor in channel4.*/\r
-#define RMT_DIV_CNT_CH4 0x000000FF\r
-#define RMT_DIV_CNT_CH4_M ((RMT_DIV_CNT_CH4_V)<<(RMT_DIV_CNT_CH4_S))\r
-#define RMT_DIV_CNT_CH4_V 0xFF\r
-#define RMT_DIV_CNT_CH4_S 0\r
-\r
-#define RMT_CH4CONF1_REG (DR_REG_RMT_BASE + 0x0044)\r
-/* RMT_IDLE_OUT_EN_CH4 : R/W ;bitpos:[19] ;default: 1'b0 ; */\r
-/*description: This is the output enable control bit for channel4 in IDLE state.*/\r
-#define RMT_IDLE_OUT_EN_CH4 (BIT(19))\r
-#define RMT_IDLE_OUT_EN_CH4_M (BIT(19))\r
-#define RMT_IDLE_OUT_EN_CH4_V 0x1\r
-#define RMT_IDLE_OUT_EN_CH4_S 19\r
-/* RMT_IDLE_OUT_LV_CH4 : R/W ;bitpos:[18] ;default: 1'b0 ; */\r
-/*description: This bit configures the output signal's level for channel4 in IDLE state.*/\r
-#define RMT_IDLE_OUT_LV_CH4 (BIT(18))\r
-#define RMT_IDLE_OUT_LV_CH4_M (BIT(18))\r
-#define RMT_IDLE_OUT_LV_CH4_V 0x1\r
-#define RMT_IDLE_OUT_LV_CH4_S 18\r
-/* RMT_REF_ALWAYS_ON_CH4 : R/W ;bitpos:[17] ;default: 1'b0 ; */\r
-/*description: This bit is used to select base clock. 1'b1:clk_apb 1'b0:clk_ref*/\r
-#define RMT_REF_ALWAYS_ON_CH4 (BIT(17))\r
-#define RMT_REF_ALWAYS_ON_CH4_M (BIT(17))\r
-#define RMT_REF_ALWAYS_ON_CH4_V 0x1\r
-#define RMT_REF_ALWAYS_ON_CH4_S 17\r
-/* RMT_REF_CNT_RST_CH4 : R/W ;bitpos:[16] ;default: 1'b0 ; */\r
-/*description: This bit is used to reset divider in channel4.*/\r
-#define RMT_REF_CNT_RST_CH4 (BIT(16))\r
-#define RMT_REF_CNT_RST_CH4_M (BIT(16))\r
-#define RMT_REF_CNT_RST_CH4_V 0x1\r
-#define RMT_REF_CNT_RST_CH4_S 16\r
-/* RMT_RX_FILTER_THRES_CH4 : R/W ;bitpos:[15:8] ;default: 8'hf ; */\r
-/*description: in receive mode channel4 ignore input pulse when the pulse width\r
- is smaller then this value.*/\r
-#define RMT_RX_FILTER_THRES_CH4 0x000000FF\r
-#define RMT_RX_FILTER_THRES_CH4_M ((RMT_RX_FILTER_THRES_CH4_V)<<(RMT_RX_FILTER_THRES_CH4_S))\r
-#define RMT_RX_FILTER_THRES_CH4_V 0xFF\r
-#define RMT_RX_FILTER_THRES_CH4_S 8\r
-/* RMT_RX_FILTER_EN_CH4 : R/W ;bitpos:[7] ;default: 1'b0 ; */\r
-/*description: This is the receive filter enable bit for channel4.*/\r
-#define RMT_RX_FILTER_EN_CH4 (BIT(7))\r
-#define RMT_RX_FILTER_EN_CH4_M (BIT(7))\r
-#define RMT_RX_FILTER_EN_CH4_V 0x1\r
-#define RMT_RX_FILTER_EN_CH4_S 7\r
-/* RMT_TX_CONTI_MODE_CH4 : R/W ;bitpos:[6] ;default: 1'b0 ; */\r
-/*description: Set this bit to continue sending from the first data to the\r
- last data in channel4.*/\r
-#define RMT_TX_CONTI_MODE_CH4 (BIT(6))\r
-#define RMT_TX_CONTI_MODE_CH4_M (BIT(6))\r
-#define RMT_TX_CONTI_MODE_CH4_V 0x1\r
-#define RMT_TX_CONTI_MODE_CH4_S 6\r
-/* RMT_MEM_OWNER_CH4 : R/W ;bitpos:[5] ;default: 1'b1 ; */\r
-/*description: This is the mark of channel4's ram usage right.1'b1：receiver\r
- uses the ram 0：transmitter uses the ram*/\r
-#define RMT_MEM_OWNER_CH4 (BIT(5))\r
-#define RMT_MEM_OWNER_CH4_M (BIT(5))\r
-#define RMT_MEM_OWNER_CH4_V 0x1\r
-#define RMT_MEM_OWNER_CH4_S 5\r
-/* RMT_APB_MEM_RST_CH4 : R/W ;bitpos:[4] ;default: 1'b0 ; */\r
-/*description: Set this bit to reset W/R ram address for channel4 by apb fifo access*/\r
-#define RMT_APB_MEM_RST_CH4 (BIT(4))\r
-#define RMT_APB_MEM_RST_CH4_M (BIT(4))\r
-#define RMT_APB_MEM_RST_CH4_V 0x1\r
-#define RMT_APB_MEM_RST_CH4_S 4\r
-/* RMT_MEM_RD_RST_CH4 : R/W ;bitpos:[3] ;default: 1'b0 ; */\r
-/*description: Set this bit to reset read ram address for channel4 by transmitter access.*/\r
-#define RMT_MEM_RD_RST_CH4 (BIT(3))\r
-#define RMT_MEM_RD_RST_CH4_M (BIT(3))\r
-#define RMT_MEM_RD_RST_CH4_V 0x1\r
-#define RMT_MEM_RD_RST_CH4_S 3\r
-/* RMT_MEM_WR_RST_CH4 : R/W ;bitpos:[2] ;default: 1'h0 ; */\r
-/*description: Set this bit to reset write ram address for channel4 by receiver access.*/\r
-#define RMT_MEM_WR_RST_CH4 (BIT(2))\r
-#define RMT_MEM_WR_RST_CH4_M (BIT(2))\r
-#define RMT_MEM_WR_RST_CH4_V 0x1\r
-#define RMT_MEM_WR_RST_CH4_S 2\r
-/* RMT_RX_EN_CH4 : R/W ;bitpos:[1] ;default: 1'h0 ; */\r
-/*description: Set this bit to enbale receving data for channel4.*/\r
-#define RMT_RX_EN_CH4 (BIT(1))\r
-#define RMT_RX_EN_CH4_M (BIT(1))\r
-#define RMT_RX_EN_CH4_V 0x1\r
-#define RMT_RX_EN_CH4_S 1\r
-/* RMT_TX_START_CH4 : R/W ;bitpos:[0] ;default: 1'h0 ; */\r
-/*description: Set this bit to start sending data for channel4.*/\r
-#define RMT_TX_START_CH4 (BIT(0))\r
-#define RMT_TX_START_CH4_M (BIT(0))\r
-#define RMT_TX_START_CH4_V 0x1\r
-#define RMT_TX_START_CH4_S 0\r
-\r
-#define RMT_CH5CONF0_REG (DR_REG_RMT_BASE + 0x0048)\r
-/* RMT_CARRIER_OUT_LV_CH5 : R/W ;bitpos:[29] ;default: 1'b1 ; */\r
-/*description: This bit is used to configure carrier wave's position for channel5.1'b1:add\r
- on low level 1'b0:add on high level.*/\r
-#define RMT_CARRIER_OUT_LV_CH5 (BIT(29))\r
-#define RMT_CARRIER_OUT_LV_CH5_M (BIT(29))\r
-#define RMT_CARRIER_OUT_LV_CH5_V 0x1\r
-#define RMT_CARRIER_OUT_LV_CH5_S 29\r
-/* RMT_CARRIER_EN_CH5 : R/W ;bitpos:[28] ;default: 1'b1 ; */\r
-/*description: This is the carrier modulation enable control bit for channel5.*/\r
-#define RMT_CARRIER_EN_CH5 (BIT(28))\r
-#define RMT_CARRIER_EN_CH5_M (BIT(28))\r
-#define RMT_CARRIER_EN_CH5_V 0x1\r
-#define RMT_CARRIER_EN_CH5_S 28\r
-/* RMT_MEM_SIZE_CH5 : R/W ;bitpos:[27:24] ;default: 4'h1 ; */\r
-/*description: This register is used to configure the the amount of memory blocks\r
- allocated to channel5.*/\r
-#define RMT_MEM_SIZE_CH5 0x0000000F\r
-#define RMT_MEM_SIZE_CH5_M ((RMT_MEM_SIZE_CH5_V)<<(RMT_MEM_SIZE_CH5_S))\r
-#define RMT_MEM_SIZE_CH5_V 0xF\r
-#define RMT_MEM_SIZE_CH5_S 24\r
-/* RMT_IDLE_THRES_CH5 : R/W ;bitpos:[23:8] ;default: 16'h1000 ; */\r
-/*description: In receive mode when the counter's value is bigger than reg_idle_thres_ch5\r
- then the receive process is done.*/\r
-#define RMT_IDLE_THRES_CH5 0x0000FFFF\r
-#define RMT_IDLE_THRES_CH5_M ((RMT_IDLE_THRES_CH5_V)<<(RMT_IDLE_THRES_CH5_S))\r
-#define RMT_IDLE_THRES_CH5_V 0xFFFF\r
-#define RMT_IDLE_THRES_CH5_S 8\r
-/* RMT_DIV_CNT_CH5 : R/W ;bitpos:[7:0] ;default: 8'h2 ; */\r
-/*description: This register is used to configure the frequency divider's factor in channel5.*/\r
-#define RMT_DIV_CNT_CH5 0x000000FF\r
-#define RMT_DIV_CNT_CH5_M ((RMT_DIV_CNT_CH5_V)<<(RMT_DIV_CNT_CH5_S))\r
-#define RMT_DIV_CNT_CH5_V 0xFF\r
-#define RMT_DIV_CNT_CH5_S 0\r
-\r
-#define RMT_CH5CONF1_REG (DR_REG_RMT_BASE + 0x004c)\r
-/* RMT_IDLE_OUT_EN_CH5 : R/W ;bitpos:[19] ;default: 1'b0 ; */\r
-/*description: This is the output enable control bit for channel5 in IDLE state.*/\r
-#define RMT_IDLE_OUT_EN_CH5 (BIT(19))\r
-#define RMT_IDLE_OUT_EN_CH5_M (BIT(19))\r
-#define RMT_IDLE_OUT_EN_CH5_V 0x1\r
-#define RMT_IDLE_OUT_EN_CH5_S 19\r
-/* RMT_IDLE_OUT_LV_CH5 : R/W ;bitpos:[18] ;default: 1'b0 ; */\r
-/*description: This bit configures the output signal's level for channel5 in IDLE state.*/\r
-#define RMT_IDLE_OUT_LV_CH5 (BIT(18))\r
-#define RMT_IDLE_OUT_LV_CH5_M (BIT(18))\r
-#define RMT_IDLE_OUT_LV_CH5_V 0x1\r
-#define RMT_IDLE_OUT_LV_CH5_S 18\r
-/* RMT_REF_ALWAYS_ON_CH5 : R/W ;bitpos:[17] ;default: 1'b0 ; */\r
-/*description: This bit is used to select base clock. 1'b1:clk_apb 1'b0:clk_ref*/\r
-#define RMT_REF_ALWAYS_ON_CH5 (BIT(17))\r
-#define RMT_REF_ALWAYS_ON_CH5_M (BIT(17))\r
-#define RMT_REF_ALWAYS_ON_CH5_V 0x1\r
-#define RMT_REF_ALWAYS_ON_CH5_S 17\r
-/* RMT_REF_CNT_RST_CH5 : R/W ;bitpos:[16] ;default: 1'b0 ; */\r
-/*description: This bit is used to reset divider in channel5.*/\r
-#define RMT_REF_CNT_RST_CH5 (BIT(16))\r
-#define RMT_REF_CNT_RST_CH5_M (BIT(16))\r
-#define RMT_REF_CNT_RST_CH5_V 0x1\r
-#define RMT_REF_CNT_RST_CH5_S 16\r
-/* RMT_RX_FILTER_THRES_CH5 : R/W ;bitpos:[15:8] ;default: 8'hf ; */\r
-/*description: in receive mode channel5 ignore input pulse when the pulse width\r
- is smaller then this value.*/\r
-#define RMT_RX_FILTER_THRES_CH5 0x000000FF\r
-#define RMT_RX_FILTER_THRES_CH5_M ((RMT_RX_FILTER_THRES_CH5_V)<<(RMT_RX_FILTER_THRES_CH5_S))\r
-#define RMT_RX_FILTER_THRES_CH5_V 0xFF\r
-#define RMT_RX_FILTER_THRES_CH5_S 8\r
-/* RMT_RX_FILTER_EN_CH5 : R/W ;bitpos:[7] ;default: 1'b0 ; */\r
-/*description: This is the receive filter enable bit for channel5.*/\r
-#define RMT_RX_FILTER_EN_CH5 (BIT(7))\r
-#define RMT_RX_FILTER_EN_CH5_M (BIT(7))\r
-#define RMT_RX_FILTER_EN_CH5_V 0x1\r
-#define RMT_RX_FILTER_EN_CH5_S 7\r
-/* RMT_TX_CONTI_MODE_CH5 : R/W ;bitpos:[6] ;default: 1'b0 ; */\r
-/*description: Set this bit to continue sending from the first data to the\r
- last data in channel5.*/\r
-#define RMT_TX_CONTI_MODE_CH5 (BIT(6))\r
-#define RMT_TX_CONTI_MODE_CH5_M (BIT(6))\r
-#define RMT_TX_CONTI_MODE_CH5_V 0x1\r
-#define RMT_TX_CONTI_MODE_CH5_S 6\r
-/* RMT_MEM_OWNER_CH5 : R/W ;bitpos:[5] ;default: 1'b1 ; */\r
-/*description: This is the mark of channel5's ram usage right.1'b1：receiver\r
- uses the ram 0：transmitter uses the ram*/\r
-#define RMT_MEM_OWNER_CH5 (BIT(5))\r
-#define RMT_MEM_OWNER_CH5_M (BIT(5))\r
-#define RMT_MEM_OWNER_CH5_V 0x1\r
-#define RMT_MEM_OWNER_CH5_S 5\r
-/* RMT_APB_MEM_RST_CH5 : R/W ;bitpos:[4] ;default: 1'b0 ; */\r
-/*description: Set this bit to reset W/R ram address for channel5 by apb fifo access*/\r
-#define RMT_APB_MEM_RST_CH5 (BIT(4))\r
-#define RMT_APB_MEM_RST_CH5_M (BIT(4))\r
-#define RMT_APB_MEM_RST_CH5_V 0x1\r
-#define RMT_APB_MEM_RST_CH5_S 4\r
-/* RMT_MEM_RD_RST_CH5 : R/W ;bitpos:[3] ;default: 1'b0 ; */\r
-/*description: Set this bit to reset read ram address for channel5 by transmitter access.*/\r
-#define RMT_MEM_RD_RST_CH5 (BIT(3))\r
-#define RMT_MEM_RD_RST_CH5_M (BIT(3))\r
-#define RMT_MEM_RD_RST_CH5_V 0x1\r
-#define RMT_MEM_RD_RST_CH5_S 3\r
-/* RMT_MEM_WR_RST_CH5 : R/W ;bitpos:[2] ;default: 1'h0 ; */\r
-/*description: Set this bit to reset write ram address for channel5 by receiver access.*/\r
-#define RMT_MEM_WR_RST_CH5 (BIT(2))\r
-#define RMT_MEM_WR_RST_CH5_M (BIT(2))\r
-#define RMT_MEM_WR_RST_CH5_V 0x1\r
-#define RMT_MEM_WR_RST_CH5_S 2\r
-/* RMT_RX_EN_CH5 : R/W ;bitpos:[1] ;default: 1'h0 ; */\r
-/*description: Set this bit to enbale receving data for channel5.*/\r
-#define RMT_RX_EN_CH5 (BIT(1))\r
-#define RMT_RX_EN_CH5_M (BIT(1))\r
-#define RMT_RX_EN_CH5_V 0x1\r
-#define RMT_RX_EN_CH5_S 1\r
-/* RMT_TX_START_CH5 : R/W ;bitpos:[0] ;default: 1'h0 ; */\r
-/*description: Set this bit to start sending data for channel5.*/\r
-#define RMT_TX_START_CH5 (BIT(0))\r
-#define RMT_TX_START_CH5_M (BIT(0))\r
-#define RMT_TX_START_CH5_V 0x1\r
-#define RMT_TX_START_CH5_S 0\r
-\r
-#define RMT_CH6CONF0_REG (DR_REG_RMT_BASE + 0x0050)\r
-/* RMT_CARRIER_OUT_LV_CH6 : R/W ;bitpos:[29] ;default: 1'b1 ; */\r
-/*description: This bit is used to configure carrier wave's position for channel6.1'b1:add\r
- on low level 1'b0:add on high level.*/\r
-#define RMT_CARRIER_OUT_LV_CH6 (BIT(29))\r
-#define RMT_CARRIER_OUT_LV_CH6_M (BIT(29))\r
-#define RMT_CARRIER_OUT_LV_CH6_V 0x1\r
-#define RMT_CARRIER_OUT_LV_CH6_S 29\r
-/* RMT_CARRIER_EN_CH6 : R/W ;bitpos:[28] ;default: 1'b1 ; */\r
-/*description: This is the carrier modulation enable control bit for channel6.*/\r
-#define RMT_CARRIER_EN_CH6 (BIT(28))\r
-#define RMT_CARRIER_EN_CH6_M (BIT(28))\r
-#define RMT_CARRIER_EN_CH6_V 0x1\r
-#define RMT_CARRIER_EN_CH6_S 28\r
-/* RMT_MEM_SIZE_CH6 : R/W ;bitpos:[27:24] ;default: 4'h1 ; */\r
-/*description: This register is used to configure the the amount of memory blocks\r
- allocated to channel6.*/\r
-#define RMT_MEM_SIZE_CH6 0x0000000F\r
-#define RMT_MEM_SIZE_CH6_M ((RMT_MEM_SIZE_CH6_V)<<(RMT_MEM_SIZE_CH6_S))\r
-#define RMT_MEM_SIZE_CH6_V 0xF\r
-#define RMT_MEM_SIZE_CH6_S 24\r
-/* RMT_IDLE_THRES_CH6 : R/W ;bitpos:[23:8] ;default: 16'h1000 ; */\r
-/*description: In receive mode when the counter's value is bigger than reg_idle_thres_ch6\r
- then the receive process is done.*/\r
-#define RMT_IDLE_THRES_CH6 0x0000FFFF\r
-#define RMT_IDLE_THRES_CH6_M ((RMT_IDLE_THRES_CH6_V)<<(RMT_IDLE_THRES_CH6_S))\r
-#define RMT_IDLE_THRES_CH6_V 0xFFFF\r
-#define RMT_IDLE_THRES_CH6_S 8\r
-/* RMT_DIV_CNT_CH6 : R/W ;bitpos:[7:0] ;default: 8'h2 ; */\r
-/*description: This register is used to configure the frequency divider's factor in channel6.*/\r
-#define RMT_DIV_CNT_CH6 0x000000FF\r
-#define RMT_DIV_CNT_CH6_M ((RMT_DIV_CNT_CH6_V)<<(RMT_DIV_CNT_CH6_S))\r
-#define RMT_DIV_CNT_CH6_V 0xFF\r
-#define RMT_DIV_CNT_CH6_S 0\r
-\r
-#define RMT_CH6CONF1_REG (DR_REG_RMT_BASE + 0x0054)\r
-/* RMT_IDLE_OUT_EN_CH6 : R/W ;bitpos:[19] ;default: 1'b0 ; */\r
-/*description: This is the output enable control bit for channel6 in IDLE state.*/\r
-#define RMT_IDLE_OUT_EN_CH6 (BIT(19))\r
-#define RMT_IDLE_OUT_EN_CH6_M (BIT(19))\r
-#define RMT_IDLE_OUT_EN_CH6_V 0x1\r
-#define RMT_IDLE_OUT_EN_CH6_S 19\r
-/* RMT_IDLE_OUT_LV_CH6 : R/W ;bitpos:[18] ;default: 1'b0 ; */\r
-/*description: This bit configures the output signal's level for channel6 in IDLE state.*/\r
-#define RMT_IDLE_OUT_LV_CH6 (BIT(18))\r
-#define RMT_IDLE_OUT_LV_CH6_M (BIT(18))\r
-#define RMT_IDLE_OUT_LV_CH6_V 0x1\r
-#define RMT_IDLE_OUT_LV_CH6_S 18\r
-/* RMT_REF_ALWAYS_ON_CH6 : R/W ;bitpos:[17] ;default: 1'b0 ; */\r
-/*description: This bit is used to select base clock. 1'b1:clk_apb 1'b0:clk_ref*/\r
-#define RMT_REF_ALWAYS_ON_CH6 (BIT(17))\r
-#define RMT_REF_ALWAYS_ON_CH6_M (BIT(17))\r
-#define RMT_REF_ALWAYS_ON_CH6_V 0x1\r
-#define RMT_REF_ALWAYS_ON_CH6_S 17\r
-/* RMT_REF_CNT_RST_CH6 : R/W ;bitpos:[16] ;default: 1'b0 ; */\r
-/*description: This bit is used to reset divider in channel6.*/\r
-#define RMT_REF_CNT_RST_CH6 (BIT(16))\r
-#define RMT_REF_CNT_RST_CH6_M (BIT(16))\r
-#define RMT_REF_CNT_RST_CH6_V 0x1\r
-#define RMT_REF_CNT_RST_CH6_S 16\r
-/* RMT_RX_FILTER_THRES_CH6 : R/W ;bitpos:[15:8] ;default: 8'hf ; */\r
-/*description: in receive mode channel6 ignore input pulse when the pulse width\r
- is smaller then this value.*/\r
-#define RMT_RX_FILTER_THRES_CH6 0x000000FF\r
-#define RMT_RX_FILTER_THRES_CH6_M ((RMT_RX_FILTER_THRES_CH6_V)<<(RMT_RX_FILTER_THRES_CH6_S))\r
-#define RMT_RX_FILTER_THRES_CH6_V 0xFF\r
-#define RMT_RX_FILTER_THRES_CH6_S 8\r
-/* RMT_RX_FILTER_EN_CH6 : R/W ;bitpos:[7] ;default: 1'b0 ; */\r
-/*description: This is the receive filter enable bit for channel6.*/\r
-#define RMT_RX_FILTER_EN_CH6 (BIT(7))\r
-#define RMT_RX_FILTER_EN_CH6_M (BIT(7))\r
-#define RMT_RX_FILTER_EN_CH6_V 0x1\r
-#define RMT_RX_FILTER_EN_CH6_S 7\r
-/* RMT_TX_CONTI_MODE_CH6 : R/W ;bitpos:[6] ;default: 1'b0 ; */\r
-/*description: Set this bit to continue sending from the first data to the\r
- last data in channel6.*/\r
-#define RMT_TX_CONTI_MODE_CH6 (BIT(6))\r
-#define RMT_TX_CONTI_MODE_CH6_M (BIT(6))\r
-#define RMT_TX_CONTI_MODE_CH6_V 0x1\r
-#define RMT_TX_CONTI_MODE_CH6_S 6\r
-/* RMT_MEM_OWNER_CH6 : R/W ;bitpos:[5] ;default: 1'b1 ; */\r
-/*description: This is the mark of channel6's ram usage right.1'b1：receiver\r
- uses the ram 0：transmitter uses the ram*/\r
-#define RMT_MEM_OWNER_CH6 (BIT(5))\r
-#define RMT_MEM_OWNER_CH6_M (BIT(5))\r
-#define RMT_MEM_OWNER_CH6_V 0x1\r
-#define RMT_MEM_OWNER_CH6_S 5\r
-/* RMT_APB_MEM_RST_CH6 : R/W ;bitpos:[4] ;default: 1'b0 ; */\r
-/*description: Set this bit to reset W/R ram address for channel6 by apb fifo access*/\r
-#define RMT_APB_MEM_RST_CH6 (BIT(4))\r
-#define RMT_APB_MEM_RST_CH6_M (BIT(4))\r
-#define RMT_APB_MEM_RST_CH6_V 0x1\r
-#define RMT_APB_MEM_RST_CH6_S 4\r
-/* RMT_MEM_RD_RST_CH6 : R/W ;bitpos:[3] ;default: 1'b0 ; */\r
-/*description: Set this bit to reset read ram address for channel6 by transmitter access.*/\r
-#define RMT_MEM_RD_RST_CH6 (BIT(3))\r
-#define RMT_MEM_RD_RST_CH6_M (BIT(3))\r
-#define RMT_MEM_RD_RST_CH6_V 0x1\r
-#define RMT_MEM_RD_RST_CH6_S 3\r
-/* RMT_MEM_WR_RST_CH6 : R/W ;bitpos:[2] ;default: 1'h0 ; */\r
-/*description: Set this bit to reset write ram address for channel6 by receiver access.*/\r
-#define RMT_MEM_WR_RST_CH6 (BIT(2))\r
-#define RMT_MEM_WR_RST_CH6_M (BIT(2))\r
-#define RMT_MEM_WR_RST_CH6_V 0x1\r
-#define RMT_MEM_WR_RST_CH6_S 2\r
-/* RMT_RX_EN_CH6 : R/W ;bitpos:[1] ;default: 1'h0 ; */\r
-/*description: Set this bit to enbale receving data for channel6.*/\r
-#define RMT_RX_EN_CH6 (BIT(1))\r
-#define RMT_RX_EN_CH6_M (BIT(1))\r
-#define RMT_RX_EN_CH6_V 0x1\r
-#define RMT_RX_EN_CH6_S 1\r
-/* RMT_TX_START_CH6 : R/W ;bitpos:[0] ;default: 1'h0 ; */\r
-/*description: Set this bit to start sending data for channel6.*/\r
-#define RMT_TX_START_CH6 (BIT(0))\r
-#define RMT_TX_START_CH6_M (BIT(0))\r
-#define RMT_TX_START_CH6_V 0x1\r
-#define RMT_TX_START_CH6_S 0\r
-\r
-#define RMT_CH7CONF0_REG (DR_REG_RMT_BASE + 0x0058)\r
-/* RMT_CARRIER_OUT_LV_CH7 : R/W ;bitpos:[29] ;default: 1'b1 ; */\r
-/*description: This bit is used to configure carrier wave's position for channel7.1'b1:add\r
- on low level 1'b0:add on high level.*/\r
-#define RMT_CARRIER_OUT_LV_CH7 (BIT(29))\r
-#define RMT_CARRIER_OUT_LV_CH7_M (BIT(29))\r
-#define RMT_CARRIER_OUT_LV_CH7_V 0x1\r
-#define RMT_CARRIER_OUT_LV_CH7_S 29\r
-/* RMT_CARRIER_EN_CH7 : R/W ;bitpos:[28] ;default: 1'b1 ; */\r
-/*description: This is the carrier modulation enable control bit for channel7.*/\r
-#define RMT_CARRIER_EN_CH7 (BIT(28))\r
-#define RMT_CARRIER_EN_CH7_M (BIT(28))\r
-#define RMT_CARRIER_EN_CH7_V 0x1\r
-#define RMT_CARRIER_EN_CH7_S 28\r
-/* RMT_MEM_SIZE_CH7 : R/W ;bitpos:[27:24] ;default: 4'h1 ; */\r
-/*description: This register is used to configure the the amount of memory blocks\r
- allocated to channel7.*/\r
-#define RMT_MEM_SIZE_CH7 0x0000000F\r
-#define RMT_MEM_SIZE_CH7_M ((RMT_MEM_SIZE_CH7_V)<<(RMT_MEM_SIZE_CH7_S))\r
-#define RMT_MEM_SIZE_CH7_V 0xF\r
-#define RMT_MEM_SIZE_CH7_S 24\r
-/* RMT_IDLE_THRES_CH7 : R/W ;bitpos:[23:8] ;default: 16'h1000 ; */\r
-/*description: In receive mode when the counter's value is bigger than reg_idle_thres_ch7\r
- then the receive process is done.*/\r
-#define RMT_IDLE_THRES_CH7 0x0000FFFF\r
-#define RMT_IDLE_THRES_CH7_M ((RMT_IDLE_THRES_CH7_V)<<(RMT_IDLE_THRES_CH7_S))\r
-#define RMT_IDLE_THRES_CH7_V 0xFFFF\r
-#define RMT_IDLE_THRES_CH7_S 8\r
-/* RMT_DIV_CNT_CH7 : R/W ;bitpos:[7:0] ;default: 8'h2 ; */\r
-/*description: This register is used to configure the frequency divider's factor in channel7.*/\r
-#define RMT_DIV_CNT_CH7 0x000000FF\r
-#define RMT_DIV_CNT_CH7_M ((RMT_DIV_CNT_CH7_V)<<(RMT_DIV_CNT_CH7_S))\r
-#define RMT_DIV_CNT_CH7_V 0xFF\r
-#define RMT_DIV_CNT_CH7_S 0\r
-\r
-#define RMT_CH7CONF1_REG (DR_REG_RMT_BASE + 0x005c)\r
-/* RMT_IDLE_OUT_EN_CH7 : R/W ;bitpos:[19] ;default: 1'b0 ; */\r
-/*description: This is the output enable control bit for channel6 in IDLE state.*/\r
-#define RMT_IDLE_OUT_EN_CH7 (BIT(19))\r
-#define RMT_IDLE_OUT_EN_CH7_M (BIT(19))\r
-#define RMT_IDLE_OUT_EN_CH7_V 0x1\r
-#define RMT_IDLE_OUT_EN_CH7_S 19\r
-/* RMT_IDLE_OUT_LV_CH7 : R/W ;bitpos:[18] ;default: 1'b0 ; */\r
-/*description: This bit configures the output signal's level for channel7 in IDLE state.*/\r
-#define RMT_IDLE_OUT_LV_CH7 (BIT(18))\r
-#define RMT_IDLE_OUT_LV_CH7_M (BIT(18))\r
-#define RMT_IDLE_OUT_LV_CH7_V 0x1\r
-#define RMT_IDLE_OUT_LV_CH7_S 18\r
-/* RMT_REF_ALWAYS_ON_CH7 : R/W ;bitpos:[17] ;default: 1'b0 ; */\r
-/*description: This bit is used to select base clock. 1'b1:clk_apb 1'b0:clk_ref*/\r
-#define RMT_REF_ALWAYS_ON_CH7 (BIT(17))\r
-#define RMT_REF_ALWAYS_ON_CH7_M (BIT(17))\r
-#define RMT_REF_ALWAYS_ON_CH7_V 0x1\r
-#define RMT_REF_ALWAYS_ON_CH7_S 17\r
-/* RMT_REF_CNT_RST_CH7 : R/W ;bitpos:[16] ;default: 1'b0 ; */\r
-/*description: This bit is used to reset divider in channel7.*/\r
-#define RMT_REF_CNT_RST_CH7 (BIT(16))\r
-#define RMT_REF_CNT_RST_CH7_M (BIT(16))\r
-#define RMT_REF_CNT_RST_CH7_V 0x1\r
-#define RMT_REF_CNT_RST_CH7_S 16\r
-/* RMT_RX_FILTER_THRES_CH7 : R/W ;bitpos:[15:8] ;default: 8'hf ; */\r
-/*description: in receive mode channel7 ignore input pulse when the pulse width\r
- is smaller then this value.*/\r
-#define RMT_RX_FILTER_THRES_CH7 0x000000FF\r
-#define RMT_RX_FILTER_THRES_CH7_M ((RMT_RX_FILTER_THRES_CH7_V)<<(RMT_RX_FILTER_THRES_CH7_S))\r
-#define RMT_RX_FILTER_THRES_CH7_V 0xFF\r
-#define RMT_RX_FILTER_THRES_CH7_S 8\r
-/* RMT_RX_FILTER_EN_CH7 : R/W ;bitpos:[7] ;default: 1'b0 ; */\r
-/*description: This is the receive filter enable bit for channel7.*/\r
-#define RMT_RX_FILTER_EN_CH7 (BIT(7))\r
-#define RMT_RX_FILTER_EN_CH7_M (BIT(7))\r
-#define RMT_RX_FILTER_EN_CH7_V 0x1\r
-#define RMT_RX_FILTER_EN_CH7_S 7\r
-/* RMT_TX_CONTI_MODE_CH7 : R/W ;bitpos:[6] ;default: 1'b0 ; */\r
-/*description: Set this bit to continue sending from the first data to the\r
- last data in channel7.*/\r
-#define RMT_TX_CONTI_MODE_CH7 (BIT(6))\r
-#define RMT_TX_CONTI_MODE_CH7_M (BIT(6))\r
-#define RMT_TX_CONTI_MODE_CH7_V 0x1\r
-#define RMT_TX_CONTI_MODE_CH7_S 6\r
-/* RMT_MEM_OWNER_CH7 : R/W ;bitpos:[5] ;default: 1'b1 ; */\r
-/*description: This is the mark of channel7's ram usage right.1'b1：receiver\r
- uses the ram 0：transmitter uses the ram*/\r
-#define RMT_MEM_OWNER_CH7 (BIT(5))\r
-#define RMT_MEM_OWNER_CH7_M (BIT(5))\r
-#define RMT_MEM_OWNER_CH7_V 0x1\r
-#define RMT_MEM_OWNER_CH7_S 5\r
-/* RMT_APB_MEM_RST_CH7 : R/W ;bitpos:[4] ;default: 1'b0 ; */\r
-/*description: Set this bit to reset W/R ram address for channel7 by apb fifo access*/\r
-#define RMT_APB_MEM_RST_CH7 (BIT(4))\r
-#define RMT_APB_MEM_RST_CH7_M (BIT(4))\r
-#define RMT_APB_MEM_RST_CH7_V 0x1\r
-#define RMT_APB_MEM_RST_CH7_S 4\r
-/* RMT_MEM_RD_RST_CH7 : R/W ;bitpos:[3] ;default: 1'b0 ; */\r
-/*description: Set this bit to reset read ram address for channel7 by transmitter access.*/\r
-#define RMT_MEM_RD_RST_CH7 (BIT(3))\r
-#define RMT_MEM_RD_RST_CH7_M (BIT(3))\r
-#define RMT_MEM_RD_RST_CH7_V 0x1\r
-#define RMT_MEM_RD_RST_CH7_S 3\r
-/* RMT_MEM_WR_RST_CH7 : R/W ;bitpos:[2] ;default: 1'h0 ; */\r
-/*description: Set this bit to reset write ram address for channel7 by receiver access.*/\r
-#define RMT_MEM_WR_RST_CH7 (BIT(2))\r
-#define RMT_MEM_WR_RST_CH7_M (BIT(2))\r
-#define RMT_MEM_WR_RST_CH7_V 0x1\r
-#define RMT_MEM_WR_RST_CH7_S 2\r
-/* RMT_RX_EN_CH7 : R/W ;bitpos:[1] ;default: 1'h0 ; */\r
-/*description: Set this bit to enbale receving data for channel7.*/\r
-#define RMT_RX_EN_CH7 (BIT(1))\r
-#define RMT_RX_EN_CH7_M (BIT(1))\r
-#define RMT_RX_EN_CH7_V 0x1\r
-#define RMT_RX_EN_CH7_S 1\r
-/* RMT_TX_START_CH7 : R/W ;bitpos:[0] ;default: 1'h0 ; */\r
-/*description: Set this bit to start sending data for channel7.*/\r
-#define RMT_TX_START_CH7 (BIT(0))\r
-#define RMT_TX_START_CH7_M (BIT(0))\r
-#define RMT_TX_START_CH7_V 0x1\r
-#define RMT_TX_START_CH7_S 0\r
-\r
-#define RMT_CH0STATUS_REG (DR_REG_RMT_BASE + 0x0060)\r
-/* RMT_STATUS_CH0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */\r
-/*description: The status for channel0*/\r
-#define RMT_STATUS_CH0 0xFFFFFFFF\r
-#define RMT_STATUS_CH0_M ((RMT_STATUS_CH0_V)<<(RMT_STATUS_CH0_S))\r
-#define RMT_STATUS_CH0_V 0xFFFFFFFF\r
-#define RMT_STATUS_CH0_S 0\r
-\r
-#define RMT_CH1STATUS_REG (DR_REG_RMT_BASE + 0x0064)\r
-/* RMT_STATUS_CH1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */\r
-/*description: The status for channel1*/\r
-#define RMT_STATUS_CH1 0xFFFFFFFF\r
-#define RMT_STATUS_CH1_M ((RMT_STATUS_CH1_V)<<(RMT_STATUS_CH1_S))\r
-#define RMT_STATUS_CH1_V 0xFFFFFFFF\r
-#define RMT_STATUS_CH1_S 0\r
-\r
-#define RMT_CH2STATUS_REG (DR_REG_RMT_BASE + 0x0068)\r
-/* RMT_STATUS_CH2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */\r
-/*description: The status for channel2*/\r
-#define RMT_STATUS_CH2 0xFFFFFFFF\r
-#define RMT_STATUS_CH2_M ((RMT_STATUS_CH2_V)<<(RMT_STATUS_CH2_S))\r
-#define RMT_STATUS_CH2_V 0xFFFFFFFF\r
-#define RMT_STATUS_CH2_S 0\r
-\r
-#define RMT_CH3STATUS_REG (DR_REG_RMT_BASE + 0x006c)\r
-/* RMT_STATUS_CH3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */\r
-/*description: The status for channel3*/\r
-#define RMT_STATUS_CH3 0xFFFFFFFF\r
-#define RMT_STATUS_CH3_M ((RMT_STATUS_CH3_V)<<(RMT_STATUS_CH3_S))\r
-#define RMT_STATUS_CH3_V 0xFFFFFFFF\r
-#define RMT_STATUS_CH3_S 0\r
-\r
-#define RMT_CH4STATUS_REG (DR_REG_RMT_BASE + 0x0070)\r
-/* RMT_STATUS_CH4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */\r
-/*description: The status for channel4*/\r
-#define RMT_STATUS_CH4 0xFFFFFFFF\r
-#define RMT_STATUS_CH4_M ((RMT_STATUS_CH4_V)<<(RMT_STATUS_CH4_S))\r
-#define RMT_STATUS_CH4_V 0xFFFFFFFF\r
-#define RMT_STATUS_CH4_S 0\r
-\r
-#define RMT_CH5STATUS_REG (DR_REG_RMT_BASE + 0x0074)\r
-/* RMT_STATUS_CH5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */\r
-/*description: The status for channel5*/\r
-#define RMT_STATUS_CH5 0xFFFFFFFF\r
-#define RMT_STATUS_CH5_M ((RMT_STATUS_CH5_V)<<(RMT_STATUS_CH5_S))\r
-#define RMT_STATUS_CH5_V 0xFFFFFFFF\r
-#define RMT_STATUS_CH5_S 0\r
-\r
-#define RMT_CH6STATUS_REG (DR_REG_RMT_BASE + 0x0078)\r
-/* RMT_STATUS_CH6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */\r
-/*description: The status for channel6*/\r
-#define RMT_STATUS_CH6 0xFFFFFFFF\r
-#define RMT_STATUS_CH6_M ((RMT_STATUS_CH6_V)<<(RMT_STATUS_CH6_S))\r
-#define RMT_STATUS_CH6_V 0xFFFFFFFF\r
-#define RMT_STATUS_CH6_S 0\r
-\r
-#define RMT_CH7STATUS_REG (DR_REG_RMT_BASE + 0x007c)\r
-/* RMT_STATUS_CH7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */\r
-/*description: The status for channel7*/\r
-#define RMT_STATUS_CH7 0xFFFFFFFF\r
-#define RMT_STATUS_CH7_M ((RMT_STATUS_CH7_V)<<(RMT_STATUS_CH7_S))\r
-#define RMT_STATUS_CH7_V 0xFFFFFFFF\r
-#define RMT_STATUS_CH7_S 0\r
-\r
-#define RMT_CH0ADDR_REG (DR_REG_RMT_BASE + 0x0080)\r
-/* RMT_APB_MEM_ADDR_CH0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */\r
-/*description: The ram relative address in channel0 by apb fifo access*/\r
-#define RMT_APB_MEM_ADDR_CH0 0xFFFFFFFF\r
-#define RMT_APB_MEM_ADDR_CH0_M ((RMT_APB_MEM_ADDR_CH0_V)<<(RMT_APB_MEM_ADDR_CH0_S))\r
-#define RMT_APB_MEM_ADDR_CH0_V 0xFFFFFFFF\r
-#define RMT_APB_MEM_ADDR_CH0_S 0\r
-\r
-#define RMT_CH1ADDR_REG (DR_REG_RMT_BASE + 0x0084)\r
-/* RMT_APB_MEM_ADDR_CH1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */\r
-/*description: The ram relative address in channel1 by apb fifo access*/\r
-#define RMT_APB_MEM_ADDR_CH1 0xFFFFFFFF\r
-#define RMT_APB_MEM_ADDR_CH1_M ((RMT_APB_MEM_ADDR_CH1_V)<<(RMT_APB_MEM_ADDR_CH1_S))\r
-#define RMT_APB_MEM_ADDR_CH1_V 0xFFFFFFFF\r
-#define RMT_APB_MEM_ADDR_CH1_S 0\r
-\r
-#define RMT_CH2ADDR_REG (DR_REG_RMT_BASE + 0x0088)\r
-/* RMT_APB_MEM_ADDR_CH2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */\r
-/*description: The ram relative address in channel2 by apb fifo access*/\r
-#define RMT_APB_MEM_ADDR_CH2 0xFFFFFFFF\r
-#define RMT_APB_MEM_ADDR_CH2_M ((RMT_APB_MEM_ADDR_CH2_V)<<(RMT_APB_MEM_ADDR_CH2_S))\r
-#define RMT_APB_MEM_ADDR_CH2_V 0xFFFFFFFF\r
-#define RMT_APB_MEM_ADDR_CH2_S 0\r
-\r
-#define RMT_CH3ADDR_REG (DR_REG_RMT_BASE + 0x008c)\r
-/* RMT_APB_MEM_ADDR_CH3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */\r
-/*description: The ram relative address in channel3 by apb fifo access*/\r
-#define RMT_APB_MEM_ADDR_CH3 0xFFFFFFFF\r
-#define RMT_APB_MEM_ADDR_CH3_M ((RMT_APB_MEM_ADDR_CH3_V)<<(RMT_APB_MEM_ADDR_CH3_S))\r
-#define RMT_APB_MEM_ADDR_CH3_V 0xFFFFFFFF\r
-#define RMT_APB_MEM_ADDR_CH3_S 0\r
-\r
-#define RMT_CH4ADDR_REG (DR_REG_RMT_BASE + 0x0090)\r
-/* RMT_APB_MEM_ADDR_CH4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */\r
-/*description: The ram relative address in channel4 by apb fifo access*/\r
-#define RMT_APB_MEM_ADDR_CH4 0xFFFFFFFF\r
-#define RMT_APB_MEM_ADDR_CH4_M ((RMT_APB_MEM_ADDR_CH4_V)<<(RMT_APB_MEM_ADDR_CH4_S))\r
-#define RMT_APB_MEM_ADDR_CH4_V 0xFFFFFFFF\r
-#define RMT_APB_MEM_ADDR_CH4_S 0\r
-\r
-#define RMT_CH5ADDR_REG (DR_REG_RMT_BASE + 0x0094)\r
-/* RMT_APB_MEM_ADDR_CH5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */\r
-/*description: The ram relative address in channel5 by apb fifo access*/\r
-#define RMT_APB_MEM_ADDR_CH5 0xFFFFFFFF\r
-#define RMT_APB_MEM_ADDR_CH5_M ((RMT_APB_MEM_ADDR_CH5_V)<<(RMT_APB_MEM_ADDR_CH5_S))\r
-#define RMT_APB_MEM_ADDR_CH5_V 0xFFFFFFFF\r
-#define RMT_APB_MEM_ADDR_CH5_S 0\r
-\r
-#define RMT_CH6ADDR_REG (DR_REG_RMT_BASE + 0x0098)\r
-/* RMT_APB_MEM_ADDR_CH6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */\r
-/*description: The ram relative address in channel6 by apb fifo access*/\r
-#define RMT_APB_MEM_ADDR_CH6 0xFFFFFFFF\r
-#define RMT_APB_MEM_ADDR_CH6_M ((RMT_APB_MEM_ADDR_CH6_V)<<(RMT_APB_MEM_ADDR_CH6_S))\r
-#define RMT_APB_MEM_ADDR_CH6_V 0xFFFFFFFF\r
-#define RMT_APB_MEM_ADDR_CH6_S 0\r
-\r
-#define RMT_CH7ADDR_REG (DR_REG_RMT_BASE + 0x009c)\r
-/* RMT_APB_MEM_ADDR_CH7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */\r
-/*description: The ram relative address in channel7 by apb fifo access*/\r
-#define RMT_APB_MEM_ADDR_CH7 0xFFFFFFFF\r
-#define RMT_APB_MEM_ADDR_CH7_M ((RMT_APB_MEM_ADDR_CH7_V)<<(RMT_APB_MEM_ADDR_CH7_S))\r
-#define RMT_APB_MEM_ADDR_CH7_V 0xFFFFFFFF\r
-#define RMT_APB_MEM_ADDR_CH7_S 0\r
-\r
-#define RMT_INT_RAW_REG (DR_REG_RMT_BASE + 0x00a0)\r
-/* RMT_CH7_TX_THR_EVENT_INT_RAW : RO ;bitpos:[31] ;default: 1'b0 ; */\r
-/*description: The interrupt raw bit for channel 7 turns to high level when\r
- transmitter in channle7 have send datas more than reg_rmt_tx_lim_ch7 after detecting this interrupt software can updata the old datas with new datas.*/\r
-#define RMT_CH7_TX_THR_EVENT_INT_RAW (BIT(31))\r
-#define RMT_CH7_TX_THR_EVENT_INT_RAW_M (BIT(31))\r
-#define RMT_CH7_TX_THR_EVENT_INT_RAW_V 0x1\r
-#define RMT_CH7_TX_THR_EVENT_INT_RAW_S 31\r
-/* RMT_CH6_TX_THR_EVENT_INT_RAW : RO ;bitpos:[30] ;default: 1'b0 ; */\r
-/*description: The interrupt raw bit for channel 6 turns to high level when\r
- transmitter in channle6 have send datas more than reg_rmt_tx_lim_ch6 after detecting this interrupt software can updata the old datas with new datas.*/\r
-#define RMT_CH6_TX_THR_EVENT_INT_RAW (BIT(30))\r
-#define RMT_CH6_TX_THR_EVENT_INT_RAW_M (BIT(30))\r
-#define RMT_CH6_TX_THR_EVENT_INT_RAW_V 0x1\r
-#define RMT_CH6_TX_THR_EVENT_INT_RAW_S 30\r
-/* RMT_CH5_TX_THR_EVENT_INT_RAW : RO ;bitpos:[29] ;default: 1'b0 ; */\r
-/*description: The interrupt raw bit for channel 5 turns to high level when\r
- transmitter in channle5 have send datas more than reg_rmt_tx_lim_ch5 after detecting this interrupt software can updata the old datas with new datas.*/\r
-#define RMT_CH5_TX_THR_EVENT_INT_RAW (BIT(29))\r
-#define RMT_CH5_TX_THR_EVENT_INT_RAW_M (BIT(29))\r
-#define RMT_CH5_TX_THR_EVENT_INT_RAW_V 0x1\r
-#define RMT_CH5_TX_THR_EVENT_INT_RAW_S 29\r
-/* RMT_CH4_TX_THR_EVENT_INT_RAW : RO ;bitpos:[28] ;default: 1'b0 ; */\r
-/*description: The interrupt raw bit for channel 4 turns to high level when\r
- transmitter in channle4 have send datas more than reg_rmt_tx_lim_ch4 after detecting this interrupt software can updata the old datas with new datas.*/\r
-#define RMT_CH4_TX_THR_EVENT_INT_RAW (BIT(28))\r
-#define RMT_CH4_TX_THR_EVENT_INT_RAW_M (BIT(28))\r
-#define RMT_CH4_TX_THR_EVENT_INT_RAW_V 0x1\r
-#define RMT_CH4_TX_THR_EVENT_INT_RAW_S 28\r
-/* RMT_CH3_TX_THR_EVENT_INT_RAW : RO ;bitpos:[27] ;default: 1'b0 ; */\r
-/*description: The interrupt raw bit for channel 3 turns to high level when\r
- transmitter in channle3 have send datas more than reg_rmt_tx_lim_ch3 after detecting this interrupt software can updata the old datas with new datas.*/\r
-#define RMT_CH3_TX_THR_EVENT_INT_RAW (BIT(27))\r
-#define RMT_CH3_TX_THR_EVENT_INT_RAW_M (BIT(27))\r
-#define RMT_CH3_TX_THR_EVENT_INT_RAW_V 0x1\r
-#define RMT_CH3_TX_THR_EVENT_INT_RAW_S 27\r
-/* RMT_CH2_TX_THR_EVENT_INT_RAW : RO ;bitpos:[26] ;default: 1'b0 ; */\r
-/*description: The interrupt raw bit for channel 2 turns to high level when\r
- transmitter in channle2 have send datas more than reg_rmt_tx_lim_ch2 after detecting this interrupt software can updata the old datas with new datas.*/\r
-#define RMT_CH2_TX_THR_EVENT_INT_RAW (BIT(26))\r
-#define RMT_CH2_TX_THR_EVENT_INT_RAW_M (BIT(26))\r
-#define RMT_CH2_TX_THR_EVENT_INT_RAW_V 0x1\r
-#define RMT_CH2_TX_THR_EVENT_INT_RAW_S 26\r
-/* RMT_CH1_TX_THR_EVENT_INT_RAW : RO ;bitpos:[25] ;default: 1'b0 ; */\r
-/*description: The interrupt raw bit for channel 1 turns to high level when\r
- transmitter in channle1 have send datas more than reg_rmt_tx_lim_ch1 after detecting this interrupt software can updata the old datas with new datas.*/\r
-#define RMT_CH1_TX_THR_EVENT_INT_RAW (BIT(25))\r
-#define RMT_CH1_TX_THR_EVENT_INT_RAW_M (BIT(25))\r
-#define RMT_CH1_TX_THR_EVENT_INT_RAW_V 0x1\r
-#define RMT_CH1_TX_THR_EVENT_INT_RAW_S 25\r
-/* RMT_CH0_TX_THR_EVENT_INT_RAW : RO ;bitpos:[24] ;default: 1'b0 ; */\r
-/*description: The interrupt raw bit for channel 0 turns to high level when\r
- transmitter in channle0 have send datas more than reg_rmt_tx_lim_ch0 after detecting this interrupt software can updata the old datas with new datas.*/\r
-#define RMT_CH0_TX_THR_EVENT_INT_RAW (BIT(24))\r
-#define RMT_CH0_TX_THR_EVENT_INT_RAW_M (BIT(24))\r
-#define RMT_CH0_TX_THR_EVENT_INT_RAW_V 0x1\r
-#define RMT_CH0_TX_THR_EVENT_INT_RAW_S 24\r
-/* RMT_CH7_ERR_INT_RAW : RO ;bitpos:[23] ;default: 1'b0 ; */\r
-/*description: The interrupt raw bit for channel 7 turns to high level when\r
- channle 7 detects some errors.*/\r
-#define RMT_CH7_ERR_INT_RAW (BIT(23))\r
-#define RMT_CH7_ERR_INT_RAW_M (BIT(23))\r
-#define RMT_CH7_ERR_INT_RAW_V 0x1\r
-#define RMT_CH7_ERR_INT_RAW_S 23\r
-/* RMT_CH7_RX_END_INT_RAW : RO ;bitpos:[22] ;default: 1'b0 ; */\r
-/*description: The interrupt raw bit for channel 7 turns to high level when\r
- the receive process is done.*/\r
-#define RMT_CH7_RX_END_INT_RAW (BIT(22))\r
-#define RMT_CH7_RX_END_INT_RAW_M (BIT(22))\r
-#define RMT_CH7_RX_END_INT_RAW_V 0x1\r
-#define RMT_CH7_RX_END_INT_RAW_S 22\r
-/* RMT_CH7_TX_END_INT_RAW : RO ;bitpos:[21] ;default: 1'b0 ; */\r
-/*description: The interrupt raw bit for channel 7 turns to high level when\r
- the transmit process is done.*/\r
-#define RMT_CH7_TX_END_INT_RAW (BIT(21))\r
-#define RMT_CH7_TX_END_INT_RAW_M (BIT(21))\r
-#define RMT_CH7_TX_END_INT_RAW_V 0x1\r
-#define RMT_CH7_TX_END_INT_RAW_S 21\r
-/* RMT_CH6_ERR_INT_RAW : RO ;bitpos:[20] ;default: 1'b0 ; */\r
-/*description: The interrupt raw bit for channel 6 turns to high level when\r
- channle 6 detects some errors.*/\r
-#define RMT_CH6_ERR_INT_RAW (BIT(20))\r
-#define RMT_CH6_ERR_INT_RAW_M (BIT(20))\r
-#define RMT_CH6_ERR_INT_RAW_V 0x1\r
-#define RMT_CH6_ERR_INT_RAW_S 20\r
-/* RMT_CH6_RX_END_INT_RAW : RO ;bitpos:[19] ;default: 1'b0 ; */\r
-/*description: The interrupt raw bit for channel 6 turns to high level when\r
- the receive process is done.*/\r
-#define RMT_CH6_RX_END_INT_RAW (BIT(19))\r
-#define RMT_CH6_RX_END_INT_RAW_M (BIT(19))\r
-#define RMT_CH6_RX_END_INT_RAW_V 0x1\r
-#define RMT_CH6_RX_END_INT_RAW_S 19\r
-/* RMT_CH6_TX_END_INT_RAW : RO ;bitpos:[18] ;default: 1'b0 ; */\r
-/*description: The interrupt raw bit for channel 6 turns to high level when\r
- the transmit process is done.*/\r
-#define RMT_CH6_TX_END_INT_RAW (BIT(18))\r
-#define RMT_CH6_TX_END_INT_RAW_M (BIT(18))\r
-#define RMT_CH6_TX_END_INT_RAW_V 0x1\r
-#define RMT_CH6_TX_END_INT_RAW_S 18\r
-/* RMT_CH5_ERR_INT_RAW : RO ;bitpos:[17] ;default: 1'b0 ; */\r
-/*description: The interrupt raw bit for channel 5 turns to high level when\r
- channle 5 detects some errors.*/\r
-#define RMT_CH5_ERR_INT_RAW (BIT(17))\r
-#define RMT_CH5_ERR_INT_RAW_M (BIT(17))\r
-#define RMT_CH5_ERR_INT_RAW_V 0x1\r
-#define RMT_CH5_ERR_INT_RAW_S 17\r
-/* RMT_CH5_RX_END_INT_RAW : RO ;bitpos:[16] ;default: 1'b0 ; */\r
-/*description: The interrupt raw bit for channel 5 turns to high level when\r
- the receive process is done.*/\r
-#define RMT_CH5_RX_END_INT_RAW (BIT(16))\r
-#define RMT_CH5_RX_END_INT_RAW_M (BIT(16))\r
-#define RMT_CH5_RX_END_INT_RAW_V 0x1\r
-#define RMT_CH5_RX_END_INT_RAW_S 16\r
-/* RMT_CH5_TX_END_INT_RAW : RO ;bitpos:[15] ;default: 1'b0 ; */\r
-/*description: The interrupt raw bit for channel 5 turns to high level when\r
- the transmit process is done.*/\r
-#define RMT_CH5_TX_END_INT_RAW (BIT(15))\r
-#define RMT_CH5_TX_END_INT_RAW_M (BIT(15))\r
-#define RMT_CH5_TX_END_INT_RAW_V 0x1\r
-#define RMT_CH5_TX_END_INT_RAW_S 15\r
-/* RMT_CH4_ERR_INT_RAW : RO ;bitpos:[14] ;default: 1'b0 ; */\r
-/*description: The interrupt raw bit for channel 4 turns to high level when\r
- channle 4 detects some errors.*/\r
-#define RMT_CH4_ERR_INT_RAW (BIT(14))\r
-#define RMT_CH4_ERR_INT_RAW_M (BIT(14))\r
-#define RMT_CH4_ERR_INT_RAW_V 0x1\r
-#define RMT_CH4_ERR_INT_RAW_S 14\r
-/* RMT_CH4_RX_END_INT_RAW : RO ;bitpos:[13] ;default: 1'b0 ; */\r
-/*description: The interrupt raw bit for channel 4 turns to high level when\r
- the receive process is done.*/\r
-#define RMT_CH4_RX_END_INT_RAW (BIT(13))\r
-#define RMT_CH4_RX_END_INT_RAW_M (BIT(13))\r
-#define RMT_CH4_RX_END_INT_RAW_V 0x1\r
-#define RMT_CH4_RX_END_INT_RAW_S 13\r
-/* RMT_CH4_TX_END_INT_RAW : RO ;bitpos:[12] ;default: 1'b0 ; */\r
-/*description: The interrupt raw bit for channel 4 turns to high level when\r
- the transmit process is done.*/\r
-#define RMT_CH4_TX_END_INT_RAW (BIT(12))\r
-#define RMT_CH4_TX_END_INT_RAW_M (BIT(12))\r
-#define RMT_CH4_TX_END_INT_RAW_V 0x1\r
-#define RMT_CH4_TX_END_INT_RAW_S 12\r
-/* RMT_CH3_ERR_INT_RAW : RO ;bitpos:[11] ;default: 1'b0 ; */\r
-/*description: The interrupt raw bit for channel 3 turns to high level when\r
- channle 3 detects some errors.*/\r
-#define RMT_CH3_ERR_INT_RAW (BIT(11))\r
-#define RMT_CH3_ERR_INT_RAW_M (BIT(11))\r
-#define RMT_CH3_ERR_INT_RAW_V 0x1\r
-#define RMT_CH3_ERR_INT_RAW_S 11\r
-/* RMT_CH3_RX_END_INT_RAW : RO ;bitpos:[10] ;default: 1'b0 ; */\r
-/*description: The interrupt raw bit for channel 3 turns to high level when\r
- the receive process is done.*/\r
-#define RMT_CH3_RX_END_INT_RAW (BIT(10))\r
-#define RMT_CH3_RX_END_INT_RAW_M (BIT(10))\r
-#define RMT_CH3_RX_END_INT_RAW_V 0x1\r
-#define RMT_CH3_RX_END_INT_RAW_S 10\r
-/* RMT_CH3_TX_END_INT_RAW : RO ;bitpos:[9] ;default: 1'b0 ; */\r
-/*description: The interrupt raw bit for channel 3 turns to high level when\r
- the transmit process is done.*/\r
-#define RMT_CH3_TX_END_INT_RAW (BIT(9))\r
-#define RMT_CH3_TX_END_INT_RAW_M (BIT(9))\r
-#define RMT_CH3_TX_END_INT_RAW_V 0x1\r
-#define RMT_CH3_TX_END_INT_RAW_S 9\r
-/* RMT_CH2_ERR_INT_RAW : RO ;bitpos:[8] ;default: 1'b0 ; */\r
-/*description: The interrupt raw bit for channel 2 turns to high level when\r
- channle 2 detects some errors.*/\r
-#define RMT_CH2_ERR_INT_RAW (BIT(8))\r
-#define RMT_CH2_ERR_INT_RAW_M (BIT(8))\r
-#define RMT_CH2_ERR_INT_RAW_V 0x1\r
-#define RMT_CH2_ERR_INT_RAW_S 8\r
-/* RMT_CH2_RX_END_INT_RAW : RO ;bitpos:[7] ;default: 1'b0 ; */\r
-/*description: The interrupt raw bit for channel 2 turns to high level when\r
- the receive process is done.*/\r
-#define RMT_CH2_RX_END_INT_RAW (BIT(7))\r
-#define RMT_CH2_RX_END_INT_RAW_M (BIT(7))\r
-#define RMT_CH2_RX_END_INT_RAW_V 0x1\r
-#define RMT_CH2_RX_END_INT_RAW_S 7\r
-/* RMT_CH2_TX_END_INT_RAW : RO ;bitpos:[6] ;default: 1'b0 ; */\r
-/*description: The interrupt raw bit for channel 2 turns to high level when\r
- the transmit process is done.*/\r
-#define RMT_CH2_TX_END_INT_RAW (BIT(6))\r
-#define RMT_CH2_TX_END_INT_RAW_M (BIT(6))\r
-#define RMT_CH2_TX_END_INT_RAW_V 0x1\r
-#define RMT_CH2_TX_END_INT_RAW_S 6\r
-/* RMT_CH1_ERR_INT_RAW : RO ;bitpos:[5] ;default: 1'b0 ; */\r
-/*description: The interrupt raw bit for channel 1 turns to high level when\r
- channle 1 detects some errors.*/\r
-#define RMT_CH1_ERR_INT_RAW (BIT(5))\r
-#define RMT_CH1_ERR_INT_RAW_M (BIT(5))\r
-#define RMT_CH1_ERR_INT_RAW_V 0x1\r
-#define RMT_CH1_ERR_INT_RAW_S 5\r
-/* RMT_CH1_RX_END_INT_RAW : RO ;bitpos:[4] ;default: 1'b0 ; */\r
-/*description: The interrupt raw bit for channel 1 turns to high level when\r
- the receive process is done.*/\r
-#define RMT_CH1_RX_END_INT_RAW (BIT(4))\r
-#define RMT_CH1_RX_END_INT_RAW_M (BIT(4))\r
-#define RMT_CH1_RX_END_INT_RAW_V 0x1\r
-#define RMT_CH1_RX_END_INT_RAW_S 4\r
-/* RMT_CH1_TX_END_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */\r
-/*description: The interrupt raw bit for channel 1 turns to high level when\r
- the transmit process is done.*/\r
-#define RMT_CH1_TX_END_INT_RAW (BIT(3))\r
-#define RMT_CH1_TX_END_INT_RAW_M (BIT(3))\r
-#define RMT_CH1_TX_END_INT_RAW_V 0x1\r
-#define RMT_CH1_TX_END_INT_RAW_S 3\r
-/* RMT_CH0_ERR_INT_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */\r
-/*description: The interrupt raw bit for channel 0 turns to high level when\r
- channle 0 detects some errors.*/\r
-#define RMT_CH0_ERR_INT_RAW (BIT(2))\r
-#define RMT_CH0_ERR_INT_RAW_M (BIT(2))\r
-#define RMT_CH0_ERR_INT_RAW_V 0x1\r
-#define RMT_CH0_ERR_INT_RAW_S 2\r
-/* RMT_CH0_RX_END_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */\r
-/*description: The interrupt raw bit for channel 0 turns to high level when\r
- the receive process is done.*/\r
-#define RMT_CH0_RX_END_INT_RAW (BIT(1))\r
-#define RMT_CH0_RX_END_INT_RAW_M (BIT(1))\r
-#define RMT_CH0_RX_END_INT_RAW_V 0x1\r
-#define RMT_CH0_RX_END_INT_RAW_S 1\r
-/* RMT_CH0_TX_END_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */\r
-/*description: The interrupt raw bit for channel 0 turns to high level when\r
- the transmit process is done.*/\r
-#define RMT_CH0_TX_END_INT_RAW (BIT(0))\r
-#define RMT_CH0_TX_END_INT_RAW_M (BIT(0))\r
-#define RMT_CH0_TX_END_INT_RAW_V 0x1\r
-#define RMT_CH0_TX_END_INT_RAW_S 0\r
-\r
-#define RMT_INT_ST_REG (DR_REG_RMT_BASE + 0x00a4)\r
-/* RMT_CH7_TX_THR_EVENT_INT_ST : RO ;bitpos:[31] ;default: 1'b0 ; */\r
-/*description: The interrupt state bit for channel 7's rmt_ch7_tx_thr_event_int_raw\r
- when mt_ch7_tx_thr_event_int_ena is set to 1.*/\r
-#define RMT_CH7_TX_THR_EVENT_INT_ST (BIT(31))\r
-#define RMT_CH7_TX_THR_EVENT_INT_ST_M (BIT(31))\r
-#define RMT_CH7_TX_THR_EVENT_INT_ST_V 0x1\r
-#define RMT_CH7_TX_THR_EVENT_INT_ST_S 31\r
-/* RMT_CH6_TX_THR_EVENT_INT_ST : RO ;bitpos:[30] ;default: 1'b0 ; */\r
-/*description: The interrupt state bit for channel 6's rmt_ch6_tx_thr_event_int_raw\r
- when mt_ch6_tx_thr_event_int_ena is set to 1.*/\r
-#define RMT_CH6_TX_THR_EVENT_INT_ST (BIT(30))\r
-#define RMT_CH6_TX_THR_EVENT_INT_ST_M (BIT(30))\r
-#define RMT_CH6_TX_THR_EVENT_INT_ST_V 0x1\r
-#define RMT_CH6_TX_THR_EVENT_INT_ST_S 30\r
-/* RMT_CH5_TX_THR_EVENT_INT_ST : RO ;bitpos:[29] ;default: 1'b0 ; */\r
-/*description: The interrupt state bit for channel 5's rmt_ch5_tx_thr_event_int_raw\r
- when mt_ch5_tx_thr_event_int_ena is set to 1.*/\r
-#define RMT_CH5_TX_THR_EVENT_INT_ST (BIT(29))\r
-#define RMT_CH5_TX_THR_EVENT_INT_ST_M (BIT(29))\r
-#define RMT_CH5_TX_THR_EVENT_INT_ST_V 0x1\r
-#define RMT_CH5_TX_THR_EVENT_INT_ST_S 29\r
-/* RMT_CH4_TX_THR_EVENT_INT_ST : RO ;bitpos:[28] ;default: 1'b0 ; */\r
-/*description: The interrupt state bit for channel 4's rmt_ch4_tx_thr_event_int_raw\r
- when mt_ch4_tx_thr_event_int_ena is set to 1.*/\r
-#define RMT_CH4_TX_THR_EVENT_INT_ST (BIT(28))\r
-#define RMT_CH4_TX_THR_EVENT_INT_ST_M (BIT(28))\r
-#define RMT_CH4_TX_THR_EVENT_INT_ST_V 0x1\r
-#define RMT_CH4_TX_THR_EVENT_INT_ST_S 28\r
-/* RMT_CH3_TX_THR_EVENT_INT_ST : RO ;bitpos:[27] ;default: 1'b0 ; */\r
-/*description: The interrupt state bit for channel 3's rmt_ch3_tx_thr_event_int_raw\r
- when mt_ch3_tx_thr_event_int_ena is set to 1.*/\r
-#define RMT_CH3_TX_THR_EVENT_INT_ST (BIT(27))\r
-#define RMT_CH3_TX_THR_EVENT_INT_ST_M (BIT(27))\r
-#define RMT_CH3_TX_THR_EVENT_INT_ST_V 0x1\r
-#define RMT_CH3_TX_THR_EVENT_INT_ST_S 27\r
-/* RMT_CH2_TX_THR_EVENT_INT_ST : RO ;bitpos:[26] ;default: 1'b0 ; */\r
-/*description: The interrupt state bit for channel 2's rmt_ch2_tx_thr_event_int_raw\r
- when mt_ch2_tx_thr_event_int_ena is set to 1.*/\r
-#define RMT_CH2_TX_THR_EVENT_INT_ST (BIT(26))\r
-#define RMT_CH2_TX_THR_EVENT_INT_ST_M (BIT(26))\r
-#define RMT_CH2_TX_THR_EVENT_INT_ST_V 0x1\r
-#define RMT_CH2_TX_THR_EVENT_INT_ST_S 26\r
-/* RMT_CH1_TX_THR_EVENT_INT_ST : RO ;bitpos:[25] ;default: 1'b0 ; */\r
-/*description: The interrupt state bit for channel 1's rmt_ch1_tx_thr_event_int_raw\r
- when mt_ch1_tx_thr_event_int_ena is set to 1.*/\r
-#define RMT_CH1_TX_THR_EVENT_INT_ST (BIT(25))\r
-#define RMT_CH1_TX_THR_EVENT_INT_ST_M (BIT(25))\r
-#define RMT_CH1_TX_THR_EVENT_INT_ST_V 0x1\r
-#define RMT_CH1_TX_THR_EVENT_INT_ST_S 25\r
-/* RMT_CH0_TX_THR_EVENT_INT_ST : RO ;bitpos:[24] ;default: 1'b0 ; */\r
-/*description: The interrupt state bit for channel 0's rmt_ch0_tx_thr_event_int_raw\r
- when mt_ch0_tx_thr_event_int_ena is set to 1.*/\r
-#define RMT_CH0_TX_THR_EVENT_INT_ST (BIT(24))\r
-#define RMT_CH0_TX_THR_EVENT_INT_ST_M (BIT(24))\r
-#define RMT_CH0_TX_THR_EVENT_INT_ST_V 0x1\r
-#define RMT_CH0_TX_THR_EVENT_INT_ST_S 24\r
-/* RMT_CH7_ERR_INT_ST : RO ;bitpos:[23] ;default: 1'b0 ; */\r
-/*description: The interrupt state bit for channel 7's rmt_ch7_err_int_raw\r
- when rmt_ch7_err_int_ena is set to 1.*/\r
-#define RMT_CH7_ERR_INT_ST (BIT(23))\r
-#define RMT_CH7_ERR_INT_ST_M (BIT(23))\r
-#define RMT_CH7_ERR_INT_ST_V 0x1\r
-#define RMT_CH7_ERR_INT_ST_S 23\r
-/* RMT_CH7_RX_END_INT_ST : RO ;bitpos:[22] ;default: 1'b0 ; */\r
-/*description: The interrupt state bit for channel 7's rmt_ch7_rx_end_int_raw\r
- when rmt_ch7_rx_end_int_ena is set to 1.*/\r
-#define RMT_CH7_RX_END_INT_ST (BIT(22))\r
-#define RMT_CH7_RX_END_INT_ST_M (BIT(22))\r
-#define RMT_CH7_RX_END_INT_ST_V 0x1\r
-#define RMT_CH7_RX_END_INT_ST_S 22\r
-/* RMT_CH7_TX_END_INT_ST : RO ;bitpos:[21] ;default: 1'b0 ; */\r
-/*description: The interrupt state bit for channel 7's mt_ch7_tx_end_int_raw\r
- when mt_ch7_tx_end_int_ena is set to 1.*/\r
-#define RMT_CH7_TX_END_INT_ST (BIT(21))\r
-#define RMT_CH7_TX_END_INT_ST_M (BIT(21))\r
-#define RMT_CH7_TX_END_INT_ST_V 0x1\r
-#define RMT_CH7_TX_END_INT_ST_S 21\r
-/* RMT_CH6_ERR_INT_ST : RO ;bitpos:[20] ;default: 1'b0 ; */\r
-/*description: The interrupt state bit for channel 6's rmt_ch6_err_int_raw\r
- when rmt_ch6_err_int_ena is set to 1.*/\r
-#define RMT_CH6_ERR_INT_ST (BIT(20))\r
-#define RMT_CH6_ERR_INT_ST_M (BIT(20))\r
-#define RMT_CH6_ERR_INT_ST_V 0x1\r
-#define RMT_CH6_ERR_INT_ST_S 20\r
-/* RMT_CH6_RX_END_INT_ST : RO ;bitpos:[19] ;default: 1'b0 ; */\r
-/*description: The interrupt state bit for channel 6's rmt_ch6_rx_end_int_raw\r
- when rmt_ch6_rx_end_int_ena is set to 1.*/\r
-#define RMT_CH6_RX_END_INT_ST (BIT(19))\r
-#define RMT_CH6_RX_END_INT_ST_M (BIT(19))\r
-#define RMT_CH6_RX_END_INT_ST_V 0x1\r
-#define RMT_CH6_RX_END_INT_ST_S 19\r
-/* RMT_CH6_TX_END_INT_ST : RO ;bitpos:[18] ;default: 1'b0 ; */\r
-/*description: The interrupt state bit for channel 6's mt_ch6_tx_end_int_raw\r
- when mt_ch6_tx_end_int_ena is set to 1.*/\r
-#define RMT_CH6_TX_END_INT_ST (BIT(18))\r
-#define RMT_CH6_TX_END_INT_ST_M (BIT(18))\r
-#define RMT_CH6_TX_END_INT_ST_V 0x1\r
-#define RMT_CH6_TX_END_INT_ST_S 18\r
-/* RMT_CH5_ERR_INT_ST : RO ;bitpos:[17] ;default: 1'b0 ; */\r
-/*description: The interrupt state bit for channel 5's rmt_ch5_err_int_raw\r
- when rmt_ch5_err_int_ena is set to 1.*/\r
-#define RMT_CH5_ERR_INT_ST (BIT(17))\r
-#define RMT_CH5_ERR_INT_ST_M (BIT(17))\r
-#define RMT_CH5_ERR_INT_ST_V 0x1\r
-#define RMT_CH5_ERR_INT_ST_S 17\r
-/* RMT_CH5_RX_END_INT_ST : RO ;bitpos:[16] ;default: 1'b0 ; */\r
-/*description: The interrupt state bit for channel 5's rmt_ch5_rx_end_int_raw\r
- when rmt_ch5_rx_end_int_ena is set to 1.*/\r
-#define RMT_CH5_RX_END_INT_ST (BIT(16))\r
-#define RMT_CH5_RX_END_INT_ST_M (BIT(16))\r
-#define RMT_CH5_RX_END_INT_ST_V 0x1\r
-#define RMT_CH5_RX_END_INT_ST_S 16\r
-/* RMT_CH5_TX_END_INT_ST : RO ;bitpos:[15] ;default: 1'b0 ; */\r
-/*description: The interrupt state bit for channel 5's mt_ch5_tx_end_int_raw\r
- when mt_ch5_tx_end_int_ena is set to 1.*/\r
-#define RMT_CH5_TX_END_INT_ST (BIT(15))\r
-#define RMT_CH5_TX_END_INT_ST_M (BIT(15))\r
-#define RMT_CH5_TX_END_INT_ST_V 0x1\r
-#define RMT_CH5_TX_END_INT_ST_S 15\r
-/* RMT_CH4_ERR_INT_ST : RO ;bitpos:[14] ;default: 1'b0 ; */\r
-/*description: The interrupt state bit for channel 4's rmt_ch4_err_int_raw\r
- when rmt_ch4_err_int_ena is set to 1.*/\r
-#define RMT_CH4_ERR_INT_ST (BIT(14))\r
-#define RMT_CH4_ERR_INT_ST_M (BIT(14))\r
-#define RMT_CH4_ERR_INT_ST_V 0x1\r
-#define RMT_CH4_ERR_INT_ST_S 14\r
-/* RMT_CH4_RX_END_INT_ST : RO ;bitpos:[13] ;default: 1'b0 ; */\r
-/*description: The interrupt state bit for channel 4's rmt_ch4_rx_end_int_raw\r
- when rmt_ch4_rx_end_int_ena is set to 1.*/\r
-#define RMT_CH4_RX_END_INT_ST (BIT(13))\r
-#define RMT_CH4_RX_END_INT_ST_M (BIT(13))\r
-#define RMT_CH4_RX_END_INT_ST_V 0x1\r
-#define RMT_CH4_RX_END_INT_ST_S 13\r
-/* RMT_CH4_TX_END_INT_ST : RO ;bitpos:[12] ;default: 1'b0 ; */\r
-/*description: The interrupt state bit for channel 4's mt_ch4_tx_end_int_raw\r
- when mt_ch4_tx_end_int_ena is set to 1.*/\r
-#define RMT_CH4_TX_END_INT_ST (BIT(12))\r
-#define RMT_CH4_TX_END_INT_ST_M (BIT(12))\r
-#define RMT_CH4_TX_END_INT_ST_V 0x1\r
-#define RMT_CH4_TX_END_INT_ST_S 12\r
-/* RMT_CH3_ERR_INT_ST : RO ;bitpos:[11] ;default: 1'b0 ; */\r
-/*description: The interrupt state bit for channel 3's rmt_ch3_err_int_raw\r
- when rmt_ch3_err_int_ena is set to 1.*/\r
-#define RMT_CH3_ERR_INT_ST (BIT(11))\r
-#define RMT_CH3_ERR_INT_ST_M (BIT(11))\r
-#define RMT_CH3_ERR_INT_ST_V 0x1\r
-#define RMT_CH3_ERR_INT_ST_S 11\r
-/* RMT_CH3_RX_END_INT_ST : RO ;bitpos:[10] ;default: 1'b0 ; */\r
-/*description: The interrupt state bit for channel 3's rmt_ch3_rx_end_int_raw\r
- when rmt_ch3_rx_end_int_ena is set to 1.*/\r
-#define RMT_CH3_RX_END_INT_ST (BIT(10))\r
-#define RMT_CH3_RX_END_INT_ST_M (BIT(10))\r
-#define RMT_CH3_RX_END_INT_ST_V 0x1\r
-#define RMT_CH3_RX_END_INT_ST_S 10\r
-/* RMT_CH3_TX_END_INT_ST : RO ;bitpos:[9] ;default: 1'b0 ; */\r
-/*description: The interrupt state bit for channel 3's mt_ch3_tx_end_int_raw\r
- when mt_ch3_tx_end_int_ena is set to 1.*/\r
-#define RMT_CH3_TX_END_INT_ST (BIT(9))\r
-#define RMT_CH3_TX_END_INT_ST_M (BIT(9))\r
-#define RMT_CH3_TX_END_INT_ST_V 0x1\r
-#define RMT_CH3_TX_END_INT_ST_S 9\r
-/* RMT_CH2_ERR_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */\r
-/*description: The interrupt state bit for channel 2's rmt_ch2_err_int_raw\r
- when rmt_ch2_err_int_ena is set to 1.*/\r
-#define RMT_CH2_ERR_INT_ST (BIT(8))\r
-#define RMT_CH2_ERR_INT_ST_M (BIT(8))\r
-#define RMT_CH2_ERR_INT_ST_V 0x1\r
-#define RMT_CH2_ERR_INT_ST_S 8\r
-/* RMT_CH2_RX_END_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */\r
-/*description: The interrupt state bit for channel 2's rmt_ch2_rx_end_int_raw\r
- when rmt_ch2_rx_end_int_ena is set to 1.*/\r
-#define RMT_CH2_RX_END_INT_ST (BIT(7))\r
-#define RMT_CH2_RX_END_INT_ST_M (BIT(7))\r
-#define RMT_CH2_RX_END_INT_ST_V 0x1\r
-#define RMT_CH2_RX_END_INT_ST_S 7\r
-/* RMT_CH2_TX_END_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */\r
-/*description: The interrupt state bit for channel 2's mt_ch2_tx_end_int_raw\r
- when mt_ch2_tx_end_int_ena is set to 1.*/\r
-#define RMT_CH2_TX_END_INT_ST (BIT(6))\r
-#define RMT_CH2_TX_END_INT_ST_M (BIT(6))\r
-#define RMT_CH2_TX_END_INT_ST_V 0x1\r
-#define RMT_CH2_TX_END_INT_ST_S 6\r
-/* RMT_CH1_ERR_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */\r
-/*description: The interrupt state bit for channel 1's rmt_ch1_err_int_raw\r
- when rmt_ch1_err_int_ena is set to 1.*/\r
-#define RMT_CH1_ERR_INT_ST (BIT(5))\r
-#define RMT_CH1_ERR_INT_ST_M (BIT(5))\r
-#define RMT_CH1_ERR_INT_ST_V 0x1\r
-#define RMT_CH1_ERR_INT_ST_S 5\r
-/* RMT_CH1_RX_END_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */\r
-/*description: The interrupt state bit for channel 1's rmt_ch1_rx_end_int_raw\r
- when rmt_ch1_rx_end_int_ena is set to 1.*/\r
-#define RMT_CH1_RX_END_INT_ST (BIT(4))\r
-#define RMT_CH1_RX_END_INT_ST_M (BIT(4))\r
-#define RMT_CH1_RX_END_INT_ST_V 0x1\r
-#define RMT_CH1_RX_END_INT_ST_S 4\r
-/* RMT_CH1_TX_END_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */\r
-/*description: The interrupt state bit for channel 1's mt_ch1_tx_end_int_raw\r
- when mt_ch1_tx_end_int_ena is set to 1.*/\r
-#define RMT_CH1_TX_END_INT_ST (BIT(3))\r
-#define RMT_CH1_TX_END_INT_ST_M (BIT(3))\r
-#define RMT_CH1_TX_END_INT_ST_V 0x1\r
-#define RMT_CH1_TX_END_INT_ST_S 3\r
-/* RMT_CH0_ERR_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */\r
-/*description: The interrupt state bit for channel 0's rmt_ch0_err_int_raw\r
- when rmt_ch0_err_int_ena is set to 0.*/\r
-#define RMT_CH0_ERR_INT_ST (BIT(2))\r
-#define RMT_CH0_ERR_INT_ST_M (BIT(2))\r
-#define RMT_CH0_ERR_INT_ST_V 0x1\r
-#define RMT_CH0_ERR_INT_ST_S 2\r
-/* RMT_CH0_RX_END_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */\r
-/*description: The interrupt state bit for channel 0's rmt_ch0_rx_end_int_raw\r
- when rmt_ch0_rx_end_int_ena is set to 0.*/\r
-#define RMT_CH0_RX_END_INT_ST (BIT(1))\r
-#define RMT_CH0_RX_END_INT_ST_M (BIT(1))\r
-#define RMT_CH0_RX_END_INT_ST_V 0x1\r
-#define RMT_CH0_RX_END_INT_ST_S 1\r
-/* RMT_CH0_TX_END_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */\r
-/*description: The interrupt state bit for channel 0's mt_ch0_tx_end_int_raw\r
- when mt_ch0_tx_end_int_ena is set to 0.*/\r
-#define RMT_CH0_TX_END_INT_ST (BIT(0))\r
-#define RMT_CH0_TX_END_INT_ST_M (BIT(0))\r
-#define RMT_CH0_TX_END_INT_ST_V 0x1\r
-#define RMT_CH0_TX_END_INT_ST_S 0\r
-\r
-#define RMT_INT_ENA_REG (DR_REG_RMT_BASE + 0x00a8)\r
-/* RMT_CH7_TX_THR_EVENT_INT_ENA : R/W ;bitpos:[31] ;default: 1'b0 ; */\r
-/*description: Set this bit to enable rmt_ch7_tx_thr_event_int_st.*/\r
-#define RMT_CH7_TX_THR_EVENT_INT_ENA (BIT(31))\r
-#define RMT_CH7_TX_THR_EVENT_INT_ENA_M (BIT(31))\r
-#define RMT_CH7_TX_THR_EVENT_INT_ENA_V 0x1\r
-#define RMT_CH7_TX_THR_EVENT_INT_ENA_S 31\r
-/* RMT_CH6_TX_THR_EVENT_INT_ENA : R/W ;bitpos:[30] ;default: 1'b0 ; */\r
-/*description: Set this bit to enable rmt_ch6_tx_thr_event_int_st.*/\r
-#define RMT_CH6_TX_THR_EVENT_INT_ENA (BIT(30))\r
-#define RMT_CH6_TX_THR_EVENT_INT_ENA_M (BIT(30))\r
-#define RMT_CH6_TX_THR_EVENT_INT_ENA_V 0x1\r
-#define RMT_CH6_TX_THR_EVENT_INT_ENA_S 30\r
-/* RMT_CH5_TX_THR_EVENT_INT_ENA : R/W ;bitpos:[29] ;default: 1'b0 ; */\r
-/*description: Set this bit to enable rmt_ch5_tx_thr_event_int_st.*/\r
-#define RMT_CH5_TX_THR_EVENT_INT_ENA (BIT(29))\r
-#define RMT_CH5_TX_THR_EVENT_INT_ENA_M (BIT(29))\r
-#define RMT_CH5_TX_THR_EVENT_INT_ENA_V 0x1\r
-#define RMT_CH5_TX_THR_EVENT_INT_ENA_S 29\r
-/* RMT_CH4_TX_THR_EVENT_INT_ENA : R/W ;bitpos:[28] ;default: 1'b0 ; */\r
-/*description: Set this bit to enable rmt_ch4_tx_thr_event_int_st.*/\r
-#define RMT_CH4_TX_THR_EVENT_INT_ENA (BIT(28))\r
-#define RMT_CH4_TX_THR_EVENT_INT_ENA_M (BIT(28))\r
-#define RMT_CH4_TX_THR_EVENT_INT_ENA_V 0x1\r
-#define RMT_CH4_TX_THR_EVENT_INT_ENA_S 28\r
-/* RMT_CH3_TX_THR_EVENT_INT_ENA : R/W ;bitpos:[27] ;default: 1'b0 ; */\r
-/*description: Set this bit to enable rmt_ch3_tx_thr_event_int_st.*/\r
-#define RMT_CH3_TX_THR_EVENT_INT_ENA (BIT(27))\r
-#define RMT_CH3_TX_THR_EVENT_INT_ENA_M (BIT(27))\r
-#define RMT_CH3_TX_THR_EVENT_INT_ENA_V 0x1\r
-#define RMT_CH3_TX_THR_EVENT_INT_ENA_S 27\r
-/* RMT_CH2_TX_THR_EVENT_INT_ENA : R/W ;bitpos:[26] ;default: 1'b0 ; */\r
-/*description: Set this bit to enable rmt_ch2_tx_thr_event_int_st.*/\r
-#define RMT_CH2_TX_THR_EVENT_INT_ENA (BIT(26))\r
-#define RMT_CH2_TX_THR_EVENT_INT_ENA_M (BIT(26))\r
-#define RMT_CH2_TX_THR_EVENT_INT_ENA_V 0x1\r
-#define RMT_CH2_TX_THR_EVENT_INT_ENA_S 26\r
-/* RMT_CH1_TX_THR_EVENT_INT_ENA : R/W ;bitpos:[25] ;default: 1'b0 ; */\r
-/*description: Set this bit to enable rmt_ch1_tx_thr_event_int_st.*/\r
-#define RMT_CH1_TX_THR_EVENT_INT_ENA (BIT(25))\r
-#define RMT_CH1_TX_THR_EVENT_INT_ENA_M (BIT(25))\r
-#define RMT_CH1_TX_THR_EVENT_INT_ENA_V 0x1\r
-#define RMT_CH1_TX_THR_EVENT_INT_ENA_S 25\r
-/* RMT_CH0_TX_THR_EVENT_INT_ENA : R/W ;bitpos:[24] ;default: 1'b0 ; */\r
-/*description: Set this bit to enable rmt_ch0_tx_thr_event_int_st.*/\r
-#define RMT_CH0_TX_THR_EVENT_INT_ENA (BIT(24))\r
-#define RMT_CH0_TX_THR_EVENT_INT_ENA_M (BIT(24))\r
-#define RMT_CH0_TX_THR_EVENT_INT_ENA_V 0x1\r
-#define RMT_CH0_TX_THR_EVENT_INT_ENA_S 24\r
-/* RMT_CH7_ERR_INT_ENA : R/W ;bitpos:[23] ;default: 1'b0 ; */\r
-/*description: Set this bit to enable rmt_ch7_err_int_st.*/\r
-#define RMT_CH7_ERR_INT_ENA (BIT(23))\r
-#define RMT_CH7_ERR_INT_ENA_M (BIT(23))\r
-#define RMT_CH7_ERR_INT_ENA_V 0x1\r
-#define RMT_CH7_ERR_INT_ENA_S 23\r
-/* RMT_CH7_RX_END_INT_ENA : R/W ;bitpos:[22] ;default: 1'b0 ; */\r
-/*description: Set this bit to enable rmt_ch7_rx_end_int_st.*/\r
-#define RMT_CH7_RX_END_INT_ENA (BIT(22))\r
-#define RMT_CH7_RX_END_INT_ENA_M (BIT(22))\r
-#define RMT_CH7_RX_END_INT_ENA_V 0x1\r
-#define RMT_CH7_RX_END_INT_ENA_S 22\r
-/* RMT_CH7_TX_END_INT_ENA : R/W ;bitpos:[21] ;default: 1'b0 ; */\r
-/*description: Set this bit to enable rmt_ch7_tx_end_int_st.*/\r
-#define RMT_CH7_TX_END_INT_ENA (BIT(21))\r
-#define RMT_CH7_TX_END_INT_ENA_M (BIT(21))\r
-#define RMT_CH7_TX_END_INT_ENA_V 0x1\r
-#define RMT_CH7_TX_END_INT_ENA_S 21\r
-/* RMT_CH6_ERR_INT_ENA : R/W ;bitpos:[20] ;default: 1'b0 ; */\r
-/*description: Set this bit to enable rmt_ch6_err_int_st.*/\r
-#define RMT_CH6_ERR_INT_ENA (BIT(20))\r
-#define RMT_CH6_ERR_INT_ENA_M (BIT(20))\r
-#define RMT_CH6_ERR_INT_ENA_V 0x1\r
-#define RMT_CH6_ERR_INT_ENA_S 20\r
-/* RMT_CH6_RX_END_INT_ENA : R/W ;bitpos:[19] ;default: 1'b0 ; */\r
-/*description: Set this bit to enable rmt_ch6_rx_end_int_st.*/\r
-#define RMT_CH6_RX_END_INT_ENA (BIT(19))\r
-#define RMT_CH6_RX_END_INT_ENA_M (BIT(19))\r
-#define RMT_CH6_RX_END_INT_ENA_V 0x1\r
-#define RMT_CH6_RX_END_INT_ENA_S 19\r
-/* RMT_CH6_TX_END_INT_ENA : R/W ;bitpos:[18] ;default: 1'b0 ; */\r
-/*description: Set this bit to enable rmt_ch6_tx_end_int_st.*/\r
-#define RMT_CH6_TX_END_INT_ENA (BIT(18))\r
-#define RMT_CH6_TX_END_INT_ENA_M (BIT(18))\r
-#define RMT_CH6_TX_END_INT_ENA_V 0x1\r
-#define RMT_CH6_TX_END_INT_ENA_S 18\r
-/* RMT_CH5_ERR_INT_ENA : R/W ;bitpos:[17] ;default: 1'b0 ; */\r
-/*description: Set this bit to enable rmt_ch5_err_int_st.*/\r
-#define RMT_CH5_ERR_INT_ENA (BIT(17))\r
-#define RMT_CH5_ERR_INT_ENA_M (BIT(17))\r
-#define RMT_CH5_ERR_INT_ENA_V 0x1\r
-#define RMT_CH5_ERR_INT_ENA_S 17\r
-/* RMT_CH5_RX_END_INT_ENA : R/W ;bitpos:[16] ;default: 1'b0 ; */\r
-/*description: Set this bit to enable rmt_ch5_rx_end_int_st.*/\r
-#define RMT_CH5_RX_END_INT_ENA (BIT(16))\r
-#define RMT_CH5_RX_END_INT_ENA_M (BIT(16))\r
-#define RMT_CH5_RX_END_INT_ENA_V 0x1\r
-#define RMT_CH5_RX_END_INT_ENA_S 16\r
-/* RMT_CH5_TX_END_INT_ENA : R/W ;bitpos:[15] ;default: 1'b0 ; */\r
-/*description: Set this bit to enable rmt_ch5_tx_end_int_st.*/\r
-#define RMT_CH5_TX_END_INT_ENA (BIT(15))\r
-#define RMT_CH5_TX_END_INT_ENA_M (BIT(15))\r
-#define RMT_CH5_TX_END_INT_ENA_V 0x1\r
-#define RMT_CH5_TX_END_INT_ENA_S 15\r
-/* RMT_CH4_ERR_INT_ENA : R/W ;bitpos:[14] ;default: 1'b0 ; */\r
-/*description: Set this bit to enable rmt_ch4_err_int_st.*/\r
-#define RMT_CH4_ERR_INT_ENA (BIT(14))\r
-#define RMT_CH4_ERR_INT_ENA_M (BIT(14))\r
-#define RMT_CH4_ERR_INT_ENA_V 0x1\r
-#define RMT_CH4_ERR_INT_ENA_S 14\r
-/* RMT_CH4_RX_END_INT_ENA : R/W ;bitpos:[13] ;default: 1'b0 ; */\r
-/*description: Set this bit to enable rmt_ch4_rx_end_int_st.*/\r
-#define RMT_CH4_RX_END_INT_ENA (BIT(13))\r
-#define RMT_CH4_RX_END_INT_ENA_M (BIT(13))\r
-#define RMT_CH4_RX_END_INT_ENA_V 0x1\r
-#define RMT_CH4_RX_END_INT_ENA_S 13\r
-/* RMT_CH4_TX_END_INT_ENA : R/W ;bitpos:[12] ;default: 1'b0 ; */\r
-/*description: Set this bit to enable rmt_ch4_tx_end_int_st.*/\r
-#define RMT_CH4_TX_END_INT_ENA (BIT(12))\r
-#define RMT_CH4_TX_END_INT_ENA_M (BIT(12))\r
-#define RMT_CH4_TX_END_INT_ENA_V 0x1\r
-#define RMT_CH4_TX_END_INT_ENA_S 12\r
-/* RMT_CH3_ERR_INT_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */\r
-/*description: Set this bit to enable rmt_ch3_err_int_st.*/\r
-#define RMT_CH3_ERR_INT_ENA (BIT(11))\r
-#define RMT_CH3_ERR_INT_ENA_M (BIT(11))\r
-#define RMT_CH3_ERR_INT_ENA_V 0x1\r
-#define RMT_CH3_ERR_INT_ENA_S 11\r
-/* RMT_CH3_RX_END_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */\r
-/*description: Set this bit to enable rmt_ch3_rx_end_int_st.*/\r
-#define RMT_CH3_RX_END_INT_ENA (BIT(10))\r
-#define RMT_CH3_RX_END_INT_ENA_M (BIT(10))\r
-#define RMT_CH3_RX_END_INT_ENA_V 0x1\r
-#define RMT_CH3_RX_END_INT_ENA_S 10\r
-/* RMT_CH3_TX_END_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */\r
-/*description: Set this bit to enable rmt_ch3_tx_end_int_st.*/\r
-#define RMT_CH3_TX_END_INT_ENA (BIT(9))\r
-#define RMT_CH3_TX_END_INT_ENA_M (BIT(9))\r
-#define RMT_CH3_TX_END_INT_ENA_V 0x1\r
-#define RMT_CH3_TX_END_INT_ENA_S 9\r
-/* RMT_CH2_ERR_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */\r
-/*description: Set this bit to enable rmt_ch2_err_int_st.*/\r
-#define RMT_CH2_ERR_INT_ENA (BIT(8))\r
-#define RMT_CH2_ERR_INT_ENA_M (BIT(8))\r
-#define RMT_CH2_ERR_INT_ENA_V 0x1\r
-#define RMT_CH2_ERR_INT_ENA_S 8\r
-/* RMT_CH2_RX_END_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */\r
-/*description: Set this bit to enable rmt_ch2_rx_end_int_st.*/\r
-#define RMT_CH2_RX_END_INT_ENA (BIT(7))\r
-#define RMT_CH2_RX_END_INT_ENA_M (BIT(7))\r
-#define RMT_CH2_RX_END_INT_ENA_V 0x1\r
-#define RMT_CH2_RX_END_INT_ENA_S 7\r
-/* RMT_CH2_TX_END_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */\r
-/*description: Set this bit to enable rmt_ch2_tx_end_int_st.*/\r
-#define RMT_CH2_TX_END_INT_ENA (BIT(6))\r
-#define RMT_CH2_TX_END_INT_ENA_M (BIT(6))\r
-#define RMT_CH2_TX_END_INT_ENA_V 0x1\r
-#define RMT_CH2_TX_END_INT_ENA_S 6\r
-/* RMT_CH1_ERR_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */\r
-/*description: Set this bit to enable rmt_ch1_err_int_st.*/\r
-#define RMT_CH1_ERR_INT_ENA (BIT(5))\r
-#define RMT_CH1_ERR_INT_ENA_M (BIT(5))\r
-#define RMT_CH1_ERR_INT_ENA_V 0x1\r
-#define RMT_CH1_ERR_INT_ENA_S 5\r
-/* RMT_CH1_RX_END_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */\r
-/*description: Set this bit to enable rmt_ch1_rx_end_int_st.*/\r
-#define RMT_CH1_RX_END_INT_ENA (BIT(4))\r
-#define RMT_CH1_RX_END_INT_ENA_M (BIT(4))\r
-#define RMT_CH1_RX_END_INT_ENA_V 0x1\r
-#define RMT_CH1_RX_END_INT_ENA_S 4\r
-/* RMT_CH1_TX_END_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */\r
-/*description: Set this bit to enable rmt_ch1_tx_end_int_st.*/\r
-#define RMT_CH1_TX_END_INT_ENA (BIT(3))\r
-#define RMT_CH1_TX_END_INT_ENA_M (BIT(3))\r
-#define RMT_CH1_TX_END_INT_ENA_V 0x1\r
-#define RMT_CH1_TX_END_INT_ENA_S 3\r
-/* RMT_CH0_ERR_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */\r
-/*description: Set this bit to enable rmt_ch0_err_int_st.*/\r
-#define RMT_CH0_ERR_INT_ENA (BIT(2))\r
-#define RMT_CH0_ERR_INT_ENA_M (BIT(2))\r
-#define RMT_CH0_ERR_INT_ENA_V 0x1\r
-#define RMT_CH0_ERR_INT_ENA_S 2\r
-/* RMT_CH0_RX_END_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */\r
-/*description: Set this bit to enable rmt_ch0_rx_end_int_st.*/\r
-#define RMT_CH0_RX_END_INT_ENA (BIT(1))\r
-#define RMT_CH0_RX_END_INT_ENA_M (BIT(1))\r
-#define RMT_CH0_RX_END_INT_ENA_V 0x1\r
-#define RMT_CH0_RX_END_INT_ENA_S 1\r
-/* RMT_CH0_TX_END_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */\r
-/*description: Set this bit to enable rmt_ch0_tx_end_int_st.*/\r
-#define RMT_CH0_TX_END_INT_ENA (BIT(0))\r
-#define RMT_CH0_TX_END_INT_ENA_M (BIT(0))\r
-#define RMT_CH0_TX_END_INT_ENA_V 0x1\r
-#define RMT_CH0_TX_END_INT_ENA_S 0\r
-\r
-#define RMT_INT_CLR_REG (DR_REG_RMT_BASE + 0x00ac)\r
-/* RMT_CH7_TX_THR_EVENT_INT_CLR : WO ;bitpos:[31] ;default: 1'b0 ; */\r
-/*description: Set this bit to clear the rmt_ch7_tx_thr_event_int_raw interrupt.*/\r
-#define RMT_CH7_TX_THR_EVENT_INT_CLR (BIT(31))\r
-#define RMT_CH7_TX_THR_EVENT_INT_CLR_M (BIT(31))\r
-#define RMT_CH7_TX_THR_EVENT_INT_CLR_V 0x1\r
-#define RMT_CH7_TX_THR_EVENT_INT_CLR_S 31\r
-/* RMT_CH6_TX_THR_EVENT_INT_CLR : WO ;bitpos:[30] ;default: 1'b0 ; */\r
-/*description: Set this bit to clear the rmt_ch6_tx_thr_event_int_raw interrupt.*/\r
-#define RMT_CH6_TX_THR_EVENT_INT_CLR (BIT(30))\r
-#define RMT_CH6_TX_THR_EVENT_INT_CLR_M (BIT(30))\r
-#define RMT_CH6_TX_THR_EVENT_INT_CLR_V 0x1\r
-#define RMT_CH6_TX_THR_EVENT_INT_CLR_S 30\r
-/* RMT_CH5_TX_THR_EVENT_INT_CLR : WO ;bitpos:[29] ;default: 1'b0 ; */\r
-/*description: Set this bit to clear the rmt_ch5_tx_thr_event_int_raw interrupt.*/\r
-#define RMT_CH5_TX_THR_EVENT_INT_CLR (BIT(29))\r
-#define RMT_CH5_TX_THR_EVENT_INT_CLR_M (BIT(29))\r
-#define RMT_CH5_TX_THR_EVENT_INT_CLR_V 0x1\r
-#define RMT_CH5_TX_THR_EVENT_INT_CLR_S 29\r
-/* RMT_CH4_TX_THR_EVENT_INT_CLR : WO ;bitpos:[28] ;default: 1'b0 ; */\r
-/*description: Set this bit to clear the rmt_ch4_tx_thr_event_int_raw interrupt.*/\r
-#define RMT_CH4_TX_THR_EVENT_INT_CLR (BIT(28))\r
-#define RMT_CH4_TX_THR_EVENT_INT_CLR_M (BIT(28))\r
-#define RMT_CH4_TX_THR_EVENT_INT_CLR_V 0x1\r
-#define RMT_CH4_TX_THR_EVENT_INT_CLR_S 28\r
-/* RMT_CH3_TX_THR_EVENT_INT_CLR : WO ;bitpos:[27] ;default: 1'b0 ; */\r
-/*description: Set this bit to clear the rmt_ch3_tx_thr_event_int_raw interrupt.*/\r
-#define RMT_CH3_TX_THR_EVENT_INT_CLR (BIT(27))\r
-#define RMT_CH3_TX_THR_EVENT_INT_CLR_M (BIT(27))\r
-#define RMT_CH3_TX_THR_EVENT_INT_CLR_V 0x1\r
-#define RMT_CH3_TX_THR_EVENT_INT_CLR_S 27\r
-/* RMT_CH2_TX_THR_EVENT_INT_CLR : WO ;bitpos:[26] ;default: 1'b0 ; */\r
-/*description: Set this bit to clear the rmt_ch2_tx_thr_event_int_raw interrupt.*/\r
-#define RMT_CH2_TX_THR_EVENT_INT_CLR (BIT(26))\r
-#define RMT_CH2_TX_THR_EVENT_INT_CLR_M (BIT(26))\r
-#define RMT_CH2_TX_THR_EVENT_INT_CLR_V 0x1\r
-#define RMT_CH2_TX_THR_EVENT_INT_CLR_S 26\r
-/* RMT_CH1_TX_THR_EVENT_INT_CLR : WO ;bitpos:[25] ;default: 1'b0 ; */\r
-/*description: Set this bit to clear the rmt_ch1_tx_thr_event_int_raw interrupt.*/\r
-#define RMT_CH1_TX_THR_EVENT_INT_CLR (BIT(25))\r
-#define RMT_CH1_TX_THR_EVENT_INT_CLR_M (BIT(25))\r
-#define RMT_CH1_TX_THR_EVENT_INT_CLR_V 0x1\r
-#define RMT_CH1_TX_THR_EVENT_INT_CLR_S 25\r
-/* RMT_CH0_TX_THR_EVENT_INT_CLR : WO ;bitpos:[24] ;default: 1'b0 ; */\r
-/*description: Set this bit to clear the rmt_ch0_tx_thr_event_int_raw interrupt.*/\r
-#define RMT_CH0_TX_THR_EVENT_INT_CLR (BIT(24))\r
-#define RMT_CH0_TX_THR_EVENT_INT_CLR_M (BIT(24))\r
-#define RMT_CH0_TX_THR_EVENT_INT_CLR_V 0x1\r
-#define RMT_CH0_TX_THR_EVENT_INT_CLR_S 24\r
-/* RMT_CH7_ERR_INT_CLR : WO ;bitpos:[23] ;default: 1'b0 ; */\r
-/*description: Set this bit to clear the rmt_ch7_err_int_raw.*/\r
-#define RMT_CH7_ERR_INT_CLR (BIT(23))\r
-#define RMT_CH7_ERR_INT_CLR_M (BIT(23))\r
-#define RMT_CH7_ERR_INT_CLR_V 0x1\r
-#define RMT_CH7_ERR_INT_CLR_S 23\r
-/* RMT_CH7_RX_END_INT_CLR : WO ;bitpos:[22] ;default: 1'b0 ; */\r
-/*description: Set this bit to clear the rmt_ch7_tx_end_int_raw.*/\r
-#define RMT_CH7_RX_END_INT_CLR (BIT(22))\r
-#define RMT_CH7_RX_END_INT_CLR_M (BIT(22))\r
-#define RMT_CH7_RX_END_INT_CLR_V 0x1\r
-#define RMT_CH7_RX_END_INT_CLR_S 22\r
-/* RMT_CH7_TX_END_INT_CLR : WO ;bitpos:[21] ;default: 1'b0 ; */\r
-/*description: Set this bit to clear the rmt_ch7_rx_end_int_raw..*/\r
-#define RMT_CH7_TX_END_INT_CLR (BIT(21))\r
-#define RMT_CH7_TX_END_INT_CLR_M (BIT(21))\r
-#define RMT_CH7_TX_END_INT_CLR_V 0x1\r
-#define RMT_CH7_TX_END_INT_CLR_S 21\r
-/* RMT_CH6_ERR_INT_CLR : WO ;bitpos:[20] ;default: 1'b0 ; */\r
-/*description: Set this bit to clear the rmt_ch6_err_int_raw.*/\r
-#define RMT_CH6_ERR_INT_CLR (BIT(20))\r
-#define RMT_CH6_ERR_INT_CLR_M (BIT(20))\r
-#define RMT_CH6_ERR_INT_CLR_V 0x1\r
-#define RMT_CH6_ERR_INT_CLR_S 20\r
-/* RMT_CH6_RX_END_INT_CLR : WO ;bitpos:[19] ;default: 1'b0 ; */\r
-/*description: Set this bit to clear the rmt_ch6_tx_end_int_raw.*/\r
-#define RMT_CH6_RX_END_INT_CLR (BIT(19))\r
-#define RMT_CH6_RX_END_INT_CLR_M (BIT(19))\r
-#define RMT_CH6_RX_END_INT_CLR_V 0x1\r
-#define RMT_CH6_RX_END_INT_CLR_S 19\r
-/* RMT_CH6_TX_END_INT_CLR : WO ;bitpos:[18] ;default: 1'b0 ; */\r
-/*description: Set this bit to clear the rmt_ch6_rx_end_int_raw..*/\r
-#define RMT_CH6_TX_END_INT_CLR (BIT(18))\r
-#define RMT_CH6_TX_END_INT_CLR_M (BIT(18))\r
-#define RMT_CH6_TX_END_INT_CLR_V 0x1\r
-#define RMT_CH6_TX_END_INT_CLR_S 18\r
-/* RMT_CH5_ERR_INT_CLR : WO ;bitpos:[17] ;default: 1'b0 ; */\r
-/*description: Set this bit to clear the rmt_ch5_err_int_raw.*/\r
-#define RMT_CH5_ERR_INT_CLR (BIT(17))\r
-#define RMT_CH5_ERR_INT_CLR_M (BIT(17))\r
-#define RMT_CH5_ERR_INT_CLR_V 0x1\r
-#define RMT_CH5_ERR_INT_CLR_S 17\r
-/* RMT_CH5_RX_END_INT_CLR : WO ;bitpos:[16] ;default: 1'b0 ; */\r
-/*description: Set this bit to clear the rmt_ch5_tx_end_int_raw.*/\r
-#define RMT_CH5_RX_END_INT_CLR (BIT(16))\r
-#define RMT_CH5_RX_END_INT_CLR_M (BIT(16))\r
-#define RMT_CH5_RX_END_INT_CLR_V 0x1\r
-#define RMT_CH5_RX_END_INT_CLR_S 16\r
-/* RMT_CH5_TX_END_INT_CLR : WO ;bitpos:[15] ;default: 1'b0 ; */\r
-/*description: Set this bit to clear the rmt_ch5_rx_end_int_raw..*/\r
-#define RMT_CH5_TX_END_INT_CLR (BIT(15))\r
-#define RMT_CH5_TX_END_INT_CLR_M (BIT(15))\r
-#define RMT_CH5_TX_END_INT_CLR_V 0x1\r
-#define RMT_CH5_TX_END_INT_CLR_S 15\r
-/* RMT_CH4_ERR_INT_CLR : WO ;bitpos:[14] ;default: 1'b0 ; */\r
-/*description: Set this bit to clear the rmt_ch4_err_int_raw.*/\r
-#define RMT_CH4_ERR_INT_CLR (BIT(14))\r
-#define RMT_CH4_ERR_INT_CLR_M (BIT(14))\r
-#define RMT_CH4_ERR_INT_CLR_V 0x1\r
-#define RMT_CH4_ERR_INT_CLR_S 14\r
-/* RMT_CH4_RX_END_INT_CLR : WO ;bitpos:[13] ;default: 1'b0 ; */\r
-/*description: Set this bit to clear the rmt_ch4_tx_end_int_raw.*/\r
-#define RMT_CH4_RX_END_INT_CLR (BIT(13))\r
-#define RMT_CH4_RX_END_INT_CLR_M (BIT(13))\r
-#define RMT_CH4_RX_END_INT_CLR_V 0x1\r
-#define RMT_CH4_RX_END_INT_CLR_S 13\r
-/* RMT_CH4_TX_END_INT_CLR : WO ;bitpos:[12] ;default: 1'b0 ; */\r
-/*description: Set this bit to clear the rmt_ch4_rx_end_int_raw..*/\r
-#define RMT_CH4_TX_END_INT_CLR (BIT(12))\r
-#define RMT_CH4_TX_END_INT_CLR_M (BIT(12))\r
-#define RMT_CH4_TX_END_INT_CLR_V 0x1\r
-#define RMT_CH4_TX_END_INT_CLR_S 12\r
-/* RMT_CH3_ERR_INT_CLR : WO ;bitpos:[11] ;default: 1'b0 ; */\r
-/*description: Set this bit to clear the rmt_ch3_err_int_raw.*/\r
-#define RMT_CH3_ERR_INT_CLR (BIT(11))\r
-#define RMT_CH3_ERR_INT_CLR_M (BIT(11))\r
-#define RMT_CH3_ERR_INT_CLR_V 0x1\r
-#define RMT_CH3_ERR_INT_CLR_S 11\r
-/* RMT_CH3_RX_END_INT_CLR : WO ;bitpos:[10] ;default: 1'b0 ; */\r
-/*description: Set this bit to clear the rmt_ch3_tx_end_int_raw.*/\r
-#define RMT_CH3_RX_END_INT_CLR (BIT(10))\r
-#define RMT_CH3_RX_END_INT_CLR_M (BIT(10))\r
-#define RMT_CH3_RX_END_INT_CLR_V 0x1\r
-#define RMT_CH3_RX_END_INT_CLR_S 10\r
-/* RMT_CH3_TX_END_INT_CLR : WO ;bitpos:[9] ;default: 1'b0 ; */\r
-/*description: Set this bit to clear the rmt_ch3_rx_end_int_raw..*/\r
-#define RMT_CH3_TX_END_INT_CLR (BIT(9))\r
-#define RMT_CH3_TX_END_INT_CLR_M (BIT(9))\r
-#define RMT_CH3_TX_END_INT_CLR_V 0x1\r
-#define RMT_CH3_TX_END_INT_CLR_S 9\r
-/* RMT_CH2_ERR_INT_CLR : WO ;bitpos:[8] ;default: 1'b0 ; */\r
-/*description: Set this bit to clear the rmt_ch2_err_int_raw.*/\r
-#define RMT_CH2_ERR_INT_CLR (BIT(8))\r
-#define RMT_CH2_ERR_INT_CLR_M (BIT(8))\r
-#define RMT_CH2_ERR_INT_CLR_V 0x1\r
-#define RMT_CH2_ERR_INT_CLR_S 8\r
-/* RMT_CH2_RX_END_INT_CLR : WO ;bitpos:[7] ;default: 1'b0 ; */\r
-/*description: Set this bit to clear the rmt_ch2_tx_end_int_raw.*/\r
-#define RMT_CH2_RX_END_INT_CLR (BIT(7))\r
-#define RMT_CH2_RX_END_INT_CLR_M (BIT(7))\r
-#define RMT_CH2_RX_END_INT_CLR_V 0x1\r
-#define RMT_CH2_RX_END_INT_CLR_S 7\r
-/* RMT_CH2_TX_END_INT_CLR : WO ;bitpos:[6] ;default: 1'b0 ; */\r
-/*description: Set this bit to clear the rmt_ch2_rx_end_int_raw..*/\r
-#define RMT_CH2_TX_END_INT_CLR (BIT(6))\r
-#define RMT_CH2_TX_END_INT_CLR_M (BIT(6))\r
-#define RMT_CH2_TX_END_INT_CLR_V 0x1\r
-#define RMT_CH2_TX_END_INT_CLR_S 6\r
-/* RMT_CH1_ERR_INT_CLR : WO ;bitpos:[5] ;default: 1'b0 ; */\r
-/*description: Set this bit to clear the rmt_ch1_err_int_raw.*/\r
-#define RMT_CH1_ERR_INT_CLR (BIT(5))\r
-#define RMT_CH1_ERR_INT_CLR_M (BIT(5))\r
-#define RMT_CH1_ERR_INT_CLR_V 0x1\r
-#define RMT_CH1_ERR_INT_CLR_S 5\r
-/* RMT_CH1_RX_END_INT_CLR : WO ;bitpos:[4] ;default: 1'b0 ; */\r
-/*description: Set this bit to clear the rmt_ch1_tx_end_int_raw.*/\r
-#define RMT_CH1_RX_END_INT_CLR (BIT(4))\r
-#define RMT_CH1_RX_END_INT_CLR_M (BIT(4))\r
-#define RMT_CH1_RX_END_INT_CLR_V 0x1\r
-#define RMT_CH1_RX_END_INT_CLR_S 4\r
-/* RMT_CH1_TX_END_INT_CLR : WO ;bitpos:[3] ;default: 1'b0 ; */\r
-/*description: Set this bit to clear the rmt_ch1_rx_end_int_raw..*/\r
-#define RMT_CH1_TX_END_INT_CLR (BIT(3))\r
-#define RMT_CH1_TX_END_INT_CLR_M (BIT(3))\r
-#define RMT_CH1_TX_END_INT_CLR_V 0x1\r
-#define RMT_CH1_TX_END_INT_CLR_S 3\r
-/* RMT_CH0_ERR_INT_CLR : WO ;bitpos:[2] ;default: 1'b0 ; */\r
-/*description: Set this bit to clear the rmt_ch0_err_int_raw.*/\r
-#define RMT_CH0_ERR_INT_CLR (BIT(2))\r
-#define RMT_CH0_ERR_INT_CLR_M (BIT(2))\r
-#define RMT_CH0_ERR_INT_CLR_V 0x1\r
-#define RMT_CH0_ERR_INT_CLR_S 2\r
-/* RMT_CH0_RX_END_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */\r
-/*description: Set this bit to clear the rmt_ch0_tx_end_int_raw.*/\r
-#define RMT_CH0_RX_END_INT_CLR (BIT(1))\r
-#define RMT_CH0_RX_END_INT_CLR_M (BIT(1))\r
-#define RMT_CH0_RX_END_INT_CLR_V 0x1\r
-#define RMT_CH0_RX_END_INT_CLR_S 1\r
-/* RMT_CH0_TX_END_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */\r
-/*description: Set this bit to clear the rmt_ch0_rx_end_int_raw..*/\r
-#define RMT_CH0_TX_END_INT_CLR (BIT(0))\r
-#define RMT_CH0_TX_END_INT_CLR_M (BIT(0))\r
-#define RMT_CH0_TX_END_INT_CLR_V 0x1\r
-#define RMT_CH0_TX_END_INT_CLR_S 0\r
-\r
-#define RMT_CH0CARRIER_DUTY_REG (DR_REG_RMT_BASE + 0x00b0)\r
-/* RMT_CARRIER_HIGH_CH0 : R/W ;bitpos:[31:16] ;default: 16'h40 ; */\r
-/*description: This register is used to configure carrier wave's high level value for channel0.*/\r
-#define RMT_CARRIER_HIGH_CH0 0x0000FFFF\r
-#define RMT_CARRIER_HIGH_CH0_M ((RMT_CARRIER_HIGH_CH0_V)<<(RMT_CARRIER_HIGH_CH0_S))\r
-#define RMT_CARRIER_HIGH_CH0_V 0xFFFF\r
-#define RMT_CARRIER_HIGH_CH0_S 16\r
-/* RMT_CARRIER_LOW_CH0 : R/W ;bitpos:[15:0] ;default: 16'h40 ; */\r
-/*description: This register is used to configure carrier wave's low level value for channel0.*/\r
-#define RMT_CARRIER_LOW_CH0 0x0000FFFF\r
-#define RMT_CARRIER_LOW_CH0_M ((RMT_CARRIER_LOW_CH0_V)<<(RMT_CARRIER_LOW_CH0_S))\r
-#define RMT_CARRIER_LOW_CH0_V 0xFFFF\r
-#define RMT_CARRIER_LOW_CH0_S 0\r
-\r
-#define RMT_CH1CARRIER_DUTY_REG (DR_REG_RMT_BASE + 0x00b4)\r
-/* RMT_CARRIER_HIGH_CH1 : R/W ;bitpos:[31:16] ;default: 16'h40 ; */\r
-/*description: This register is used to configure carrier wave's high level value for channel1.*/\r
-#define RMT_CARRIER_HIGH_CH1 0x0000FFFF\r
-#define RMT_CARRIER_HIGH_CH1_M ((RMT_CARRIER_HIGH_CH1_V)<<(RMT_CARRIER_HIGH_CH1_S))\r
-#define RMT_CARRIER_HIGH_CH1_V 0xFFFF\r
-#define RMT_CARRIER_HIGH_CH1_S 16\r
-/* RMT_CARRIER_LOW_CH1 : R/W ;bitpos:[15:0] ;default: 16'h40 ; */\r
-/*description: This register is used to configure carrier wave's low level value for channel1.*/\r
-#define RMT_CARRIER_LOW_CH1 0x0000FFFF\r
-#define RMT_CARRIER_LOW_CH1_M ((RMT_CARRIER_LOW_CH1_V)<<(RMT_CARRIER_LOW_CH1_S))\r
-#define RMT_CARRIER_LOW_CH1_V 0xFFFF\r
-#define RMT_CARRIER_LOW_CH1_S 0\r
-\r
-#define RMT_CH2CARRIER_DUTY_REG (DR_REG_RMT_BASE + 0x00b8)\r
-/* RMT_CARRIER_HIGH_CH2 : R/W ;bitpos:[31:16] ;default: 16'h40 ; */\r
-/*description: This register is used to configure carrier wave's high level value for channel2.*/\r
-#define RMT_CARRIER_HIGH_CH2 0x0000FFFF\r
-#define RMT_CARRIER_HIGH_CH2_M ((RMT_CARRIER_HIGH_CH2_V)<<(RMT_CARRIER_HIGH_CH2_S))\r
-#define RMT_CARRIER_HIGH_CH2_V 0xFFFF\r
-#define RMT_CARRIER_HIGH_CH2_S 16\r
-/* RMT_CARRIER_LOW_CH2 : R/W ;bitpos:[15:0] ;default: 16'h40 ; */\r
-/*description: This register is used to configure carrier wave's low level value for channel2.*/\r
-#define RMT_CARRIER_LOW_CH2 0x0000FFFF\r
-#define RMT_CARRIER_LOW_CH2_M ((RMT_CARRIER_LOW_CH2_V)<<(RMT_CARRIER_LOW_CH2_S))\r
-#define RMT_CARRIER_LOW_CH2_V 0xFFFF\r
-#define RMT_CARRIER_LOW_CH2_S 0\r
-\r
-#define RMT_CH3CARRIER_DUTY_REG (DR_REG_RMT_BASE + 0x00bc)\r
-/* RMT_CARRIER_HIGH_CH3 : R/W ;bitpos:[31:16] ;default: 16'h40 ; */\r
-/*description: This register is used to configure carrier wave's high level value for channel3.*/\r
-#define RMT_CARRIER_HIGH_CH3 0x0000FFFF\r
-#define RMT_CARRIER_HIGH_CH3_M ((RMT_CARRIER_HIGH_CH3_V)<<(RMT_CARRIER_HIGH_CH3_S))\r
-#define RMT_CARRIER_HIGH_CH3_V 0xFFFF\r
-#define RMT_CARRIER_HIGH_CH3_S 16\r
-/* RMT_CARRIER_LOW_CH3 : R/W ;bitpos:[15:0] ;default: 16'h40 ; */\r
-/*description: This register is used to configure carrier wave's low level value for channel3.*/\r
-#define RMT_CARRIER_LOW_CH3 0x0000FFFF\r
-#define RMT_CARRIER_LOW_CH3_M ((RMT_CARRIER_LOW_CH3_V)<<(RMT_CARRIER_LOW_CH3_S))\r
-#define RMT_CARRIER_LOW_CH3_V 0xFFFF\r
-#define RMT_CARRIER_LOW_CH3_S 0\r
-\r
-#define RMT_CH4CARRIER_DUTY_REG (DR_REG_RMT_BASE + 0x00c0)\r
-/* RMT_CARRIER_HIGH_CH4 : R/W ;bitpos:[31:16] ;default: 16'h40 ; */\r
-/*description: This register is used to configure carrier wave's high level value for channel4.*/\r
-#define RMT_CARRIER_HIGH_CH4 0x0000FFFF\r
-#define RMT_CARRIER_HIGH_CH4_M ((RMT_CARRIER_HIGH_CH4_V)<<(RMT_CARRIER_HIGH_CH4_S))\r
-#define RMT_CARRIER_HIGH_CH4_V 0xFFFF\r
-#define RMT_CARRIER_HIGH_CH4_S 16\r
-/* RMT_CARRIER_LOW_CH4 : R/W ;bitpos:[15:0] ;default: 16'h40 ; */\r
-/*description: This register is used to configure carrier wave's low level value for channel4.*/\r
-#define RMT_CARRIER_LOW_CH4 0x0000FFFF\r
-#define RMT_CARRIER_LOW_CH4_M ((RMT_CARRIER_LOW_CH4_V)<<(RMT_CARRIER_LOW_CH4_S))\r
-#define RMT_CARRIER_LOW_CH4_V 0xFFFF\r
-#define RMT_CARRIER_LOW_CH4_S 0\r
-\r
-#define RMT_CH5CARRIER_DUTY_REG (DR_REG_RMT_BASE + 0x00c4)\r
-/* RMT_CARRIER_HIGH_CH5 : R/W ;bitpos:[31:16] ;default: 16'h40 ; */\r
-/*description: This register is used to configure carrier wave's high level value for channel5.*/\r
-#define RMT_CARRIER_HIGH_CH5 0x0000FFFF\r
-#define RMT_CARRIER_HIGH_CH5_M ((RMT_CARRIER_HIGH_CH5_V)<<(RMT_CARRIER_HIGH_CH5_S))\r
-#define RMT_CARRIER_HIGH_CH5_V 0xFFFF\r
-#define RMT_CARRIER_HIGH_CH5_S 16\r
-/* RMT_CARRIER_LOW_CH5 : R/W ;bitpos:[15:0] ;default: 16'h40 ; */\r
-/*description: This register is used to configure carrier wave's low level value for channel5.*/\r
-#define RMT_CARRIER_LOW_CH5 0x0000FFFF\r
-#define RMT_CARRIER_LOW_CH5_M ((RMT_CARRIER_LOW_CH5_V)<<(RMT_CARRIER_LOW_CH5_S))\r
-#define RMT_CARRIER_LOW_CH5_V 0xFFFF\r
-#define RMT_CARRIER_LOW_CH5_S 0\r
-\r
-#define RMT_CH6CARRIER_DUTY_REG (DR_REG_RMT_BASE + 0x00c8)\r
-/* RMT_CARRIER_HIGH_CH6 : R/W ;bitpos:[31:16] ;default: 16'h40 ; */\r
-/*description: This register is used to configure carrier wave's high level value for channel6.*/\r
-#define RMT_CARRIER_HIGH_CH6 0x0000FFFF\r
-#define RMT_CARRIER_HIGH_CH6_M ((RMT_CARRIER_HIGH_CH6_V)<<(RMT_CARRIER_HIGH_CH6_S))\r
-#define RMT_CARRIER_HIGH_CH6_V 0xFFFF\r
-#define RMT_CARRIER_HIGH_CH6_S 16\r
-/* RMT_CARRIER_LOW_CH6 : R/W ;bitpos:[15:0] ;default: 16'h40 ; */\r
-/*description: This register is used to configure carrier wave's low level value for channel6.*/\r
-#define RMT_CARRIER_LOW_CH6 0x0000FFFF\r
-#define RMT_CARRIER_LOW_CH6_M ((RMT_CARRIER_LOW_CH6_V)<<(RMT_CARRIER_LOW_CH6_S))\r
-#define RMT_CARRIER_LOW_CH6_V 0xFFFF\r
-#define RMT_CARRIER_LOW_CH6_S 0\r
-\r
-#define RMT_CH7CARRIER_DUTY_REG (DR_REG_RMT_BASE + 0x00cc)\r
-/* RMT_CARRIER_HIGH_CH7 : R/W ;bitpos:[31:16] ;default: 16'h40 ; */\r
-/*description: This register is used to configure carrier wave's high level value for channel7.*/\r
-#define RMT_CARRIER_HIGH_CH7 0x0000FFFF\r
-#define RMT_CARRIER_HIGH_CH7_M ((RMT_CARRIER_HIGH_CH7_V)<<(RMT_CARRIER_HIGH_CH7_S))\r
-#define RMT_CARRIER_HIGH_CH7_V 0xFFFF\r
-#define RMT_CARRIER_HIGH_CH7_S 16\r
-/* RMT_CARRIER_LOW_CH7 : R/W ;bitpos:[15:0] ;default: 16'h40 ; */\r
-/*description: This register is used to configure carrier wave's low level value for channel7.*/\r
-#define RMT_CARRIER_LOW_CH7 0x0000FFFF\r
-#define RMT_CARRIER_LOW_CH7_M ((RMT_CARRIER_LOW_CH7_V)<<(RMT_CARRIER_LOW_CH7_S))\r
-#define RMT_CARRIER_LOW_CH7_V 0xFFFF\r
-#define RMT_CARRIER_LOW_CH7_S 0\r
-\r
-#define RMT_CH0_TX_LIM_REG (DR_REG_RMT_BASE + 0x00d0)\r
-/* RMT_TX_LIM_CH0 : R/W ;bitpos:[8:0] ;default: 9'h80 ; */\r
-/*description: When channel0 sends more than reg_rmt_tx_lim_ch0 datas then channel0\r
- produce the relative interrupt.*/\r
-#define RMT_TX_LIM_CH0 0x000001FF\r
-#define RMT_TX_LIM_CH0_M ((RMT_TX_LIM_CH0_V)<<(RMT_TX_LIM_CH0_S))\r
-#define RMT_TX_LIM_CH0_V 0x1FF\r
-#define RMT_TX_LIM_CH0_S 0\r
-\r
-#define RMT_CH1_TX_LIM_REG (DR_REG_RMT_BASE + 0x00d4)\r
-/* RMT_TX_LIM_CH1 : R/W ;bitpos:[8:0] ;default: 9'h80 ; */\r
-/*description: When channel1 sends more than reg_rmt_tx_lim_ch1 datas then channel1\r
- produce the relative interrupt.*/\r
-#define RMT_TX_LIM_CH1 0x000001FF\r
-#define RMT_TX_LIM_CH1_M ((RMT_TX_LIM_CH1_V)<<(RMT_TX_LIM_CH1_S))\r
-#define RMT_TX_LIM_CH1_V 0x1FF\r
-#define RMT_TX_LIM_CH1_S 0\r
-\r
-#define RMT_CH2_TX_LIM_REG (DR_REG_RMT_BASE + 0x00d8)\r
-/* RMT_TX_LIM_CH2 : R/W ;bitpos:[8:0] ;default: 9'h80 ; */\r
-/*description: When channel2 sends more than reg_rmt_tx_lim_ch2 datas then channel2\r
- produce the relative interrupt.*/\r
-#define RMT_TX_LIM_CH2 0x000001FF\r
-#define RMT_TX_LIM_CH2_M ((RMT_TX_LIM_CH2_V)<<(RMT_TX_LIM_CH2_S))\r
-#define RMT_TX_LIM_CH2_V 0x1FF\r
-#define RMT_TX_LIM_CH2_S 0\r
-\r
-#define RMT_CH3_TX_LIM_REG (DR_REG_RMT_BASE + 0x00dc)\r
-/* RMT_TX_LIM_CH3 : R/W ;bitpos:[8:0] ;default: 9'h80 ; */\r
-/*description: When channel3 sends more than reg_rmt_tx_lim_ch3 datas then channel3\r
- produce the relative interrupt.*/\r
-#define RMT_TX_LIM_CH3 0x000001FF\r
-#define RMT_TX_LIM_CH3_M ((RMT_TX_LIM_CH3_V)<<(RMT_TX_LIM_CH3_S))\r
-#define RMT_TX_LIM_CH3_V 0x1FF\r
-#define RMT_TX_LIM_CH3_S 0\r
-\r
-#define RMT_CH4_TX_LIM_REG (DR_REG_RMT_BASE + 0x00e0)\r
-/* RMT_TX_LIM_CH4 : R/W ;bitpos:[8:0] ;default: 9'h80 ; */\r
-/*description: When channel4 sends more than reg_rmt_tx_lim_ch4 datas then channel4\r
- produce the relative interrupt.*/\r
-#define RMT_TX_LIM_CH4 0x000001FF\r
-#define RMT_TX_LIM_CH4_M ((RMT_TX_LIM_CH4_V)<<(RMT_TX_LIM_CH4_S))\r
-#define RMT_TX_LIM_CH4_V 0x1FF\r
-#define RMT_TX_LIM_CH4_S 0\r
-\r
-#define RMT_CH5_TX_LIM_REG (DR_REG_RMT_BASE + 0x00e4)\r
-/* RMT_TX_LIM_CH5 : R/W ;bitpos:[8:0] ;default: 9'h80 ; */\r
-/*description: When channel5 sends more than reg_rmt_tx_lim_ch5 datas then channel5\r
- produce the relative interrupt.*/\r
-#define RMT_TX_LIM_CH5 0x000001FF\r
-#define RMT_TX_LIM_CH5_M ((RMT_TX_LIM_CH5_V)<<(RMT_TX_LIM_CH5_S))\r
-#define RMT_TX_LIM_CH5_V 0x1FF\r
-#define RMT_TX_LIM_CH5_S 0\r
-\r
-#define RMT_CH6_TX_LIM_REG (DR_REG_RMT_BASE + 0x00e8)\r
-/* RMT_TX_LIM_CH6 : R/W ;bitpos:[8:0] ;default: 9'h80 ; */\r
-/*description: When channel6 sends more than reg_rmt_tx_lim_ch6 datas then channel6\r
- produce the relative interrupt.*/\r
-#define RMT_TX_LIM_CH6 0x000001FF\r
-#define RMT_TX_LIM_CH6_M ((RMT_TX_LIM_CH6_V)<<(RMT_TX_LIM_CH6_S))\r
-#define RMT_TX_LIM_CH6_V 0x1FF\r
-#define RMT_TX_LIM_CH6_S 0\r
-\r
-#define RMT_CH7_TX_LIM_REG (DR_REG_RMT_BASE + 0x00ec)\r
-/* RMT_TX_LIM_CH7 : R/W ;bitpos:[8:0] ;default: 9'h80 ; */\r
-/*description: When channel7 sends more than reg_rmt_tx_lim_ch7 datas then channel7\r
- produce the relative interrupt.*/\r
-#define RMT_TX_LIM_CH7 0x000001FF\r
-#define RMT_TX_LIM_CH7_M ((RMT_TX_LIM_CH7_V)<<(RMT_TX_LIM_CH7_S))\r
-#define RMT_TX_LIM_CH7_V 0x1FF\r
-#define RMT_TX_LIM_CH7_S 0\r
-\r
-#define RMT_APB_CONF_REG (DR_REG_RMT_BASE + 0x00f0)\r
-/* RMT_MEM_TX_WRAP_EN : R/W ;bitpos:[1] ;default: 1'b0 ; */\r
-/*description: when datas need to be send is more than channel's mem can store\r
- then set this bit to enable reusage of mem this bit is used together with reg_rmt_tx_lim_chn.*/\r
-#define RMT_MEM_TX_WRAP_EN (BIT(1))\r
-#define RMT_MEM_TX_WRAP_EN_M (BIT(1))\r
-#define RMT_MEM_TX_WRAP_EN_V 0x1\r
-#define RMT_MEM_TX_WRAP_EN_S 1\r
-/* RMT_APB_FIFO_MASK : R/W ;bitpos:[0] ;default: 1'h0 ; */\r
-/*description: Set this bit to disable apb fifo access*/\r
-#define RMT_APB_FIFO_MASK (BIT(0))\r
-#define RMT_APB_FIFO_MASK_M (BIT(0))\r
-#define RMT_APB_FIFO_MASK_V 0x1\r
-#define RMT_APB_FIFO_MASK_S 0\r
-\r
-#define RMT_DATE_REG (DR_REG_RMT_BASE + 0x00fc)\r
-/* RMT_DATE : R/W ;bitpos:[31:0] ;default: 32'h16022600 ; */\r
-/*description: This is the version register.*/\r
-#define RMT_DATE 0xFFFFFFFF\r
-#define RMT_DATE_M ((RMT_DATE_V)<<(RMT_DATE_S))\r
-#define RMT_DATE_V 0xFFFFFFFF\r
-#define RMT_DATE_S 0\r
-\r
-/* RMT memory block address */\r
-#define RMT_CHANNEL_MEM(i) (DR_REG_RMT_BASE + 0x800 + 64 * 4 * (i))\r
-\r
-\r
-#endif /*_SOC_RMT_REG_H_ */\r
-\r
-\r
+// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+#ifndef _SOC_RMT_REG_H_
+#define _SOC_RMT_REG_H_
+
+#include "soc.h"
+#define RMT_CH0DATA_REG (DR_REG_RMT_BASE + 0x0000)
+
+#define RMT_CH1DATA_REG (DR_REG_RMT_BASE + 0x0004)
+
+#define RMT_CH2DATA_REG (DR_REG_RMT_BASE + 0x0008)
+
+#define RMT_CH3DATA_REG (DR_REG_RMT_BASE + 0x000c)
+
+#define RMT_CH4DATA_REG (DR_REG_RMT_BASE + 0x0010)
+
+#define RMT_CH5DATA_REG (DR_REG_RMT_BASE + 0x0014)
+
+#define RMT_CH6DATA_REG (DR_REG_RMT_BASE + 0x0018)
+
+#define RMT_CH7DATA_REG (DR_REG_RMT_BASE + 0x001c)
+
+#define RMT_CH0CONF0_REG (DR_REG_RMT_BASE + 0x0020)
+/* RMT_CLK_EN : R/W ;bitpos:[31] ;default: 1'h0 ; */
+/*description: This bit is used to control clock.when software config RMT
+ internal registers it controls the register clock.*/
+#define RMT_CLK_EN (BIT(31))
+#define RMT_CLK_EN_M (BIT(31))
+#define RMT_CLK_EN_V 0x1
+#define RMT_CLK_EN_S 31
+/* RMT_MEM_PD : R/W ;bitpos:[30] ;default: 1'b0 ; */
+/*description: This bit is used to reduce power consumed by mem. 1:mem is in low power state.*/
+#define RMT_MEM_PD (BIT(30))
+#define RMT_MEM_PD_M (BIT(30))
+#define RMT_MEM_PD_V 0x1
+#define RMT_MEM_PD_S 30
+/* RMT_CARRIER_OUT_LV_CH0 : R/W ;bitpos:[29] ;default: 1'b1 ; */
+/*description: This bit is used to configure the way carrier wave is modulated
+ for channel0.1'b1:transmit on low output level 1'b0:transmit on high output level.*/
+#define RMT_CARRIER_OUT_LV_CH0 (BIT(29))
+#define RMT_CARRIER_OUT_LV_CH0_M (BIT(29))
+#define RMT_CARRIER_OUT_LV_CH0_V 0x1
+#define RMT_CARRIER_OUT_LV_CH0_S 29
+/* RMT_CARRIER_EN_CH0 : R/W ;bitpos:[28] ;default: 1'b1 ; */
+/*description: This is the carrier modulation enable control bit for channel0.*/
+#define RMT_CARRIER_EN_CH0 (BIT(28))
+#define RMT_CARRIER_EN_CH0_M (BIT(28))
+#define RMT_CARRIER_EN_CH0_V 0x1
+#define RMT_CARRIER_EN_CH0_S 28
+/* RMT_MEM_SIZE_CH0 : R/W ;bitpos:[27:24] ;default: 4'h1 ; */
+/*description: This register is used to configure the the amount of memory blocks
+ allocated to channel0.*/
+#define RMT_MEM_SIZE_CH0 0x0000000F
+#define RMT_MEM_SIZE_CH0_M ((RMT_MEM_SIZE_CH0_V)<<(RMT_MEM_SIZE_CH0_S))
+#define RMT_MEM_SIZE_CH0_V 0xF
+#define RMT_MEM_SIZE_CH0_S 24
+/* RMT_IDLE_THRES_CH0 : R/W ;bitpos:[23:8] ;default: 16'h1000 ; */
+/*description: In receive mode when no edge is detected on the input signal
+ for longer than reg_idle_thres_ch0 then the receive process is done.*/
+#define RMT_IDLE_THRES_CH0 0x0000FFFF
+#define RMT_IDLE_THRES_CH0_M ((RMT_IDLE_THRES_CH0_V)<<(RMT_IDLE_THRES_CH0_S))
+#define RMT_IDLE_THRES_CH0_V 0xFFFF
+#define RMT_IDLE_THRES_CH0_S 8
+/* RMT_DIV_CNT_CH0 : R/W ;bitpos:[7:0] ;default: 8'h2 ; */
+/*description: This register is used to configure the frequency divider's factor in channel0.*/
+#define RMT_DIV_CNT_CH0 0x000000FF
+#define RMT_DIV_CNT_CH0_M ((RMT_DIV_CNT_CH0_V)<<(RMT_DIV_CNT_CH0_S))
+#define RMT_DIV_CNT_CH0_V 0xFF
+#define RMT_DIV_CNT_CH0_S 0
+
+#define RMT_CH0CONF1_REG (DR_REG_RMT_BASE + 0x0024)
+/* RMT_IDLE_OUT_EN_CH0 : R/W ;bitpos:[19] ;default: 1'b0 ; */
+/*description: This is the output enable control bit for channel0 in IDLE state.*/
+#define RMT_IDLE_OUT_EN_CH0 (BIT(19))
+#define RMT_IDLE_OUT_EN_CH0_M (BIT(19))
+#define RMT_IDLE_OUT_EN_CH0_V 0x1
+#define RMT_IDLE_OUT_EN_CH0_S 19
+/* RMT_IDLE_OUT_LV_CH0 : R/W ;bitpos:[18] ;default: 1'b0 ; */
+/*description: This bit configures the output signal's level for channel0 in IDLE state.*/
+#define RMT_IDLE_OUT_LV_CH0 (BIT(18))
+#define RMT_IDLE_OUT_LV_CH0_M (BIT(18))
+#define RMT_IDLE_OUT_LV_CH0_V 0x1
+#define RMT_IDLE_OUT_LV_CH0_S 18
+/* RMT_REF_ALWAYS_ON_CH0 : R/W ;bitpos:[17] ;default: 1'b0 ; */
+/*description: This bit is used to select base clock. 1'b1:clk_apb 1'b0:clk_ref*/
+#define RMT_REF_ALWAYS_ON_CH0 (BIT(17))
+#define RMT_REF_ALWAYS_ON_CH0_M (BIT(17))
+#define RMT_REF_ALWAYS_ON_CH0_V 0x1
+#define RMT_REF_ALWAYS_ON_CH0_S 17
+/* RMT_REF_CNT_RST_CH0 : R/W ;bitpos:[16] ;default: 1'b0 ; */
+/*description: This bit is used to reset divider in channel0.*/
+#define RMT_REF_CNT_RST_CH0 (BIT(16))
+#define RMT_REF_CNT_RST_CH0_M (BIT(16))
+#define RMT_REF_CNT_RST_CH0_V 0x1
+#define RMT_REF_CNT_RST_CH0_S 16
+/* RMT_RX_FILTER_THRES_CH0 : R/W ;bitpos:[15:8] ;default: 8'hf ; */
+/*description: in receive mode channel0 ignore input pulse when the pulse width
+ is smaller then this value.*/
+#define RMT_RX_FILTER_THRES_CH0 0x000000FF
+#define RMT_RX_FILTER_THRES_CH0_M ((RMT_RX_FILTER_THRES_CH0_V)<<(RMT_RX_FILTER_THRES_CH0_S))
+#define RMT_RX_FILTER_THRES_CH0_V 0xFF
+#define RMT_RX_FILTER_THRES_CH0_S 8
+/* RMT_RX_FILTER_EN_CH0 : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: This is the receive filter enable bit for channel0.*/
+#define RMT_RX_FILTER_EN_CH0 (BIT(7))
+#define RMT_RX_FILTER_EN_CH0_M (BIT(7))
+#define RMT_RX_FILTER_EN_CH0_V 0x1
+#define RMT_RX_FILTER_EN_CH0_S 7
+/* RMT_TX_CONTI_MODE_CH0 : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: Set this bit to continue sending from the first data to the
+ last data in channel0 again and again.*/
+#define RMT_TX_CONTI_MODE_CH0 (BIT(6))
+#define RMT_TX_CONTI_MODE_CH0_M (BIT(6))
+#define RMT_TX_CONTI_MODE_CH0_V 0x1
+#define RMT_TX_CONTI_MODE_CH0_S 6
+/* RMT_MEM_OWNER_CH0 : R/W ;bitpos:[5] ;default: 1'b1 ; */
+/*description: This is the mark of channel0's ram usage right.1'b1：receiver
+ uses the ram 0：transmitter uses the ram*/
+#define RMT_MEM_OWNER_CH0 (BIT(5))
+#define RMT_MEM_OWNER_CH0_M (BIT(5))
+#define RMT_MEM_OWNER_CH0_V 0x1
+#define RMT_MEM_OWNER_CH0_S 5
+/* RMT_APB_MEM_RST_CH0 : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: Set this bit to reset W/R ram address for channel0 by apb fifo access*/
+#define RMT_APB_MEM_RST_CH0 (BIT(4))
+#define RMT_APB_MEM_RST_CH0_M (BIT(4))
+#define RMT_APB_MEM_RST_CH0_V 0x1
+#define RMT_APB_MEM_RST_CH0_S 4
+/* RMT_MEM_RD_RST_CH0 : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: Set this bit to reset read ram address for channel0 by transmitter access.*/
+#define RMT_MEM_RD_RST_CH0 (BIT(3))
+#define RMT_MEM_RD_RST_CH0_M (BIT(3))
+#define RMT_MEM_RD_RST_CH0_V 0x1
+#define RMT_MEM_RD_RST_CH0_S 3
+/* RMT_MEM_WR_RST_CH0 : R/W ;bitpos:[2] ;default: 1'h0 ; */
+/*description: Set this bit to reset write ram address for channel0 by receiver access.*/
+#define RMT_MEM_WR_RST_CH0 (BIT(2))
+#define RMT_MEM_WR_RST_CH0_M (BIT(2))
+#define RMT_MEM_WR_RST_CH0_V 0x1
+#define RMT_MEM_WR_RST_CH0_S 2
+/* RMT_RX_EN_CH0 : R/W ;bitpos:[1] ;default: 1'h0 ; */
+/*description: Set this bit to enbale receving data for channel0.*/
+#define RMT_RX_EN_CH0 (BIT(1))
+#define RMT_RX_EN_CH0_M (BIT(1))
+#define RMT_RX_EN_CH0_V 0x1
+#define RMT_RX_EN_CH0_S 1
+/* RMT_TX_START_CH0 : R/W ;bitpos:[0] ;default: 1'h0 ; */
+/*description: Set this bit to start sending data for channel0.*/
+#define RMT_TX_START_CH0 (BIT(0))
+#define RMT_TX_START_CH0_M (BIT(0))
+#define RMT_TX_START_CH0_V 0x1
+#define RMT_TX_START_CH0_S 0
+
+#define RMT_CH1CONF0_REG (DR_REG_RMT_BASE + 0x0028)
+/* RMT_CARRIER_OUT_LV_CH1 : R/W ;bitpos:[29] ;default: 1'b1 ; */
+/*description: This bit is used to configure the way carrier wave is modulated
+ for channel1.1'b1:transmit on low output level 1'b0:transmit on high output level.*/
+#define RMT_CARRIER_OUT_LV_CH1 (BIT(29))
+#define RMT_CARRIER_OUT_LV_CH1_M (BIT(29))
+#define RMT_CARRIER_OUT_LV_CH1_V 0x1
+#define RMT_CARRIER_OUT_LV_CH1_S 29
+/* RMT_CARRIER_EN_CH1 : R/W ;bitpos:[28] ;default: 1'b1 ; */
+/*description: This is the carrier modulation enable control bit for channel1.*/
+#define RMT_CARRIER_EN_CH1 (BIT(28))
+#define RMT_CARRIER_EN_CH1_M (BIT(28))
+#define RMT_CARRIER_EN_CH1_V 0x1
+#define RMT_CARRIER_EN_CH1_S 28
+/* RMT_MEM_SIZE_CH1 : R/W ;bitpos:[27:24] ;default: 4'h1 ; */
+/*description: This register is used to configure the the amount of memory blocks
+ allocated to channel1.*/
+#define RMT_MEM_SIZE_CH1 0x0000000F
+#define RMT_MEM_SIZE_CH1_M ((RMT_MEM_SIZE_CH1_V)<<(RMT_MEM_SIZE_CH1_S))
+#define RMT_MEM_SIZE_CH1_V 0xF
+#define RMT_MEM_SIZE_CH1_S 24
+/* RMT_IDLE_THRES_CH1 : R/W ;bitpos:[23:8] ;default: 16'h1000 ; */
+/*description: This register is used to configure the the amount of memory blocks
+ allocated to channel1.*/
+#define RMT_IDLE_THRES_CH1 0x0000FFFF
+#define RMT_IDLE_THRES_CH1_M ((RMT_IDLE_THRES_CH1_V)<<(RMT_IDLE_THRES_CH1_S))
+#define RMT_IDLE_THRES_CH1_V 0xFFFF
+#define RMT_IDLE_THRES_CH1_S 8
+/* RMT_DIV_CNT_CH1 : R/W ;bitpos:[7:0] ;default: 8'h2 ; */
+/*description: This register is used to configure the frequency divider's factor in channel1.*/
+#define RMT_DIV_CNT_CH1 0x000000FF
+#define RMT_DIV_CNT_CH1_M ((RMT_DIV_CNT_CH1_V)<<(RMT_DIV_CNT_CH1_S))
+#define RMT_DIV_CNT_CH1_V 0xFF
+#define RMT_DIV_CNT_CH1_S 0
+
+#define RMT_CH1CONF1_REG (DR_REG_RMT_BASE + 0x002c)
+/* RMT_IDLE_OUT_EN_CH1 : R/W ;bitpos:[19] ;default: 1'b0 ; */
+/*description: This is the output enable control bit for channel1 in IDLE state.*/
+#define RMT_IDLE_OUT_EN_CH1 (BIT(19))
+#define RMT_IDLE_OUT_EN_CH1_M (BIT(19))
+#define RMT_IDLE_OUT_EN_CH1_V 0x1
+#define RMT_IDLE_OUT_EN_CH1_S 19
+/* RMT_IDLE_OUT_LV_CH1 : R/W ;bitpos:[18] ;default: 1'b0 ; */
+/*description: This bit configures the output signal's level for channel1 in IDLE state.*/
+#define RMT_IDLE_OUT_LV_CH1 (BIT(18))
+#define RMT_IDLE_OUT_LV_CH1_M (BIT(18))
+#define RMT_IDLE_OUT_LV_CH1_V 0x1
+#define RMT_IDLE_OUT_LV_CH1_S 18
+/* RMT_REF_ALWAYS_ON_CH1 : R/W ;bitpos:[17] ;default: 1'b0 ; */
+/*description: This bit is used to select base clock. 1'b1:clk_apb 1'b0:clk_ref*/
+#define RMT_REF_ALWAYS_ON_CH1 (BIT(17))
+#define RMT_REF_ALWAYS_ON_CH1_M (BIT(17))
+#define RMT_REF_ALWAYS_ON_CH1_V 0x1
+#define RMT_REF_ALWAYS_ON_CH1_S 17
+/* RMT_REF_CNT_RST_CH1 : R/W ;bitpos:[16] ;default: 1'b0 ; */
+/*description: This bit is used to reset divider in channel1.*/
+#define RMT_REF_CNT_RST_CH1 (BIT(16))
+#define RMT_REF_CNT_RST_CH1_M (BIT(16))
+#define RMT_REF_CNT_RST_CH1_V 0x1
+#define RMT_REF_CNT_RST_CH1_S 16
+/* RMT_RX_FILTER_THRES_CH1 : R/W ;bitpos:[15:8] ;default: 8'hf ; */
+/*description: in receive mode channel1 ignore input pulse when the pulse width
+ is smaller then this value.*/
+#define RMT_RX_FILTER_THRES_CH1 0x000000FF
+#define RMT_RX_FILTER_THRES_CH1_M ((RMT_RX_FILTER_THRES_CH1_V)<<(RMT_RX_FILTER_THRES_CH1_S))
+#define RMT_RX_FILTER_THRES_CH1_V 0xFF
+#define RMT_RX_FILTER_THRES_CH1_S 8
+/* RMT_RX_FILTER_EN_CH1 : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: This is the receive filter enable bit for channel1.*/
+#define RMT_RX_FILTER_EN_CH1 (BIT(7))
+#define RMT_RX_FILTER_EN_CH1_M (BIT(7))
+#define RMT_RX_FILTER_EN_CH1_V 0x1
+#define RMT_RX_FILTER_EN_CH1_S 7
+/* RMT_TX_CONTI_MODE_CH1 : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: Set this bit to continue sending from the first data to the
+ last data in channel1 again and again.*/
+#define RMT_TX_CONTI_MODE_CH1 (BIT(6))
+#define RMT_TX_CONTI_MODE_CH1_M (BIT(6))
+#define RMT_TX_CONTI_MODE_CH1_V 0x1
+#define RMT_TX_CONTI_MODE_CH1_S 6
+/* RMT_MEM_OWNER_CH1 : R/W ;bitpos:[5] ;default: 1'b1 ; */
+/*description: This is the mark of channel1's ram usage right.1'b1：receiver
+ uses the ram 0：transmitter uses the ram*/
+#define RMT_MEM_OWNER_CH1 (BIT(5))
+#define RMT_MEM_OWNER_CH1_M (BIT(5))
+#define RMT_MEM_OWNER_CH1_V 0x1
+#define RMT_MEM_OWNER_CH1_S 5
+/* RMT_APB_MEM_RST_CH1 : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: Set this bit to reset W/R ram address for channel1 by apb fifo access*/
+#define RMT_APB_MEM_RST_CH1 (BIT(4))
+#define RMT_APB_MEM_RST_CH1_M (BIT(4))
+#define RMT_APB_MEM_RST_CH1_V 0x1
+#define RMT_APB_MEM_RST_CH1_S 4
+/* RMT_MEM_RD_RST_CH1 : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: Set this bit to reset read ram address for channel1 by transmitter access.*/
+#define RMT_MEM_RD_RST_CH1 (BIT(3))
+#define RMT_MEM_RD_RST_CH1_M (BIT(3))
+#define RMT_MEM_RD_RST_CH1_V 0x1
+#define RMT_MEM_RD_RST_CH1_S 3
+/* RMT_MEM_WR_RST_CH1 : R/W ;bitpos:[2] ;default: 1'h0 ; */
+/*description: Set this bit to reset write ram address for channel1 by receiver access.*/
+#define RMT_MEM_WR_RST_CH1 (BIT(2))
+#define RMT_MEM_WR_RST_CH1_M (BIT(2))
+#define RMT_MEM_WR_RST_CH1_V 0x1
+#define RMT_MEM_WR_RST_CH1_S 2
+/* RMT_RX_EN_CH1 : R/W ;bitpos:[1] ;default: 1'h0 ; */
+/*description: Set this bit to enbale receving data for channel1.*/
+#define RMT_RX_EN_CH1 (BIT(1))
+#define RMT_RX_EN_CH1_M (BIT(1))
+#define RMT_RX_EN_CH1_V 0x1
+#define RMT_RX_EN_CH1_S 1
+/* RMT_TX_START_CH1 : R/W ;bitpos:[0] ;default: 1'h0 ; */
+/*description: Set this bit to start sending data for channel1.*/
+#define RMT_TX_START_CH1 (BIT(0))
+#define RMT_TX_START_CH1_M (BIT(0))
+#define RMT_TX_START_CH1_V 0x1
+#define RMT_TX_START_CH1_S 0
+
+#define RMT_CH2CONF0_REG (DR_REG_RMT_BASE + 0x0030)
+/* RMT_CARRIER_OUT_LV_CH2 : R/W ;bitpos:[29] ;default: 1'b1 ; */
+/*description: This bit is used to configure carrier wave's position for channel2.1'b1:add
+ on low level 1'b0:add on high level.*/
+#define RMT_CARRIER_OUT_LV_CH2 (BIT(29))
+#define RMT_CARRIER_OUT_LV_CH2_M (BIT(29))
+#define RMT_CARRIER_OUT_LV_CH2_V 0x1
+#define RMT_CARRIER_OUT_LV_CH2_S 29
+/* RMT_CARRIER_EN_CH2 : R/W ;bitpos:[28] ;default: 1'b1 ; */
+/*description: This is the carrier modulation enable control bit for channel2.*/
+#define RMT_CARRIER_EN_CH2 (BIT(28))
+#define RMT_CARRIER_EN_CH2_M (BIT(28))
+#define RMT_CARRIER_EN_CH2_V 0x1
+#define RMT_CARRIER_EN_CH2_S 28
+/* RMT_MEM_SIZE_CH2 : R/W ;bitpos:[27:24] ;default: 4'h1 ; */
+/*description: This register is used to configure the the amount of memory blocks
+ allocated to channel2.*/
+#define RMT_MEM_SIZE_CH2 0x0000000F
+#define RMT_MEM_SIZE_CH2_M ((RMT_MEM_SIZE_CH2_V)<<(RMT_MEM_SIZE_CH2_S))
+#define RMT_MEM_SIZE_CH2_V 0xF
+#define RMT_MEM_SIZE_CH2_S 24
+/* RMT_IDLE_THRES_CH2 : R/W ;bitpos:[23:8] ;default: 16'h1000 ; */
+/*description: In receive mode when the counter's value is bigger than reg_idle_thres_ch2
+ then the receive process is done.*/
+#define RMT_IDLE_THRES_CH2 0x0000FFFF
+#define RMT_IDLE_THRES_CH2_M ((RMT_IDLE_THRES_CH2_V)<<(RMT_IDLE_THRES_CH2_S))
+#define RMT_IDLE_THRES_CH2_V 0xFFFF
+#define RMT_IDLE_THRES_CH2_S 8
+/* RMT_DIV_CNT_CH2 : R/W ;bitpos:[7:0] ;default: 8'h2 ; */
+/*description: This register is used to configure the frequency divider's factor in channel2.*/
+#define RMT_DIV_CNT_CH2 0x000000FF
+#define RMT_DIV_CNT_CH2_M ((RMT_DIV_CNT_CH2_V)<<(RMT_DIV_CNT_CH2_S))
+#define RMT_DIV_CNT_CH2_V 0xFF
+#define RMT_DIV_CNT_CH2_S 0
+
+#define RMT_CH2CONF1_REG (DR_REG_RMT_BASE + 0x0034)
+/* RMT_IDLE_OUT_EN_CH2 : R/W ;bitpos:[19] ;default: 1'b0 ; */
+/*description: This is the output enable control bit for channel2 in IDLE state.*/
+#define RMT_IDLE_OUT_EN_CH2 (BIT(19))
+#define RMT_IDLE_OUT_EN_CH2_M (BIT(19))
+#define RMT_IDLE_OUT_EN_CH2_V 0x1
+#define RMT_IDLE_OUT_EN_CH2_S 19
+/* RMT_IDLE_OUT_LV_CH2 : R/W ;bitpos:[18] ;default: 1'b0 ; */
+/*description: This bit configures the output signal's level for channel2 in IDLE state.*/
+#define RMT_IDLE_OUT_LV_CH2 (BIT(18))
+#define RMT_IDLE_OUT_LV_CH2_M (BIT(18))
+#define RMT_IDLE_OUT_LV_CH2_V 0x1
+#define RMT_IDLE_OUT_LV_CH2_S 18
+/* RMT_REF_ALWAYS_ON_CH2 : R/W ;bitpos:[17] ;default: 1'b0 ; */
+/*description: This bit is used to select base clock. 1'b1:clk_apb 1'b0:clk_ref*/
+#define RMT_REF_ALWAYS_ON_CH2 (BIT(17))
+#define RMT_REF_ALWAYS_ON_CH2_M (BIT(17))
+#define RMT_REF_ALWAYS_ON_CH2_V 0x1
+#define RMT_REF_ALWAYS_ON_CH2_S 17
+/* RMT_REF_CNT_RST_CH2 : R/W ;bitpos:[16] ;default: 1'b0 ; */
+/*description: This bit is used to reset divider in channel2.*/
+#define RMT_REF_CNT_RST_CH2 (BIT(16))
+#define RMT_REF_CNT_RST_CH2_M (BIT(16))
+#define RMT_REF_CNT_RST_CH2_V 0x1
+#define RMT_REF_CNT_RST_CH2_S 16
+/* RMT_RX_FILTER_THRES_CH2 : R/W ;bitpos:[15:8] ;default: 8'hf ; */
+/*description: in receive mode channel2 ignore input pulse when the pulse width
+ is smaller then this value.*/
+#define RMT_RX_FILTER_THRES_CH2 0x000000FF
+#define RMT_RX_FILTER_THRES_CH2_M ((RMT_RX_FILTER_THRES_CH2_V)<<(RMT_RX_FILTER_THRES_CH2_S))
+#define RMT_RX_FILTER_THRES_CH2_V 0xFF
+#define RMT_RX_FILTER_THRES_CH2_S 8
+/* RMT_RX_FILTER_EN_CH2 : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: This is the receive filter enable bit for channel2.*/
+#define RMT_RX_FILTER_EN_CH2 (BIT(7))
+#define RMT_RX_FILTER_EN_CH2_M (BIT(7))
+#define RMT_RX_FILTER_EN_CH2_V 0x1
+#define RMT_RX_FILTER_EN_CH2_S 7
+/* RMT_TX_CONTI_MODE_CH2 : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: Set this bit to continue sending from the first data to the
+ last data in channel2.*/
+#define RMT_TX_CONTI_MODE_CH2 (BIT(6))
+#define RMT_TX_CONTI_MODE_CH2_M (BIT(6))
+#define RMT_TX_CONTI_MODE_CH2_V 0x1
+#define RMT_TX_CONTI_MODE_CH2_S 6
+/* RMT_MEM_OWNER_CH2 : R/W ;bitpos:[5] ;default: 1'b1 ; */
+/*description: This is the mark of channel2's ram usage right.1'b1：receiver
+ uses the ram 0：transmitter uses the ram*/
+#define RMT_MEM_OWNER_CH2 (BIT(5))
+#define RMT_MEM_OWNER_CH2_M (BIT(5))
+#define RMT_MEM_OWNER_CH2_V 0x1
+#define RMT_MEM_OWNER_CH2_S 5
+/* RMT_APB_MEM_RST_CH2 : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: Set this bit to reset W/R ram address for channel2 by apb fifo access*/
+#define RMT_APB_MEM_RST_CH2 (BIT(4))
+#define RMT_APB_MEM_RST_CH2_M (BIT(4))
+#define RMT_APB_MEM_RST_CH2_V 0x1
+#define RMT_APB_MEM_RST_CH2_S 4
+/* RMT_MEM_RD_RST_CH2 : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: Set this bit to reset read ram address for channel2 by transmitter access.*/
+#define RMT_MEM_RD_RST_CH2 (BIT(3))
+#define RMT_MEM_RD_RST_CH2_M (BIT(3))
+#define RMT_MEM_RD_RST_CH2_V 0x1
+#define RMT_MEM_RD_RST_CH2_S 3
+/* RMT_MEM_WR_RST_CH2 : R/W ;bitpos:[2] ;default: 1'h0 ; */
+/*description: Set this bit to reset write ram address for channel2 by receiver access.*/
+#define RMT_MEM_WR_RST_CH2 (BIT(2))
+#define RMT_MEM_WR_RST_CH2_M (BIT(2))
+#define RMT_MEM_WR_RST_CH2_V 0x1
+#define RMT_MEM_WR_RST_CH2_S 2
+/* RMT_RX_EN_CH2 : R/W ;bitpos:[1] ;default: 1'h0 ; */
+/*description: Set this bit to enbale receving data for channel2.*/
+#define RMT_RX_EN_CH2 (BIT(1))
+#define RMT_RX_EN_CH2_M (BIT(1))
+#define RMT_RX_EN_CH2_V 0x1
+#define RMT_RX_EN_CH2_S 1
+/* RMT_TX_START_CH2 : R/W ;bitpos:[0] ;default: 1'h0 ; */
+/*description: Set this bit to start sending data for channel2.*/
+#define RMT_TX_START_CH2 (BIT(0))
+#define RMT_TX_START_CH2_M (BIT(0))
+#define RMT_TX_START_CH2_V 0x1
+#define RMT_TX_START_CH2_S 0
+
+#define RMT_CH3CONF0_REG (DR_REG_RMT_BASE + 0x0038)
+/* RMT_CARRIER_OUT_LV_CH3 : R/W ;bitpos:[29] ;default: 1'b1 ; */
+/*description: This bit is used to configure carrier wave's position for channel3.1'b1:add
+ on low level 1'b0:add on high level.*/
+#define RMT_CARRIER_OUT_LV_CH3 (BIT(29))
+#define RMT_CARRIER_OUT_LV_CH3_M (BIT(29))
+#define RMT_CARRIER_OUT_LV_CH3_V 0x1
+#define RMT_CARRIER_OUT_LV_CH3_S 29
+/* RMT_CARRIER_EN_CH3 : R/W ;bitpos:[28] ;default: 1'b1 ; */
+/*description: This is the carrier modulation enable control bit for channel3.*/
+#define RMT_CARRIER_EN_CH3 (BIT(28))
+#define RMT_CARRIER_EN_CH3_M (BIT(28))
+#define RMT_CARRIER_EN_CH3_V 0x1
+#define RMT_CARRIER_EN_CH3_S 28
+/* RMT_MEM_SIZE_CH3 : R/W ;bitpos:[27:24] ;default: 4'h1 ; */
+/*description: This register is used to configure the the amount of memory blocks
+ allocated to channel3.*/
+#define RMT_MEM_SIZE_CH3 0x0000000F
+#define RMT_MEM_SIZE_CH3_M ((RMT_MEM_SIZE_CH3_V)<<(RMT_MEM_SIZE_CH3_S))
+#define RMT_MEM_SIZE_CH3_V 0xF
+#define RMT_MEM_SIZE_CH3_S 24
+/* RMT_IDLE_THRES_CH3 : R/W ;bitpos:[23:8] ;default: 16'h1000 ; */
+/*description: In receive mode when the counter's value is bigger than reg_idle_thres_ch3
+ then the receive process is done.*/
+#define RMT_IDLE_THRES_CH3 0x0000FFFF
+#define RMT_IDLE_THRES_CH3_M ((RMT_IDLE_THRES_CH3_V)<<(RMT_IDLE_THRES_CH3_S))
+#define RMT_IDLE_THRES_CH3_V 0xFFFF
+#define RMT_IDLE_THRES_CH3_S 8
+/* RMT_DIV_CNT_CH3 : R/W ;bitpos:[7:0] ;default: 8'h2 ; */
+/*description: This register is used to configure the frequency divider's factor in channel3.*/
+#define RMT_DIV_CNT_CH3 0x000000FF
+#define RMT_DIV_CNT_CH3_M ((RMT_DIV_CNT_CH3_V)<<(RMT_DIV_CNT_CH3_S))
+#define RMT_DIV_CNT_CH3_V 0xFF
+#define RMT_DIV_CNT_CH3_S 0
+
+#define RMT_CH3CONF1_REG (DR_REG_RMT_BASE + 0x003c)
+/* RMT_IDLE_OUT_EN_CH3 : R/W ;bitpos:[19] ;default: 1'b0 ; */
+/*description: This is the output enable control bit for channel3 in IDLE state.*/
+#define RMT_IDLE_OUT_EN_CH3 (BIT(19))
+#define RMT_IDLE_OUT_EN_CH3_M (BIT(19))
+#define RMT_IDLE_OUT_EN_CH3_V 0x1
+#define RMT_IDLE_OUT_EN_CH3_S 19
+/* RMT_IDLE_OUT_LV_CH3 : R/W ;bitpos:[18] ;default: 1'b0 ; */
+/*description: This bit configures the output signal's level for channel3 in IDLE state.*/
+#define RMT_IDLE_OUT_LV_CH3 (BIT(18))
+#define RMT_IDLE_OUT_LV_CH3_M (BIT(18))
+#define RMT_IDLE_OUT_LV_CH3_V 0x1
+#define RMT_IDLE_OUT_LV_CH3_S 18
+/* RMT_REF_ALWAYS_ON_CH3 : R/W ;bitpos:[17] ;default: 1'b0 ; */
+/*description: This bit is used to select base clock. 1'b1:clk_apb 1'b0:clk_ref*/
+#define RMT_REF_ALWAYS_ON_CH3 (BIT(17))
+#define RMT_REF_ALWAYS_ON_CH3_M (BIT(17))
+#define RMT_REF_ALWAYS_ON_CH3_V 0x1
+#define RMT_REF_ALWAYS_ON_CH3_S 17
+/* RMT_REF_CNT_RST_CH3 : R/W ;bitpos:[16] ;default: 1'b0 ; */
+/*description: This bit is used to reset divider in channel3.*/
+#define RMT_REF_CNT_RST_CH3 (BIT(16))
+#define RMT_REF_CNT_RST_CH3_M (BIT(16))
+#define RMT_REF_CNT_RST_CH3_V 0x1
+#define RMT_REF_CNT_RST_CH3_S 16
+/* RMT_RX_FILTER_THRES_CH3 : R/W ;bitpos:[15:8] ;default: 8'hf ; */
+/*description: in receive mode channel3 ignore input pulse when the pulse width
+ is smaller then this value.*/
+#define RMT_RX_FILTER_THRES_CH3 0x000000FF
+#define RMT_RX_FILTER_THRES_CH3_M ((RMT_RX_FILTER_THRES_CH3_V)<<(RMT_RX_FILTER_THRES_CH3_S))
+#define RMT_RX_FILTER_THRES_CH3_V 0xFF
+#define RMT_RX_FILTER_THRES_CH3_S 8
+/* RMT_RX_FILTER_EN_CH3 : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: This is the receive filter enable bit for channel3.*/
+#define RMT_RX_FILTER_EN_CH3 (BIT(7))
+#define RMT_RX_FILTER_EN_CH3_M (BIT(7))
+#define RMT_RX_FILTER_EN_CH3_V 0x1
+#define RMT_RX_FILTER_EN_CH3_S 7
+/* RMT_TX_CONTI_MODE_CH3 : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: Set this bit to continue sending from the first data to the
+ last data in channel3.*/
+#define RMT_TX_CONTI_MODE_CH3 (BIT(6))
+#define RMT_TX_CONTI_MODE_CH3_M (BIT(6))
+#define RMT_TX_CONTI_MODE_CH3_V 0x1
+#define RMT_TX_CONTI_MODE_CH3_S 6
+/* RMT_MEM_OWNER_CH3 : R/W ;bitpos:[5] ;default: 1'b1 ; */
+/*description: This is the mark of channel3's ram usage right.1'b1：receiver
+ uses the ram 0：transmitter uses the ram*/
+#define RMT_MEM_OWNER_CH3 (BIT(5))
+#define RMT_MEM_OWNER_CH3_M (BIT(5))
+#define RMT_MEM_OWNER_CH3_V 0x1
+#define RMT_MEM_OWNER_CH3_S 5
+/* RMT_APB_MEM_RST_CH3 : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: Set this bit to reset W/R ram address for channel3 by apb fifo access*/
+#define RMT_APB_MEM_RST_CH3 (BIT(4))
+#define RMT_APB_MEM_RST_CH3_M (BIT(4))
+#define RMT_APB_MEM_RST_CH3_V 0x1
+#define RMT_APB_MEM_RST_CH3_S 4
+/* RMT_MEM_RD_RST_CH3 : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: Set this bit to reset read ram address for channel3 by transmitter access.*/
+#define RMT_MEM_RD_RST_CH3 (BIT(3))
+#define RMT_MEM_RD_RST_CH3_M (BIT(3))
+#define RMT_MEM_RD_RST_CH3_V 0x1
+#define RMT_MEM_RD_RST_CH3_S 3
+/* RMT_MEM_WR_RST_CH3 : R/W ;bitpos:[2] ;default: 1'h0 ; */
+/*description: Set this bit to reset write ram address for channel3 by receiver access.*/
+#define RMT_MEM_WR_RST_CH3 (BIT(2))
+#define RMT_MEM_WR_RST_CH3_M (BIT(2))
+#define RMT_MEM_WR_RST_CH3_V 0x1
+#define RMT_MEM_WR_RST_CH3_S 2
+/* RMT_RX_EN_CH3 : R/W ;bitpos:[1] ;default: 1'h0 ; */
+/*description: Set this bit to enbale receving data for channel3.*/
+#define RMT_RX_EN_CH3 (BIT(1))
+#define RMT_RX_EN_CH3_M (BIT(1))
+#define RMT_RX_EN_CH3_V 0x1
+#define RMT_RX_EN_CH3_S 1
+/* RMT_TX_START_CH3 : R/W ;bitpos:[0] ;default: 1'h0 ; */
+/*description: Set this bit to start sending data for channel3.*/
+#define RMT_TX_START_CH3 (BIT(0))
+#define RMT_TX_START_CH3_M (BIT(0))
+#define RMT_TX_START_CH3_V 0x1
+#define RMT_TX_START_CH3_S 0
+
+#define RMT_CH4CONF0_REG (DR_REG_RMT_BASE + 0x0040)
+/* RMT_CARRIER_OUT_LV_CH4 : R/W ;bitpos:[29] ;default: 1'b1 ; */
+/*description: This bit is used to configure carrier wave's position for channel4.1'b1:add
+ on low level 1'b0:add on high level.*/
+#define RMT_CARRIER_OUT_LV_CH4 (BIT(29))
+#define RMT_CARRIER_OUT_LV_CH4_M (BIT(29))
+#define RMT_CARRIER_OUT_LV_CH4_V 0x1
+#define RMT_CARRIER_OUT_LV_CH4_S 29
+/* RMT_CARRIER_EN_CH4 : R/W ;bitpos:[28] ;default: 1'b1 ; */
+/*description: This is the carrier modulation enable control bit for channel4.*/
+#define RMT_CARRIER_EN_CH4 (BIT(28))
+#define RMT_CARRIER_EN_CH4_M (BIT(28))
+#define RMT_CARRIER_EN_CH4_V 0x1
+#define RMT_CARRIER_EN_CH4_S 28
+/* RMT_MEM_SIZE_CH4 : R/W ;bitpos:[27:24] ;default: 4'h1 ; */
+/*description: This register is used to configure the the amount of memory blocks
+ allocated to channel4.*/
+#define RMT_MEM_SIZE_CH4 0x0000000F
+#define RMT_MEM_SIZE_CH4_M ((RMT_MEM_SIZE_CH4_V)<<(RMT_MEM_SIZE_CH4_S))
+#define RMT_MEM_SIZE_CH4_V 0xF
+#define RMT_MEM_SIZE_CH4_S 24
+/* RMT_IDLE_THRES_CH4 : R/W ;bitpos:[23:8] ;default: 16'h1000 ; */
+/*description: In receive mode when the counter's value is bigger than reg_idle_thres_ch4
+ then the receive process is done.*/
+#define RMT_IDLE_THRES_CH4 0x0000FFFF
+#define RMT_IDLE_THRES_CH4_M ((RMT_IDLE_THRES_CH4_V)<<(RMT_IDLE_THRES_CH4_S))
+#define RMT_IDLE_THRES_CH4_V 0xFFFF
+#define RMT_IDLE_THRES_CH4_S 8
+/* RMT_DIV_CNT_CH4 : R/W ;bitpos:[7:0] ;default: 8'h2 ; */
+/*description: This register is used to configure the frequency divider's factor in channel4.*/
+#define RMT_DIV_CNT_CH4 0x000000FF
+#define RMT_DIV_CNT_CH4_M ((RMT_DIV_CNT_CH4_V)<<(RMT_DIV_CNT_CH4_S))
+#define RMT_DIV_CNT_CH4_V 0xFF
+#define RMT_DIV_CNT_CH4_S 0
+
+#define RMT_CH4CONF1_REG (DR_REG_RMT_BASE + 0x0044)
+/* RMT_IDLE_OUT_EN_CH4 : R/W ;bitpos:[19] ;default: 1'b0 ; */
+/*description: This is the output enable control bit for channel4 in IDLE state.*/
+#define RMT_IDLE_OUT_EN_CH4 (BIT(19))
+#define RMT_IDLE_OUT_EN_CH4_M (BIT(19))
+#define RMT_IDLE_OUT_EN_CH4_V 0x1
+#define RMT_IDLE_OUT_EN_CH4_S 19
+/* RMT_IDLE_OUT_LV_CH4 : R/W ;bitpos:[18] ;default: 1'b0 ; */
+/*description: This bit configures the output signal's level for channel4 in IDLE state.*/
+#define RMT_IDLE_OUT_LV_CH4 (BIT(18))
+#define RMT_IDLE_OUT_LV_CH4_M (BIT(18))
+#define RMT_IDLE_OUT_LV_CH4_V 0x1
+#define RMT_IDLE_OUT_LV_CH4_S 18
+/* RMT_REF_ALWAYS_ON_CH4 : R/W ;bitpos:[17] ;default: 1'b0 ; */
+/*description: This bit is used to select base clock. 1'b1:clk_apb 1'b0:clk_ref*/
+#define RMT_REF_ALWAYS_ON_CH4 (BIT(17))
+#define RMT_REF_ALWAYS_ON_CH4_M (BIT(17))
+#define RMT_REF_ALWAYS_ON_CH4_V 0x1
+#define RMT_REF_ALWAYS_ON_CH4_S 17
+/* RMT_REF_CNT_RST_CH4 : R/W ;bitpos:[16] ;default: 1'b0 ; */
+/*description: This bit is used to reset divider in channel4.*/
+#define RMT_REF_CNT_RST_CH4 (BIT(16))
+#define RMT_REF_CNT_RST_CH4_M (BIT(16))
+#define RMT_REF_CNT_RST_CH4_V 0x1
+#define RMT_REF_CNT_RST_CH4_S 16
+/* RMT_RX_FILTER_THRES_CH4 : R/W ;bitpos:[15:8] ;default: 8'hf ; */
+/*description: in receive mode channel4 ignore input pulse when the pulse width
+ is smaller then this value.*/
+#define RMT_RX_FILTER_THRES_CH4 0x000000FF
+#define RMT_RX_FILTER_THRES_CH4_M ((RMT_RX_FILTER_THRES_CH4_V)<<(RMT_RX_FILTER_THRES_CH4_S))
+#define RMT_RX_FILTER_THRES_CH4_V 0xFF
+#define RMT_RX_FILTER_THRES_CH4_S 8
+/* RMT_RX_FILTER_EN_CH4 : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: This is the receive filter enable bit for channel4.*/
+#define RMT_RX_FILTER_EN_CH4 (BIT(7))
+#define RMT_RX_FILTER_EN_CH4_M (BIT(7))
+#define RMT_RX_FILTER_EN_CH4_V 0x1
+#define RMT_RX_FILTER_EN_CH4_S 7
+/* RMT_TX_CONTI_MODE_CH4 : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: Set this bit to continue sending from the first data to the
+ last data in channel4.*/
+#define RMT_TX_CONTI_MODE_CH4 (BIT(6))
+#define RMT_TX_CONTI_MODE_CH4_M (BIT(6))
+#define RMT_TX_CONTI_MODE_CH4_V 0x1
+#define RMT_TX_CONTI_MODE_CH4_S 6
+/* RMT_MEM_OWNER_CH4 : R/W ;bitpos:[5] ;default: 1'b1 ; */
+/*description: This is the mark of channel4's ram usage right.1'b1：receiver
+ uses the ram 0：transmitter uses the ram*/
+#define RMT_MEM_OWNER_CH4 (BIT(5))
+#define RMT_MEM_OWNER_CH4_M (BIT(5))
+#define RMT_MEM_OWNER_CH4_V 0x1
+#define RMT_MEM_OWNER_CH4_S 5
+/* RMT_APB_MEM_RST_CH4 : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: Set this bit to reset W/R ram address for channel4 by apb fifo access*/
+#define RMT_APB_MEM_RST_CH4 (BIT(4))
+#define RMT_APB_MEM_RST_CH4_M (BIT(4))
+#define RMT_APB_MEM_RST_CH4_V 0x1
+#define RMT_APB_MEM_RST_CH4_S 4
+/* RMT_MEM_RD_RST_CH4 : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: Set this bit to reset read ram address for channel4 by transmitter access.*/
+#define RMT_MEM_RD_RST_CH4 (BIT(3))
+#define RMT_MEM_RD_RST_CH4_M (BIT(3))
+#define RMT_MEM_RD_RST_CH4_V 0x1
+#define RMT_MEM_RD_RST_CH4_S 3
+/* RMT_MEM_WR_RST_CH4 : R/W ;bitpos:[2] ;default: 1'h0 ; */
+/*description: Set this bit to reset write ram address for channel4 by receiver access.*/
+#define RMT_MEM_WR_RST_CH4 (BIT(2))
+#define RMT_MEM_WR_RST_CH4_M (BIT(2))
+#define RMT_MEM_WR_RST_CH4_V 0x1
+#define RMT_MEM_WR_RST_CH4_S 2
+/* RMT_RX_EN_CH4 : R/W ;bitpos:[1] ;default: 1'h0 ; */
+/*description: Set this bit to enbale receving data for channel4.*/
+#define RMT_RX_EN_CH4 (BIT(1))
+#define RMT_RX_EN_CH4_M (BIT(1))
+#define RMT_RX_EN_CH4_V 0x1
+#define RMT_RX_EN_CH4_S 1
+/* RMT_TX_START_CH4 : R/W ;bitpos:[0] ;default: 1'h0 ; */
+/*description: Set this bit to start sending data for channel4.*/
+#define RMT_TX_START_CH4 (BIT(0))
+#define RMT_TX_START_CH4_M (BIT(0))
+#define RMT_TX_START_CH4_V 0x1
+#define RMT_TX_START_CH4_S 0
+
+#define RMT_CH5CONF0_REG (DR_REG_RMT_BASE + 0x0048)
+/* RMT_CARRIER_OUT_LV_CH5 : R/W ;bitpos:[29] ;default: 1'b1 ; */
+/*description: This bit is used to configure carrier wave's position for channel5.1'b1:add
+ on low level 1'b0:add on high level.*/
+#define RMT_CARRIER_OUT_LV_CH5 (BIT(29))
+#define RMT_CARRIER_OUT_LV_CH5_M (BIT(29))
+#define RMT_CARRIER_OUT_LV_CH5_V 0x1
+#define RMT_CARRIER_OUT_LV_CH5_S 29
+/* RMT_CARRIER_EN_CH5 : R/W ;bitpos:[28] ;default: 1'b1 ; */
+/*description: This is the carrier modulation enable control bit for channel5.*/
+#define RMT_CARRIER_EN_CH5 (BIT(28))
+#define RMT_CARRIER_EN_CH5_M (BIT(28))
+#define RMT_CARRIER_EN_CH5_V 0x1
+#define RMT_CARRIER_EN_CH5_S 28
+/* RMT_MEM_SIZE_CH5 : R/W ;bitpos:[27:24] ;default: 4'h1 ; */
+/*description: This register is used to configure the the amount of memory blocks
+ allocated to channel5.*/
+#define RMT_MEM_SIZE_CH5 0x0000000F
+#define RMT_MEM_SIZE_CH5_M ((RMT_MEM_SIZE_CH5_V)<<(RMT_MEM_SIZE_CH5_S))
+#define RMT_MEM_SIZE_CH5_V 0xF
+#define RMT_MEM_SIZE_CH5_S 24
+/* RMT_IDLE_THRES_CH5 : R/W ;bitpos:[23:8] ;default: 16'h1000 ; */
+/*description: In receive mode when the counter's value is bigger than reg_idle_thres_ch5
+ then the receive process is done.*/
+#define RMT_IDLE_THRES_CH5 0x0000FFFF
+#define RMT_IDLE_THRES_CH5_M ((RMT_IDLE_THRES_CH5_V)<<(RMT_IDLE_THRES_CH5_S))
+#define RMT_IDLE_THRES_CH5_V 0xFFFF
+#define RMT_IDLE_THRES_CH5_S 8
+/* RMT_DIV_CNT_CH5 : R/W ;bitpos:[7:0] ;default: 8'h2 ; */
+/*description: This register is used to configure the frequency divider's factor in channel5.*/
+#define RMT_DIV_CNT_CH5 0x000000FF
+#define RMT_DIV_CNT_CH5_M ((RMT_DIV_CNT_CH5_V)<<(RMT_DIV_CNT_CH5_S))
+#define RMT_DIV_CNT_CH5_V 0xFF
+#define RMT_DIV_CNT_CH5_S 0
+
+#define RMT_CH5CONF1_REG (DR_REG_RMT_BASE + 0x004c)
+/* RMT_IDLE_OUT_EN_CH5 : R/W ;bitpos:[19] ;default: 1'b0 ; */
+/*description: This is the output enable control bit for channel5 in IDLE state.*/
+#define RMT_IDLE_OUT_EN_CH5 (BIT(19))
+#define RMT_IDLE_OUT_EN_CH5_M (BIT(19))
+#define RMT_IDLE_OUT_EN_CH5_V 0x1
+#define RMT_IDLE_OUT_EN_CH5_S 19
+/* RMT_IDLE_OUT_LV_CH5 : R/W ;bitpos:[18] ;default: 1'b0 ; */
+/*description: This bit configures the output signal's level for channel5 in IDLE state.*/
+#define RMT_IDLE_OUT_LV_CH5 (BIT(18))
+#define RMT_IDLE_OUT_LV_CH5_M (BIT(18))
+#define RMT_IDLE_OUT_LV_CH5_V 0x1
+#define RMT_IDLE_OUT_LV_CH5_S 18
+/* RMT_REF_ALWAYS_ON_CH5 : R/W ;bitpos:[17] ;default: 1'b0 ; */
+/*description: This bit is used to select base clock. 1'b1:clk_apb 1'b0:clk_ref*/
+#define RMT_REF_ALWAYS_ON_CH5 (BIT(17))
+#define RMT_REF_ALWAYS_ON_CH5_M (BIT(17))
+#define RMT_REF_ALWAYS_ON_CH5_V 0x1
+#define RMT_REF_ALWAYS_ON_CH5_S 17
+/* RMT_REF_CNT_RST_CH5 : R/W ;bitpos:[16] ;default: 1'b0 ; */
+/*description: This bit is used to reset divider in channel5.*/
+#define RMT_REF_CNT_RST_CH5 (BIT(16))
+#define RMT_REF_CNT_RST_CH5_M (BIT(16))
+#define RMT_REF_CNT_RST_CH5_V 0x1
+#define RMT_REF_CNT_RST_CH5_S 16
+/* RMT_RX_FILTER_THRES_CH5 : R/W ;bitpos:[15:8] ;default: 8'hf ; */
+/*description: in receive mode channel5 ignore input pulse when the pulse width
+ is smaller then this value.*/
+#define RMT_RX_FILTER_THRES_CH5 0x000000FF
+#define RMT_RX_FILTER_THRES_CH5_M ((RMT_RX_FILTER_THRES_CH5_V)<<(RMT_RX_FILTER_THRES_CH5_S))
+#define RMT_RX_FILTER_THRES_CH5_V 0xFF
+#define RMT_RX_FILTER_THRES_CH5_S 8
+/* RMT_RX_FILTER_EN_CH5 : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: This is the receive filter enable bit for channel5.*/
+#define RMT_RX_FILTER_EN_CH5 (BIT(7))
+#define RMT_RX_FILTER_EN_CH5_M (BIT(7))
+#define RMT_RX_FILTER_EN_CH5_V 0x1
+#define RMT_RX_FILTER_EN_CH5_S 7
+/* RMT_TX_CONTI_MODE_CH5 : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: Set this bit to continue sending from the first data to the
+ last data in channel5.*/
+#define RMT_TX_CONTI_MODE_CH5 (BIT(6))
+#define RMT_TX_CONTI_MODE_CH5_M (BIT(6))
+#define RMT_TX_CONTI_MODE_CH5_V 0x1
+#define RMT_TX_CONTI_MODE_CH5_S 6
+/* RMT_MEM_OWNER_CH5 : R/W ;bitpos:[5] ;default: 1'b1 ; */
+/*description: This is the mark of channel5's ram usage right.1'b1：receiver
+ uses the ram 0：transmitter uses the ram*/
+#define RMT_MEM_OWNER_CH5 (BIT(5))
+#define RMT_MEM_OWNER_CH5_M (BIT(5))
+#define RMT_MEM_OWNER_CH5_V 0x1
+#define RMT_MEM_OWNER_CH5_S 5
+/* RMT_APB_MEM_RST_CH5 : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: Set this bit to reset W/R ram address for channel5 by apb fifo access*/
+#define RMT_APB_MEM_RST_CH5 (BIT(4))
+#define RMT_APB_MEM_RST_CH5_M (BIT(4))
+#define RMT_APB_MEM_RST_CH5_V 0x1
+#define RMT_APB_MEM_RST_CH5_S 4
+/* RMT_MEM_RD_RST_CH5 : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: Set this bit to reset read ram address for channel5 by transmitter access.*/
+#define RMT_MEM_RD_RST_CH5 (BIT(3))
+#define RMT_MEM_RD_RST_CH5_M (BIT(3))
+#define RMT_MEM_RD_RST_CH5_V 0x1
+#define RMT_MEM_RD_RST_CH5_S 3
+/* RMT_MEM_WR_RST_CH5 : R/W ;bitpos:[2] ;default: 1'h0 ; */
+/*description: Set this bit to reset write ram address for channel5 by receiver access.*/
+#define RMT_MEM_WR_RST_CH5 (BIT(2))
+#define RMT_MEM_WR_RST_CH5_M (BIT(2))
+#define RMT_MEM_WR_RST_CH5_V 0x1
+#define RMT_MEM_WR_RST_CH5_S 2
+/* RMT_RX_EN_CH5 : R/W ;bitpos:[1] ;default: 1'h0 ; */
+/*description: Set this bit to enbale receving data for channel5.*/
+#define RMT_RX_EN_CH5 (BIT(1))
+#define RMT_RX_EN_CH5_M (BIT(1))
+#define RMT_RX_EN_CH5_V 0x1
+#define RMT_RX_EN_CH5_S 1
+/* RMT_TX_START_CH5 : R/W ;bitpos:[0] ;default: 1'h0 ; */
+/*description: Set this bit to start sending data for channel5.*/
+#define RMT_TX_START_CH5 (BIT(0))
+#define RMT_TX_START_CH5_M (BIT(0))
+#define RMT_TX_START_CH5_V 0x1
+#define RMT_TX_START_CH5_S 0
+
+#define RMT_CH6CONF0_REG (DR_REG_RMT_BASE + 0x0050)
+/* RMT_CARRIER_OUT_LV_CH6 : R/W ;bitpos:[29] ;default: 1'b1 ; */
+/*description: This bit is used to configure carrier wave's position for channel6.1'b1:add
+ on low level 1'b0:add on high level.*/
+#define RMT_CARRIER_OUT_LV_CH6 (BIT(29))
+#define RMT_CARRIER_OUT_LV_CH6_M (BIT(29))
+#define RMT_CARRIER_OUT_LV_CH6_V 0x1
+#define RMT_CARRIER_OUT_LV_CH6_S 29
+/* RMT_CARRIER_EN_CH6 : R/W ;bitpos:[28] ;default: 1'b1 ; */
+/*description: This is the carrier modulation enable control bit for channel6.*/
+#define RMT_CARRIER_EN_CH6 (BIT(28))
+#define RMT_CARRIER_EN_CH6_M (BIT(28))
+#define RMT_CARRIER_EN_CH6_V 0x1
+#define RMT_CARRIER_EN_CH6_S 28
+/* RMT_MEM_SIZE_CH6 : R/W ;bitpos:[27:24] ;default: 4'h1 ; */
+/*description: This register is used to configure the the amount of memory blocks
+ allocated to channel6.*/
+#define RMT_MEM_SIZE_CH6 0x0000000F
+#define RMT_MEM_SIZE_CH6_M ((RMT_MEM_SIZE_CH6_V)<<(RMT_MEM_SIZE_CH6_S))
+#define RMT_MEM_SIZE_CH6_V 0xF
+#define RMT_MEM_SIZE_CH6_S 24
+/* RMT_IDLE_THRES_CH6 : R/W ;bitpos:[23:8] ;default: 16'h1000 ; */
+/*description: In receive mode when the counter's value is bigger than reg_idle_thres_ch6
+ then the receive process is done.*/
+#define RMT_IDLE_THRES_CH6 0x0000FFFF
+#define RMT_IDLE_THRES_CH6_M ((RMT_IDLE_THRES_CH6_V)<<(RMT_IDLE_THRES_CH6_S))
+#define RMT_IDLE_THRES_CH6_V 0xFFFF
+#define RMT_IDLE_THRES_CH6_S 8
+/* RMT_DIV_CNT_CH6 : R/W ;bitpos:[7:0] ;default: 8'h2 ; */
+/*description: This register is used to configure the frequency divider's factor in channel6.*/
+#define RMT_DIV_CNT_CH6 0x000000FF
+#define RMT_DIV_CNT_CH6_M ((RMT_DIV_CNT_CH6_V)<<(RMT_DIV_CNT_CH6_S))
+#define RMT_DIV_CNT_CH6_V 0xFF
+#define RMT_DIV_CNT_CH6_S 0
+
+#define RMT_CH6CONF1_REG (DR_REG_RMT_BASE + 0x0054)
+/* RMT_IDLE_OUT_EN_CH6 : R/W ;bitpos:[19] ;default: 1'b0 ; */
+/*description: This is the output enable control bit for channel6 in IDLE state.*/
+#define RMT_IDLE_OUT_EN_CH6 (BIT(19))
+#define RMT_IDLE_OUT_EN_CH6_M (BIT(19))
+#define RMT_IDLE_OUT_EN_CH6_V 0x1
+#define RMT_IDLE_OUT_EN_CH6_S 19
+/* RMT_IDLE_OUT_LV_CH6 : R/W ;bitpos:[18] ;default: 1'b0 ; */
+/*description: This bit configures the output signal's level for channel6 in IDLE state.*/
+#define RMT_IDLE_OUT_LV_CH6 (BIT(18))
+#define RMT_IDLE_OUT_LV_CH6_M (BIT(18))
+#define RMT_IDLE_OUT_LV_CH6_V 0x1
+#define RMT_IDLE_OUT_LV_CH6_S 18
+/* RMT_REF_ALWAYS_ON_CH6 : R/W ;bitpos:[17] ;default: 1'b0 ; */
+/*description: This bit is used to select base clock. 1'b1:clk_apb 1'b0:clk_ref*/
+#define RMT_REF_ALWAYS_ON_CH6 (BIT(17))
+#define RMT_REF_ALWAYS_ON_CH6_M (BIT(17))
+#define RMT_REF_ALWAYS_ON_CH6_V 0x1
+#define RMT_REF_ALWAYS_ON_CH6_S 17
+/* RMT_REF_CNT_RST_CH6 : R/W ;bitpos:[16] ;default: 1'b0 ; */
+/*description: This bit is used to reset divider in channel6.*/
+#define RMT_REF_CNT_RST_CH6 (BIT(16))
+#define RMT_REF_CNT_RST_CH6_M (BIT(16))
+#define RMT_REF_CNT_RST_CH6_V 0x1
+#define RMT_REF_CNT_RST_CH6_S 16
+/* RMT_RX_FILTER_THRES_CH6 : R/W ;bitpos:[15:8] ;default: 8'hf ; */
+/*description: in receive mode channel6 ignore input pulse when the pulse width
+ is smaller then this value.*/
+#define RMT_RX_FILTER_THRES_CH6 0x000000FF
+#define RMT_RX_FILTER_THRES_CH6_M ((RMT_RX_FILTER_THRES_CH6_V)<<(RMT_RX_FILTER_THRES_CH6_S))
+#define RMT_RX_FILTER_THRES_CH6_V 0xFF
+#define RMT_RX_FILTER_THRES_CH6_S 8
+/* RMT_RX_FILTER_EN_CH6 : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: This is the receive filter enable bit for channel6.*/
+#define RMT_RX_FILTER_EN_CH6 (BIT(7))
+#define RMT_RX_FILTER_EN_CH6_M (BIT(7))
+#define RMT_RX_FILTER_EN_CH6_V 0x1
+#define RMT_RX_FILTER_EN_CH6_S 7
+/* RMT_TX_CONTI_MODE_CH6 : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: Set this bit to continue sending from the first data to the
+ last data in channel6.*/
+#define RMT_TX_CONTI_MODE_CH6 (BIT(6))
+#define RMT_TX_CONTI_MODE_CH6_M (BIT(6))
+#define RMT_TX_CONTI_MODE_CH6_V 0x1
+#define RMT_TX_CONTI_MODE_CH6_S 6
+/* RMT_MEM_OWNER_CH6 : R/W ;bitpos:[5] ;default: 1'b1 ; */
+/*description: This is the mark of channel6's ram usage right.1'b1：receiver
+ uses the ram 0：transmitter uses the ram*/
+#define RMT_MEM_OWNER_CH6 (BIT(5))
+#define RMT_MEM_OWNER_CH6_M (BIT(5))
+#define RMT_MEM_OWNER_CH6_V 0x1
+#define RMT_MEM_OWNER_CH6_S 5
+/* RMT_APB_MEM_RST_CH6 : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: Set this bit to reset W/R ram address for channel6 by apb fifo access*/
+#define RMT_APB_MEM_RST_CH6 (BIT(4))
+#define RMT_APB_MEM_RST_CH6_M (BIT(4))
+#define RMT_APB_MEM_RST_CH6_V 0x1
+#define RMT_APB_MEM_RST_CH6_S 4
+/* RMT_MEM_RD_RST_CH6 : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: Set this bit to reset read ram address for channel6 by transmitter access.*/
+#define RMT_MEM_RD_RST_CH6 (BIT(3))
+#define RMT_MEM_RD_RST_CH6_M (BIT(3))
+#define RMT_MEM_RD_RST_CH6_V 0x1
+#define RMT_MEM_RD_RST_CH6_S 3
+/* RMT_MEM_WR_RST_CH6 : R/W ;bitpos:[2] ;default: 1'h0 ; */
+/*description: Set this bit to reset write ram address for channel6 by receiver access.*/
+#define RMT_MEM_WR_RST_CH6 (BIT(2))
+#define RMT_MEM_WR_RST_CH6_M (BIT(2))
+#define RMT_MEM_WR_RST_CH6_V 0x1
+#define RMT_MEM_WR_RST_CH6_S 2
+/* RMT_RX_EN_CH6 : R/W ;bitpos:[1] ;default: 1'h0 ; */
+/*description: Set this bit to enbale receving data for channel6.*/
+#define RMT_RX_EN_CH6 (BIT(1))
+#define RMT_RX_EN_CH6_M (BIT(1))
+#define RMT_RX_EN_CH6_V 0x1
+#define RMT_RX_EN_CH6_S 1
+/* RMT_TX_START_CH6 : R/W ;bitpos:[0] ;default: 1'h0 ; */
+/*description: Set this bit to start sending data for channel6.*/
+#define RMT_TX_START_CH6 (BIT(0))
+#define RMT_TX_START_CH6_M (BIT(0))
+#define RMT_TX_START_CH6_V 0x1
+#define RMT_TX_START_CH6_S 0
+
+#define RMT_CH7CONF0_REG (DR_REG_RMT_BASE + 0x0058)
+/* RMT_CARRIER_OUT_LV_CH7 : R/W ;bitpos:[29] ;default: 1'b1 ; */
+/*description: This bit is used to configure carrier wave's position for channel7.1'b1:add
+ on low level 1'b0:add on high level.*/
+#define RMT_CARRIER_OUT_LV_CH7 (BIT(29))
+#define RMT_CARRIER_OUT_LV_CH7_M (BIT(29))
+#define RMT_CARRIER_OUT_LV_CH7_V 0x1
+#define RMT_CARRIER_OUT_LV_CH7_S 29
+/* RMT_CARRIER_EN_CH7 : R/W ;bitpos:[28] ;default: 1'b1 ; */
+/*description: This is the carrier modulation enable control bit for channel7.*/
+#define RMT_CARRIER_EN_CH7 (BIT(28))
+#define RMT_CARRIER_EN_CH7_M (BIT(28))
+#define RMT_CARRIER_EN_CH7_V 0x1
+#define RMT_CARRIER_EN_CH7_S 28
+/* RMT_MEM_SIZE_CH7 : R/W ;bitpos:[27:24] ;default: 4'h1 ; */
+/*description: This register is used to configure the the amount of memory blocks
+ allocated to channel7.*/
+#define RMT_MEM_SIZE_CH7 0x0000000F
+#define RMT_MEM_SIZE_CH7_M ((RMT_MEM_SIZE_CH7_V)<<(RMT_MEM_SIZE_CH7_S))
+#define RMT_MEM_SIZE_CH7_V 0xF
+#define RMT_MEM_SIZE_CH7_S 24
+/* RMT_IDLE_THRES_CH7 : R/W ;bitpos:[23:8] ;default: 16'h1000 ; */
+/*description: In receive mode when the counter's value is bigger than reg_idle_thres_ch7
+ then the receive process is done.*/
+#define RMT_IDLE_THRES_CH7 0x0000FFFF
+#define RMT_IDLE_THRES_CH7_M ((RMT_IDLE_THRES_CH7_V)<<(RMT_IDLE_THRES_CH7_S))
+#define RMT_IDLE_THRES_CH7_V 0xFFFF
+#define RMT_IDLE_THRES_CH7_S 8
+/* RMT_DIV_CNT_CH7 : R/W ;bitpos:[7:0] ;default: 8'h2 ; */
+/*description: This register is used to configure the frequency divider's factor in channel7.*/
+#define RMT_DIV_CNT_CH7 0x000000FF
+#define RMT_DIV_CNT_CH7_M ((RMT_DIV_CNT_CH7_V)<<(RMT_DIV_CNT_CH7_S))
+#define RMT_DIV_CNT_CH7_V 0xFF
+#define RMT_DIV_CNT_CH7_S 0
+
+#define RMT_CH7CONF1_REG (DR_REG_RMT_BASE + 0x005c)
+/* RMT_IDLE_OUT_EN_CH7 : R/W ;bitpos:[19] ;default: 1'b0 ; */
+/*description: This is the output enable control bit for channel6 in IDLE state.*/
+#define RMT_IDLE_OUT_EN_CH7 (BIT(19))
+#define RMT_IDLE_OUT_EN_CH7_M (BIT(19))
+#define RMT_IDLE_OUT_EN_CH7_V 0x1
+#define RMT_IDLE_OUT_EN_CH7_S 19
+/* RMT_IDLE_OUT_LV_CH7 : R/W ;bitpos:[18] ;default: 1'b0 ; */
+/*description: This bit configures the output signal's level for channel7 in IDLE state.*/
+#define RMT_IDLE_OUT_LV_CH7 (BIT(18))
+#define RMT_IDLE_OUT_LV_CH7_M (BIT(18))
+#define RMT_IDLE_OUT_LV_CH7_V 0x1
+#define RMT_IDLE_OUT_LV_CH7_S 18
+/* RMT_REF_ALWAYS_ON_CH7 : R/W ;bitpos:[17] ;default: 1'b0 ; */
+/*description: This bit is used to select base clock. 1'b1:clk_apb 1'b0:clk_ref*/
+#define RMT_REF_ALWAYS_ON_CH7 (BIT(17))
+#define RMT_REF_ALWAYS_ON_CH7_M (BIT(17))
+#define RMT_REF_ALWAYS_ON_CH7_V 0x1
+#define RMT_REF_ALWAYS_ON_CH7_S 17
+/* RMT_REF_CNT_RST_CH7 : R/W ;bitpos:[16] ;default: 1'b0 ; */
+/*description: This bit is used to reset divider in channel7.*/
+#define RMT_REF_CNT_RST_CH7 (BIT(16))
+#define RMT_REF_CNT_RST_CH7_M (BIT(16))
+#define RMT_REF_CNT_RST_CH7_V 0x1
+#define RMT_REF_CNT_RST_CH7_S 16
+/* RMT_RX_FILTER_THRES_CH7 : R/W ;bitpos:[15:8] ;default: 8'hf ; */
+/*description: in receive mode channel7 ignore input pulse when the pulse width
+ is smaller then this value.*/
+#define RMT_RX_FILTER_THRES_CH7 0x000000FF
+#define RMT_RX_FILTER_THRES_CH7_M ((RMT_RX_FILTER_THRES_CH7_V)<<(RMT_RX_FILTER_THRES_CH7_S))
+#define RMT_RX_FILTER_THRES_CH7_V 0xFF
+#define RMT_RX_FILTER_THRES_CH7_S 8
+/* RMT_RX_FILTER_EN_CH7 : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: This is the receive filter enable bit for channel7.*/
+#define RMT_RX_FILTER_EN_CH7 (BIT(7))
+#define RMT_RX_FILTER_EN_CH7_M (BIT(7))
+#define RMT_RX_FILTER_EN_CH7_V 0x1
+#define RMT_RX_FILTER_EN_CH7_S 7
+/* RMT_TX_CONTI_MODE_CH7 : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: Set this bit to continue sending from the first data to the
+ last data in channel7.*/
+#define RMT_TX_CONTI_MODE_CH7 (BIT(6))
+#define RMT_TX_CONTI_MODE_CH7_M (BIT(6))
+#define RMT_TX_CONTI_MODE_CH7_V 0x1
+#define RMT_TX_CONTI_MODE_CH7_S 6
+/* RMT_MEM_OWNER_CH7 : R/W ;bitpos:[5] ;default: 1'b1 ; */
+/*description: This is the mark of channel7's ram usage right.1'b1：receiver
+ uses the ram 0：transmitter uses the ram*/
+#define RMT_MEM_OWNER_CH7 (BIT(5))
+#define RMT_MEM_OWNER_CH7_M (BIT(5))
+#define RMT_MEM_OWNER_CH7_V 0x1
+#define RMT_MEM_OWNER_CH7_S 5
+/* RMT_APB_MEM_RST_CH7 : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: Set this bit to reset W/R ram address for channel7 by apb fifo access*/
+#define RMT_APB_MEM_RST_CH7 (BIT(4))
+#define RMT_APB_MEM_RST_CH7_M (BIT(4))
+#define RMT_APB_MEM_RST_CH7_V 0x1
+#define RMT_APB_MEM_RST_CH7_S 4
+/* RMT_MEM_RD_RST_CH7 : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: Set this bit to reset read ram address for channel7 by transmitter access.*/
+#define RMT_MEM_RD_RST_CH7 (BIT(3))
+#define RMT_MEM_RD_RST_CH7_M (BIT(3))
+#define RMT_MEM_RD_RST_CH7_V 0x1
+#define RMT_MEM_RD_RST_CH7_S 3
+/* RMT_MEM_WR_RST_CH7 : R/W ;bitpos:[2] ;default: 1'h0 ; */
+/*description: Set this bit to reset write ram address for channel7 by receiver access.*/
+#define RMT_MEM_WR_RST_CH7 (BIT(2))
+#define RMT_MEM_WR_RST_CH7_M (BIT(2))
+#define RMT_MEM_WR_RST_CH7_V 0x1
+#define RMT_MEM_WR_RST_CH7_S 2
+/* RMT_RX_EN_CH7 : R/W ;bitpos:[1] ;default: 1'h0 ; */
+/*description: Set this bit to enbale receving data for channel7.*/
+#define RMT_RX_EN_CH7 (BIT(1))
+#define RMT_RX_EN_CH7_M (BIT(1))
+#define RMT_RX_EN_CH7_V 0x1
+#define RMT_RX_EN_CH7_S 1
+/* RMT_TX_START_CH7 : R/W ;bitpos:[0] ;default: 1'h0 ; */
+/*description: Set this bit to start sending data for channel7.*/
+#define RMT_TX_START_CH7 (BIT(0))
+#define RMT_TX_START_CH7_M (BIT(0))
+#define RMT_TX_START_CH7_V 0x1
+#define RMT_TX_START_CH7_S 0
+
+#define RMT_CH0STATUS_REG (DR_REG_RMT_BASE + 0x0060)
+/* RMT_STATUS_CH0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: The status for channel0*/
+#define RMT_STATUS_CH0 0xFFFFFFFF
+#define RMT_STATUS_CH0_M ((RMT_STATUS_CH0_V)<<(RMT_STATUS_CH0_S))
+#define RMT_STATUS_CH0_V 0xFFFFFFFF
+#define RMT_STATUS_CH0_S 0
+
+#define RMT_CH1STATUS_REG (DR_REG_RMT_BASE + 0x0064)
+/* RMT_STATUS_CH1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: The status for channel1*/
+#define RMT_STATUS_CH1 0xFFFFFFFF
+#define RMT_STATUS_CH1_M ((RMT_STATUS_CH1_V)<<(RMT_STATUS_CH1_S))
+#define RMT_STATUS_CH1_V 0xFFFFFFFF
+#define RMT_STATUS_CH1_S 0
+
+#define RMT_CH2STATUS_REG (DR_REG_RMT_BASE + 0x0068)
+/* RMT_STATUS_CH2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: The status for channel2*/
+#define RMT_STATUS_CH2 0xFFFFFFFF
+#define RMT_STATUS_CH2_M ((RMT_STATUS_CH2_V)<<(RMT_STATUS_CH2_S))
+#define RMT_STATUS_CH2_V 0xFFFFFFFF
+#define RMT_STATUS_CH2_S 0
+
+#define RMT_CH3STATUS_REG (DR_REG_RMT_BASE + 0x006c)
+/* RMT_STATUS_CH3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: The status for channel3*/
+#define RMT_STATUS_CH3 0xFFFFFFFF
+#define RMT_STATUS_CH3_M ((RMT_STATUS_CH3_V)<<(RMT_STATUS_CH3_S))
+#define RMT_STATUS_CH3_V 0xFFFFFFFF
+#define RMT_STATUS_CH3_S 0
+
+#define RMT_CH4STATUS_REG (DR_REG_RMT_BASE + 0x0070)
+/* RMT_STATUS_CH4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: The status for channel4*/
+#define RMT_STATUS_CH4 0xFFFFFFFF
+#define RMT_STATUS_CH4_M ((RMT_STATUS_CH4_V)<<(RMT_STATUS_CH4_S))
+#define RMT_STATUS_CH4_V 0xFFFFFFFF
+#define RMT_STATUS_CH4_S 0
+
+#define RMT_CH5STATUS_REG (DR_REG_RMT_BASE + 0x0074)
+/* RMT_STATUS_CH5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: The status for channel5*/
+#define RMT_STATUS_CH5 0xFFFFFFFF
+#define RMT_STATUS_CH5_M ((RMT_STATUS_CH5_V)<<(RMT_STATUS_CH5_S))
+#define RMT_STATUS_CH5_V 0xFFFFFFFF
+#define RMT_STATUS_CH5_S 0
+
+#define RMT_CH6STATUS_REG (DR_REG_RMT_BASE + 0x0078)
+/* RMT_STATUS_CH6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: The status for channel6*/
+#define RMT_STATUS_CH6 0xFFFFFFFF
+#define RMT_STATUS_CH6_M ((RMT_STATUS_CH6_V)<<(RMT_STATUS_CH6_S))
+#define RMT_STATUS_CH6_V 0xFFFFFFFF
+#define RMT_STATUS_CH6_S 0
+
+#define RMT_CH7STATUS_REG (DR_REG_RMT_BASE + 0x007c)
+/* RMT_STATUS_CH7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: The status for channel7*/
+#define RMT_STATUS_CH7 0xFFFFFFFF
+#define RMT_STATUS_CH7_M ((RMT_STATUS_CH7_V)<<(RMT_STATUS_CH7_S))
+#define RMT_STATUS_CH7_V 0xFFFFFFFF
+#define RMT_STATUS_CH7_S 0
+
+#define RMT_CH0ADDR_REG (DR_REG_RMT_BASE + 0x0080)
+/* RMT_APB_MEM_ADDR_CH0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: The ram relative address in channel0 by apb fifo access*/
+#define RMT_APB_MEM_ADDR_CH0 0xFFFFFFFF
+#define RMT_APB_MEM_ADDR_CH0_M ((RMT_APB_MEM_ADDR_CH0_V)<<(RMT_APB_MEM_ADDR_CH0_S))
+#define RMT_APB_MEM_ADDR_CH0_V 0xFFFFFFFF
+#define RMT_APB_MEM_ADDR_CH0_S 0
+
+#define RMT_CH1ADDR_REG (DR_REG_RMT_BASE + 0x0084)
+/* RMT_APB_MEM_ADDR_CH1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: The ram relative address in channel1 by apb fifo access*/
+#define RMT_APB_MEM_ADDR_CH1 0xFFFFFFFF
+#define RMT_APB_MEM_ADDR_CH1_M ((RMT_APB_MEM_ADDR_CH1_V)<<(RMT_APB_MEM_ADDR_CH1_S))
+#define RMT_APB_MEM_ADDR_CH1_V 0xFFFFFFFF
+#define RMT_APB_MEM_ADDR_CH1_S 0
+
+#define RMT_CH2ADDR_REG (DR_REG_RMT_BASE + 0x0088)
+/* RMT_APB_MEM_ADDR_CH2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: The ram relative address in channel2 by apb fifo access*/
+#define RMT_APB_MEM_ADDR_CH2 0xFFFFFFFF
+#define RMT_APB_MEM_ADDR_CH2_M ((RMT_APB_MEM_ADDR_CH2_V)<<(RMT_APB_MEM_ADDR_CH2_S))
+#define RMT_APB_MEM_ADDR_CH2_V 0xFFFFFFFF
+#define RMT_APB_MEM_ADDR_CH2_S 0
+
+#define RMT_CH3ADDR_REG (DR_REG_RMT_BASE + 0x008c)
+/* RMT_APB_MEM_ADDR_CH3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: The ram relative address in channel3 by apb fifo access*/
+#define RMT_APB_MEM_ADDR_CH3 0xFFFFFFFF
+#define RMT_APB_MEM_ADDR_CH3_M ((RMT_APB_MEM_ADDR_CH3_V)<<(RMT_APB_MEM_ADDR_CH3_S))
+#define RMT_APB_MEM_ADDR_CH3_V 0xFFFFFFFF
+#define RMT_APB_MEM_ADDR_CH3_S 0
+
+#define RMT_CH4ADDR_REG (DR_REG_RMT_BASE + 0x0090)
+/* RMT_APB_MEM_ADDR_CH4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: The ram relative address in channel4 by apb fifo access*/
+#define RMT_APB_MEM_ADDR_CH4 0xFFFFFFFF
+#define RMT_APB_MEM_ADDR_CH4_M ((RMT_APB_MEM_ADDR_CH4_V)<<(RMT_APB_MEM_ADDR_CH4_S))
+#define RMT_APB_MEM_ADDR_CH4_V 0xFFFFFFFF
+#define RMT_APB_MEM_ADDR_CH4_S 0
+
+#define RMT_CH5ADDR_REG (DR_REG_RMT_BASE + 0x0094)
+/* RMT_APB_MEM_ADDR_CH5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: The ram relative address in channel5 by apb fifo access*/
+#define RMT_APB_MEM_ADDR_CH5 0xFFFFFFFF
+#define RMT_APB_MEM_ADDR_CH5_M ((RMT_APB_MEM_ADDR_CH5_V)<<(RMT_APB_MEM_ADDR_CH5_S))
+#define RMT_APB_MEM_ADDR_CH5_V 0xFFFFFFFF
+#define RMT_APB_MEM_ADDR_CH5_S 0
+
+#define RMT_CH6ADDR_REG (DR_REG_RMT_BASE + 0x0098)
+/* RMT_APB_MEM_ADDR_CH6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: The ram relative address in channel6 by apb fifo access*/
+#define RMT_APB_MEM_ADDR_CH6 0xFFFFFFFF
+#define RMT_APB_MEM_ADDR_CH6_M ((RMT_APB_MEM_ADDR_CH6_V)<<(RMT_APB_MEM_ADDR_CH6_S))
+#define RMT_APB_MEM_ADDR_CH6_V 0xFFFFFFFF
+#define RMT_APB_MEM_ADDR_CH6_S 0
+
+#define RMT_CH7ADDR_REG (DR_REG_RMT_BASE + 0x009c)
+/* RMT_APB_MEM_ADDR_CH7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: The ram relative address in channel7 by apb fifo access*/
+#define RMT_APB_MEM_ADDR_CH7 0xFFFFFFFF
+#define RMT_APB_MEM_ADDR_CH7_M ((RMT_APB_MEM_ADDR_CH7_V)<<(RMT_APB_MEM_ADDR_CH7_S))
+#define RMT_APB_MEM_ADDR_CH7_V 0xFFFFFFFF
+#define RMT_APB_MEM_ADDR_CH7_S 0
+
+#define RMT_INT_RAW_REG (DR_REG_RMT_BASE + 0x00a0)
+/* RMT_CH7_TX_THR_EVENT_INT_RAW : RO ;bitpos:[31] ;default: 1'b0 ; */
+/*description: The interrupt raw bit for channel 7 turns to high level when
+ transmitter in channle7 have send datas more than reg_rmt_tx_lim_ch7 after detecting this interrupt software can updata the old datas with new datas.*/
+#define RMT_CH7_TX_THR_EVENT_INT_RAW (BIT(31))
+#define RMT_CH7_TX_THR_EVENT_INT_RAW_M (BIT(31))
+#define RMT_CH7_TX_THR_EVENT_INT_RAW_V 0x1
+#define RMT_CH7_TX_THR_EVENT_INT_RAW_S 31
+/* RMT_CH6_TX_THR_EVENT_INT_RAW : RO ;bitpos:[30] ;default: 1'b0 ; */
+/*description: The interrupt raw bit for channel 6 turns to high level when
+ transmitter in channle6 have send datas more than reg_rmt_tx_lim_ch6 after detecting this interrupt software can updata the old datas with new datas.*/
+#define RMT_CH6_TX_THR_EVENT_INT_RAW (BIT(30))
+#define RMT_CH6_TX_THR_EVENT_INT_RAW_M (BIT(30))
+#define RMT_CH6_TX_THR_EVENT_INT_RAW_V 0x1
+#define RMT_CH6_TX_THR_EVENT_INT_RAW_S 30
+/* RMT_CH5_TX_THR_EVENT_INT_RAW : RO ;bitpos:[29] ;default: 1'b0 ; */
+/*description: The interrupt raw bit for channel 5 turns to high level when
+ transmitter in channle5 have send datas more than reg_rmt_tx_lim_ch5 after detecting this interrupt software can updata the old datas with new datas.*/
+#define RMT_CH5_TX_THR_EVENT_INT_RAW (BIT(29))
+#define RMT_CH5_TX_THR_EVENT_INT_RAW_M (BIT(29))
+#define RMT_CH5_TX_THR_EVENT_INT_RAW_V 0x1
+#define RMT_CH5_TX_THR_EVENT_INT_RAW_S 29
+/* RMT_CH4_TX_THR_EVENT_INT_RAW : RO ;bitpos:[28] ;default: 1'b0 ; */
+/*description: The interrupt raw bit for channel 4 turns to high level when
+ transmitter in channle4 have send datas more than reg_rmt_tx_lim_ch4 after detecting this interrupt software can updata the old datas with new datas.*/
+#define RMT_CH4_TX_THR_EVENT_INT_RAW (BIT(28))
+#define RMT_CH4_TX_THR_EVENT_INT_RAW_M (BIT(28))
+#define RMT_CH4_TX_THR_EVENT_INT_RAW_V 0x1
+#define RMT_CH4_TX_THR_EVENT_INT_RAW_S 28
+/* RMT_CH3_TX_THR_EVENT_INT_RAW : RO ;bitpos:[27] ;default: 1'b0 ; */
+/*description: The interrupt raw bit for channel 3 turns to high level when
+ transmitter in channle3 have send datas more than reg_rmt_tx_lim_ch3 after detecting this interrupt software can updata the old datas with new datas.*/
+#define RMT_CH3_TX_THR_EVENT_INT_RAW (BIT(27))
+#define RMT_CH3_TX_THR_EVENT_INT_RAW_M (BIT(27))
+#define RMT_CH3_TX_THR_EVENT_INT_RAW_V 0x1
+#define RMT_CH3_TX_THR_EVENT_INT_RAW_S 27
+/* RMT_CH2_TX_THR_EVENT_INT_RAW : RO ;bitpos:[26] ;default: 1'b0 ; */
+/*description: The interrupt raw bit for channel 2 turns to high level when
+ transmitter in channle2 have send datas more than reg_rmt_tx_lim_ch2 after detecting this interrupt software can updata the old datas with new datas.*/
+#define RMT_CH2_TX_THR_EVENT_INT_RAW (BIT(26))
+#define RMT_CH2_TX_THR_EVENT_INT_RAW_M (BIT(26))
+#define RMT_CH2_TX_THR_EVENT_INT_RAW_V 0x1
+#define RMT_CH2_TX_THR_EVENT_INT_RAW_S 26
+/* RMT_CH1_TX_THR_EVENT_INT_RAW : RO ;bitpos:[25] ;default: 1'b0 ; */
+/*description: The interrupt raw bit for channel 1 turns to high level when
+ transmitter in channle1 have send datas more than reg_rmt_tx_lim_ch1 after detecting this interrupt software can updata the old datas with new datas.*/
+#define RMT_CH1_TX_THR_EVENT_INT_RAW (BIT(25))
+#define RMT_CH1_TX_THR_EVENT_INT_RAW_M (BIT(25))
+#define RMT_CH1_TX_THR_EVENT_INT_RAW_V 0x1
+#define RMT_CH1_TX_THR_EVENT_INT_RAW_S 25
+/* RMT_CH0_TX_THR_EVENT_INT_RAW : RO ;bitpos:[24] ;default: 1'b0 ; */
+/*description: The interrupt raw bit for channel 0 turns to high level when
+ transmitter in channle0 have send datas more than reg_rmt_tx_lim_ch0 after detecting this interrupt software can updata the old datas with new datas.*/
+#define RMT_CH0_TX_THR_EVENT_INT_RAW (BIT(24))
+#define RMT_CH0_TX_THR_EVENT_INT_RAW_M (BIT(24))
+#define RMT_CH0_TX_THR_EVENT_INT_RAW_V 0x1
+#define RMT_CH0_TX_THR_EVENT_INT_RAW_S 24
+/* RMT_CH7_ERR_INT_RAW : RO ;bitpos:[23] ;default: 1'b0 ; */
+/*description: The interrupt raw bit for channel 7 turns to high level when
+ channle 7 detects some errors.*/
+#define RMT_CH7_ERR_INT_RAW (BIT(23))
+#define RMT_CH7_ERR_INT_RAW_M (BIT(23))
+#define RMT_CH7_ERR_INT_RAW_V 0x1
+#define RMT_CH7_ERR_INT_RAW_S 23
+/* RMT_CH7_RX_END_INT_RAW : RO ;bitpos:[22] ;default: 1'b0 ; */
+/*description: The interrupt raw bit for channel 7 turns to high level when
+ the receive process is done.*/
+#define RMT_CH7_RX_END_INT_RAW (BIT(22))
+#define RMT_CH7_RX_END_INT_RAW_M (BIT(22))
+#define RMT_CH7_RX_END_INT_RAW_V 0x1
+#define RMT_CH7_RX_END_INT_RAW_S 22
+/* RMT_CH7_TX_END_INT_RAW : RO ;bitpos:[21] ;default: 1'b0 ; */
+/*description: The interrupt raw bit for channel 7 turns to high level when
+ the transmit process is done.*/
+#define RMT_CH7_TX_END_INT_RAW (BIT(21))
+#define RMT_CH7_TX_END_INT_RAW_M (BIT(21))
+#define RMT_CH7_TX_END_INT_RAW_V 0x1
+#define RMT_CH7_TX_END_INT_RAW_S 21
+/* RMT_CH6_ERR_INT_RAW : RO ;bitpos:[20] ;default: 1'b0 ; */
+/*description: The interrupt raw bit for channel 6 turns to high level when
+ channle 6 detects some errors.*/
+#define RMT_CH6_ERR_INT_RAW (BIT(20))
+#define RMT_CH6_ERR_INT_RAW_M (BIT(20))
+#define RMT_CH6_ERR_INT_RAW_V 0x1
+#define RMT_CH6_ERR_INT_RAW_S 20
+/* RMT_CH6_RX_END_INT_RAW : RO ;bitpos:[19] ;default: 1'b0 ; */
+/*description: The interrupt raw bit for channel 6 turns to high level when
+ the receive process is done.*/
+#define RMT_CH6_RX_END_INT_RAW (BIT(19))
+#define RMT_CH6_RX_END_INT_RAW_M (BIT(19))
+#define RMT_CH6_RX_END_INT_RAW_V 0x1
+#define RMT_CH6_RX_END_INT_RAW_S 19
+/* RMT_CH6_TX_END_INT_RAW : RO ;bitpos:[18] ;default: 1'b0 ; */
+/*description: The interrupt raw bit for channel 6 turns to high level when
+ the transmit process is done.*/
+#define RMT_CH6_TX_END_INT_RAW (BIT(18))
+#define RMT_CH6_TX_END_INT_RAW_M (BIT(18))
+#define RMT_CH6_TX_END_INT_RAW_V 0x1
+#define RMT_CH6_TX_END_INT_RAW_S 18
+/* RMT_CH5_ERR_INT_RAW : RO ;bitpos:[17] ;default: 1'b0 ; */
+/*description: The interrupt raw bit for channel 5 turns to high level when
+ channle 5 detects some errors.*/
+#define RMT_CH5_ERR_INT_RAW (BIT(17))
+#define RMT_CH5_ERR_INT_RAW_M (BIT(17))
+#define RMT_CH5_ERR_INT_RAW_V 0x1
+#define RMT_CH5_ERR_INT_RAW_S 17
+/* RMT_CH5_RX_END_INT_RAW : RO ;bitpos:[16] ;default: 1'b0 ; */
+/*description: The interrupt raw bit for channel 5 turns to high level when
+ the receive process is done.*/
+#define RMT_CH5_RX_END_INT_RAW (BIT(16))
+#define RMT_CH5_RX_END_INT_RAW_M (BIT(16))
+#define RMT_CH5_RX_END_INT_RAW_V 0x1
+#define RMT_CH5_RX_END_INT_RAW_S 16
+/* RMT_CH5_TX_END_INT_RAW : RO ;bitpos:[15] ;default: 1'b0 ; */
+/*description: The interrupt raw bit for channel 5 turns to high level when
+ the transmit process is done.*/
+#define RMT_CH5_TX_END_INT_RAW (BIT(15))
+#define RMT_CH5_TX_END_INT_RAW_M (BIT(15))
+#define RMT_CH5_TX_END_INT_RAW_V 0x1
+#define RMT_CH5_TX_END_INT_RAW_S 15
+/* RMT_CH4_ERR_INT_RAW : RO ;bitpos:[14] ;default: 1'b0 ; */
+/*description: The interrupt raw bit for channel 4 turns to high level when
+ channle 4 detects some errors.*/
+#define RMT_CH4_ERR_INT_RAW (BIT(14))
+#define RMT_CH4_ERR_INT_RAW_M (BIT(14))
+#define RMT_CH4_ERR_INT_RAW_V 0x1
+#define RMT_CH4_ERR_INT_RAW_S 14
+/* RMT_CH4_RX_END_INT_RAW : RO ;bitpos:[13] ;default: 1'b0 ; */
+/*description: The interrupt raw bit for channel 4 turns to high level when
+ the receive process is done.*/
+#define RMT_CH4_RX_END_INT_RAW (BIT(13))
+#define RMT_CH4_RX_END_INT_RAW_M (BIT(13))
+#define RMT_CH4_RX_END_INT_RAW_V 0x1
+#define RMT_CH4_RX_END_INT_RAW_S 13
+/* RMT_CH4_TX_END_INT_RAW : RO ;bitpos:[12] ;default: 1'b0 ; */
+/*description: The interrupt raw bit for channel 4 turns to high level when
+ the transmit process is done.*/
+#define RMT_CH4_TX_END_INT_RAW (BIT(12))
+#define RMT_CH4_TX_END_INT_RAW_M (BIT(12))
+#define RMT_CH4_TX_END_INT_RAW_V 0x1
+#define RMT_CH4_TX_END_INT_RAW_S 12
+/* RMT_CH3_ERR_INT_RAW : RO ;bitpos:[11] ;default: 1'b0 ; */
+/*description: The interrupt raw bit for channel 3 turns to high level when
+ channle 3 detects some errors.*/
+#define RMT_CH3_ERR_INT_RAW (BIT(11))
+#define RMT_CH3_ERR_INT_RAW_M (BIT(11))
+#define RMT_CH3_ERR_INT_RAW_V 0x1
+#define RMT_CH3_ERR_INT_RAW_S 11
+/* RMT_CH3_RX_END_INT_RAW : RO ;bitpos:[10] ;default: 1'b0 ; */
+/*description: The interrupt raw bit for channel 3 turns to high level when
+ the receive process is done.*/
+#define RMT_CH3_RX_END_INT_RAW (BIT(10))
+#define RMT_CH3_RX_END_INT_RAW_M (BIT(10))
+#define RMT_CH3_RX_END_INT_RAW_V 0x1
+#define RMT_CH3_RX_END_INT_RAW_S 10
+/* RMT_CH3_TX_END_INT_RAW : RO ;bitpos:[9] ;default: 1'b0 ; */
+/*description: The interrupt raw bit for channel 3 turns to high level when
+ the transmit process is done.*/
+#define RMT_CH3_TX_END_INT_RAW (BIT(9))
+#define RMT_CH3_TX_END_INT_RAW_M (BIT(9))
+#define RMT_CH3_TX_END_INT_RAW_V 0x1
+#define RMT_CH3_TX_END_INT_RAW_S 9
+/* RMT_CH2_ERR_INT_RAW : RO ;bitpos:[8] ;default: 1'b0 ; */
+/*description: The interrupt raw bit for channel 2 turns to high level when
+ channle 2 detects some errors.*/
+#define RMT_CH2_ERR_INT_RAW (BIT(8))
+#define RMT_CH2_ERR_INT_RAW_M (BIT(8))
+#define RMT_CH2_ERR_INT_RAW_V 0x1
+#define RMT_CH2_ERR_INT_RAW_S 8
+/* RMT_CH2_RX_END_INT_RAW : RO ;bitpos:[7] ;default: 1'b0 ; */
+/*description: The interrupt raw bit for channel 2 turns to high level when
+ the receive process is done.*/
+#define RMT_CH2_RX_END_INT_RAW (BIT(7))
+#define RMT_CH2_RX_END_INT_RAW_M (BIT(7))
+#define RMT_CH2_RX_END_INT_RAW_V 0x1
+#define RMT_CH2_RX_END_INT_RAW_S 7
+/* RMT_CH2_TX_END_INT_RAW : RO ;bitpos:[6] ;default: 1'b0 ; */
+/*description: The interrupt raw bit for channel 2 turns to high level when
+ the transmit process is done.*/
+#define RMT_CH2_TX_END_INT_RAW (BIT(6))
+#define RMT_CH2_TX_END_INT_RAW_M (BIT(6))
+#define RMT_CH2_TX_END_INT_RAW_V 0x1
+#define RMT_CH2_TX_END_INT_RAW_S 6
+/* RMT_CH1_ERR_INT_RAW : RO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: The interrupt raw bit for channel 1 turns to high level when
+ channle 1 detects some errors.*/
+#define RMT_CH1_ERR_INT_RAW (BIT(5))
+#define RMT_CH1_ERR_INT_RAW_M (BIT(5))
+#define RMT_CH1_ERR_INT_RAW_V 0x1
+#define RMT_CH1_ERR_INT_RAW_S 5
+/* RMT_CH1_RX_END_INT_RAW : RO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: The interrupt raw bit for channel 1 turns to high level when
+ the receive process is done.*/
+#define RMT_CH1_RX_END_INT_RAW (BIT(4))
+#define RMT_CH1_RX_END_INT_RAW_M (BIT(4))
+#define RMT_CH1_RX_END_INT_RAW_V 0x1
+#define RMT_CH1_RX_END_INT_RAW_S 4
+/* RMT_CH1_TX_END_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: The interrupt raw bit for channel 1 turns to high level when
+ the transmit process is done.*/
+#define RMT_CH1_TX_END_INT_RAW (BIT(3))
+#define RMT_CH1_TX_END_INT_RAW_M (BIT(3))
+#define RMT_CH1_TX_END_INT_RAW_V 0x1
+#define RMT_CH1_TX_END_INT_RAW_S 3
+/* RMT_CH0_ERR_INT_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */
+/*description: The interrupt raw bit for channel 0 turns to high level when
+ channle 0 detects some errors.*/
+#define RMT_CH0_ERR_INT_RAW (BIT(2))
+#define RMT_CH0_ERR_INT_RAW_M (BIT(2))
+#define RMT_CH0_ERR_INT_RAW_V 0x1
+#define RMT_CH0_ERR_INT_RAW_S 2
+/* RMT_CH0_RX_END_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: The interrupt raw bit for channel 0 turns to high level when
+ the receive process is done.*/
+#define RMT_CH0_RX_END_INT_RAW (BIT(1))
+#define RMT_CH0_RX_END_INT_RAW_M (BIT(1))
+#define RMT_CH0_RX_END_INT_RAW_V 0x1
+#define RMT_CH0_RX_END_INT_RAW_S 1
+/* RMT_CH0_TX_END_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: The interrupt raw bit for channel 0 turns to high level when
+ the transmit process is done.*/
+#define RMT_CH0_TX_END_INT_RAW (BIT(0))
+#define RMT_CH0_TX_END_INT_RAW_M (BIT(0))
+#define RMT_CH0_TX_END_INT_RAW_V 0x1
+#define RMT_CH0_TX_END_INT_RAW_S 0
+
+#define RMT_INT_ST_REG (DR_REG_RMT_BASE + 0x00a4)
+/* RMT_CH7_TX_THR_EVENT_INT_ST : RO ;bitpos:[31] ;default: 1'b0 ; */
+/*description: The interrupt state bit for channel 7's rmt_ch7_tx_thr_event_int_raw
+ when mt_ch7_tx_thr_event_int_ena is set to 1.*/
+#define RMT_CH7_TX_THR_EVENT_INT_ST (BIT(31))
+#define RMT_CH7_TX_THR_EVENT_INT_ST_M (BIT(31))
+#define RMT_CH7_TX_THR_EVENT_INT_ST_V 0x1
+#define RMT_CH7_TX_THR_EVENT_INT_ST_S 31
+/* RMT_CH6_TX_THR_EVENT_INT_ST : RO ;bitpos:[30] ;default: 1'b0 ; */
+/*description: The interrupt state bit for channel 6's rmt_ch6_tx_thr_event_int_raw
+ when mt_ch6_tx_thr_event_int_ena is set to 1.*/
+#define RMT_CH6_TX_THR_EVENT_INT_ST (BIT(30))
+#define RMT_CH6_TX_THR_EVENT_INT_ST_M (BIT(30))
+#define RMT_CH6_TX_THR_EVENT_INT_ST_V 0x1
+#define RMT_CH6_TX_THR_EVENT_INT_ST_S 30
+/* RMT_CH5_TX_THR_EVENT_INT_ST : RO ;bitpos:[29] ;default: 1'b0 ; */
+/*description: The interrupt state bit for channel 5's rmt_ch5_tx_thr_event_int_raw
+ when mt_ch5_tx_thr_event_int_ena is set to 1.*/
+#define RMT_CH5_TX_THR_EVENT_INT_ST (BIT(29))
+#define RMT_CH5_TX_THR_EVENT_INT_ST_M (BIT(29))
+#define RMT_CH5_TX_THR_EVENT_INT_ST_V 0x1
+#define RMT_CH5_TX_THR_EVENT_INT_ST_S 29
+/* RMT_CH4_TX_THR_EVENT_INT_ST : RO ;bitpos:[28] ;default: 1'b0 ; */
+/*description: The interrupt state bit for channel 4's rmt_ch4_tx_thr_event_int_raw
+ when mt_ch4_tx_thr_event_int_ena is set to 1.*/
+#define RMT_CH4_TX_THR_EVENT_INT_ST (BIT(28))
+#define RMT_CH4_TX_THR_EVENT_INT_ST_M (BIT(28))
+#define RMT_CH4_TX_THR_EVENT_INT_ST_V 0x1
+#define RMT_CH4_TX_THR_EVENT_INT_ST_S 28
+/* RMT_CH3_TX_THR_EVENT_INT_ST : RO ;bitpos:[27] ;default: 1'b0 ; */
+/*description: The interrupt state bit for channel 3's rmt_ch3_tx_thr_event_int_raw
+ when mt_ch3_tx_thr_event_int_ena is set to 1.*/
+#define RMT_CH3_TX_THR_EVENT_INT_ST (BIT(27))
+#define RMT_CH3_TX_THR_EVENT_INT_ST_M (BIT(27))
+#define RMT_CH3_TX_THR_EVENT_INT_ST_V 0x1
+#define RMT_CH3_TX_THR_EVENT_INT_ST_S 27
+/* RMT_CH2_TX_THR_EVENT_INT_ST : RO ;bitpos:[26] ;default: 1'b0 ; */
+/*description: The interrupt state bit for channel 2's rmt_ch2_tx_thr_event_int_raw
+ when mt_ch2_tx_thr_event_int_ena is set to 1.*/
+#define RMT_CH2_TX_THR_EVENT_INT_ST (BIT(26))
+#define RMT_CH2_TX_THR_EVENT_INT_ST_M (BIT(26))
+#define RMT_CH2_TX_THR_EVENT_INT_ST_V 0x1
+#define RMT_CH2_TX_THR_EVENT_INT_ST_S 26
+/* RMT_CH1_TX_THR_EVENT_INT_ST : RO ;bitpos:[25] ;default: 1'b0 ; */
+/*description: The interrupt state bit for channel 1's rmt_ch1_tx_thr_event_int_raw
+ when mt_ch1_tx_thr_event_int_ena is set to 1.*/
+#define RMT_CH1_TX_THR_EVENT_INT_ST (BIT(25))
+#define RMT_CH1_TX_THR_EVENT_INT_ST_M (BIT(25))
+#define RMT_CH1_TX_THR_EVENT_INT_ST_V 0x1
+#define RMT_CH1_TX_THR_EVENT_INT_ST_S 25
+/* RMT_CH0_TX_THR_EVENT_INT_ST : RO ;bitpos:[24] ;default: 1'b0 ; */
+/*description: The interrupt state bit for channel 0's rmt_ch0_tx_thr_event_int_raw
+ when mt_ch0_tx_thr_event_int_ena is set to 1.*/
+#define RMT_CH0_TX_THR_EVENT_INT_ST (BIT(24))
+#define RMT_CH0_TX_THR_EVENT_INT_ST_M (BIT(24))
+#define RMT_CH0_TX_THR_EVENT_INT_ST_V 0x1
+#define RMT_CH0_TX_THR_EVENT_INT_ST_S 24
+/* RMT_CH7_ERR_INT_ST : RO ;bitpos:[23] ;default: 1'b0 ; */
+/*description: The interrupt state bit for channel 7's rmt_ch7_err_int_raw
+ when rmt_ch7_err_int_ena is set to 1.*/
+#define RMT_CH7_ERR_INT_ST (BIT(23))
+#define RMT_CH7_ERR_INT_ST_M (BIT(23))
+#define RMT_CH7_ERR_INT_ST_V 0x1
+#define RMT_CH7_ERR_INT_ST_S 23
+/* RMT_CH7_RX_END_INT_ST : RO ;bitpos:[22] ;default: 1'b0 ; */
+/*description: The interrupt state bit for channel 7's rmt_ch7_rx_end_int_raw
+ when rmt_ch7_rx_end_int_ena is set to 1.*/
+#define RMT_CH7_RX_END_INT_ST (BIT(22))
+#define RMT_CH7_RX_END_INT_ST_M (BIT(22))
+#define RMT_CH7_RX_END_INT_ST_V 0x1
+#define RMT_CH7_RX_END_INT_ST_S 22
+/* RMT_CH7_TX_END_INT_ST : RO ;bitpos:[21] ;default: 1'b0 ; */
+/*description: The interrupt state bit for channel 7's mt_ch7_tx_end_int_raw
+ when mt_ch7_tx_end_int_ena is set to 1.*/
+#define RMT_CH7_TX_END_INT_ST (BIT(21))
+#define RMT_CH7_TX_END_INT_ST_M (BIT(21))
+#define RMT_CH7_TX_END_INT_ST_V 0x1
+#define RMT_CH7_TX_END_INT_ST_S 21
+/* RMT_CH6_ERR_INT_ST : RO ;bitpos:[20] ;default: 1'b0 ; */
+/*description: The interrupt state bit for channel 6's rmt_ch6_err_int_raw
+ when rmt_ch6_err_int_ena is set to 1.*/
+#define RMT_CH6_ERR_INT_ST (BIT(20))
+#define RMT_CH6_ERR_INT_ST_M (BIT(20))
+#define RMT_CH6_ERR_INT_ST_V 0x1
+#define RMT_CH6_ERR_INT_ST_S 20
+/* RMT_CH6_RX_END_INT_ST : RO ;bitpos:[19] ;default: 1'b0 ; */
+/*description: The interrupt state bit for channel 6's rmt_ch6_rx_end_int_raw
+ when rmt_ch6_rx_end_int_ena is set to 1.*/
+#define RMT_CH6_RX_END_INT_ST (BIT(19))
+#define RMT_CH6_RX_END_INT_ST_M (BIT(19))
+#define RMT_CH6_RX_END_INT_ST_V 0x1
+#define RMT_CH6_RX_END_INT_ST_S 19
+/* RMT_CH6_TX_END_INT_ST : RO ;bitpos:[18] ;default: 1'b0 ; */
+/*description: The interrupt state bit for channel 6's mt_ch6_tx_end_int_raw
+ when mt_ch6_tx_end_int_ena is set to 1.*/
+#define RMT_CH6_TX_END_INT_ST (BIT(18))
+#define RMT_CH6_TX_END_INT_ST_M (BIT(18))
+#define RMT_CH6_TX_END_INT_ST_V 0x1
+#define RMT_CH6_TX_END_INT_ST_S 18
+/* RMT_CH5_ERR_INT_ST : RO ;bitpos:[17] ;default: 1'b0 ; */
+/*description: The interrupt state bit for channel 5's rmt_ch5_err_int_raw
+ when rmt_ch5_err_int_ena is set to 1.*/
+#define RMT_CH5_ERR_INT_ST (BIT(17))
+#define RMT_CH5_ERR_INT_ST_M (BIT(17))
+#define RMT_CH5_ERR_INT_ST_V 0x1
+#define RMT_CH5_ERR_INT_ST_S 17
+/* RMT_CH5_RX_END_INT_ST : RO ;bitpos:[16] ;default: 1'b0 ; */
+/*description: The interrupt state bit for channel 5's rmt_ch5_rx_end_int_raw
+ when rmt_ch5_rx_end_int_ena is set to 1.*/
+#define RMT_CH5_RX_END_INT_ST (BIT(16))
+#define RMT_CH5_RX_END_INT_ST_M (BIT(16))
+#define RMT_CH5_RX_END_INT_ST_V 0x1
+#define RMT_CH5_RX_END_INT_ST_S 16
+/* RMT_CH5_TX_END_INT_ST : RO ;bitpos:[15] ;default: 1'b0 ; */
+/*description: The interrupt state bit for channel 5's mt_ch5_tx_end_int_raw
+ when mt_ch5_tx_end_int_ena is set to 1.*/
+#define RMT_CH5_TX_END_INT_ST (BIT(15))
+#define RMT_CH5_TX_END_INT_ST_M (BIT(15))
+#define RMT_CH5_TX_END_INT_ST_V 0x1
+#define RMT_CH5_TX_END_INT_ST_S 15
+/* RMT_CH4_ERR_INT_ST : RO ;bitpos:[14] ;default: 1'b0 ; */
+/*description: The interrupt state bit for channel 4's rmt_ch4_err_int_raw
+ when rmt_ch4_err_int_ena is set to 1.*/
+#define RMT_CH4_ERR_INT_ST (BIT(14))
+#define RMT_CH4_ERR_INT_ST_M (BIT(14))
+#define RMT_CH4_ERR_INT_ST_V 0x1
+#define RMT_CH4_ERR_INT_ST_S 14
+/* RMT_CH4_RX_END_INT_ST : RO ;bitpos:[13] ;default: 1'b0 ; */
+/*description: The interrupt state bit for channel 4's rmt_ch4_rx_end_int_raw
+ when rmt_ch4_rx_end_int_ena is set to 1.*/
+#define RMT_CH4_RX_END_INT_ST (BIT(13))
+#define RMT_CH4_RX_END_INT_ST_M (BIT(13))
+#define RMT_CH4_RX_END_INT_ST_V 0x1
+#define RMT_CH4_RX_END_INT_ST_S 13
+/* RMT_CH4_TX_END_INT_ST : RO ;bitpos:[12] ;default: 1'b0 ; */
+/*description: The interrupt state bit for channel 4's mt_ch4_tx_end_int_raw
+ when mt_ch4_tx_end_int_ena is set to 1.*/
+#define RMT_CH4_TX_END_INT_ST (BIT(12))
+#define RMT_CH4_TX_END_INT_ST_M (BIT(12))
+#define RMT_CH4_TX_END_INT_ST_V 0x1
+#define RMT_CH4_TX_END_INT_ST_S 12
+/* RMT_CH3_ERR_INT_ST : RO ;bitpos:[11] ;default: 1'b0 ; */
+/*description: The interrupt state bit for channel 3's rmt_ch3_err_int_raw
+ when rmt_ch3_err_int_ena is set to 1.*/
+#define RMT_CH3_ERR_INT_ST (BIT(11))
+#define RMT_CH3_ERR_INT_ST_M (BIT(11))
+#define RMT_CH3_ERR_INT_ST_V 0x1
+#define RMT_CH3_ERR_INT_ST_S 11
+/* RMT_CH3_RX_END_INT_ST : RO ;bitpos:[10] ;default: 1'b0 ; */
+/*description: The interrupt state bit for channel 3's rmt_ch3_rx_end_int_raw
+ when rmt_ch3_rx_end_int_ena is set to 1.*/
+#define RMT_CH3_RX_END_INT_ST (BIT(10))
+#define RMT_CH3_RX_END_INT_ST_M (BIT(10))
+#define RMT_CH3_RX_END_INT_ST_V 0x1
+#define RMT_CH3_RX_END_INT_ST_S 10
+/* RMT_CH3_TX_END_INT_ST : RO ;bitpos:[9] ;default: 1'b0 ; */
+/*description: The interrupt state bit for channel 3's mt_ch3_tx_end_int_raw
+ when mt_ch3_tx_end_int_ena is set to 1.*/
+#define RMT_CH3_TX_END_INT_ST (BIT(9))
+#define RMT_CH3_TX_END_INT_ST_M (BIT(9))
+#define RMT_CH3_TX_END_INT_ST_V 0x1
+#define RMT_CH3_TX_END_INT_ST_S 9
+/* RMT_CH2_ERR_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */
+/*description: The interrupt state bit for channel 2's rmt_ch2_err_int_raw
+ when rmt_ch2_err_int_ena is set to 1.*/
+#define RMT_CH2_ERR_INT_ST (BIT(8))
+#define RMT_CH2_ERR_INT_ST_M (BIT(8))
+#define RMT_CH2_ERR_INT_ST_V 0x1
+#define RMT_CH2_ERR_INT_ST_S 8
+/* RMT_CH2_RX_END_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */
+/*description: The interrupt state bit for channel 2's rmt_ch2_rx_end_int_raw
+ when rmt_ch2_rx_end_int_ena is set to 1.*/
+#define RMT_CH2_RX_END_INT_ST (BIT(7))
+#define RMT_CH2_RX_END_INT_ST_M (BIT(7))
+#define RMT_CH2_RX_END_INT_ST_V 0x1
+#define RMT_CH2_RX_END_INT_ST_S 7
+/* RMT_CH2_TX_END_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */
+/*description: The interrupt state bit for channel 2's mt_ch2_tx_end_int_raw
+ when mt_ch2_tx_end_int_ena is set to 1.*/
+#define RMT_CH2_TX_END_INT_ST (BIT(6))
+#define RMT_CH2_TX_END_INT_ST_M (BIT(6))
+#define RMT_CH2_TX_END_INT_ST_V 0x1
+#define RMT_CH2_TX_END_INT_ST_S 6
+/* RMT_CH1_ERR_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: The interrupt state bit for channel 1's rmt_ch1_err_int_raw
+ when rmt_ch1_err_int_ena is set to 1.*/
+#define RMT_CH1_ERR_INT_ST (BIT(5))
+#define RMT_CH1_ERR_INT_ST_M (BIT(5))
+#define RMT_CH1_ERR_INT_ST_V 0x1
+#define RMT_CH1_ERR_INT_ST_S 5
+/* RMT_CH1_RX_END_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: The interrupt state bit for channel 1's rmt_ch1_rx_end_int_raw
+ when rmt_ch1_rx_end_int_ena is set to 1.*/
+#define RMT_CH1_RX_END_INT_ST (BIT(4))
+#define RMT_CH1_RX_END_INT_ST_M (BIT(4))
+#define RMT_CH1_RX_END_INT_ST_V 0x1
+#define RMT_CH1_RX_END_INT_ST_S 4
+/* RMT_CH1_TX_END_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: The interrupt state bit for channel 1's mt_ch1_tx_end_int_raw
+ when mt_ch1_tx_end_int_ena is set to 1.*/
+#define RMT_CH1_TX_END_INT_ST (BIT(3))
+#define RMT_CH1_TX_END_INT_ST_M (BIT(3))
+#define RMT_CH1_TX_END_INT_ST_V 0x1
+#define RMT_CH1_TX_END_INT_ST_S 3
+/* RMT_CH0_ERR_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */
+/*description: The interrupt state bit for channel 0's rmt_ch0_err_int_raw
+ when rmt_ch0_err_int_ena is set to 0.*/
+#define RMT_CH0_ERR_INT_ST (BIT(2))
+#define RMT_CH0_ERR_INT_ST_M (BIT(2))
+#define RMT_CH0_ERR_INT_ST_V 0x1
+#define RMT_CH0_ERR_INT_ST_S 2
+/* RMT_CH0_RX_END_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: The interrupt state bit for channel 0's rmt_ch0_rx_end_int_raw
+ when rmt_ch0_rx_end_int_ena is set to 0.*/
+#define RMT_CH0_RX_END_INT_ST (BIT(1))
+#define RMT_CH0_RX_END_INT_ST_M (BIT(1))
+#define RMT_CH0_RX_END_INT_ST_V 0x1
+#define RMT_CH0_RX_END_INT_ST_S 1
+/* RMT_CH0_TX_END_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: The interrupt state bit for channel 0's mt_ch0_tx_end_int_raw
+ when mt_ch0_tx_end_int_ena is set to 0.*/
+#define RMT_CH0_TX_END_INT_ST (BIT(0))
+#define RMT_CH0_TX_END_INT_ST_M (BIT(0))
+#define RMT_CH0_TX_END_INT_ST_V 0x1
+#define RMT_CH0_TX_END_INT_ST_S 0
+
+#define RMT_INT_ENA_REG (DR_REG_RMT_BASE + 0x00a8)
+/* RMT_CH7_TX_THR_EVENT_INT_ENA : R/W ;bitpos:[31] ;default: 1'b0 ; */
+/*description: Set this bit to enable rmt_ch7_tx_thr_event_int_st.*/
+#define RMT_CH7_TX_THR_EVENT_INT_ENA (BIT(31))
+#define RMT_CH7_TX_THR_EVENT_INT_ENA_M (BIT(31))
+#define RMT_CH7_TX_THR_EVENT_INT_ENA_V 0x1
+#define RMT_CH7_TX_THR_EVENT_INT_ENA_S 31
+/* RMT_CH6_TX_THR_EVENT_INT_ENA : R/W ;bitpos:[30] ;default: 1'b0 ; */
+/*description: Set this bit to enable rmt_ch6_tx_thr_event_int_st.*/
+#define RMT_CH6_TX_THR_EVENT_INT_ENA (BIT(30))
+#define RMT_CH6_TX_THR_EVENT_INT_ENA_M (BIT(30))
+#define RMT_CH6_TX_THR_EVENT_INT_ENA_V 0x1
+#define RMT_CH6_TX_THR_EVENT_INT_ENA_S 30
+/* RMT_CH5_TX_THR_EVENT_INT_ENA : R/W ;bitpos:[29] ;default: 1'b0 ; */
+/*description: Set this bit to enable rmt_ch5_tx_thr_event_int_st.*/
+#define RMT_CH5_TX_THR_EVENT_INT_ENA (BIT(29))
+#define RMT_CH5_TX_THR_EVENT_INT_ENA_M (BIT(29))
+#define RMT_CH5_TX_THR_EVENT_INT_ENA_V 0x1
+#define RMT_CH5_TX_THR_EVENT_INT_ENA_S 29
+/* RMT_CH4_TX_THR_EVENT_INT_ENA : R/W ;bitpos:[28] ;default: 1'b0 ; */
+/*description: Set this bit to enable rmt_ch4_tx_thr_event_int_st.*/
+#define RMT_CH4_TX_THR_EVENT_INT_ENA (BIT(28))
+#define RMT_CH4_TX_THR_EVENT_INT_ENA_M (BIT(28))
+#define RMT_CH4_TX_THR_EVENT_INT_ENA_V 0x1
+#define RMT_CH4_TX_THR_EVENT_INT_ENA_S 28
+/* RMT_CH3_TX_THR_EVENT_INT_ENA : R/W ;bitpos:[27] ;default: 1'b0 ; */
+/*description: Set this bit to enable rmt_ch3_tx_thr_event_int_st.*/
+#define RMT_CH3_TX_THR_EVENT_INT_ENA (BIT(27))
+#define RMT_CH3_TX_THR_EVENT_INT_ENA_M (BIT(27))
+#define RMT_CH3_TX_THR_EVENT_INT_ENA_V 0x1
+#define RMT_CH3_TX_THR_EVENT_INT_ENA_S 27
+/* RMT_CH2_TX_THR_EVENT_INT_ENA : R/W ;bitpos:[26] ;default: 1'b0 ; */
+/*description: Set this bit to enable rmt_ch2_tx_thr_event_int_st.*/
+#define RMT_CH2_TX_THR_EVENT_INT_ENA (BIT(26))
+#define RMT_CH2_TX_THR_EVENT_INT_ENA_M (BIT(26))
+#define RMT_CH2_TX_THR_EVENT_INT_ENA_V 0x1
+#define RMT_CH2_TX_THR_EVENT_INT_ENA_S 26
+/* RMT_CH1_TX_THR_EVENT_INT_ENA : R/W ;bitpos:[25] ;default: 1'b0 ; */
+/*description: Set this bit to enable rmt_ch1_tx_thr_event_int_st.*/
+#define RMT_CH1_TX_THR_EVENT_INT_ENA (BIT(25))
+#define RMT_CH1_TX_THR_EVENT_INT_ENA_M (BIT(25))
+#define RMT_CH1_TX_THR_EVENT_INT_ENA_V 0x1
+#define RMT_CH1_TX_THR_EVENT_INT_ENA_S 25
+/* RMT_CH0_TX_THR_EVENT_INT_ENA : R/W ;bitpos:[24] ;default: 1'b0 ; */
+/*description: Set this bit to enable rmt_ch0_tx_thr_event_int_st.*/
+#define RMT_CH0_TX_THR_EVENT_INT_ENA (BIT(24))
+#define RMT_CH0_TX_THR_EVENT_INT_ENA_M (BIT(24))
+#define RMT_CH0_TX_THR_EVENT_INT_ENA_V 0x1
+#define RMT_CH0_TX_THR_EVENT_INT_ENA_S 24
+/* RMT_CH7_ERR_INT_ENA : R/W ;bitpos:[23] ;default: 1'b0 ; */
+/*description: Set this bit to enable rmt_ch7_err_int_st.*/
+#define RMT_CH7_ERR_INT_ENA (BIT(23))
+#define RMT_CH7_ERR_INT_ENA_M (BIT(23))
+#define RMT_CH7_ERR_INT_ENA_V 0x1
+#define RMT_CH7_ERR_INT_ENA_S 23
+/* RMT_CH7_RX_END_INT_ENA : R/W ;bitpos:[22] ;default: 1'b0 ; */
+/*description: Set this bit to enable rmt_ch7_rx_end_int_st.*/
+#define RMT_CH7_RX_END_INT_ENA (BIT(22))
+#define RMT_CH7_RX_END_INT_ENA_M (BIT(22))
+#define RMT_CH7_RX_END_INT_ENA_V 0x1
+#define RMT_CH7_RX_END_INT_ENA_S 22
+/* RMT_CH7_TX_END_INT_ENA : R/W ;bitpos:[21] ;default: 1'b0 ; */
+/*description: Set this bit to enable rmt_ch7_tx_end_int_st.*/
+#define RMT_CH7_TX_END_INT_ENA (BIT(21))
+#define RMT_CH7_TX_END_INT_ENA_M (BIT(21))
+#define RMT_CH7_TX_END_INT_ENA_V 0x1
+#define RMT_CH7_TX_END_INT_ENA_S 21
+/* RMT_CH6_ERR_INT_ENA : R/W ;bitpos:[20] ;default: 1'b0 ; */
+/*description: Set this bit to enable rmt_ch6_err_int_st.*/
+#define RMT_CH6_ERR_INT_ENA (BIT(20))
+#define RMT_CH6_ERR_INT_ENA_M (BIT(20))
+#define RMT_CH6_ERR_INT_ENA_V 0x1
+#define RMT_CH6_ERR_INT_ENA_S 20
+/* RMT_CH6_RX_END_INT_ENA : R/W ;bitpos:[19] ;default: 1'b0 ; */
+/*description: Set this bit to enable rmt_ch6_rx_end_int_st.*/
+#define RMT_CH6_RX_END_INT_ENA (BIT(19))
+#define RMT_CH6_RX_END_INT_ENA_M (BIT(19))
+#define RMT_CH6_RX_END_INT_ENA_V 0x1
+#define RMT_CH6_RX_END_INT_ENA_S 19
+/* RMT_CH6_TX_END_INT_ENA : R/W ;bitpos:[18] ;default: 1'b0 ; */
+/*description: Set this bit to enable rmt_ch6_tx_end_int_st.*/
+#define RMT_CH6_TX_END_INT_ENA (BIT(18))
+#define RMT_CH6_TX_END_INT_ENA_M (BIT(18))
+#define RMT_CH6_TX_END_INT_ENA_V 0x1
+#define RMT_CH6_TX_END_INT_ENA_S 18
+/* RMT_CH5_ERR_INT_ENA : R/W ;bitpos:[17] ;default: 1'b0 ; */
+/*description: Set this bit to enable rmt_ch5_err_int_st.*/
+#define RMT_CH5_ERR_INT_ENA (BIT(17))
+#define RMT_CH5_ERR_INT_ENA_M (BIT(17))
+#define RMT_CH5_ERR_INT_ENA_V 0x1
+#define RMT_CH5_ERR_INT_ENA_S 17
+/* RMT_CH5_RX_END_INT_ENA : R/W ;bitpos:[16] ;default: 1'b0 ; */
+/*description: Set this bit to enable rmt_ch5_rx_end_int_st.*/
+#define RMT_CH5_RX_END_INT_ENA (BIT(16))
+#define RMT_CH5_RX_END_INT_ENA_M (BIT(16))
+#define RMT_CH5_RX_END_INT_ENA_V 0x1
+#define RMT_CH5_RX_END_INT_ENA_S 16
+/* RMT_CH5_TX_END_INT_ENA : R/W ;bitpos:[15] ;default: 1'b0 ; */
+/*description: Set this bit to enable rmt_ch5_tx_end_int_st.*/
+#define RMT_CH5_TX_END_INT_ENA (BIT(15))
+#define RMT_CH5_TX_END_INT_ENA_M (BIT(15))
+#define RMT_CH5_TX_END_INT_ENA_V 0x1
+#define RMT_CH5_TX_END_INT_ENA_S 15
+/* RMT_CH4_ERR_INT_ENA : R/W ;bitpos:[14] ;default: 1'b0 ; */
+/*description: Set this bit to enable rmt_ch4_err_int_st.*/
+#define RMT_CH4_ERR_INT_ENA (BIT(14))
+#define RMT_CH4_ERR_INT_ENA_M (BIT(14))
+#define RMT_CH4_ERR_INT_ENA_V 0x1
+#define RMT_CH4_ERR_INT_ENA_S 14
+/* RMT_CH4_RX_END_INT_ENA : R/W ;bitpos:[13] ;default: 1'b0 ; */
+/*description: Set this bit to enable rmt_ch4_rx_end_int_st.*/
+#define RMT_CH4_RX_END_INT_ENA (BIT(13))
+#define RMT_CH4_RX_END_INT_ENA_M (BIT(13))
+#define RMT_CH4_RX_END_INT_ENA_V 0x1
+#define RMT_CH4_RX_END_INT_ENA_S 13
+/* RMT_CH4_TX_END_INT_ENA : R/W ;bitpos:[12] ;default: 1'b0 ; */
+/*description: Set this bit to enable rmt_ch4_tx_end_int_st.*/
+#define RMT_CH4_TX_END_INT_ENA (BIT(12))
+#define RMT_CH4_TX_END_INT_ENA_M (BIT(12))
+#define RMT_CH4_TX_END_INT_ENA_V 0x1
+#define RMT_CH4_TX_END_INT_ENA_S 12
+/* RMT_CH3_ERR_INT_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */
+/*description: Set this bit to enable rmt_ch3_err_int_st.*/
+#define RMT_CH3_ERR_INT_ENA (BIT(11))
+#define RMT_CH3_ERR_INT_ENA_M (BIT(11))
+#define RMT_CH3_ERR_INT_ENA_V 0x1
+#define RMT_CH3_ERR_INT_ENA_S 11
+/* RMT_CH3_RX_END_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */
+/*description: Set this bit to enable rmt_ch3_rx_end_int_st.*/
+#define RMT_CH3_RX_END_INT_ENA (BIT(10))
+#define RMT_CH3_RX_END_INT_ENA_M (BIT(10))
+#define RMT_CH3_RX_END_INT_ENA_V 0x1
+#define RMT_CH3_RX_END_INT_ENA_S 10
+/* RMT_CH3_TX_END_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */
+/*description: Set this bit to enable rmt_ch3_tx_end_int_st.*/
+#define RMT_CH3_TX_END_INT_ENA (BIT(9))
+#define RMT_CH3_TX_END_INT_ENA_M (BIT(9))
+#define RMT_CH3_TX_END_INT_ENA_V 0x1
+#define RMT_CH3_TX_END_INT_ENA_S 9
+/* RMT_CH2_ERR_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */
+/*description: Set this bit to enable rmt_ch2_err_int_st.*/
+#define RMT_CH2_ERR_INT_ENA (BIT(8))
+#define RMT_CH2_ERR_INT_ENA_M (BIT(8))
+#define RMT_CH2_ERR_INT_ENA_V 0x1
+#define RMT_CH2_ERR_INT_ENA_S 8
+/* RMT_CH2_RX_END_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: Set this bit to enable rmt_ch2_rx_end_int_st.*/
+#define RMT_CH2_RX_END_INT_ENA (BIT(7))
+#define RMT_CH2_RX_END_INT_ENA_M (BIT(7))
+#define RMT_CH2_RX_END_INT_ENA_V 0x1
+#define RMT_CH2_RX_END_INT_ENA_S 7
+/* RMT_CH2_TX_END_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: Set this bit to enable rmt_ch2_tx_end_int_st.*/
+#define RMT_CH2_TX_END_INT_ENA (BIT(6))
+#define RMT_CH2_TX_END_INT_ENA_M (BIT(6))
+#define RMT_CH2_TX_END_INT_ENA_V 0x1
+#define RMT_CH2_TX_END_INT_ENA_S 6
+/* RMT_CH1_ERR_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: Set this bit to enable rmt_ch1_err_int_st.*/
+#define RMT_CH1_ERR_INT_ENA (BIT(5))
+#define RMT_CH1_ERR_INT_ENA_M (BIT(5))
+#define RMT_CH1_ERR_INT_ENA_V 0x1
+#define RMT_CH1_ERR_INT_ENA_S 5
+/* RMT_CH1_RX_END_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: Set this bit to enable rmt_ch1_rx_end_int_st.*/
+#define RMT_CH1_RX_END_INT_ENA (BIT(4))
+#define RMT_CH1_RX_END_INT_ENA_M (BIT(4))
+#define RMT_CH1_RX_END_INT_ENA_V 0x1
+#define RMT_CH1_RX_END_INT_ENA_S 4
+/* RMT_CH1_TX_END_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: Set this bit to enable rmt_ch1_tx_end_int_st.*/
+#define RMT_CH1_TX_END_INT_ENA (BIT(3))
+#define RMT_CH1_TX_END_INT_ENA_M (BIT(3))
+#define RMT_CH1_TX_END_INT_ENA_V 0x1
+#define RMT_CH1_TX_END_INT_ENA_S 3
+/* RMT_CH0_ERR_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: Set this bit to enable rmt_ch0_err_int_st.*/
+#define RMT_CH0_ERR_INT_ENA (BIT(2))
+#define RMT_CH0_ERR_INT_ENA_M (BIT(2))
+#define RMT_CH0_ERR_INT_ENA_V 0x1
+#define RMT_CH0_ERR_INT_ENA_S 2
+/* RMT_CH0_RX_END_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: Set this bit to enable rmt_ch0_rx_end_int_st.*/
+#define RMT_CH0_RX_END_INT_ENA (BIT(1))
+#define RMT_CH0_RX_END_INT_ENA_M (BIT(1))
+#define RMT_CH0_RX_END_INT_ENA_V 0x1
+#define RMT_CH0_RX_END_INT_ENA_S 1
+/* RMT_CH0_TX_END_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: Set this bit to enable rmt_ch0_tx_end_int_st.*/
+#define RMT_CH0_TX_END_INT_ENA (BIT(0))
+#define RMT_CH0_TX_END_INT_ENA_M (BIT(0))
+#define RMT_CH0_TX_END_INT_ENA_V 0x1
+#define RMT_CH0_TX_END_INT_ENA_S 0
+
+#define RMT_INT_CLR_REG (DR_REG_RMT_BASE + 0x00ac)
+/* RMT_CH7_TX_THR_EVENT_INT_CLR : WO ;bitpos:[31] ;default: 1'b0 ; */
+/*description: Set this bit to clear the rmt_ch7_tx_thr_event_int_raw interrupt.*/
+#define RMT_CH7_TX_THR_EVENT_INT_CLR (BIT(31))
+#define RMT_CH7_TX_THR_EVENT_INT_CLR_M (BIT(31))
+#define RMT_CH7_TX_THR_EVENT_INT_CLR_V 0x1
+#define RMT_CH7_TX_THR_EVENT_INT_CLR_S 31
+/* RMT_CH6_TX_THR_EVENT_INT_CLR : WO ;bitpos:[30] ;default: 1'b0 ; */
+/*description: Set this bit to clear the rmt_ch6_tx_thr_event_int_raw interrupt.*/
+#define RMT_CH6_TX_THR_EVENT_INT_CLR (BIT(30))
+#define RMT_CH6_TX_THR_EVENT_INT_CLR_M (BIT(30))
+#define RMT_CH6_TX_THR_EVENT_INT_CLR_V 0x1
+#define RMT_CH6_TX_THR_EVENT_INT_CLR_S 30
+/* RMT_CH5_TX_THR_EVENT_INT_CLR : WO ;bitpos:[29] ;default: 1'b0 ; */
+/*description: Set this bit to clear the rmt_ch5_tx_thr_event_int_raw interrupt.*/
+#define RMT_CH5_TX_THR_EVENT_INT_CLR (BIT(29))
+#define RMT_CH5_TX_THR_EVENT_INT_CLR_M (BIT(29))
+#define RMT_CH5_TX_THR_EVENT_INT_CLR_V 0x1
+#define RMT_CH5_TX_THR_EVENT_INT_CLR_S 29
+/* RMT_CH4_TX_THR_EVENT_INT_CLR : WO ;bitpos:[28] ;default: 1'b0 ; */
+/*description: Set this bit to clear the rmt_ch4_tx_thr_event_int_raw interrupt.*/
+#define RMT_CH4_TX_THR_EVENT_INT_CLR (BIT(28))
+#define RMT_CH4_TX_THR_EVENT_INT_CLR_M (BIT(28))
+#define RMT_CH4_TX_THR_EVENT_INT_CLR_V 0x1
+#define RMT_CH4_TX_THR_EVENT_INT_CLR_S 28
+/* RMT_CH3_TX_THR_EVENT_INT_CLR : WO ;bitpos:[27] ;default: 1'b0 ; */
+/*description: Set this bit to clear the rmt_ch3_tx_thr_event_int_raw interrupt.*/
+#define RMT_CH3_TX_THR_EVENT_INT_CLR (BIT(27))
+#define RMT_CH3_TX_THR_EVENT_INT_CLR_M (BIT(27))
+#define RMT_CH3_TX_THR_EVENT_INT_CLR_V 0x1
+#define RMT_CH3_TX_THR_EVENT_INT_CLR_S 27
+/* RMT_CH2_TX_THR_EVENT_INT_CLR : WO ;bitpos:[26] ;default: 1'b0 ; */
+/*description: Set this bit to clear the rmt_ch2_tx_thr_event_int_raw interrupt.*/
+#define RMT_CH2_TX_THR_EVENT_INT_CLR (BIT(26))
+#define RMT_CH2_TX_THR_EVENT_INT_CLR_M (BIT(26))
+#define RMT_CH2_TX_THR_EVENT_INT_CLR_V 0x1
+#define RMT_CH2_TX_THR_EVENT_INT_CLR_S 26
+/* RMT_CH1_TX_THR_EVENT_INT_CLR : WO ;bitpos:[25] ;default: 1'b0 ; */
+/*description: Set this bit to clear the rmt_ch1_tx_thr_event_int_raw interrupt.*/
+#define RMT_CH1_TX_THR_EVENT_INT_CLR (BIT(25))
+#define RMT_CH1_TX_THR_EVENT_INT_CLR_M (BIT(25))
+#define RMT_CH1_TX_THR_EVENT_INT_CLR_V 0x1
+#define RMT_CH1_TX_THR_EVENT_INT_CLR_S 25
+/* RMT_CH0_TX_THR_EVENT_INT_CLR : WO ;bitpos:[24] ;default: 1'b0 ; */
+/*description: Set this bit to clear the rmt_ch0_tx_thr_event_int_raw interrupt.*/
+#define RMT_CH0_TX_THR_EVENT_INT_CLR (BIT(24))
+#define RMT_CH0_TX_THR_EVENT_INT_CLR_M (BIT(24))
+#define RMT_CH0_TX_THR_EVENT_INT_CLR_V 0x1
+#define RMT_CH0_TX_THR_EVENT_INT_CLR_S 24
+/* RMT_CH7_ERR_INT_CLR : WO ;bitpos:[23] ;default: 1'b0 ; */
+/*description: Set this bit to clear the rmt_ch7_err_int_raw.*/
+#define RMT_CH7_ERR_INT_CLR (BIT(23))
+#define RMT_CH7_ERR_INT_CLR_M (BIT(23))
+#define RMT_CH7_ERR_INT_CLR_V 0x1
+#define RMT_CH7_ERR_INT_CLR_S 23
+/* RMT_CH7_RX_END_INT_CLR : WO ;bitpos:[22] ;default: 1'b0 ; */
+/*description: Set this bit to clear the rmt_ch7_tx_end_int_raw.*/
+#define RMT_CH7_RX_END_INT_CLR (BIT(22))
+#define RMT_CH7_RX_END_INT_CLR_M (BIT(22))
+#define RMT_CH7_RX_END_INT_CLR_V 0x1
+#define RMT_CH7_RX_END_INT_CLR_S 22
+/* RMT_CH7_TX_END_INT_CLR : WO ;bitpos:[21] ;default: 1'b0 ; */
+/*description: Set this bit to clear the rmt_ch7_rx_end_int_raw..*/
+#define RMT_CH7_TX_END_INT_CLR (BIT(21))
+#define RMT_CH7_TX_END_INT_CLR_M (BIT(21))
+#define RMT_CH7_TX_END_INT_CLR_V 0x1
+#define RMT_CH7_TX_END_INT_CLR_S 21
+/* RMT_CH6_ERR_INT_CLR : WO ;bitpos:[20] ;default: 1'b0 ; */
+/*description: Set this bit to clear the rmt_ch6_err_int_raw.*/
+#define RMT_CH6_ERR_INT_CLR (BIT(20))
+#define RMT_CH6_ERR_INT_CLR_M (BIT(20))
+#define RMT_CH6_ERR_INT_CLR_V 0x1
+#define RMT_CH6_ERR_INT_CLR_S 20
+/* RMT_CH6_RX_END_INT_CLR : WO ;bitpos:[19] ;default: 1'b0 ; */
+/*description: Set this bit to clear the rmt_ch6_tx_end_int_raw.*/
+#define RMT_CH6_RX_END_INT_CLR (BIT(19))
+#define RMT_CH6_RX_END_INT_CLR_M (BIT(19))
+#define RMT_CH6_RX_END_INT_CLR_V 0x1
+#define RMT_CH6_RX_END_INT_CLR_S 19
+/* RMT_CH6_TX_END_INT_CLR : WO ;bitpos:[18] ;default: 1'b0 ; */
+/*description: Set this bit to clear the rmt_ch6_rx_end_int_raw..*/
+#define RMT_CH6_TX_END_INT_CLR (BIT(18))
+#define RMT_CH6_TX_END_INT_CLR_M (BIT(18))
+#define RMT_CH6_TX_END_INT_CLR_V 0x1
+#define RMT_CH6_TX_END_INT_CLR_S 18
+/* RMT_CH5_ERR_INT_CLR : WO ;bitpos:[17] ;default: 1'b0 ; */
+/*description: Set this bit to clear the rmt_ch5_err_int_raw.*/
+#define RMT_CH5_ERR_INT_CLR (BIT(17))
+#define RMT_CH5_ERR_INT_CLR_M (BIT(17))
+#define RMT_CH5_ERR_INT_CLR_V 0x1
+#define RMT_CH5_ERR_INT_CLR_S 17
+/* RMT_CH5_RX_END_INT_CLR : WO ;bitpos:[16] ;default: 1'b0 ; */
+/*description: Set this bit to clear the rmt_ch5_tx_end_int_raw.*/
+#define RMT_CH5_RX_END_INT_CLR (BIT(16))
+#define RMT_CH5_RX_END_INT_CLR_M (BIT(16))
+#define RMT_CH5_RX_END_INT_CLR_V 0x1
+#define RMT_CH5_RX_END_INT_CLR_S 16
+/* RMT_CH5_TX_END_INT_CLR : WO ;bitpos:[15] ;default: 1'b0 ; */
+/*description: Set this bit to clear the rmt_ch5_rx_end_int_raw..*/
+#define RMT_CH5_TX_END_INT_CLR (BIT(15))
+#define RMT_CH5_TX_END_INT_CLR_M (BIT(15))
+#define RMT_CH5_TX_END_INT_CLR_V 0x1
+#define RMT_CH5_TX_END_INT_CLR_S 15
+/* RMT_CH4_ERR_INT_CLR : WO ;bitpos:[14] ;default: 1'b0 ; */
+/*description: Set this bit to clear the rmt_ch4_err_int_raw.*/
+#define RMT_CH4_ERR_INT_CLR (BIT(14))
+#define RMT_CH4_ERR_INT_CLR_M (BIT(14))
+#define RMT_CH4_ERR_INT_CLR_V 0x1
+#define RMT_CH4_ERR_INT_CLR_S 14
+/* RMT_CH4_RX_END_INT_CLR : WO ;bitpos:[13] ;default: 1'b0 ; */
+/*description: Set this bit to clear the rmt_ch4_tx_end_int_raw.*/
+#define RMT_CH4_RX_END_INT_CLR (BIT(13))
+#define RMT_CH4_RX_END_INT_CLR_M (BIT(13))
+#define RMT_CH4_RX_END_INT_CLR_V 0x1
+#define RMT_CH4_RX_END_INT_CLR_S 13
+/* RMT_CH4_TX_END_INT_CLR : WO ;bitpos:[12] ;default: 1'b0 ; */
+/*description: Set this bit to clear the rmt_ch4_rx_end_int_raw..*/
+#define RMT_CH4_TX_END_INT_CLR (BIT(12))
+#define RMT_CH4_TX_END_INT_CLR_M (BIT(12))
+#define RMT_CH4_TX_END_INT_CLR_V 0x1
+#define RMT_CH4_TX_END_INT_CLR_S 12
+/* RMT_CH3_ERR_INT_CLR : WO ;bitpos:[11] ;default: 1'b0 ; */
+/*description: Set this bit to clear the rmt_ch3_err_int_raw.*/
+#define RMT_CH3_ERR_INT_CLR (BIT(11))
+#define RMT_CH3_ERR_INT_CLR_M (BIT(11))
+#define RMT_CH3_ERR_INT_CLR_V 0x1
+#define RMT_CH3_ERR_INT_CLR_S 11
+/* RMT_CH3_RX_END_INT_CLR : WO ;bitpos:[10] ;default: 1'b0 ; */
+/*description: Set this bit to clear the rmt_ch3_tx_end_int_raw.*/
+#define RMT_CH3_RX_END_INT_CLR (BIT(10))
+#define RMT_CH3_RX_END_INT_CLR_M (BIT(10))
+#define RMT_CH3_RX_END_INT_CLR_V 0x1
+#define RMT_CH3_RX_END_INT_CLR_S 10
+/* RMT_CH3_TX_END_INT_CLR : WO ;bitpos:[9] ;default: 1'b0 ; */
+/*description: Set this bit to clear the rmt_ch3_rx_end_int_raw..*/
+#define RMT_CH3_TX_END_INT_CLR (BIT(9))
+#define RMT_CH3_TX_END_INT_CLR_M (BIT(9))
+#define RMT_CH3_TX_END_INT_CLR_V 0x1
+#define RMT_CH3_TX_END_INT_CLR_S 9
+/* RMT_CH2_ERR_INT_CLR : WO ;bitpos:[8] ;default: 1'b0 ; */
+/*description: Set this bit to clear the rmt_ch2_err_int_raw.*/
+#define RMT_CH2_ERR_INT_CLR (BIT(8))
+#define RMT_CH2_ERR_INT_CLR_M (BIT(8))
+#define RMT_CH2_ERR_INT_CLR_V 0x1
+#define RMT_CH2_ERR_INT_CLR_S 8
+/* RMT_CH2_RX_END_INT_CLR : WO ;bitpos:[7] ;default: 1'b0 ; */
+/*description: Set this bit to clear the rmt_ch2_tx_end_int_raw.*/
+#define RMT_CH2_RX_END_INT_CLR (BIT(7))
+#define RMT_CH2_RX_END_INT_CLR_M (BIT(7))
+#define RMT_CH2_RX_END_INT_CLR_V 0x1
+#define RMT_CH2_RX_END_INT_CLR_S 7
+/* RMT_CH2_TX_END_INT_CLR : WO ;bitpos:[6] ;default: 1'b0 ; */
+/*description: Set this bit to clear the rmt_ch2_rx_end_int_raw..*/
+#define RMT_CH2_TX_END_INT_CLR (BIT(6))
+#define RMT_CH2_TX_END_INT_CLR_M (BIT(6))
+#define RMT_CH2_TX_END_INT_CLR_V 0x1
+#define RMT_CH2_TX_END_INT_CLR_S 6
+/* RMT_CH1_ERR_INT_CLR : WO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: Set this bit to clear the rmt_ch1_err_int_raw.*/
+#define RMT_CH1_ERR_INT_CLR (BIT(5))
+#define RMT_CH1_ERR_INT_CLR_M (BIT(5))
+#define RMT_CH1_ERR_INT_CLR_V 0x1
+#define RMT_CH1_ERR_INT_CLR_S 5
+/* RMT_CH1_RX_END_INT_CLR : WO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: Set this bit to clear the rmt_ch1_tx_end_int_raw.*/
+#define RMT_CH1_RX_END_INT_CLR (BIT(4))
+#define RMT_CH1_RX_END_INT_CLR_M (BIT(4))
+#define RMT_CH1_RX_END_INT_CLR_V 0x1
+#define RMT_CH1_RX_END_INT_CLR_S 4
+/* RMT_CH1_TX_END_INT_CLR : WO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: Set this bit to clear the rmt_ch1_rx_end_int_raw..*/
+#define RMT_CH1_TX_END_INT_CLR (BIT(3))
+#define RMT_CH1_TX_END_INT_CLR_M (BIT(3))
+#define RMT_CH1_TX_END_INT_CLR_V 0x1
+#define RMT_CH1_TX_END_INT_CLR_S 3
+/* RMT_CH0_ERR_INT_CLR : WO ;bitpos:[2] ;default: 1'b0 ; */
+/*description: Set this bit to clear the rmt_ch0_err_int_raw.*/
+#define RMT_CH0_ERR_INT_CLR (BIT(2))
+#define RMT_CH0_ERR_INT_CLR_M (BIT(2))
+#define RMT_CH0_ERR_INT_CLR_V 0x1
+#define RMT_CH0_ERR_INT_CLR_S 2
+/* RMT_CH0_RX_END_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: Set this bit to clear the rmt_ch0_tx_end_int_raw.*/
+#define RMT_CH0_RX_END_INT_CLR (BIT(1))
+#define RMT_CH0_RX_END_INT_CLR_M (BIT(1))
+#define RMT_CH0_RX_END_INT_CLR_V 0x1
+#define RMT_CH0_RX_END_INT_CLR_S 1
+/* RMT_CH0_TX_END_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: Set this bit to clear the rmt_ch0_rx_end_int_raw..*/
+#define RMT_CH0_TX_END_INT_CLR (BIT(0))
+#define RMT_CH0_TX_END_INT_CLR_M (BIT(0))
+#define RMT_CH0_TX_END_INT_CLR_V 0x1
+#define RMT_CH0_TX_END_INT_CLR_S 0
+
+#define RMT_CH0CARRIER_DUTY_REG (DR_REG_RMT_BASE + 0x00b0)
+/* RMT_CARRIER_HIGH_CH0 : R/W ;bitpos:[31:16] ;default: 16'h40 ; */
+/*description: This register is used to configure carrier wave's high level value for channel0.*/
+#define RMT_CARRIER_HIGH_CH0 0x0000FFFF
+#define RMT_CARRIER_HIGH_CH0_M ((RMT_CARRIER_HIGH_CH0_V)<<(RMT_CARRIER_HIGH_CH0_S))
+#define RMT_CARRIER_HIGH_CH0_V 0xFFFF
+#define RMT_CARRIER_HIGH_CH0_S 16
+/* RMT_CARRIER_LOW_CH0 : R/W ;bitpos:[15:0] ;default: 16'h40 ; */
+/*description: This register is used to configure carrier wave's low level value for channel0.*/
+#define RMT_CARRIER_LOW_CH0 0x0000FFFF
+#define RMT_CARRIER_LOW_CH0_M ((RMT_CARRIER_LOW_CH0_V)<<(RMT_CARRIER_LOW_CH0_S))
+#define RMT_CARRIER_LOW_CH0_V 0xFFFF
+#define RMT_CARRIER_LOW_CH0_S 0
+
+#define RMT_CH1CARRIER_DUTY_REG (DR_REG_RMT_BASE + 0x00b4)
+/* RMT_CARRIER_HIGH_CH1 : R/W ;bitpos:[31:16] ;default: 16'h40 ; */
+/*description: This register is used to configure carrier wave's high level value for channel1.*/
+#define RMT_CARRIER_HIGH_CH1 0x0000FFFF
+#define RMT_CARRIER_HIGH_CH1_M ((RMT_CARRIER_HIGH_CH1_V)<<(RMT_CARRIER_HIGH_CH1_S))
+#define RMT_CARRIER_HIGH_CH1_V 0xFFFF
+#define RMT_CARRIER_HIGH_CH1_S 16
+/* RMT_CARRIER_LOW_CH1 : R/W ;bitpos:[15:0] ;default: 16'h40 ; */
+/*description: This register is used to configure carrier wave's low level value for channel1.*/
+#define RMT_CARRIER_LOW_CH1 0x0000FFFF
+#define RMT_CARRIER_LOW_CH1_M ((RMT_CARRIER_LOW_CH1_V)<<(RMT_CARRIER_LOW_CH1_S))
+#define RMT_CARRIER_LOW_CH1_V 0xFFFF
+#define RMT_CARRIER_LOW_CH1_S 0
+
+#define RMT_CH2CARRIER_DUTY_REG (DR_REG_RMT_BASE + 0x00b8)
+/* RMT_CARRIER_HIGH_CH2 : R/W ;bitpos:[31:16] ;default: 16'h40 ; */
+/*description: This register is used to configure carrier wave's high level value for channel2.*/
+#define RMT_CARRIER_HIGH_CH2 0x0000FFFF
+#define RMT_CARRIER_HIGH_CH2_M ((RMT_CARRIER_HIGH_CH2_V)<<(RMT_CARRIER_HIGH_CH2_S))
+#define RMT_CARRIER_HIGH_CH2_V 0xFFFF
+#define RMT_CARRIER_HIGH_CH2_S 16
+/* RMT_CARRIER_LOW_CH2 : R/W ;bitpos:[15:0] ;default: 16'h40 ; */
+/*description: This register is used to configure carrier wave's low level value for channel2.*/
+#define RMT_CARRIER_LOW_CH2 0x0000FFFF
+#define RMT_CARRIER_LOW_CH2_M ((RMT_CARRIER_LOW_CH2_V)<<(RMT_CARRIER_LOW_CH2_S))
+#define RMT_CARRIER_LOW_CH2_V 0xFFFF
+#define RMT_CARRIER_LOW_CH2_S 0
+
+#define RMT_CH3CARRIER_DUTY_REG (DR_REG_RMT_BASE + 0x00bc)
+/* RMT_CARRIER_HIGH_CH3 : R/W ;bitpos:[31:16] ;default: 16'h40 ; */
+/*description: This register is used to configure carrier wave's high level value for channel3.*/
+#define RMT_CARRIER_HIGH_CH3 0x0000FFFF
+#define RMT_CARRIER_HIGH_CH3_M ((RMT_CARRIER_HIGH_CH3_V)<<(RMT_CARRIER_HIGH_CH3_S))
+#define RMT_CARRIER_HIGH_CH3_V 0xFFFF
+#define RMT_CARRIER_HIGH_CH3_S 16
+/* RMT_CARRIER_LOW_CH3 : R/W ;bitpos:[15:0] ;default: 16'h40 ; */
+/*description: This register is used to configure carrier wave's low level value for channel3.*/
+#define RMT_CARRIER_LOW_CH3 0x0000FFFF
+#define RMT_CARRIER_LOW_CH3_M ((RMT_CARRIER_LOW_CH3_V)<<(RMT_CARRIER_LOW_CH3_S))
+#define RMT_CARRIER_LOW_CH3_V 0xFFFF
+#define RMT_CARRIER_LOW_CH3_S 0
+
+#define RMT_CH4CARRIER_DUTY_REG (DR_REG_RMT_BASE + 0x00c0)
+/* RMT_CARRIER_HIGH_CH4 : R/W ;bitpos:[31:16] ;default: 16'h40 ; */
+/*description: This register is used to configure carrier wave's high level value for channel4.*/
+#define RMT_CARRIER_HIGH_CH4 0x0000FFFF
+#define RMT_CARRIER_HIGH_CH4_M ((RMT_CARRIER_HIGH_CH4_V)<<(RMT_CARRIER_HIGH_CH4_S))
+#define RMT_CARRIER_HIGH_CH4_V 0xFFFF
+#define RMT_CARRIER_HIGH_CH4_S 16
+/* RMT_CARRIER_LOW_CH4 : R/W ;bitpos:[15:0] ;default: 16'h40 ; */
+/*description: This register is used to configure carrier wave's low level value for channel4.*/
+#define RMT_CARRIER_LOW_CH4 0x0000FFFF
+#define RMT_CARRIER_LOW_CH4_M ((RMT_CARRIER_LOW_CH4_V)<<(RMT_CARRIER_LOW_CH4_S))
+#define RMT_CARRIER_LOW_CH4_V 0xFFFF
+#define RMT_CARRIER_LOW_CH4_S 0
+
+#define RMT_CH5CARRIER_DUTY_REG (DR_REG_RMT_BASE + 0x00c4)
+/* RMT_CARRIER_HIGH_CH5 : R/W ;bitpos:[31:16] ;default: 16'h40 ; */
+/*description: This register is used to configure carrier wave's high level value for channel5.*/
+#define RMT_CARRIER_HIGH_CH5 0x0000FFFF
+#define RMT_CARRIER_HIGH_CH5_M ((RMT_CARRIER_HIGH_CH5_V)<<(RMT_CARRIER_HIGH_CH5_S))
+#define RMT_CARRIER_HIGH_CH5_V 0xFFFF
+#define RMT_CARRIER_HIGH_CH5_S 16
+/* RMT_CARRIER_LOW_CH5 : R/W ;bitpos:[15:0] ;default: 16'h40 ; */
+/*description: This register is used to configure carrier wave's low level value for channel5.*/
+#define RMT_CARRIER_LOW_CH5 0x0000FFFF
+#define RMT_CARRIER_LOW_CH5_M ((RMT_CARRIER_LOW_CH5_V)<<(RMT_CARRIER_LOW_CH5_S))
+#define RMT_CARRIER_LOW_CH5_V 0xFFFF
+#define RMT_CARRIER_LOW_CH5_S 0
+
+#define RMT_CH6CARRIER_DUTY_REG (DR_REG_RMT_BASE + 0x00c8)
+/* RMT_CARRIER_HIGH_CH6 : R/W ;bitpos:[31:16] ;default: 16'h40 ; */
+/*description: This register is used to configure carrier wave's high level value for channel6.*/
+#define RMT_CARRIER_HIGH_CH6 0x0000FFFF
+#define RMT_CARRIER_HIGH_CH6_M ((RMT_CARRIER_HIGH_CH6_V)<<(RMT_CARRIER_HIGH_CH6_S))
+#define RMT_CARRIER_HIGH_CH6_V 0xFFFF
+#define RMT_CARRIER_HIGH_CH6_S 16
+/* RMT_CARRIER_LOW_CH6 : R/W ;bitpos:[15:0] ;default: 16'h40 ; */
+/*description: This register is used to configure carrier wave's low level value for channel6.*/
+#define RMT_CARRIER_LOW_CH6 0x0000FFFF
+#define RMT_CARRIER_LOW_CH6_M ((RMT_CARRIER_LOW_CH6_V)<<(RMT_CARRIER_LOW_CH6_S))
+#define RMT_CARRIER_LOW_CH6_V 0xFFFF
+#define RMT_CARRIER_LOW_CH6_S 0
+
+#define RMT_CH7CARRIER_DUTY_REG (DR_REG_RMT_BASE + 0x00cc)
+/* RMT_CARRIER_HIGH_CH7 : R/W ;bitpos:[31:16] ;default: 16'h40 ; */
+/*description: This register is used to configure carrier wave's high level value for channel7.*/
+#define RMT_CARRIER_HIGH_CH7 0x0000FFFF
+#define RMT_CARRIER_HIGH_CH7_M ((RMT_CARRIER_HIGH_CH7_V)<<(RMT_CARRIER_HIGH_CH7_S))
+#define RMT_CARRIER_HIGH_CH7_V 0xFFFF
+#define RMT_CARRIER_HIGH_CH7_S 16
+/* RMT_CARRIER_LOW_CH7 : R/W ;bitpos:[15:0] ;default: 16'h40 ; */
+/*description: This register is used to configure carrier wave's low level value for channel7.*/
+#define RMT_CARRIER_LOW_CH7 0x0000FFFF
+#define RMT_CARRIER_LOW_CH7_M ((RMT_CARRIER_LOW_CH7_V)<<(RMT_CARRIER_LOW_CH7_S))
+#define RMT_CARRIER_LOW_CH7_V 0xFFFF
+#define RMT_CARRIER_LOW_CH7_S 0
+
+#define RMT_CH0_TX_LIM_REG (DR_REG_RMT_BASE + 0x00d0)
+/* RMT_TX_LIM_CH0 : R/W ;bitpos:[8:0] ;default: 9'h80 ; */
+/*description: When channel0 sends more than reg_rmt_tx_lim_ch0 datas then channel0
+ produce the relative interrupt.*/
+#define RMT_TX_LIM_CH0 0x000001FF
+#define RMT_TX_LIM_CH0_M ((RMT_TX_LIM_CH0_V)<<(RMT_TX_LIM_CH0_S))
+#define RMT_TX_LIM_CH0_V 0x1FF
+#define RMT_TX_LIM_CH0_S 0
+
+#define RMT_CH1_TX_LIM_REG (DR_REG_RMT_BASE + 0x00d4)
+/* RMT_TX_LIM_CH1 : R/W ;bitpos:[8:0] ;default: 9'h80 ; */
+/*description: When channel1 sends more than reg_rmt_tx_lim_ch1 datas then channel1
+ produce the relative interrupt.*/
+#define RMT_TX_LIM_CH1 0x000001FF
+#define RMT_TX_LIM_CH1_M ((RMT_TX_LIM_CH1_V)<<(RMT_TX_LIM_CH1_S))
+#define RMT_TX_LIM_CH1_V 0x1FF
+#define RMT_TX_LIM_CH1_S 0
+
+#define RMT_CH2_TX_LIM_REG (DR_REG_RMT_BASE + 0x00d8)
+/* RMT_TX_LIM_CH2 : R/W ;bitpos:[8:0] ;default: 9'h80 ; */
+/*description: When channel2 sends more than reg_rmt_tx_lim_ch2 datas then channel2
+ produce the relative interrupt.*/
+#define RMT_TX_LIM_CH2 0x000001FF
+#define RMT_TX_LIM_CH2_M ((RMT_TX_LIM_CH2_V)<<(RMT_TX_LIM_CH2_S))
+#define RMT_TX_LIM_CH2_V 0x1FF
+#define RMT_TX_LIM_CH2_S 0
+
+#define RMT_CH3_TX_LIM_REG (DR_REG_RMT_BASE + 0x00dc)
+/* RMT_TX_LIM_CH3 : R/W ;bitpos:[8:0] ;default: 9'h80 ; */
+/*description: When channel3 sends more than reg_rmt_tx_lim_ch3 datas then channel3
+ produce the relative interrupt.*/
+#define RMT_TX_LIM_CH3 0x000001FF
+#define RMT_TX_LIM_CH3_M ((RMT_TX_LIM_CH3_V)<<(RMT_TX_LIM_CH3_S))
+#define RMT_TX_LIM_CH3_V 0x1FF
+#define RMT_TX_LIM_CH3_S 0
+
+#define RMT_CH4_TX_LIM_REG (DR_REG_RMT_BASE + 0x00e0)
+/* RMT_TX_LIM_CH4 : R/W ;bitpos:[8:0] ;default: 9'h80 ; */
+/*description: When channel4 sends more than reg_rmt_tx_lim_ch4 datas then channel4
+ produce the relative interrupt.*/
+#define RMT_TX_LIM_CH4 0x000001FF
+#define RMT_TX_LIM_CH4_M ((RMT_TX_LIM_CH4_V)<<(RMT_TX_LIM_CH4_S))
+#define RMT_TX_LIM_CH4_V 0x1FF
+#define RMT_TX_LIM_CH4_S 0
+
+#define RMT_CH5_TX_LIM_REG (DR_REG_RMT_BASE + 0x00e4)
+/* RMT_TX_LIM_CH5 : R/W ;bitpos:[8:0] ;default: 9'h80 ; */
+/*description: When channel5 sends more than reg_rmt_tx_lim_ch5 datas then channel5
+ produce the relative interrupt.*/
+#define RMT_TX_LIM_CH5 0x000001FF
+#define RMT_TX_LIM_CH5_M ((RMT_TX_LIM_CH5_V)<<(RMT_TX_LIM_CH5_S))
+#define RMT_TX_LIM_CH5_V 0x1FF
+#define RMT_TX_LIM_CH5_S 0
+
+#define RMT_CH6_TX_LIM_REG (DR_REG_RMT_BASE + 0x00e8)
+/* RMT_TX_LIM_CH6 : R/W ;bitpos:[8:0] ;default: 9'h80 ; */
+/*description: When channel6 sends more than reg_rmt_tx_lim_ch6 datas then channel6
+ produce the relative interrupt.*/
+#define RMT_TX_LIM_CH6 0x000001FF
+#define RMT_TX_LIM_CH6_M ((RMT_TX_LIM_CH6_V)<<(RMT_TX_LIM_CH6_S))
+#define RMT_TX_LIM_CH6_V 0x1FF
+#define RMT_TX_LIM_CH6_S 0
+
+#define RMT_CH7_TX_LIM_REG (DR_REG_RMT_BASE + 0x00ec)
+/* RMT_TX_LIM_CH7 : R/W ;bitpos:[8:0] ;default: 9'h80 ; */
+/*description: When channel7 sends more than reg_rmt_tx_lim_ch7 datas then channel7
+ produce the relative interrupt.*/
+#define RMT_TX_LIM_CH7 0x000001FF
+#define RMT_TX_LIM_CH7_M ((RMT_TX_LIM_CH7_V)<<(RMT_TX_LIM_CH7_S))
+#define RMT_TX_LIM_CH7_V 0x1FF
+#define RMT_TX_LIM_CH7_S 0
+
+#define RMT_APB_CONF_REG (DR_REG_RMT_BASE + 0x00f0)
+/* RMT_MEM_TX_WRAP_EN : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: when datas need to be send is more than channel's mem can store
+ then set this bit to enable reusage of mem this bit is used together with reg_rmt_tx_lim_chn.*/
+#define RMT_MEM_TX_WRAP_EN (BIT(1))
+#define RMT_MEM_TX_WRAP_EN_M (BIT(1))
+#define RMT_MEM_TX_WRAP_EN_V 0x1
+#define RMT_MEM_TX_WRAP_EN_S 1
+/* RMT_APB_FIFO_MASK : R/W ;bitpos:[0] ;default: 1'h0 ; */
+/*description: Set this bit to disable apb fifo access*/
+#define RMT_APB_FIFO_MASK (BIT(0))
+#define RMT_APB_FIFO_MASK_M (BIT(0))
+#define RMT_APB_FIFO_MASK_V 0x1
+#define RMT_APB_FIFO_MASK_S 0
+
+#define RMT_DATE_REG (DR_REG_RMT_BASE + 0x00fc)
+/* RMT_DATE : R/W ;bitpos:[31:0] ;default: 32'h16022600 ; */
+/*description: This is the version register.*/
+#define RMT_DATE 0xFFFFFFFF
+#define RMT_DATE_M ((RMT_DATE_V)<<(RMT_DATE_S))
+#define RMT_DATE_V 0xFFFFFFFF
+#define RMT_DATE_S 0
+
+/* RMT memory block address */
+#define RMT_CHANNEL_MEM(i) (DR_REG_RMT_BASE + 0x800 + 64 * 4 * (i))
+
+
+#endif /*_SOC_RMT_REG_H_ */
+
+
-// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD\r
-//\r
-// Licensed under the Apache License, Version 2.0 (the "License");\r
-// you may not use this file except in compliance with the License.\r
-// You may obtain a copy of the License at\r
-\r
-// http://www.apache.org/licenses/LICENSE-2.0\r
-//\r
-// Unless required by applicable law or agreed to in writing, software\r
-// distributed under the License is distributed on an "AS IS" BASIS,\r
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
-// See the License for the specific language governing permissions and\r
-// limitations under the License.\r
-#ifndef _SOC_RTC_IO_REG_H_\r
-#define _SOC_RTC_IO_REG_H_\r
-\r
-\r
-#include "soc.h"\r
-#define RTC_GPIO_OUT_REG (DR_REG_RTCIO_BASE + 0x0)\r
-/* RTC_GPIO_OUT_DATA : R/W ;bitpos:[31:14] ;default: 0 ; */\r
-/*description: GPIO0~17 output value*/\r
-#define RTC_GPIO_OUT_DATA 0x0003FFFF\r
-#define RTC_GPIO_OUT_DATA_M ((RTC_GPIO_OUT_DATA_V)<<(RTC_GPIO_OUT_DATA_S))\r
-#define RTC_GPIO_OUT_DATA_V 0x3FFFF\r
-#define RTC_GPIO_OUT_DATA_S 14\r
-\r
-#define RTC_GPIO_OUT_W1TS_REG (DR_REG_RTCIO_BASE + 0x4)\r
-/* RTC_GPIO_OUT_DATA_W1TS : WO ;bitpos:[31:14] ;default: 0 ; */\r
-/*description: GPIO0~17 output value write 1 to set*/\r
-#define RTC_GPIO_OUT_DATA_W1TS 0x0003FFFF\r
-#define RTC_GPIO_OUT_DATA_W1TS_M ((RTC_GPIO_OUT_DATA_W1TS_V)<<(RTC_GPIO_OUT_DATA_W1TS_S))\r
-#define RTC_GPIO_OUT_DATA_W1TS_V 0x3FFFF\r
-#define RTC_GPIO_OUT_DATA_W1TS_S 14\r
-\r
-#define RTC_GPIO_OUT_W1TC_REG (DR_REG_RTCIO_BASE + 0x8)\r
-/* RTC_GPIO_OUT_DATA_W1TC : WO ;bitpos:[31:14] ;default: 0 ; */\r
-/*description: GPIO0~17 output value write 1 to clear*/\r
-#define RTC_GPIO_OUT_DATA_W1TC 0x0003FFFF\r
-#define RTC_GPIO_OUT_DATA_W1TC_M ((RTC_GPIO_OUT_DATA_W1TC_V)<<(RTC_GPIO_OUT_DATA_W1TC_S))\r
-#define RTC_GPIO_OUT_DATA_W1TC_V 0x3FFFF\r
-#define RTC_GPIO_OUT_DATA_W1TC_S 14\r
-\r
-#define RTC_GPIO_ENABLE_REG (DR_REG_RTCIO_BASE + 0xc)\r
-/* RTC_GPIO_ENABLE : R/W ;bitpos:[31:14] ;default: 0 ; */\r
-/*description: GPIO0~17 output enable*/\r
-#define RTC_GPIO_ENABLE 0x0003FFFF\r
-#define RTC_GPIO_ENABLE_M ((RTC_GPIO_ENABLE_V)<<(RTC_GPIO_ENABLE_S))\r
-#define RTC_GPIO_ENABLE_V 0x3FFFF\r
-#define RTC_GPIO_ENABLE_S 14\r
-\r
-#define RTC_GPIO_ENABLE_W1TS_REG (DR_REG_RTCIO_BASE + 0x10)\r
-/* RTC_GPIO_ENABLE_W1TS : WO ;bitpos:[31:14] ;default: 0 ; */\r
-/*description: GPIO0~17 output enable write 1 to set*/\r
-#define RTC_GPIO_ENABLE_W1TS 0x0003FFFF\r
-#define RTC_GPIO_ENABLE_W1TS_M ((RTC_GPIO_ENABLE_W1TS_V)<<(RTC_GPIO_ENABLE_W1TS_S))\r
-#define RTC_GPIO_ENABLE_W1TS_V 0x3FFFF\r
-#define RTC_GPIO_ENABLE_W1TS_S 14\r
-\r
-#define RTC_GPIO_ENABLE_W1TC_REG (DR_REG_RTCIO_BASE + 0x14)\r
-/* RTC_GPIO_ENABLE_W1TC : WO ;bitpos:[31:14] ;default: 0 ; */\r
-/*description: GPIO0~17 output enable write 1 to clear*/\r
-#define RTC_GPIO_ENABLE_W1TC 0x0003FFFF\r
-#define RTC_GPIO_ENABLE_W1TC_M ((RTC_GPIO_ENABLE_W1TC_V)<<(RTC_GPIO_ENABLE_W1TC_S))\r
-#define RTC_GPIO_ENABLE_W1TC_V 0x3FFFF\r
-#define RTC_GPIO_ENABLE_W1TC_S 14\r
-\r
-#define RTC_GPIO_STATUS_REG (DR_REG_RTCIO_BASE + 0x18)\r
-/* RTC_GPIO_STATUS_INT : R/W ;bitpos:[31:14] ;default: 0 ; */\r
-/*description: GPIO0~17 interrupt status*/\r
-#define RTC_GPIO_STATUS_INT 0x0003FFFF\r
-#define RTC_GPIO_STATUS_INT_M ((RTC_GPIO_STATUS_INT_V)<<(RTC_GPIO_STATUS_INT_S))\r
-#define RTC_GPIO_STATUS_INT_V 0x3FFFF\r
-#define RTC_GPIO_STATUS_INT_S 14\r
-\r
-#define RTC_GPIO_STATUS_W1TS_REG (DR_REG_RTCIO_BASE + 0x1c)\r
-/* RTC_GPIO_STATUS_INT_W1TS : WO ;bitpos:[31:14] ;default: 0 ; */\r
-/*description: GPIO0~17 interrupt status write 1 to set*/\r
-#define RTC_GPIO_STATUS_INT_W1TS 0x0003FFFF\r
-#define RTC_GPIO_STATUS_INT_W1TS_M ((RTC_GPIO_STATUS_INT_W1TS_V)<<(RTC_GPIO_STATUS_INT_W1TS_S))\r
-#define RTC_GPIO_STATUS_INT_W1TS_V 0x3FFFF\r
-#define RTC_GPIO_STATUS_INT_W1TS_S 14\r
-\r
-#define RTC_GPIO_STATUS_W1TC_REG (DR_REG_RTCIO_BASE + 0x20)\r
-/* RTC_GPIO_STATUS_INT_W1TC : WO ;bitpos:[31:14] ;default: 0 ; */\r
-/*description: GPIO0~17 interrupt status write 1 to clear*/\r
-#define RTC_GPIO_STATUS_INT_W1TC 0x0003FFFF\r
-#define RTC_GPIO_STATUS_INT_W1TC_M ((RTC_GPIO_STATUS_INT_W1TC_V)<<(RTC_GPIO_STATUS_INT_W1TC_S))\r
-#define RTC_GPIO_STATUS_INT_W1TC_V 0x3FFFF\r
-#define RTC_GPIO_STATUS_INT_W1TC_S 14\r
-\r
-#define RTC_GPIO_IN_REG (DR_REG_RTCIO_BASE + 0x24)\r
-/* RTC_GPIO_IN_NEXT : RO ;bitpos:[31:14] ;default: ; */\r
-/*description: GPIO0~17 input value*/\r
-#define RTC_GPIO_IN_NEXT 0x0003FFFF\r
-#define RTC_GPIO_IN_NEXT_M ((RTC_GPIO_IN_NEXT_V)<<(RTC_GPIO_IN_NEXT_S))\r
-#define RTC_GPIO_IN_NEXT_V 0x3FFFF\r
-#define RTC_GPIO_IN_NEXT_S 14\r
-\r
-#define RTC_GPIO_PIN0_REG (DR_REG_RTCIO_BASE + 0x28)\r
-/* RTC_GPIO_PIN0_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */\r
-/*description: GPIO wake up enable only available in light sleep*/\r
-#define RTC_GPIO_PIN0_WAKEUP_ENABLE (BIT(10))\r
-#define RTC_GPIO_PIN0_WAKEUP_ENABLE_M (BIT(10))\r
-#define RTC_GPIO_PIN0_WAKEUP_ENABLE_V 0x1\r
-#define RTC_GPIO_PIN0_WAKEUP_ENABLE_S 10\r
-/* RTC_GPIO_PIN0_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */\r
-/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge\r
- trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/\r
-#define RTC_GPIO_PIN0_INT_TYPE 0x00000007\r
-#define RTC_GPIO_PIN0_INT_TYPE_M ((RTC_GPIO_PIN0_INT_TYPE_V)<<(RTC_GPIO_PIN0_INT_TYPE_S))\r
-#define RTC_GPIO_PIN0_INT_TYPE_V 0x7\r
-#define RTC_GPIO_PIN0_INT_TYPE_S 7\r
-/* RTC_GPIO_PIN0_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */\r
-/*description: if set to 0: normal output if set to 1: open drain*/\r
-#define RTC_GPIO_PIN0_PAD_DRIVER (BIT(2))\r
-#define RTC_GPIO_PIN0_PAD_DRIVER_M (BIT(2))\r
-#define RTC_GPIO_PIN0_PAD_DRIVER_V 0x1\r
-#define RTC_GPIO_PIN0_PAD_DRIVER_S 2\r
-\r
-#define RTC_GPIO_PIN1_REG (DR_REG_RTCIO_BASE + 0x2c)\r
-/* RTC_GPIO_PIN1_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */\r
-/*description: GPIO wake up enable only available in light sleep*/\r
-#define RTC_GPIO_PIN1_WAKEUP_ENABLE (BIT(10))\r
-#define RTC_GPIO_PIN1_WAKEUP_ENABLE_M (BIT(10))\r
-#define RTC_GPIO_PIN1_WAKEUP_ENABLE_V 0x1\r
-#define RTC_GPIO_PIN1_WAKEUP_ENABLE_S 10\r
-/* RTC_GPIO_PIN1_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */\r
-/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge\r
- trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/\r
-#define RTC_GPIO_PIN1_INT_TYPE 0x00000007\r
-#define RTC_GPIO_PIN1_INT_TYPE_M ((RTC_GPIO_PIN1_INT_TYPE_V)<<(RTC_GPIO_PIN1_INT_TYPE_S))\r
-#define RTC_GPIO_PIN1_INT_TYPE_V 0x7\r
-#define RTC_GPIO_PIN1_INT_TYPE_S 7\r
-/* RTC_GPIO_PIN1_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */\r
-/*description: if set to 0: normal output if set to 1: open drain*/\r
-#define RTC_GPIO_PIN1_PAD_DRIVER (BIT(2))\r
-#define RTC_GPIO_PIN1_PAD_DRIVER_M (BIT(2))\r
-#define RTC_GPIO_PIN1_PAD_DRIVER_V 0x1\r
-#define RTC_GPIO_PIN1_PAD_DRIVER_S 2\r
-\r
-#define RTC_GPIO_PIN2_REG (DR_REG_RTCIO_BASE + 0x30)\r
-/* RTC_GPIO_PIN2_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */\r
-/*description: GPIO wake up enable only available in light sleep*/\r
-#define RTC_GPIO_PIN2_WAKEUP_ENABLE (BIT(10))\r
-#define RTC_GPIO_PIN2_WAKEUP_ENABLE_M (BIT(10))\r
-#define RTC_GPIO_PIN2_WAKEUP_ENABLE_V 0x1\r
-#define RTC_GPIO_PIN2_WAKEUP_ENABLE_S 10\r
-/* RTC_GPIO_PIN2_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */\r
-/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge\r
- trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/\r
-#define RTC_GPIO_PIN2_INT_TYPE 0x00000007\r
-#define RTC_GPIO_PIN2_INT_TYPE_M ((RTC_GPIO_PIN2_INT_TYPE_V)<<(RTC_GPIO_PIN2_INT_TYPE_S))\r
-#define RTC_GPIO_PIN2_INT_TYPE_V 0x7\r
-#define RTC_GPIO_PIN2_INT_TYPE_S 7\r
-/* RTC_GPIO_PIN2_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */\r
-/*description: if set to 0: normal output if set to 1: open drain*/\r
-#define RTC_GPIO_PIN2_PAD_DRIVER (BIT(2))\r
-#define RTC_GPIO_PIN2_PAD_DRIVER_M (BIT(2))\r
-#define RTC_GPIO_PIN2_PAD_DRIVER_V 0x1\r
-#define RTC_GPIO_PIN2_PAD_DRIVER_S 2\r
-\r
-#define RTC_GPIO_PIN3_REG (DR_REG_RTCIO_BASE + 0x34)\r
-/* RTC_GPIO_PIN3_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */\r
-/*description: GPIO wake up enable only available in light sleep*/\r
-#define RTC_GPIO_PIN3_WAKEUP_ENABLE (BIT(10))\r
-#define RTC_GPIO_PIN3_WAKEUP_ENABLE_M (BIT(10))\r
-#define RTC_GPIO_PIN3_WAKEUP_ENABLE_V 0x1\r
-#define RTC_GPIO_PIN3_WAKEUP_ENABLE_S 10\r
-/* RTC_GPIO_PIN3_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */\r
-/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge\r
- trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/\r
-#define RTC_GPIO_PIN3_INT_TYPE 0x00000007\r
-#define RTC_GPIO_PIN3_INT_TYPE_M ((RTC_GPIO_PIN3_INT_TYPE_V)<<(RTC_GPIO_PIN3_INT_TYPE_S))\r
-#define RTC_GPIO_PIN3_INT_TYPE_V 0x7\r
-#define RTC_GPIO_PIN3_INT_TYPE_S 7\r
-/* RTC_GPIO_PIN3_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */\r
-/*description: if set to 0: normal output if set to 1: open drain*/\r
-#define RTC_GPIO_PIN3_PAD_DRIVER (BIT(2))\r
-#define RTC_GPIO_PIN3_PAD_DRIVER_M (BIT(2))\r
-#define RTC_GPIO_PIN3_PAD_DRIVER_V 0x1\r
-#define RTC_GPIO_PIN3_PAD_DRIVER_S 2\r
-\r
-#define RTC_GPIO_PIN4_REG (DR_REG_RTCIO_BASE + 0x38)\r
-/* RTC_GPIO_PIN4_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */\r
-/*description: GPIO wake up enable only available in light sleep*/\r
-#define RTC_GPIO_PIN4_WAKEUP_ENABLE (BIT(10))\r
-#define RTC_GPIO_PIN4_WAKEUP_ENABLE_M (BIT(10))\r
-#define RTC_GPIO_PIN4_WAKEUP_ENABLE_V 0x1\r
-#define RTC_GPIO_PIN4_WAKEUP_ENABLE_S 10\r
-/* RTC_GPIO_PIN4_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */\r
-/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge\r
- trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/\r
-#define RTC_GPIO_PIN4_INT_TYPE 0x00000007\r
-#define RTC_GPIO_PIN4_INT_TYPE_M ((RTC_GPIO_PIN4_INT_TYPE_V)<<(RTC_GPIO_PIN4_INT_TYPE_S))\r
-#define RTC_GPIO_PIN4_INT_TYPE_V 0x7\r
-#define RTC_GPIO_PIN4_INT_TYPE_S 7\r
-/* RTC_GPIO_PIN4_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */\r
-/*description: if set to 0: normal output if set to 1: open drain*/\r
-#define RTC_GPIO_PIN4_PAD_DRIVER (BIT(2))\r
-#define RTC_GPIO_PIN4_PAD_DRIVER_M (BIT(2))\r
-#define RTC_GPIO_PIN4_PAD_DRIVER_V 0x1\r
-#define RTC_GPIO_PIN4_PAD_DRIVER_S 2\r
-\r
-#define RTC_GPIO_PIN5_REG (DR_REG_RTCIO_BASE + 0x3c)\r
-/* RTC_GPIO_PIN5_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */\r
-/*description: GPIO wake up enable only available in light sleep*/\r
-#define RTC_GPIO_PIN5_WAKEUP_ENABLE (BIT(10))\r
-#define RTC_GPIO_PIN5_WAKEUP_ENABLE_M (BIT(10))\r
-#define RTC_GPIO_PIN5_WAKEUP_ENABLE_V 0x1\r
-#define RTC_GPIO_PIN5_WAKEUP_ENABLE_S 10\r
-/* RTC_GPIO_PIN5_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */\r
-/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge\r
- trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/\r
-#define RTC_GPIO_PIN5_INT_TYPE 0x00000007\r
-#define RTC_GPIO_PIN5_INT_TYPE_M ((RTC_GPIO_PIN5_INT_TYPE_V)<<(RTC_GPIO_PIN5_INT_TYPE_S))\r
-#define RTC_GPIO_PIN5_INT_TYPE_V 0x7\r
-#define RTC_GPIO_PIN5_INT_TYPE_S 7\r
-/* RTC_GPIO_PIN5_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */\r
-/*description: if set to 0: normal output if set to 1: open drain*/\r
-#define RTC_GPIO_PIN5_PAD_DRIVER (BIT(2))\r
-#define RTC_GPIO_PIN5_PAD_DRIVER_M (BIT(2))\r
-#define RTC_GPIO_PIN5_PAD_DRIVER_V 0x1\r
-#define RTC_GPIO_PIN5_PAD_DRIVER_S 2\r
-\r
-#define RTC_GPIO_PIN6_REG (DR_REG_RTCIO_BASE + 0x40)\r
-/* RTC_GPIO_PIN6_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */\r
-/*description: GPIO wake up enable only available in light sleep*/\r
-#define RTC_GPIO_PIN6_WAKEUP_ENABLE (BIT(10))\r
-#define RTC_GPIO_PIN6_WAKEUP_ENABLE_M (BIT(10))\r
-#define RTC_GPIO_PIN6_WAKEUP_ENABLE_V 0x1\r
-#define RTC_GPIO_PIN6_WAKEUP_ENABLE_S 10\r
-/* RTC_GPIO_PIN6_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */\r
-/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge\r
- trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/\r
-#define RTC_GPIO_PIN6_INT_TYPE 0x00000007\r
-#define RTC_GPIO_PIN6_INT_TYPE_M ((RTC_GPIO_PIN6_INT_TYPE_V)<<(RTC_GPIO_PIN6_INT_TYPE_S))\r
-#define RTC_GPIO_PIN6_INT_TYPE_V 0x7\r
-#define RTC_GPIO_PIN6_INT_TYPE_S 7\r
-/* RTC_GPIO_PIN6_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */\r
-/*description: if set to 0: normal output if set to 1: open drain*/\r
-#define RTC_GPIO_PIN6_PAD_DRIVER (BIT(2))\r
-#define RTC_GPIO_PIN6_PAD_DRIVER_M (BIT(2))\r
-#define RTC_GPIO_PIN6_PAD_DRIVER_V 0x1\r
-#define RTC_GPIO_PIN6_PAD_DRIVER_S 2\r
-\r
-#define RTC_GPIO_PIN7_REG (DR_REG_RTCIO_BASE + 0x44)\r
-/* RTC_GPIO_PIN7_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */\r
-/*description: GPIO wake up enable only available in light sleep*/\r
-#define RTC_GPIO_PIN7_WAKEUP_ENABLE (BIT(10))\r
-#define RTC_GPIO_PIN7_WAKEUP_ENABLE_M (BIT(10))\r
-#define RTC_GPIO_PIN7_WAKEUP_ENABLE_V 0x1\r
-#define RTC_GPIO_PIN7_WAKEUP_ENABLE_S 10\r
-/* RTC_GPIO_PIN7_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */\r
-/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge\r
- trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/\r
-#define RTC_GPIO_PIN7_INT_TYPE 0x00000007\r
-#define RTC_GPIO_PIN7_INT_TYPE_M ((RTC_GPIO_PIN7_INT_TYPE_V)<<(RTC_GPIO_PIN7_INT_TYPE_S))\r
-#define RTC_GPIO_PIN7_INT_TYPE_V 0x7\r
-#define RTC_GPIO_PIN7_INT_TYPE_S 7\r
-/* RTC_GPIO_PIN7_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */\r
-/*description: if set to 0: normal output if set to 1: open drain*/\r
-#define RTC_GPIO_PIN7_PAD_DRIVER (BIT(2))\r
-#define RTC_GPIO_PIN7_PAD_DRIVER_M (BIT(2))\r
-#define RTC_GPIO_PIN7_PAD_DRIVER_V 0x1\r
-#define RTC_GPIO_PIN7_PAD_DRIVER_S 2\r
-\r
-#define RTC_GPIO_PIN8_REG (DR_REG_RTCIO_BASE + 0x48)\r
-/* RTC_GPIO_PIN8_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */\r
-/*description: GPIO wake up enable only available in light sleep*/\r
-#define RTC_GPIO_PIN8_WAKEUP_ENABLE (BIT(10))\r
-#define RTC_GPIO_PIN8_WAKEUP_ENABLE_M (BIT(10))\r
-#define RTC_GPIO_PIN8_WAKEUP_ENABLE_V 0x1\r
-#define RTC_GPIO_PIN8_WAKEUP_ENABLE_S 10\r
-/* RTC_GPIO_PIN8_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */\r
-/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge\r
- trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/\r
-#define RTC_GPIO_PIN8_INT_TYPE 0x00000007\r
-#define RTC_GPIO_PIN8_INT_TYPE_M ((RTC_GPIO_PIN8_INT_TYPE_V)<<(RTC_GPIO_PIN8_INT_TYPE_S))\r
-#define RTC_GPIO_PIN8_INT_TYPE_V 0x7\r
-#define RTC_GPIO_PIN8_INT_TYPE_S 7\r
-/* RTC_GPIO_PIN8_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */\r
-/*description: if set to 0: normal output if set to 1: open drain*/\r
-#define RTC_GPIO_PIN8_PAD_DRIVER (BIT(2))\r
-#define RTC_GPIO_PIN8_PAD_DRIVER_M (BIT(2))\r
-#define RTC_GPIO_PIN8_PAD_DRIVER_V 0x1\r
-#define RTC_GPIO_PIN8_PAD_DRIVER_S 2\r
-\r
-#define RTC_GPIO_PIN9_REG (DR_REG_RTCIO_BASE + 0x4c)\r
-/* RTC_GPIO_PIN9_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */\r
-/*description: GPIO wake up enable only available in light sleep*/\r
-#define RTC_GPIO_PIN9_WAKEUP_ENABLE (BIT(10))\r
-#define RTC_GPIO_PIN9_WAKEUP_ENABLE_M (BIT(10))\r
-#define RTC_GPIO_PIN9_WAKEUP_ENABLE_V 0x1\r
-#define RTC_GPIO_PIN9_WAKEUP_ENABLE_S 10\r
-/* RTC_GPIO_PIN9_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */\r
-/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge\r
- trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/\r
-#define RTC_GPIO_PIN9_INT_TYPE 0x00000007\r
-#define RTC_GPIO_PIN9_INT_TYPE_M ((RTC_GPIO_PIN9_INT_TYPE_V)<<(RTC_GPIO_PIN9_INT_TYPE_S))\r
-#define RTC_GPIO_PIN9_INT_TYPE_V 0x7\r
-#define RTC_GPIO_PIN9_INT_TYPE_S 7\r
-/* RTC_GPIO_PIN9_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */\r
-/*description: if set to 0: normal output if set to 1: open drain*/\r
-#define RTC_GPIO_PIN9_PAD_DRIVER (BIT(2))\r
-#define RTC_GPIO_PIN9_PAD_DRIVER_M (BIT(2))\r
-#define RTC_GPIO_PIN9_PAD_DRIVER_V 0x1\r
-#define RTC_GPIO_PIN9_PAD_DRIVER_S 2\r
-\r
-#define RTC_GPIO_PIN10_REG (DR_REG_RTCIO_BASE + 0x50)\r
-/* RTC_GPIO_PIN10_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */\r
-/*description: GPIO wake up enable only available in light sleep*/\r
-#define RTC_GPIO_PIN10_WAKEUP_ENABLE (BIT(10))\r
-#define RTC_GPIO_PIN10_WAKEUP_ENABLE_M (BIT(10))\r
-#define RTC_GPIO_PIN10_WAKEUP_ENABLE_V 0x1\r
-#define RTC_GPIO_PIN10_WAKEUP_ENABLE_S 10\r
-/* RTC_GPIO_PIN10_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */\r
-/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge\r
- trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/\r
-#define RTC_GPIO_PIN10_INT_TYPE 0x00000007\r
-#define RTC_GPIO_PIN10_INT_TYPE_M ((RTC_GPIO_PIN10_INT_TYPE_V)<<(RTC_GPIO_PIN10_INT_TYPE_S))\r
-#define RTC_GPIO_PIN10_INT_TYPE_V 0x7\r
-#define RTC_GPIO_PIN10_INT_TYPE_S 7\r
-/* RTC_GPIO_PIN10_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */\r
-/*description: if set to 0: normal output if set to 1: open drain*/\r
-#define RTC_GPIO_PIN10_PAD_DRIVER (BIT(2))\r
-#define RTC_GPIO_PIN10_PAD_DRIVER_M (BIT(2))\r
-#define RTC_GPIO_PIN10_PAD_DRIVER_V 0x1\r
-#define RTC_GPIO_PIN10_PAD_DRIVER_S 2\r
-\r
-#define RTC_GPIO_PIN11_REG (DR_REG_RTCIO_BASE + 0x54)\r
-/* RTC_GPIO_PIN11_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */\r
-/*description: GPIO wake up enable only available in light sleep*/\r
-#define RTC_GPIO_PIN11_WAKEUP_ENABLE (BIT(10))\r
-#define RTC_GPIO_PIN11_WAKEUP_ENABLE_M (BIT(10))\r
-#define RTC_GPIO_PIN11_WAKEUP_ENABLE_V 0x1\r
-#define RTC_GPIO_PIN11_WAKEUP_ENABLE_S 10\r
-/* RTC_GPIO_PIN11_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */\r
-/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge\r
- trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/\r
-#define RTC_GPIO_PIN11_INT_TYPE 0x00000007\r
-#define RTC_GPIO_PIN11_INT_TYPE_M ((RTC_GPIO_PIN11_INT_TYPE_V)<<(RTC_GPIO_PIN11_INT_TYPE_S))\r
-#define RTC_GPIO_PIN11_INT_TYPE_V 0x7\r
-#define RTC_GPIO_PIN11_INT_TYPE_S 7\r
-/* RTC_GPIO_PIN11_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */\r
-/*description: if set to 0: normal output if set to 1: open drain*/\r
-#define RTC_GPIO_PIN11_PAD_DRIVER (BIT(2))\r
-#define RTC_GPIO_PIN11_PAD_DRIVER_M (BIT(2))\r
-#define RTC_GPIO_PIN11_PAD_DRIVER_V 0x1\r
-#define RTC_GPIO_PIN11_PAD_DRIVER_S 2\r
-\r
-#define RTC_GPIO_PIN12_REG (DR_REG_RTCIO_BASE + 0x58)\r
-/* RTC_GPIO_PIN12_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */\r
-/*description: GPIO wake up enable only available in light sleep*/\r
-#define RTC_GPIO_PIN12_WAKEUP_ENABLE (BIT(10))\r
-#define RTC_GPIO_PIN12_WAKEUP_ENABLE_M (BIT(10))\r
-#define RTC_GPIO_PIN12_WAKEUP_ENABLE_V 0x1\r
-#define RTC_GPIO_PIN12_WAKEUP_ENABLE_S 10\r
-/* RTC_GPIO_PIN12_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */\r
-/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge\r
- trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/\r
-#define RTC_GPIO_PIN12_INT_TYPE 0x00000007\r
-#define RTC_GPIO_PIN12_INT_TYPE_M ((RTC_GPIO_PIN12_INT_TYPE_V)<<(RTC_GPIO_PIN12_INT_TYPE_S))\r
-#define RTC_GPIO_PIN12_INT_TYPE_V 0x7\r
-#define RTC_GPIO_PIN12_INT_TYPE_S 7\r
-/* RTC_GPIO_PIN12_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */\r
-/*description: if set to 0: normal output if set to 1: open drain*/\r
-#define RTC_GPIO_PIN12_PAD_DRIVER (BIT(2))\r
-#define RTC_GPIO_PIN12_PAD_DRIVER_M (BIT(2))\r
-#define RTC_GPIO_PIN12_PAD_DRIVER_V 0x1\r
-#define RTC_GPIO_PIN12_PAD_DRIVER_S 2\r
-\r
-#define RTC_GPIO_PIN13_REG (DR_REG_RTCIO_BASE + 0x5c)\r
-/* RTC_GPIO_PIN13_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */\r
-/*description: GPIO wake up enable only available in light sleep*/\r
-#define RTC_GPIO_PIN13_WAKEUP_ENABLE (BIT(10))\r
-#define RTC_GPIO_PIN13_WAKEUP_ENABLE_M (BIT(10))\r
-#define RTC_GPIO_PIN13_WAKEUP_ENABLE_V 0x1\r
-#define RTC_GPIO_PIN13_WAKEUP_ENABLE_S 10\r
-/* RTC_GPIO_PIN13_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */\r
-/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge\r
- trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/\r
-#define RTC_GPIO_PIN13_INT_TYPE 0x00000007\r
-#define RTC_GPIO_PIN13_INT_TYPE_M ((RTC_GPIO_PIN13_INT_TYPE_V)<<(RTC_GPIO_PIN13_INT_TYPE_S))\r
-#define RTC_GPIO_PIN13_INT_TYPE_V 0x7\r
-#define RTC_GPIO_PIN13_INT_TYPE_S 7\r
-/* RTC_GPIO_PIN13_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */\r
-/*description: if set to 0: normal output if set to 1: open drain*/\r
-#define RTC_GPIO_PIN13_PAD_DRIVER (BIT(2))\r
-#define RTC_GPIO_PIN13_PAD_DRIVER_M (BIT(2))\r
-#define RTC_GPIO_PIN13_PAD_DRIVER_V 0x1\r
-#define RTC_GPIO_PIN13_PAD_DRIVER_S 2\r
-\r
-#define RTC_GPIO_PIN14_REG (DR_REG_RTCIO_BASE + 0x60)\r
-/* RTC_GPIO_PIN14_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */\r
-/*description: GPIO wake up enable only available in light sleep*/\r
-#define RTC_GPIO_PIN14_WAKEUP_ENABLE (BIT(10))\r
-#define RTC_GPIO_PIN14_WAKEUP_ENABLE_M (BIT(10))\r
-#define RTC_GPIO_PIN14_WAKEUP_ENABLE_V 0x1\r
-#define RTC_GPIO_PIN14_WAKEUP_ENABLE_S 10\r
-/* RTC_GPIO_PIN14_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */\r
-/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge\r
- trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/\r
-#define RTC_GPIO_PIN14_INT_TYPE 0x00000007\r
-#define RTC_GPIO_PIN14_INT_TYPE_M ((RTC_GPIO_PIN14_INT_TYPE_V)<<(RTC_GPIO_PIN14_INT_TYPE_S))\r
-#define RTC_GPIO_PIN14_INT_TYPE_V 0x7\r
-#define RTC_GPIO_PIN14_INT_TYPE_S 7\r
-/* RTC_GPIO_PIN14_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */\r
-/*description: if set to 0: normal output if set to 1: open drain*/\r
-#define RTC_GPIO_PIN14_PAD_DRIVER (BIT(2))\r
-#define RTC_GPIO_PIN14_PAD_DRIVER_M (BIT(2))\r
-#define RTC_GPIO_PIN14_PAD_DRIVER_V 0x1\r
-#define RTC_GPIO_PIN14_PAD_DRIVER_S 2\r
-\r
-#define RTC_GPIO_PIN15_REG (DR_REG_RTCIO_BASE + 0x64)\r
-/* RTC_GPIO_PIN15_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */\r
-/*description: GPIO wake up enable only available in light sleep*/\r
-#define RTC_GPIO_PIN15_WAKEUP_ENABLE (BIT(10))\r
-#define RTC_GPIO_PIN15_WAKEUP_ENABLE_M (BIT(10))\r
-#define RTC_GPIO_PIN15_WAKEUP_ENABLE_V 0x1\r
-#define RTC_GPIO_PIN15_WAKEUP_ENABLE_S 10\r
-/* RTC_GPIO_PIN15_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */\r
-/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge\r
- trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/\r
-#define RTC_GPIO_PIN15_INT_TYPE 0x00000007\r
-#define RTC_GPIO_PIN15_INT_TYPE_M ((RTC_GPIO_PIN15_INT_TYPE_V)<<(RTC_GPIO_PIN15_INT_TYPE_S))\r
-#define RTC_GPIO_PIN15_INT_TYPE_V 0x7\r
-#define RTC_GPIO_PIN15_INT_TYPE_S 7\r
-/* RTC_GPIO_PIN15_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */\r
-/*description: if set to 0: normal output if set to 1: open drain*/\r
-#define RTC_GPIO_PIN15_PAD_DRIVER (BIT(2))\r
-#define RTC_GPIO_PIN15_PAD_DRIVER_M (BIT(2))\r
-#define RTC_GPIO_PIN15_PAD_DRIVER_V 0x1\r
-#define RTC_GPIO_PIN15_PAD_DRIVER_S 2\r
-\r
-#define RTC_GPIO_PIN16_REG (DR_REG_RTCIO_BASE + 0x68)\r
-/* RTC_GPIO_PIN16_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */\r
-/*description: GPIO wake up enable only available in light sleep*/\r
-#define RTC_GPIO_PIN16_WAKEUP_ENABLE (BIT(10))\r
-#define RTC_GPIO_PIN16_WAKEUP_ENABLE_M (BIT(10))\r
-#define RTC_GPIO_PIN16_WAKEUP_ENABLE_V 0x1\r
-#define RTC_GPIO_PIN16_WAKEUP_ENABLE_S 10\r
-/* RTC_GPIO_PIN16_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */\r
-/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge\r
- trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/\r
-#define RTC_GPIO_PIN16_INT_TYPE 0x00000007\r
-#define RTC_GPIO_PIN16_INT_TYPE_M ((RTC_GPIO_PIN16_INT_TYPE_V)<<(RTC_GPIO_PIN16_INT_TYPE_S))\r
-#define RTC_GPIO_PIN16_INT_TYPE_V 0x7\r
-#define RTC_GPIO_PIN16_INT_TYPE_S 7\r
-/* RTC_GPIO_PIN16_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */\r
-/*description: if set to 0: normal output if set to 1: open drain*/\r
-#define RTC_GPIO_PIN16_PAD_DRIVER (BIT(2))\r
-#define RTC_GPIO_PIN16_PAD_DRIVER_M (BIT(2))\r
-#define RTC_GPIO_PIN16_PAD_DRIVER_V 0x1\r
-#define RTC_GPIO_PIN16_PAD_DRIVER_S 2\r
-\r
-#define RTC_GPIO_PIN17_REG (DR_REG_RTCIO_BASE + 0x6c)\r
-/* RTC_GPIO_PIN17_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */\r
-/*description: GPIO wake up enable only available in light sleep*/\r
-#define RTC_GPIO_PIN17_WAKEUP_ENABLE (BIT(10))\r
-#define RTC_GPIO_PIN17_WAKEUP_ENABLE_M (BIT(10))\r
-#define RTC_GPIO_PIN17_WAKEUP_ENABLE_V 0x1\r
-#define RTC_GPIO_PIN17_WAKEUP_ENABLE_S 10\r
-/* RTC_GPIO_PIN17_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */\r
-/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge\r
- trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/\r
-#define RTC_GPIO_PIN17_INT_TYPE 0x00000007\r
-#define RTC_GPIO_PIN17_INT_TYPE_M ((RTC_GPIO_PIN17_INT_TYPE_V)<<(RTC_GPIO_PIN17_INT_TYPE_S))\r
-#define RTC_GPIO_PIN17_INT_TYPE_V 0x7\r
-#define RTC_GPIO_PIN17_INT_TYPE_S 7\r
-/* RTC_GPIO_PIN17_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */\r
-/*description: if set to 0: normal output if set to 1: open drain*/\r
-#define RTC_GPIO_PIN17_PAD_DRIVER (BIT(2))\r
-#define RTC_GPIO_PIN17_PAD_DRIVER_M (BIT(2))\r
-#define RTC_GPIO_PIN17_PAD_DRIVER_V 0x1\r
-#define RTC_GPIO_PIN17_PAD_DRIVER_S 2\r
-\r
-#define RTC_IO_RTC_DEBUG_SEL_REG (DR_REG_RTCIO_BASE + 0x70)\r
-/* RTC_IO_DEBUG_12M_NO_GATING : R/W ;bitpos:[25] ;default: 1'd0 ; */\r
-/*description: */\r
-#define RTC_IO_DEBUG_12M_NO_GATING (BIT(25))\r
-#define RTC_IO_DEBUG_12M_NO_GATING_M (BIT(25))\r
-#define RTC_IO_DEBUG_12M_NO_GATING_V 0x1\r
-#define RTC_IO_DEBUG_12M_NO_GATING_S 25\r
-/* RTC_IO_DEBUG_SEL4 : R/W ;bitpos:[24:20] ;default: 5'd0 ; */\r
-/*description: */\r
-#define RTC_IO_DEBUG_SEL4 0x0000001F\r
-#define RTC_IO_DEBUG_SEL4_M ((RTC_IO_DEBUG_SEL4_V)<<(RTC_IO_DEBUG_SEL4_S))\r
-#define RTC_IO_DEBUG_SEL4_V 0x1F\r
-#define RTC_IO_DEBUG_SEL4_S 20\r
-/* RTC_IO_DEBUG_SEL3 : R/W ;bitpos:[19:15] ;default: 5'd0 ; */\r
-/*description: */\r
-#define RTC_IO_DEBUG_SEL3 0x0000001F\r
-#define RTC_IO_DEBUG_SEL3_M ((RTC_IO_DEBUG_SEL3_V)<<(RTC_IO_DEBUG_SEL3_S))\r
-#define RTC_IO_DEBUG_SEL3_V 0x1F\r
-#define RTC_IO_DEBUG_SEL3_S 15\r
-/* RTC_IO_DEBUG_SEL2 : R/W ;bitpos:[14:10] ;default: 5'd0 ; */\r
-/*description: */\r
-#define RTC_IO_DEBUG_SEL2 0x0000001F\r
-#define RTC_IO_DEBUG_SEL2_M ((RTC_IO_DEBUG_SEL2_V)<<(RTC_IO_DEBUG_SEL2_S))\r
-#define RTC_IO_DEBUG_SEL2_V 0x1F\r
-#define RTC_IO_DEBUG_SEL2_S 10\r
-/* RTC_IO_DEBUG_SEL1 : R/W ;bitpos:[9:5] ;default: 5'd0 ; */\r
-/*description: */\r
-#define RTC_IO_DEBUG_SEL1 0x0000001F\r
-#define RTC_IO_DEBUG_SEL1_M ((RTC_IO_DEBUG_SEL1_V)<<(RTC_IO_DEBUG_SEL1_S))\r
-#define RTC_IO_DEBUG_SEL1_V 0x1F\r
-#define RTC_IO_DEBUG_SEL1_S 5\r
-/* RTC_IO_DEBUG_SEL0 : R/W ;bitpos:[4:0] ;default: 5'd0 ; */\r
-/*description: */\r
-#define RTC_IO_DEBUG_SEL0 0x0000001F\r
-#define RTC_IO_DEBUG_SEL0_M ((RTC_IO_DEBUG_SEL0_V)<<(RTC_IO_DEBUG_SEL0_S))\r
-#define RTC_IO_DEBUG_SEL0_V 0x1F\r
-#define RTC_IO_DEBUG_SEL0_S 0\r
-\r
-#define RTC_IO_DIG_PAD_HOLD_REG (DR_REG_RTCIO_BASE + 0x74)\r
-/* RTC_IO_DIG_PAD_HOLD : R/W ;bitpos:[31:0] ;default: 1'd0 ; */\r
-/*description: select the digital pad hold value.*/\r
-#define RTC_IO_DIG_PAD_HOLD 0xFFFFFFFF\r
-#define RTC_IO_DIG_PAD_HOLD_M ((RTC_IO_DIG_PAD_HOLD_V)<<(RTC_IO_DIG_PAD_HOLD_S))\r
-#define RTC_IO_DIG_PAD_HOLD_V 0xFFFFFFFF\r
-#define RTC_IO_DIG_PAD_HOLD_S 0\r
-\r
-#define RTC_IO_HALL_SENS_REG (DR_REG_RTCIO_BASE + 0x78)\r
-/* RTC_IO_XPD_HALL : R/W ;bitpos:[31] ;default: 1'd0 ; */\r
-/*description: Power on hall sensor and connect to VP and VN*/\r
-#define RTC_IO_XPD_HALL (BIT(31))\r
-#define RTC_IO_XPD_HALL_M (BIT(31))\r
-#define RTC_IO_XPD_HALL_V 0x1\r
-#define RTC_IO_XPD_HALL_S 31\r
-/* RTC_IO_HALL_PHASE : R/W ;bitpos:[30] ;default: 1'd0 ; */\r
-/*description: Reverse phase of hall sensor*/\r
-#define RTC_IO_HALL_PHASE (BIT(30))\r
-#define RTC_IO_HALL_PHASE_M (BIT(30))\r
-#define RTC_IO_HALL_PHASE_V 0x1\r
-#define RTC_IO_HALL_PHASE_S 30\r
-\r
-#define RTC_IO_SENSOR_PADS_REG (DR_REG_RTCIO_BASE + 0x7c)\r
-/* RTC_IO_SENSE1_HOLD : R/W ;bitpos:[31] ;default: 1'd0 ; */\r
-/*description: hold the current value of the output when setting the hold to Ò1Ó*/\r
-#define RTC_IO_SENSE1_HOLD (BIT(31))\r
-#define RTC_IO_SENSE1_HOLD_M (BIT(31))\r
-#define RTC_IO_SENSE1_HOLD_V 0x1\r
-#define RTC_IO_SENSE1_HOLD_S 31\r
-/* RTC_IO_SENSE2_HOLD : R/W ;bitpos:[30] ;default: 1'd0 ; */\r
-/*description: hold the current value of the output when setting the hold to Ò1Ó*/\r
-#define RTC_IO_SENSE2_HOLD (BIT(30))\r
-#define RTC_IO_SENSE2_HOLD_M (BIT(30))\r
-#define RTC_IO_SENSE2_HOLD_V 0x1\r
-#define RTC_IO_SENSE2_HOLD_S 30\r
-/* RTC_IO_SENSE3_HOLD : R/W ;bitpos:[29] ;default: 1'd0 ; */\r
-/*description: hold the current value of the output when setting the hold to Ò1Ó*/\r
-#define RTC_IO_SENSE3_HOLD (BIT(29))\r
-#define RTC_IO_SENSE3_HOLD_M (BIT(29))\r
-#define RTC_IO_SENSE3_HOLD_V 0x1\r
-#define RTC_IO_SENSE3_HOLD_S 29\r
-/* RTC_IO_SENSE4_HOLD : R/W ;bitpos:[28] ;default: 1'd0 ; */\r
-/*description: hold the current value of the output when setting the hold to Ò1Ó*/\r
-#define RTC_IO_SENSE4_HOLD (BIT(28))\r
-#define RTC_IO_SENSE4_HOLD_M (BIT(28))\r
-#define RTC_IO_SENSE4_HOLD_V 0x1\r
-#define RTC_IO_SENSE4_HOLD_S 28\r
-/* RTC_IO_SENSE1_MUX_SEL : R/W ;bitpos:[27] ;default: 1'd0 ; */\r
-/*description: Ò1Ó select the digital function Ó0Óslection the rtc function*/\r
-#define RTC_IO_SENSE1_MUX_SEL (BIT(27))\r
-#define RTC_IO_SENSE1_MUX_SEL_M (BIT(27))\r
-#define RTC_IO_SENSE1_MUX_SEL_V 0x1\r
-#define RTC_IO_SENSE1_MUX_SEL_S 27\r
-/* RTC_IO_SENSE2_MUX_SEL : R/W ;bitpos:[26] ;default: 1'd0 ; */\r
-/*description: Ò1Ó select the digital function Ó0Óslection the rtc function*/\r
-#define RTC_IO_SENSE2_MUX_SEL (BIT(26))\r
-#define RTC_IO_SENSE2_MUX_SEL_M (BIT(26))\r
-#define RTC_IO_SENSE2_MUX_SEL_V 0x1\r
-#define RTC_IO_SENSE2_MUX_SEL_S 26\r
-/* RTC_IO_SENSE3_MUX_SEL : R/W ;bitpos:[25] ;default: 1'd0 ; */\r
-/*description: Ò1Ó select the digital function Ó0Óslection the rtc function*/\r
-#define RTC_IO_SENSE3_MUX_SEL (BIT(25))\r
-#define RTC_IO_SENSE3_MUX_SEL_M (BIT(25))\r
-#define RTC_IO_SENSE3_MUX_SEL_V 0x1\r
-#define RTC_IO_SENSE3_MUX_SEL_S 25\r
-/* RTC_IO_SENSE4_MUX_SEL : R/W ;bitpos:[24] ;default: 1'd0 ; */\r
-/*description: Ò1Ó select the digital function Ó0Óslection the rtc function*/\r
-#define RTC_IO_SENSE4_MUX_SEL (BIT(24))\r
-#define RTC_IO_SENSE4_MUX_SEL_M (BIT(24))\r
-#define RTC_IO_SENSE4_MUX_SEL_V 0x1\r
-#define RTC_IO_SENSE4_MUX_SEL_S 24\r
-/* RTC_IO_SENSE1_FUN_SEL : R/W ;bitpos:[23:22] ;default: 2'd0 ; */\r
-/*description: the functional selection signal of the pad*/\r
-#define RTC_IO_SENSE1_FUN_SEL 0x00000003\r
-#define RTC_IO_SENSE1_FUN_SEL_M ((RTC_IO_SENSE1_FUN_SEL_V)<<(RTC_IO_SENSE1_FUN_SEL_S))\r
-#define RTC_IO_SENSE1_FUN_SEL_V 0x3\r
-#define RTC_IO_SENSE1_FUN_SEL_S 22\r
-/* RTC_IO_SENSE1_SLP_SEL : R/W ;bitpos:[21] ;default: 1'd0 ; */\r
-/*description: the sleep status selection signal of the pad*/\r
-#define RTC_IO_SENSE1_SLP_SEL (BIT(21))\r
-#define RTC_IO_SENSE1_SLP_SEL_M (BIT(21))\r
-#define RTC_IO_SENSE1_SLP_SEL_V 0x1\r
-#define RTC_IO_SENSE1_SLP_SEL_S 21\r
-/* RTC_IO_SENSE1_SLP_IE : R/W ;bitpos:[20] ;default: 1'd0 ; */\r
-/*description: the input enable of the pad in sleep status*/\r
-#define RTC_IO_SENSE1_SLP_IE (BIT(20))\r
-#define RTC_IO_SENSE1_SLP_IE_M (BIT(20))\r
-#define RTC_IO_SENSE1_SLP_IE_V 0x1\r
-#define RTC_IO_SENSE1_SLP_IE_S 20\r
-/* RTC_IO_SENSE1_FUN_IE : R/W ;bitpos:[19] ;default: 1'd0 ; */\r
-/*description: the input enable of the pad*/\r
-#define RTC_IO_SENSE1_FUN_IE (BIT(19))\r
-#define RTC_IO_SENSE1_FUN_IE_M (BIT(19))\r
-#define RTC_IO_SENSE1_FUN_IE_V 0x1\r
-#define RTC_IO_SENSE1_FUN_IE_S 19\r
-/* RTC_IO_SENSE2_FUN_SEL : R/W ;bitpos:[18:17] ;default: 2'd0 ; */\r
-/*description: the functional selection signal of the pad*/\r
-#define RTC_IO_SENSE2_FUN_SEL 0x00000003\r
-#define RTC_IO_SENSE2_FUN_SEL_M ((RTC_IO_SENSE2_FUN_SEL_V)<<(RTC_IO_SENSE2_FUN_SEL_S))\r
-#define RTC_IO_SENSE2_FUN_SEL_V 0x3\r
-#define RTC_IO_SENSE2_FUN_SEL_S 17\r
-/* RTC_IO_SENSE2_SLP_SEL : R/W ;bitpos:[16] ;default: 1'd0 ; */\r
-/*description: the sleep status selection signal of the pad*/\r
-#define RTC_IO_SENSE2_SLP_SEL (BIT(16))\r
-#define RTC_IO_SENSE2_SLP_SEL_M (BIT(16))\r
-#define RTC_IO_SENSE2_SLP_SEL_V 0x1\r
-#define RTC_IO_SENSE2_SLP_SEL_S 16\r
-/* RTC_IO_SENSE2_SLP_IE : R/W ;bitpos:[15] ;default: 1'd0 ; */\r
-/*description: the input enable of the pad in sleep status*/\r
-#define RTC_IO_SENSE2_SLP_IE (BIT(15))\r
-#define RTC_IO_SENSE2_SLP_IE_M (BIT(15))\r
-#define RTC_IO_SENSE2_SLP_IE_V 0x1\r
-#define RTC_IO_SENSE2_SLP_IE_S 15\r
-/* RTC_IO_SENSE2_FUN_IE : R/W ;bitpos:[14] ;default: 1'd0 ; */\r
-/*description: the input enable of the pad*/\r
-#define RTC_IO_SENSE2_FUN_IE (BIT(14))\r
-#define RTC_IO_SENSE2_FUN_IE_M (BIT(14))\r
-#define RTC_IO_SENSE2_FUN_IE_V 0x1\r
-#define RTC_IO_SENSE2_FUN_IE_S 14\r
-/* RTC_IO_SENSE3_FUN_SEL : R/W ;bitpos:[13:12] ;default: 2'd0 ; */\r
-/*description: the functional selection signal of the pad*/\r
-#define RTC_IO_SENSE3_FUN_SEL 0x00000003\r
-#define RTC_IO_SENSE3_FUN_SEL_M ((RTC_IO_SENSE3_FUN_SEL_V)<<(RTC_IO_SENSE3_FUN_SEL_S))\r
-#define RTC_IO_SENSE3_FUN_SEL_V 0x3\r
-#define RTC_IO_SENSE3_FUN_SEL_S 12\r
-/* RTC_IO_SENSE3_SLP_SEL : R/W ;bitpos:[11] ;default: 1'd0 ; */\r
-/*description: the sleep status selection signal of the pad*/\r
-#define RTC_IO_SENSE3_SLP_SEL (BIT(11))\r
-#define RTC_IO_SENSE3_SLP_SEL_M (BIT(11))\r
-#define RTC_IO_SENSE3_SLP_SEL_V 0x1\r
-#define RTC_IO_SENSE3_SLP_SEL_S 11\r
-/* RTC_IO_SENSE3_SLP_IE : R/W ;bitpos:[10] ;default: 1'd0 ; */\r
-/*description: the input enable of the pad in sleep status*/\r
-#define RTC_IO_SENSE3_SLP_IE (BIT(10))\r
-#define RTC_IO_SENSE3_SLP_IE_M (BIT(10))\r
-#define RTC_IO_SENSE3_SLP_IE_V 0x1\r
-#define RTC_IO_SENSE3_SLP_IE_S 10\r
-/* RTC_IO_SENSE3_FUN_IE : R/W ;bitpos:[9] ;default: 1'd0 ; */\r
-/*description: the input enable of the pad*/\r
-#define RTC_IO_SENSE3_FUN_IE (BIT(9))\r
-#define RTC_IO_SENSE3_FUN_IE_M (BIT(9))\r
-#define RTC_IO_SENSE3_FUN_IE_V 0x1\r
-#define RTC_IO_SENSE3_FUN_IE_S 9\r
-/* RTC_IO_SENSE4_FUN_SEL : R/W ;bitpos:[8:7] ;default: 2'd0 ; */\r
-/*description: the functional selection signal of the pad*/\r
-#define RTC_IO_SENSE4_FUN_SEL 0x00000003\r
-#define RTC_IO_SENSE4_FUN_SEL_M ((RTC_IO_SENSE4_FUN_SEL_V)<<(RTC_IO_SENSE4_FUN_SEL_S))\r
-#define RTC_IO_SENSE4_FUN_SEL_V 0x3\r
-#define RTC_IO_SENSE4_FUN_SEL_S 7\r
-/* RTC_IO_SENSE4_SLP_SEL : R/W ;bitpos:[6] ;default: 1'd0 ; */\r
-/*description: the sleep status selection signal of the pad*/\r
-#define RTC_IO_SENSE4_SLP_SEL (BIT(6))\r
-#define RTC_IO_SENSE4_SLP_SEL_M (BIT(6))\r
-#define RTC_IO_SENSE4_SLP_SEL_V 0x1\r
-#define RTC_IO_SENSE4_SLP_SEL_S 6\r
-/* RTC_IO_SENSE4_SLP_IE : R/W ;bitpos:[5] ;default: 1'd0 ; */\r
-/*description: the input enable of the pad in sleep status*/\r
-#define RTC_IO_SENSE4_SLP_IE (BIT(5))\r
-#define RTC_IO_SENSE4_SLP_IE_M (BIT(5))\r
-#define RTC_IO_SENSE4_SLP_IE_V 0x1\r
-#define RTC_IO_SENSE4_SLP_IE_S 5\r
-/* RTC_IO_SENSE4_FUN_IE : R/W ;bitpos:[4] ;default: 1'd0 ; */\r
-/*description: the input enable of the pad*/\r
-#define RTC_IO_SENSE4_FUN_IE (BIT(4))\r
-#define RTC_IO_SENSE4_FUN_IE_M (BIT(4))\r
-#define RTC_IO_SENSE4_FUN_IE_V 0x1\r
-#define RTC_IO_SENSE4_FUN_IE_S 4\r
-\r
-#define RTC_IO_ADC_PAD_REG (DR_REG_RTCIO_BASE + 0x80)\r
-/* RTC_IO_ADC1_HOLD : R/W ;bitpos:[31] ;default: 1'd0 ; */\r
-/*description: hold the current value of the output when setting the hold to Ò1Ó*/\r
-#define RTC_IO_ADC1_HOLD (BIT(31))\r
-#define RTC_IO_ADC1_HOLD_M (BIT(31))\r
-#define RTC_IO_ADC1_HOLD_V 0x1\r
-#define RTC_IO_ADC1_HOLD_S 31\r
-/* RTC_IO_ADC2_HOLD : R/W ;bitpos:[30] ;default: 1'd0 ; */\r
-/*description: hold the current value of the output when setting the hold to Ò1Ó*/\r
-#define RTC_IO_ADC2_HOLD (BIT(30))\r
-#define RTC_IO_ADC2_HOLD_M (BIT(30))\r
-#define RTC_IO_ADC2_HOLD_V 0x1\r
-#define RTC_IO_ADC2_HOLD_S 30\r
-/* RTC_IO_ADC1_MUX_SEL : R/W ;bitpos:[29] ;default: 1'd0 ; */\r
-/*description: Ò1Ó select the digital function Ó0Óslection the rtc function*/\r
-#define RTC_IO_ADC1_MUX_SEL (BIT(29))\r
-#define RTC_IO_ADC1_MUX_SEL_M (BIT(29))\r
-#define RTC_IO_ADC1_MUX_SEL_V 0x1\r
-#define RTC_IO_ADC1_MUX_SEL_S 29\r
-/* RTC_IO_ADC2_MUX_SEL : R/W ;bitpos:[28] ;default: 1'd0 ; */\r
-/*description: Ò1Ó select the digital function Ó0Óslection the rtc function*/\r
-#define RTC_IO_ADC2_MUX_SEL (BIT(28))\r
-#define RTC_IO_ADC2_MUX_SEL_M (BIT(28))\r
-#define RTC_IO_ADC2_MUX_SEL_V 0x1\r
-#define RTC_IO_ADC2_MUX_SEL_S 28\r
-/* RTC_IO_ADC1_FUN_SEL : R/W ;bitpos:[27:26] ;default: 2'd0 ; */\r
-/*description: the functional selection signal of the pad*/\r
-#define RTC_IO_ADC1_FUN_SEL 0x00000003\r
-#define RTC_IO_ADC1_FUN_SEL_M ((RTC_IO_ADC1_FUN_SEL_V)<<(RTC_IO_ADC1_FUN_SEL_S))\r
-#define RTC_IO_ADC1_FUN_SEL_V 0x3\r
-#define RTC_IO_ADC1_FUN_SEL_S 26\r
-/* RTC_IO_ADC1_SLP_SEL : R/W ;bitpos:[25] ;default: 1'd0 ; */\r
-/*description: the sleep status selection signal of the pad*/\r
-#define RTC_IO_ADC1_SLP_SEL (BIT(25))\r
-#define RTC_IO_ADC1_SLP_SEL_M (BIT(25))\r
-#define RTC_IO_ADC1_SLP_SEL_V 0x1\r
-#define RTC_IO_ADC1_SLP_SEL_S 25\r
-/* RTC_IO_ADC1_SLP_IE : R/W ;bitpos:[24] ;default: 1'd0 ; */\r
-/*description: the input enable of the pad in sleep status*/\r
-#define RTC_IO_ADC1_SLP_IE (BIT(24))\r
-#define RTC_IO_ADC1_SLP_IE_M (BIT(24))\r
-#define RTC_IO_ADC1_SLP_IE_V 0x1\r
-#define RTC_IO_ADC1_SLP_IE_S 24\r
-/* RTC_IO_ADC1_FUN_IE : R/W ;bitpos:[23] ;default: 1'd0 ; */\r
-/*description: the input enable of the pad*/\r
-#define RTC_IO_ADC1_FUN_IE (BIT(23))\r
-#define RTC_IO_ADC1_FUN_IE_M (BIT(23))\r
-#define RTC_IO_ADC1_FUN_IE_V 0x1\r
-#define RTC_IO_ADC1_FUN_IE_S 23\r
-/* RTC_IO_ADC2_FUN_SEL : R/W ;bitpos:[22:21] ;default: 2'd0 ; */\r
-/*description: the functional selection signal of the pad*/\r
-#define RTC_IO_ADC2_FUN_SEL 0x00000003\r
-#define RTC_IO_ADC2_FUN_SEL_M ((RTC_IO_ADC2_FUN_SEL_V)<<(RTC_IO_ADC2_FUN_SEL_S))\r
-#define RTC_IO_ADC2_FUN_SEL_V 0x3\r
-#define RTC_IO_ADC2_FUN_SEL_S 21\r
-/* RTC_IO_ADC2_SLP_SEL : R/W ;bitpos:[20] ;default: 1'd0 ; */\r
-/*description: the sleep status selection signal of the pad*/\r
-#define RTC_IO_ADC2_SLP_SEL (BIT(20))\r
-#define RTC_IO_ADC2_SLP_SEL_M (BIT(20))\r
-#define RTC_IO_ADC2_SLP_SEL_V 0x1\r
-#define RTC_IO_ADC2_SLP_SEL_S 20\r
-/* RTC_IO_ADC2_SLP_IE : R/W ;bitpos:[19] ;default: 1'd0 ; */\r
-/*description: the input enable of the pad in sleep status*/\r
-#define RTC_IO_ADC2_SLP_IE (BIT(19))\r
-#define RTC_IO_ADC2_SLP_IE_M (BIT(19))\r
-#define RTC_IO_ADC2_SLP_IE_V 0x1\r
-#define RTC_IO_ADC2_SLP_IE_S 19\r
-/* RTC_IO_ADC2_FUN_IE : R/W ;bitpos:[18] ;default: 1'd0 ; */\r
-/*description: the input enable of the pad*/\r
-#define RTC_IO_ADC2_FUN_IE (BIT(18))\r
-#define RTC_IO_ADC2_FUN_IE_M (BIT(18))\r
-#define RTC_IO_ADC2_FUN_IE_V 0x1\r
-#define RTC_IO_ADC2_FUN_IE_S 18\r
-\r
-#define RTC_IO_PAD_DAC1_REG (DR_REG_RTCIO_BASE + 0x84)\r
-/* RTC_IO_PDAC1_DRV : R/W ;bitpos:[31:30] ;default: 2'd2 ; */\r
-/*description: the driver strength of the pad*/\r
-#define RTC_IO_PDAC1_DRV 0x00000003\r
-#define RTC_IO_PDAC1_DRV_M ((RTC_IO_PDAC1_DRV_V)<<(RTC_IO_PDAC1_DRV_S))\r
-#define RTC_IO_PDAC1_DRV_V 0x3\r
-#define RTC_IO_PDAC1_DRV_S 30\r
-/* RTC_IO_PDAC1_HOLD : R/W ;bitpos:[29] ;default: 1'd0 ; */\r
-/*description: hold the current value of the output when setting the hold to Ò1Ó*/\r
-#define RTC_IO_PDAC1_HOLD (BIT(29))\r
-#define RTC_IO_PDAC1_HOLD_M (BIT(29))\r
-#define RTC_IO_PDAC1_HOLD_V 0x1\r
-#define RTC_IO_PDAC1_HOLD_S 29\r
-/* RTC_IO_PDAC1_RDE : R/W ;bitpos:[28] ;default: 1'd0 ; */\r
-/*description: the pull down enable of the pad*/\r
-#define RTC_IO_PDAC1_RDE (BIT(28))\r
-#define RTC_IO_PDAC1_RDE_M (BIT(28))\r
-#define RTC_IO_PDAC1_RDE_V 0x1\r
-#define RTC_IO_PDAC1_RDE_S 28\r
-/* RTC_IO_PDAC1_RUE : R/W ;bitpos:[27] ;default: 1'd0 ; */\r
-/*description: the pull up enable of the pad*/\r
-#define RTC_IO_PDAC1_RUE (BIT(27))\r
-#define RTC_IO_PDAC1_RUE_M (BIT(27))\r
-#define RTC_IO_PDAC1_RUE_V 0x1\r
-#define RTC_IO_PDAC1_RUE_S 27\r
-/* RTC_IO_PDAC1_DAC : R/W ;bitpos:[26:19] ;default: 8'd0 ; */\r
-/*description: PAD DAC1 control code.*/\r
-#define RTC_IO_PDAC1_DAC 0x000000FF\r
-#define RTC_IO_PDAC1_DAC_M ((RTC_IO_PDAC1_DAC_V)<<(RTC_IO_PDAC1_DAC_S))\r
-#define RTC_IO_PDAC1_DAC_V 0xFF\r
-#define RTC_IO_PDAC1_DAC_S 19\r
-/* RTC_IO_PDAC1_XPD_DAC : R/W ;bitpos:[18] ;default: 1'd0 ; */\r
-/*description: Power on DAC1. Usually we need to tristate PDAC1 if we power\r
- on the DAC i.e. IE=0 OE=0 RDE=0 RUE=0*/\r
-#define RTC_IO_PDAC1_XPD_DAC (BIT(18))\r
-#define RTC_IO_PDAC1_XPD_DAC_M (BIT(18))\r
-#define RTC_IO_PDAC1_XPD_DAC_V 0x1\r
-#define RTC_IO_PDAC1_XPD_DAC_S 18\r
-/* RTC_IO_PDAC1_MUX_SEL : R/W ;bitpos:[17] ;default: 1'd0 ; */\r
-/*description: Ò1Ó select the digital function Ó0Óslection the rtc function*/\r
-#define RTC_IO_PDAC1_MUX_SEL (BIT(17))\r
-#define RTC_IO_PDAC1_MUX_SEL_M (BIT(17))\r
-#define RTC_IO_PDAC1_MUX_SEL_V 0x1\r
-#define RTC_IO_PDAC1_MUX_SEL_S 17\r
-/* RTC_IO_PDAC1_FUN_SEL : R/W ;bitpos:[16:15] ;default: 2'd0 ; */\r
-/*description: the functional selection signal of the pad*/\r
-#define RTC_IO_PDAC1_FUN_SEL 0x00000003\r
-#define RTC_IO_PDAC1_FUN_SEL_M ((RTC_IO_PDAC1_FUN_SEL_V)<<(RTC_IO_PDAC1_FUN_SEL_S))\r
-#define RTC_IO_PDAC1_FUN_SEL_V 0x3\r
-#define RTC_IO_PDAC1_FUN_SEL_S 15\r
-/* RTC_IO_PDAC1_SLP_SEL : R/W ;bitpos:[14] ;default: 1'd0 ; */\r
-/*description: the sleep status selection signal of the pad*/\r
-#define RTC_IO_PDAC1_SLP_SEL (BIT(14))\r
-#define RTC_IO_PDAC1_SLP_SEL_M (BIT(14))\r
-#define RTC_IO_PDAC1_SLP_SEL_V 0x1\r
-#define RTC_IO_PDAC1_SLP_SEL_S 14\r
-/* RTC_IO_PDAC1_SLP_IE : R/W ;bitpos:[13] ;default: 1'd0 ; */\r
-/*description: the input enable of the pad in sleep status*/\r
-#define RTC_IO_PDAC1_SLP_IE (BIT(13))\r
-#define RTC_IO_PDAC1_SLP_IE_M (BIT(13))\r
-#define RTC_IO_PDAC1_SLP_IE_V 0x1\r
-#define RTC_IO_PDAC1_SLP_IE_S 13\r
-/* RTC_IO_PDAC1_SLP_OE : R/W ;bitpos:[12] ;default: 1'd0 ; */\r
-/*description: the output enable of the pad in sleep status*/\r
-#define RTC_IO_PDAC1_SLP_OE (BIT(12))\r
-#define RTC_IO_PDAC1_SLP_OE_M (BIT(12))\r
-#define RTC_IO_PDAC1_SLP_OE_V 0x1\r
-#define RTC_IO_PDAC1_SLP_OE_S 12\r
-/* RTC_IO_PDAC1_FUN_IE : R/W ;bitpos:[11] ;default: 1'd0 ; */\r
-/*description: the input enable of the pad*/\r
-#define RTC_IO_PDAC1_FUN_IE (BIT(11))\r
-#define RTC_IO_PDAC1_FUN_IE_M (BIT(11))\r
-#define RTC_IO_PDAC1_FUN_IE_V 0x1\r
-#define RTC_IO_PDAC1_FUN_IE_S 11\r
-/* RTC_IO_PDAC1_DAC_XPD_FORCE : R/W ;bitpos:[10] ;default: 1'd0 ; */\r
-/*description: Power on DAC1. Usually we need to tristate PDAC1 if we power\r
- on the DAC i.e. IE=0 OE=0 RDE=0 RUE=0*/\r
-#define RTC_IO_PDAC1_DAC_XPD_FORCE (BIT(10))\r
-#define RTC_IO_PDAC1_DAC_XPD_FORCE_M (BIT(10))\r
-#define RTC_IO_PDAC1_DAC_XPD_FORCE_V 0x1\r
-#define RTC_IO_PDAC1_DAC_XPD_FORCE_S 10\r
-\r
-#define RTC_IO_PAD_DAC2_REG (DR_REG_RTCIO_BASE + 0x88)\r
-/* RTC_IO_PDAC2_DRV : R/W ;bitpos:[31:30] ;default: 2'd2 ; */\r
-/*description: the driver strength of the pad*/\r
-#define RTC_IO_PDAC2_DRV 0x00000003\r
-#define RTC_IO_PDAC2_DRV_M ((RTC_IO_PDAC2_DRV_V)<<(RTC_IO_PDAC2_DRV_S))\r
-#define RTC_IO_PDAC2_DRV_V 0x3\r
-#define RTC_IO_PDAC2_DRV_S 30\r
-/* RTC_IO_PDAC2_HOLD : R/W ;bitpos:[29] ;default: 1'd0 ; */\r
-/*description: hold the current value of the output when setting the hold to Ò1Ó*/\r
-#define RTC_IO_PDAC2_HOLD (BIT(29))\r
-#define RTC_IO_PDAC2_HOLD_M (BIT(29))\r
-#define RTC_IO_PDAC2_HOLD_V 0x1\r
-#define RTC_IO_PDAC2_HOLD_S 29\r
-/* RTC_IO_PDAC2_RDE : R/W ;bitpos:[28] ;default: 1'd0 ; */\r
-/*description: the pull down enable of the pad*/\r
-#define RTC_IO_PDAC2_RDE (BIT(28))\r
-#define RTC_IO_PDAC2_RDE_M (BIT(28))\r
-#define RTC_IO_PDAC2_RDE_V 0x1\r
-#define RTC_IO_PDAC2_RDE_S 28\r
-/* RTC_IO_PDAC2_RUE : R/W ;bitpos:[27] ;default: 1'd0 ; */\r
-/*description: the pull up enable of the pad*/\r
-#define RTC_IO_PDAC2_RUE (BIT(27))\r
-#define RTC_IO_PDAC2_RUE_M (BIT(27))\r
-#define RTC_IO_PDAC2_RUE_V 0x1\r
-#define RTC_IO_PDAC2_RUE_S 27\r
-/* RTC_IO_PDAC2_DAC : R/W ;bitpos:[26:19] ;default: 8'd0 ; */\r
-/*description: PAD DAC2 control code.*/\r
-#define RTC_IO_PDAC2_DAC 0x000000FF\r
-#define RTC_IO_PDAC2_DAC_M ((RTC_IO_PDAC2_DAC_V)<<(RTC_IO_PDAC2_DAC_S))\r
-#define RTC_IO_PDAC2_DAC_V 0xFF\r
-#define RTC_IO_PDAC2_DAC_S 19\r
-/* RTC_IO_PDAC2_XPD_DAC : R/W ;bitpos:[18] ;default: 1'd0 ; */\r
-/*description: Power on DAC2. Usually we need to tristate PDAC1 if we power\r
- on the DAC i.e. IE=0 OE=0 RDE=0 RUE=0*/\r
-#define RTC_IO_PDAC2_XPD_DAC (BIT(18))\r
-#define RTC_IO_PDAC2_XPD_DAC_M (BIT(18))\r
-#define RTC_IO_PDAC2_XPD_DAC_V 0x1\r
-#define RTC_IO_PDAC2_XPD_DAC_S 18\r
-/* RTC_IO_PDAC2_MUX_SEL : R/W ;bitpos:[17] ;default: 1'd0 ; */\r
-/*description: Ò1Ó select the digital function Ó0Óslection the rtc function*/\r
-#define RTC_IO_PDAC2_MUX_SEL (BIT(17))\r
-#define RTC_IO_PDAC2_MUX_SEL_M (BIT(17))\r
-#define RTC_IO_PDAC2_MUX_SEL_V 0x1\r
-#define RTC_IO_PDAC2_MUX_SEL_S 17\r
-/* RTC_IO_PDAC2_FUN_SEL : R/W ;bitpos:[16:15] ;default: 2'd0 ; */\r
-/*description: the functional selection signal of the pad*/\r
-#define RTC_IO_PDAC2_FUN_SEL 0x00000003\r
-#define RTC_IO_PDAC2_FUN_SEL_M ((RTC_IO_PDAC2_FUN_SEL_V)<<(RTC_IO_PDAC2_FUN_SEL_S))\r
-#define RTC_IO_PDAC2_FUN_SEL_V 0x3\r
-#define RTC_IO_PDAC2_FUN_SEL_S 15\r
-/* RTC_IO_PDAC2_SLP_SEL : R/W ;bitpos:[14] ;default: 1'd0 ; */\r
-/*description: the sleep status selection signal of the pad*/\r
-#define RTC_IO_PDAC2_SLP_SEL (BIT(14))\r
-#define RTC_IO_PDAC2_SLP_SEL_M (BIT(14))\r
-#define RTC_IO_PDAC2_SLP_SEL_V 0x1\r
-#define RTC_IO_PDAC2_SLP_SEL_S 14\r
-/* RTC_IO_PDAC2_SLP_IE : R/W ;bitpos:[13] ;default: 1'd0 ; */\r
-/*description: the input enable of the pad in sleep status*/\r
-#define RTC_IO_PDAC2_SLP_IE (BIT(13))\r
-#define RTC_IO_PDAC2_SLP_IE_M (BIT(13))\r
-#define RTC_IO_PDAC2_SLP_IE_V 0x1\r
-#define RTC_IO_PDAC2_SLP_IE_S 13\r
-/* RTC_IO_PDAC2_SLP_OE : R/W ;bitpos:[12] ;default: 1'd0 ; */\r
-/*description: the output enable of the pad in sleep status*/\r
-#define RTC_IO_PDAC2_SLP_OE (BIT(12))\r
-#define RTC_IO_PDAC2_SLP_OE_M (BIT(12))\r
-#define RTC_IO_PDAC2_SLP_OE_V 0x1\r
-#define RTC_IO_PDAC2_SLP_OE_S 12\r
-/* RTC_IO_PDAC2_FUN_IE : R/W ;bitpos:[11] ;default: 1'd0 ; */\r
-/*description: the input enable of the pad*/\r
-#define RTC_IO_PDAC2_FUN_IE (BIT(11))\r
-#define RTC_IO_PDAC2_FUN_IE_M (BIT(11))\r
-#define RTC_IO_PDAC2_FUN_IE_V 0x1\r
-#define RTC_IO_PDAC2_FUN_IE_S 11\r
-/* RTC_IO_PDAC2_DAC_XPD_FORCE : R/W ;bitpos:[10] ;default: 1'd0 ; */\r
-/*description: Power on DAC2. Usually we need to tristate PDAC2 if we power\r
- on the DAC i.e. IE=0 OE=0 RDE=0 RUE=0*/\r
-#define RTC_IO_PDAC2_DAC_XPD_FORCE (BIT(10))\r
-#define RTC_IO_PDAC2_DAC_XPD_FORCE_M (BIT(10))\r
-#define RTC_IO_PDAC2_DAC_XPD_FORCE_V 0x1\r
-#define RTC_IO_PDAC2_DAC_XPD_FORCE_S 10\r
-\r
-#define RTC_IO_XTAL_32K_PAD_REG (DR_REG_RTCIO_BASE + 0x8c)\r
-/* RTC_IO_X32N_DRV : R/W ;bitpos:[31:30] ;default: 2'd2 ; */\r
-/*description: the driver strength of the pad*/\r
-#define RTC_IO_X32N_DRV 0x00000003\r
-#define RTC_IO_X32N_DRV_M ((RTC_IO_X32N_DRV_V)<<(RTC_IO_X32N_DRV_S))\r
-#define RTC_IO_X32N_DRV_V 0x3\r
-#define RTC_IO_X32N_DRV_S 30\r
-/* RTC_IO_X32N_HOLD : R/W ;bitpos:[29] ;default: 1'd0 ; */\r
-/*description: hold the current value of the output when setting the hold to Ò1Ó*/\r
-#define RTC_IO_X32N_HOLD (BIT(29))\r
-#define RTC_IO_X32N_HOLD_M (BIT(29))\r
-#define RTC_IO_X32N_HOLD_V 0x1\r
-#define RTC_IO_X32N_HOLD_S 29\r
-/* RTC_IO_X32N_RDE : R/W ;bitpos:[28] ;default: 1'd0 ; */\r
-/*description: the pull down enable of the pad*/\r
-#define RTC_IO_X32N_RDE (BIT(28))\r
-#define RTC_IO_X32N_RDE_M (BIT(28))\r
-#define RTC_IO_X32N_RDE_V 0x1\r
-#define RTC_IO_X32N_RDE_S 28\r
-/* RTC_IO_X32N_RUE : R/W ;bitpos:[27] ;default: 1'd0 ; */\r
-/*description: the pull up enable of the pad*/\r
-#define RTC_IO_X32N_RUE (BIT(27))\r
-#define RTC_IO_X32N_RUE_M (BIT(27))\r
-#define RTC_IO_X32N_RUE_V 0x1\r
-#define RTC_IO_X32N_RUE_S 27\r
-/* RTC_IO_X32P_DRV : R/W ;bitpos:[26:25] ;default: 2'd2 ; */\r
-/*description: the driver strength of the pad*/\r
-#define RTC_IO_X32P_DRV 0x00000003\r
-#define RTC_IO_X32P_DRV_M ((RTC_IO_X32P_DRV_V)<<(RTC_IO_X32P_DRV_S))\r
-#define RTC_IO_X32P_DRV_V 0x3\r
-#define RTC_IO_X32P_DRV_S 25\r
-/* RTC_IO_X32P_HOLD : R/W ;bitpos:[24] ;default: 1'd0 ; */\r
-/*description: hold the current value of the output when setting the hold to Ò1Ó*/\r
-#define RTC_IO_X32P_HOLD (BIT(24))\r
-#define RTC_IO_X32P_HOLD_M (BIT(24))\r
-#define RTC_IO_X32P_HOLD_V 0x1\r
-#define RTC_IO_X32P_HOLD_S 24\r
-/* RTC_IO_X32P_RDE : R/W ;bitpos:[23] ;default: 1'd0 ; */\r
-/*description: the pull down enable of the pad*/\r
-#define RTC_IO_X32P_RDE (BIT(23))\r
-#define RTC_IO_X32P_RDE_M (BIT(23))\r
-#define RTC_IO_X32P_RDE_V 0x1\r
-#define RTC_IO_X32P_RDE_S 23\r
-/* RTC_IO_X32P_RUE : R/W ;bitpos:[22] ;default: 1'd0 ; */\r
-/*description: the pull up enable of the pad*/\r
-#define RTC_IO_X32P_RUE (BIT(22))\r
-#define RTC_IO_X32P_RUE_M (BIT(22))\r
-#define RTC_IO_X32P_RUE_V 0x1\r
-#define RTC_IO_X32P_RUE_S 22\r
-/* RTC_IO_DAC_XTAL_32K : R/W ;bitpos:[21:20] ;default: 2'b01 ; */\r
-/*description: 32K XTAL bias current DAC.*/\r
-#define RTC_IO_DAC_XTAL_32K 0x00000003\r
-#define RTC_IO_DAC_XTAL_32K_M ((RTC_IO_DAC_XTAL_32K_V)<<(RTC_IO_DAC_XTAL_32K_S))\r
-#define RTC_IO_DAC_XTAL_32K_V 0x3\r
-#define RTC_IO_DAC_XTAL_32K_S 20\r
-/* RTC_IO_XPD_XTAL_32K : R/W ;bitpos:[19] ;default: 1'd0 ; */\r
-/*description: Power up 32kHz crystal oscillator*/\r
-#define RTC_IO_XPD_XTAL_32K (BIT(19))\r
-#define RTC_IO_XPD_XTAL_32K_M (BIT(19))\r
-#define RTC_IO_XPD_XTAL_32K_V 0x1\r
-#define RTC_IO_XPD_XTAL_32K_S 19\r
-/* RTC_IO_X32N_MUX_SEL : R/W ;bitpos:[18] ;default: 1'd0 ; */\r
-/*description: Ò1Ó select the digital function Ó0Óslection the rtc function*/\r
-#define RTC_IO_X32N_MUX_SEL (BIT(18))\r
-#define RTC_IO_X32N_MUX_SEL_M (BIT(18))\r
-#define RTC_IO_X32N_MUX_SEL_V 0x1\r
-#define RTC_IO_X32N_MUX_SEL_S 18\r
-/* RTC_IO_X32P_MUX_SEL : R/W ;bitpos:[17] ;default: 1'd0 ; */\r
-/*description: Ò1Ó select the digital function Ó0Óslection the rtc function*/\r
-#define RTC_IO_X32P_MUX_SEL (BIT(17))\r
-#define RTC_IO_X32P_MUX_SEL_M (BIT(17))\r
-#define RTC_IO_X32P_MUX_SEL_V 0x1\r
-#define RTC_IO_X32P_MUX_SEL_S 17\r
-/* RTC_IO_X32N_FUN_SEL : R/W ;bitpos:[16:15] ;default: 2'd0 ; */\r
-/*description: the functional selection signal of the pad*/\r
-#define RTC_IO_X32N_FUN_SEL 0x00000003\r
-#define RTC_IO_X32N_FUN_SEL_M ((RTC_IO_X32N_FUN_SEL_V)<<(RTC_IO_X32N_FUN_SEL_S))\r
-#define RTC_IO_X32N_FUN_SEL_V 0x3\r
-#define RTC_IO_X32N_FUN_SEL_S 15\r
-/* RTC_IO_X32N_SLP_SEL : R/W ;bitpos:[14] ;default: 1'd0 ; */\r
-/*description: the sleep status selection signal of the pad*/\r
-#define RTC_IO_X32N_SLP_SEL (BIT(14))\r
-#define RTC_IO_X32N_SLP_SEL_M (BIT(14))\r
-#define RTC_IO_X32N_SLP_SEL_V 0x1\r
-#define RTC_IO_X32N_SLP_SEL_S 14\r
-/* RTC_IO_X32N_SLP_IE : R/W ;bitpos:[13] ;default: 1'd0 ; */\r
-/*description: the input enable of the pad in sleep status*/\r
-#define RTC_IO_X32N_SLP_IE (BIT(13))\r
-#define RTC_IO_X32N_SLP_IE_M (BIT(13))\r
-#define RTC_IO_X32N_SLP_IE_V 0x1\r
-#define RTC_IO_X32N_SLP_IE_S 13\r
-/* RTC_IO_X32N_SLP_OE : R/W ;bitpos:[12] ;default: 1'd0 ; */\r
-/*description: the output enable of the pad in sleep status*/\r
-#define RTC_IO_X32N_SLP_OE (BIT(12))\r
-#define RTC_IO_X32N_SLP_OE_M (BIT(12))\r
-#define RTC_IO_X32N_SLP_OE_V 0x1\r
-#define RTC_IO_X32N_SLP_OE_S 12\r
-/* RTC_IO_X32N_FUN_IE : R/W ;bitpos:[11] ;default: 1'd0 ; */\r
-/*description: the input enable of the pad*/\r
-#define RTC_IO_X32N_FUN_IE (BIT(11))\r
-#define RTC_IO_X32N_FUN_IE_M (BIT(11))\r
-#define RTC_IO_X32N_FUN_IE_V 0x1\r
-#define RTC_IO_X32N_FUN_IE_S 11\r
-/* RTC_IO_X32P_FUN_SEL : R/W ;bitpos:[10:9] ;default: 2'd0 ; */\r
-/*description: the functional selection signal of the pad*/\r
-#define RTC_IO_X32P_FUN_SEL 0x00000003\r
-#define RTC_IO_X32P_FUN_SEL_M ((RTC_IO_X32P_FUN_SEL_V)<<(RTC_IO_X32P_FUN_SEL_S))\r
-#define RTC_IO_X32P_FUN_SEL_V 0x3\r
-#define RTC_IO_X32P_FUN_SEL_S 9\r
-/* RTC_IO_X32P_SLP_SEL : R/W ;bitpos:[8] ;default: 1'd0 ; */\r
-/*description: the sleep status selection signal of the pad*/\r
-#define RTC_IO_X32P_SLP_SEL (BIT(8))\r
-#define RTC_IO_X32P_SLP_SEL_M (BIT(8))\r
-#define RTC_IO_X32P_SLP_SEL_V 0x1\r
-#define RTC_IO_X32P_SLP_SEL_S 8\r
-/* RTC_IO_X32P_SLP_IE : R/W ;bitpos:[7] ;default: 1'd0 ; */\r
-/*description: the input enable of the pad in sleep status*/\r
-#define RTC_IO_X32P_SLP_IE (BIT(7))\r
-#define RTC_IO_X32P_SLP_IE_M (BIT(7))\r
-#define RTC_IO_X32P_SLP_IE_V 0x1\r
-#define RTC_IO_X32P_SLP_IE_S 7\r
-/* RTC_IO_X32P_SLP_OE : R/W ;bitpos:[6] ;default: 1'd0 ; */\r
-/*description: the output enable of the pad in sleep status*/\r
-#define RTC_IO_X32P_SLP_OE (BIT(6))\r
-#define RTC_IO_X32P_SLP_OE_M (BIT(6))\r
-#define RTC_IO_X32P_SLP_OE_V 0x1\r
-#define RTC_IO_X32P_SLP_OE_S 6\r
-/* RTC_IO_X32P_FUN_IE : R/W ;bitpos:[5] ;default: 1'd0 ; */\r
-/*description: the input enable of the pad*/\r
-#define RTC_IO_X32P_FUN_IE (BIT(5))\r
-#define RTC_IO_X32P_FUN_IE_M (BIT(5))\r
-#define RTC_IO_X32P_FUN_IE_V 0x1\r
-#define RTC_IO_X32P_FUN_IE_S 5\r
-/* RTC_IO_DRES_XTAL_32K : R/W ;bitpos:[4:3] ;default: 2'b10 ; */\r
-/*description: 32K XTAL resistor bias control.*/\r
-#define RTC_IO_DRES_XTAL_32K 0x00000003\r
-#define RTC_IO_DRES_XTAL_32K_M ((RTC_IO_DRES_XTAL_32K_V)<<(RTC_IO_DRES_XTAL_32K_S))\r
-#define RTC_IO_DRES_XTAL_32K_V 0x3\r
-#define RTC_IO_DRES_XTAL_32K_S 3\r
-/* RTC_IO_DBIAS_XTAL_32K : R/W ;bitpos:[2:1] ;default: 2'b00 ; */\r
-/*description: 32K XTAL self-bias reference control.*/\r
-#define RTC_IO_DBIAS_XTAL_32K 0x00000003\r
-#define RTC_IO_DBIAS_XTAL_32K_M ((RTC_IO_DBIAS_XTAL_32K_V)<<(RTC_IO_DBIAS_XTAL_32K_S))\r
-#define RTC_IO_DBIAS_XTAL_32K_V 0x3\r
-#define RTC_IO_DBIAS_XTAL_32K_S 1\r
-\r
-#define RTC_IO_TOUCH_CFG_REG (DR_REG_RTCIO_BASE + 0x90)\r
-/* RTC_IO_TOUCH_XPD_BIAS : R/W ;bitpos:[31] ;default: 1'd0 ; */\r
-/*description: touch sensor bias power on.*/\r
-#define RTC_IO_TOUCH_XPD_BIAS (BIT(31))\r
-#define RTC_IO_TOUCH_XPD_BIAS_M (BIT(31))\r
-#define RTC_IO_TOUCH_XPD_BIAS_V 0x1\r
-#define RTC_IO_TOUCH_XPD_BIAS_S 31\r
-/* RTC_IO_TOUCH_DREFH : R/W ;bitpos:[30:29] ;default: 2'b11 ; */\r
-/*description: touch sensor saw wave top voltage.*/\r
-#define RTC_IO_TOUCH_DREFH 0x00000003\r
-#define RTC_IO_TOUCH_DREFH_M ((RTC_IO_TOUCH_DREFH_V)<<(RTC_IO_TOUCH_DREFH_S))\r
-#define RTC_IO_TOUCH_DREFH_V 0x3\r
-#define RTC_IO_TOUCH_DREFH_S 29\r
-/* RTC_IO_TOUCH_DREFL : R/W ;bitpos:[28:27] ;default: 2'b00 ; */\r
-/*description: touch sensor saw wave bottom voltage.*/\r
-#define RTC_IO_TOUCH_DREFL 0x00000003\r
-#define RTC_IO_TOUCH_DREFL_M ((RTC_IO_TOUCH_DREFL_V)<<(RTC_IO_TOUCH_DREFL_S))\r
-#define RTC_IO_TOUCH_DREFL_V 0x3\r
-#define RTC_IO_TOUCH_DREFL_S 27\r
-/* RTC_IO_TOUCH_DRANGE : R/W ;bitpos:[26:25] ;default: 2'b11 ; */\r
-/*description: touch sensor saw wave voltage range.*/\r
-#define RTC_IO_TOUCH_DRANGE 0x00000003\r
-#define RTC_IO_TOUCH_DRANGE_M ((RTC_IO_TOUCH_DRANGE_V)<<(RTC_IO_TOUCH_DRANGE_S))\r
-#define RTC_IO_TOUCH_DRANGE_V 0x3\r
-#define RTC_IO_TOUCH_DRANGE_S 25\r
-/* RTC_IO_TOUCH_DCUR : R/W ;bitpos:[24:23] ;default: 2'b00 ; */\r
-/*description: touch sensor bias current. Should have option to tie with BIAS_SLEEP(When\r
- BIAS_SLEEP this setting is available*/\r
-#define RTC_IO_TOUCH_DCUR 0x00000003\r
-#define RTC_IO_TOUCH_DCUR_M ((RTC_IO_TOUCH_DCUR_V)<<(RTC_IO_TOUCH_DCUR_S))\r
-#define RTC_IO_TOUCH_DCUR_V 0x3\r
-#define RTC_IO_TOUCH_DCUR_S 23\r
-\r
-#define RTC_IO_TOUCH_PAD0_REG (DR_REG_RTCIO_BASE + 0x94)\r
-/* RTC_IO_TOUCH_PAD0_HOLD : R/W ;bitpos:[31] ;default: 1'd0 ; */\r
-/*description: hold the current value of the output when setting the hold to Ò1Ó*/\r
-#define RTC_IO_TOUCH_PAD0_HOLD (BIT(31))\r
-#define RTC_IO_TOUCH_PAD0_HOLD_M (BIT(31))\r
-#define RTC_IO_TOUCH_PAD0_HOLD_V 0x1\r
-#define RTC_IO_TOUCH_PAD0_HOLD_S 31\r
-/* RTC_IO_TOUCH_PAD0_DRV : R/W ;bitpos:[30:29] ;default: 2'd2 ; */\r
-/*description: the driver strength of the pad*/\r
-#define RTC_IO_TOUCH_PAD0_DRV 0x00000003\r
-#define RTC_IO_TOUCH_PAD0_DRV_M ((RTC_IO_TOUCH_PAD0_DRV_V)<<(RTC_IO_TOUCH_PAD0_DRV_S))\r
-#define RTC_IO_TOUCH_PAD0_DRV_V 0x3\r
-#define RTC_IO_TOUCH_PAD0_DRV_S 29\r
-/* RTC_IO_TOUCH_PAD0_RDE : R/W ;bitpos:[28] ;default: 1'd1 ; */\r
-/*description: the pull down enable of the pad*/\r
-#define RTC_IO_TOUCH_PAD0_RDE (BIT(28))\r
-#define RTC_IO_TOUCH_PAD0_RDE_M (BIT(28))\r
-#define RTC_IO_TOUCH_PAD0_RDE_V 0x1\r
-#define RTC_IO_TOUCH_PAD0_RDE_S 28\r
-/* RTC_IO_TOUCH_PAD0_RUE : R/W ;bitpos:[27] ;default: 1'd0 ; */\r
-/*description: the pull up enable of the pad*/\r
-#define RTC_IO_TOUCH_PAD0_RUE (BIT(27))\r
-#define RTC_IO_TOUCH_PAD0_RUE_M (BIT(27))\r
-#define RTC_IO_TOUCH_PAD0_RUE_V 0x1\r
-#define RTC_IO_TOUCH_PAD0_RUE_S 27\r
-/* RTC_IO_TOUCH_PAD0_DAC : R/W ;bitpos:[25:23] ;default: 3'h4 ; */\r
-/*description: touch sensor slope control. 3-bit for each touch panel default 100.*/\r
-#define RTC_IO_TOUCH_PAD0_DAC 0x00000007\r
-#define RTC_IO_TOUCH_PAD0_DAC_M ((RTC_IO_TOUCH_PAD0_DAC_V)<<(RTC_IO_TOUCH_PAD0_DAC_S))\r
-#define RTC_IO_TOUCH_PAD0_DAC_V 0x7\r
-#define RTC_IO_TOUCH_PAD0_DAC_S 23\r
-/* RTC_IO_TOUCH_PAD0_START : R/W ;bitpos:[22] ;default: 1'd0 ; */\r
-/*description: start touch sensor.*/\r
-#define RTC_IO_TOUCH_PAD0_START (BIT(22))\r
-#define RTC_IO_TOUCH_PAD0_START_M (BIT(22))\r
-#define RTC_IO_TOUCH_PAD0_START_V 0x1\r
-#define RTC_IO_TOUCH_PAD0_START_S 22\r
-/* RTC_IO_TOUCH_PAD0_TIE_OPT : R/W ;bitpos:[21] ;default: 1'd0 ; */\r
-/*description: default touch sensor tie option. 0: tie low 1: tie high.*/\r
-#define RTC_IO_TOUCH_PAD0_TIE_OPT (BIT(21))\r
-#define RTC_IO_TOUCH_PAD0_TIE_OPT_M (BIT(21))\r
-#define RTC_IO_TOUCH_PAD0_TIE_OPT_V 0x1\r
-#define RTC_IO_TOUCH_PAD0_TIE_OPT_S 21\r
-/* RTC_IO_TOUCH_PAD0_XPD : R/W ;bitpos:[20] ;default: 1'd0 ; */\r
-/*description: touch sensor power on.*/\r
-#define RTC_IO_TOUCH_PAD0_XPD (BIT(20))\r
-#define RTC_IO_TOUCH_PAD0_XPD_M (BIT(20))\r
-#define RTC_IO_TOUCH_PAD0_XPD_V 0x1\r
-#define RTC_IO_TOUCH_PAD0_XPD_S 20\r
-/* RTC_IO_TOUCH_PAD0_MUX_SEL : R/W ;bitpos:[19] ;default: 1'd0 ; */\r
-/*description: Ò1Ó select the digital function Ó0Óslection the rtc function*/\r
-#define RTC_IO_TOUCH_PAD0_MUX_SEL (BIT(19))\r
-#define RTC_IO_TOUCH_PAD0_MUX_SEL_M (BIT(19))\r
-#define RTC_IO_TOUCH_PAD0_MUX_SEL_V 0x1\r
-#define RTC_IO_TOUCH_PAD0_MUX_SEL_S 19\r
-/* RTC_IO_TOUCH_PAD0_FUN_SEL : R/W ;bitpos:[18:17] ;default: 2'd0 ; */\r
-/*description: the functional selection signal of the pad*/\r
-#define RTC_IO_TOUCH_PAD0_FUN_SEL 0x00000003\r
-#define RTC_IO_TOUCH_PAD0_FUN_SEL_M ((RTC_IO_TOUCH_PAD0_FUN_SEL_V)<<(RTC_IO_TOUCH_PAD0_FUN_SEL_S))\r
-#define RTC_IO_TOUCH_PAD0_FUN_SEL_V 0x3\r
-#define RTC_IO_TOUCH_PAD0_FUN_SEL_S 17\r
-/* RTC_IO_TOUCH_PAD0_SLP_SEL : R/W ;bitpos:[16] ;default: 1'd0 ; */\r
-/*description: the sleep status selection signal of the pad*/\r
-#define RTC_IO_TOUCH_PAD0_SLP_SEL (BIT(16))\r
-#define RTC_IO_TOUCH_PAD0_SLP_SEL_M (BIT(16))\r
-#define RTC_IO_TOUCH_PAD0_SLP_SEL_V 0x1\r
-#define RTC_IO_TOUCH_PAD0_SLP_SEL_S 16\r
-/* RTC_IO_TOUCH_PAD0_SLP_IE : R/W ;bitpos:[15] ;default: 1'd0 ; */\r
-/*description: the input enable of the pad in sleep status*/\r
-#define RTC_IO_TOUCH_PAD0_SLP_IE (BIT(15))\r
-#define RTC_IO_TOUCH_PAD0_SLP_IE_M (BIT(15))\r
-#define RTC_IO_TOUCH_PAD0_SLP_IE_V 0x1\r
-#define RTC_IO_TOUCH_PAD0_SLP_IE_S 15\r
-/* RTC_IO_TOUCH_PAD0_SLP_OE : R/W ;bitpos:[14] ;default: 1'd0 ; */\r
-/*description: the output enable of the pad in sleep status*/\r
-#define RTC_IO_TOUCH_PAD0_SLP_OE (BIT(14))\r
-#define RTC_IO_TOUCH_PAD0_SLP_OE_M (BIT(14))\r
-#define RTC_IO_TOUCH_PAD0_SLP_OE_V 0x1\r
-#define RTC_IO_TOUCH_PAD0_SLP_OE_S 14\r
-/* RTC_IO_TOUCH_PAD0_FUN_IE : R/W ;bitpos:[13] ;default: 1'd0 ; */\r
-/*description: the input enable of the pad*/\r
-#define RTC_IO_TOUCH_PAD0_FUN_IE (BIT(13))\r
-#define RTC_IO_TOUCH_PAD0_FUN_IE_M (BIT(13))\r
-#define RTC_IO_TOUCH_PAD0_FUN_IE_V 0x1\r
-#define RTC_IO_TOUCH_PAD0_FUN_IE_S 13\r
-/* RTC_IO_TOUCH_PAD0_TO_GPIO : R/W ;bitpos:[12] ;default: 1'd0 ; */\r
-/*description: connect the rtc pad input to digital pad input Ó0Ó is availbale GPIO4*/\r
-#define RTC_IO_TOUCH_PAD0_TO_GPIO (BIT(12))\r
-#define RTC_IO_TOUCH_PAD0_TO_GPIO_M (BIT(12))\r
-#define RTC_IO_TOUCH_PAD0_TO_GPIO_V 0x1\r
-#define RTC_IO_TOUCH_PAD0_TO_GPIO_S 12\r
-\r
-#define RTC_IO_TOUCH_PAD1_REG (DR_REG_RTCIO_BASE + 0x98)\r
-/* RTC_IO_TOUCH_PAD1_HOLD : R/W ;bitpos:[31] ;default: 1'd0 ; */\r
-/*description: */\r
-#define RTC_IO_TOUCH_PAD1_HOLD (BIT(31))\r
-#define RTC_IO_TOUCH_PAD1_HOLD_M (BIT(31))\r
-#define RTC_IO_TOUCH_PAD1_HOLD_V 0x1\r
-#define RTC_IO_TOUCH_PAD1_HOLD_S 31\r
-/* RTC_IO_TOUCH_PAD1_DRV : R/W ;bitpos:[30:29] ;default: 2'd2 ; */\r
-/*description: the driver strength of the pad*/\r
-#define RTC_IO_TOUCH_PAD1_DRV 0x00000003\r
-#define RTC_IO_TOUCH_PAD1_DRV_M ((RTC_IO_TOUCH_PAD1_DRV_V)<<(RTC_IO_TOUCH_PAD1_DRV_S))\r
-#define RTC_IO_TOUCH_PAD1_DRV_V 0x3\r
-#define RTC_IO_TOUCH_PAD1_DRV_S 29\r
-/* RTC_IO_TOUCH_PAD1_RDE : R/W ;bitpos:[28] ;default: 1'd0 ; */\r
-/*description: the pull down enable of the pad*/\r
-#define RTC_IO_TOUCH_PAD1_RDE (BIT(28))\r
-#define RTC_IO_TOUCH_PAD1_RDE_M (BIT(28))\r
-#define RTC_IO_TOUCH_PAD1_RDE_V 0x1\r
-#define RTC_IO_TOUCH_PAD1_RDE_S 28\r
-/* RTC_IO_TOUCH_PAD1_RUE : R/W ;bitpos:[27] ;default: 1'd1 ; */\r
-/*description: the pull up enable of the pad*/\r
-#define RTC_IO_TOUCH_PAD1_RUE (BIT(27))\r
-#define RTC_IO_TOUCH_PAD1_RUE_M (BIT(27))\r
-#define RTC_IO_TOUCH_PAD1_RUE_V 0x1\r
-#define RTC_IO_TOUCH_PAD1_RUE_S 27\r
-/* RTC_IO_TOUCH_PAD1_DAC : R/W ;bitpos:[25:23] ;default: 3'h4 ; */\r
-/*description: touch sensor slope control. 3-bit for each touch panel default 100.*/\r
-#define RTC_IO_TOUCH_PAD1_DAC 0x00000007\r
-#define RTC_IO_TOUCH_PAD1_DAC_M ((RTC_IO_TOUCH_PAD1_DAC_V)<<(RTC_IO_TOUCH_PAD1_DAC_S))\r
-#define RTC_IO_TOUCH_PAD1_DAC_V 0x7\r
-#define RTC_IO_TOUCH_PAD1_DAC_S 23\r
-/* RTC_IO_TOUCH_PAD1_START : R/W ;bitpos:[22] ;default: 1'd0 ; */\r
-/*description: start touch sensor.*/\r
-#define RTC_IO_TOUCH_PAD1_START (BIT(22))\r
-#define RTC_IO_TOUCH_PAD1_START_M (BIT(22))\r
-#define RTC_IO_TOUCH_PAD1_START_V 0x1\r
-#define RTC_IO_TOUCH_PAD1_START_S 22\r
-/* RTC_IO_TOUCH_PAD1_TIE_OPT : R/W ;bitpos:[21] ;default: 1'd0 ; */\r
-/*description: default touch sensor tie option. 0: tie low 1: tie high.*/\r
-#define RTC_IO_TOUCH_PAD1_TIE_OPT (BIT(21))\r
-#define RTC_IO_TOUCH_PAD1_TIE_OPT_M (BIT(21))\r
-#define RTC_IO_TOUCH_PAD1_TIE_OPT_V 0x1\r
-#define RTC_IO_TOUCH_PAD1_TIE_OPT_S 21\r
-/* RTC_IO_TOUCH_PAD1_XPD : R/W ;bitpos:[20] ;default: 1'd0 ; */\r
-/*description: touch sensor power on.*/\r
-#define RTC_IO_TOUCH_PAD1_XPD (BIT(20))\r
-#define RTC_IO_TOUCH_PAD1_XPD_M (BIT(20))\r
-#define RTC_IO_TOUCH_PAD1_XPD_V 0x1\r
-#define RTC_IO_TOUCH_PAD1_XPD_S 20\r
-/* RTC_IO_TOUCH_PAD1_MUX_SEL : R/W ;bitpos:[19] ;default: 1'd0 ; */\r
-/*description: Ò1Ó select the digital function Ó0Óslection the rtc function*/\r
-#define RTC_IO_TOUCH_PAD1_MUX_SEL (BIT(19))\r
-#define RTC_IO_TOUCH_PAD1_MUX_SEL_M (BIT(19))\r
-#define RTC_IO_TOUCH_PAD1_MUX_SEL_V 0x1\r
-#define RTC_IO_TOUCH_PAD1_MUX_SEL_S 19\r
-/* RTC_IO_TOUCH_PAD1_FUN_SEL : R/W ;bitpos:[18:17] ;default: 2'd0 ; */\r
-/*description: the functional selection signal of the pad*/\r
-#define RTC_IO_TOUCH_PAD1_FUN_SEL 0x00000003\r
-#define RTC_IO_TOUCH_PAD1_FUN_SEL_M ((RTC_IO_TOUCH_PAD1_FUN_SEL_V)<<(RTC_IO_TOUCH_PAD1_FUN_SEL_S))\r
-#define RTC_IO_TOUCH_PAD1_FUN_SEL_V 0x3\r
-#define RTC_IO_TOUCH_PAD1_FUN_SEL_S 17\r
-/* RTC_IO_TOUCH_PAD1_SLP_SEL : R/W ;bitpos:[16] ;default: 1'd0 ; */\r
-/*description: the sleep status selection signal of the pad*/\r
-#define RTC_IO_TOUCH_PAD1_SLP_SEL (BIT(16))\r
-#define RTC_IO_TOUCH_PAD1_SLP_SEL_M (BIT(16))\r
-#define RTC_IO_TOUCH_PAD1_SLP_SEL_V 0x1\r
-#define RTC_IO_TOUCH_PAD1_SLP_SEL_S 16\r
-/* RTC_IO_TOUCH_PAD1_SLP_IE : R/W ;bitpos:[15] ;default: 1'd0 ; */\r
-/*description: the input enable of the pad in sleep status*/\r
-#define RTC_IO_TOUCH_PAD1_SLP_IE (BIT(15))\r
-#define RTC_IO_TOUCH_PAD1_SLP_IE_M (BIT(15))\r
-#define RTC_IO_TOUCH_PAD1_SLP_IE_V 0x1\r
-#define RTC_IO_TOUCH_PAD1_SLP_IE_S 15\r
-/* RTC_IO_TOUCH_PAD1_SLP_OE : R/W ;bitpos:[14] ;default: 1'd0 ; */\r
-/*description: the output enable of the pad in sleep status*/\r
-#define RTC_IO_TOUCH_PAD1_SLP_OE (BIT(14))\r
-#define RTC_IO_TOUCH_PAD1_SLP_OE_M (BIT(14))\r
-#define RTC_IO_TOUCH_PAD1_SLP_OE_V 0x1\r
-#define RTC_IO_TOUCH_PAD1_SLP_OE_S 14\r
-/* RTC_IO_TOUCH_PAD1_FUN_IE : R/W ;bitpos:[13] ;default: 1'd0 ; */\r
-/*description: the input enable of the pad*/\r
-#define RTC_IO_TOUCH_PAD1_FUN_IE (BIT(13))\r
-#define RTC_IO_TOUCH_PAD1_FUN_IE_M (BIT(13))\r
-#define RTC_IO_TOUCH_PAD1_FUN_IE_V 0x1\r
-#define RTC_IO_TOUCH_PAD1_FUN_IE_S 13\r
-/* RTC_IO_TOUCH_PAD1_TO_GPIO : R/W ;bitpos:[12] ;default: 1'd0 ; */\r
-/*description: connect the rtc pad input to digital pad input Ó0Ó is availbale.GPIO0*/\r
-#define RTC_IO_TOUCH_PAD1_TO_GPIO (BIT(12))\r
-#define RTC_IO_TOUCH_PAD1_TO_GPIO_M (BIT(12))\r
-#define RTC_IO_TOUCH_PAD1_TO_GPIO_V 0x1\r
-#define RTC_IO_TOUCH_PAD1_TO_GPIO_S 12\r
-\r
-#define RTC_IO_TOUCH_PAD2_REG (DR_REG_RTCIO_BASE + 0x9c)\r
-/* RTC_IO_TOUCH_PAD2_HOLD : R/W ;bitpos:[31] ;default: 1'd0 ; */\r
-/*description: hold the current value of the output when setting the hold to Ò1Ó*/\r
-#define RTC_IO_TOUCH_PAD2_HOLD (BIT(31))\r
-#define RTC_IO_TOUCH_PAD2_HOLD_M (BIT(31))\r
-#define RTC_IO_TOUCH_PAD2_HOLD_V 0x1\r
-#define RTC_IO_TOUCH_PAD2_HOLD_S 31\r
-/* RTC_IO_TOUCH_PAD2_DRV : R/W ;bitpos:[30:29] ;default: 2'd2 ; */\r
-/*description: the driver strength of the pad*/\r
-#define RTC_IO_TOUCH_PAD2_DRV 0x00000003\r
-#define RTC_IO_TOUCH_PAD2_DRV_M ((RTC_IO_TOUCH_PAD2_DRV_V)<<(RTC_IO_TOUCH_PAD2_DRV_S))\r
-#define RTC_IO_TOUCH_PAD2_DRV_V 0x3\r
-#define RTC_IO_TOUCH_PAD2_DRV_S 29\r
-/* RTC_IO_TOUCH_PAD2_RDE : R/W ;bitpos:[28] ;default: 1'd1 ; */\r
-/*description: the pull down enable of the pad*/\r
-#define RTC_IO_TOUCH_PAD2_RDE (BIT(28))\r
-#define RTC_IO_TOUCH_PAD2_RDE_M (BIT(28))\r
-#define RTC_IO_TOUCH_PAD2_RDE_V 0x1\r
-#define RTC_IO_TOUCH_PAD2_RDE_S 28\r
-/* RTC_IO_TOUCH_PAD2_RUE : R/W ;bitpos:[27] ;default: 1'd0 ; */\r
-/*description: the pull up enable of the pad*/\r
-#define RTC_IO_TOUCH_PAD2_RUE (BIT(27))\r
-#define RTC_IO_TOUCH_PAD2_RUE_M (BIT(27))\r
-#define RTC_IO_TOUCH_PAD2_RUE_V 0x1\r
-#define RTC_IO_TOUCH_PAD2_RUE_S 27\r
-/* RTC_IO_TOUCH_PAD2_DAC : R/W ;bitpos:[25:23] ;default: 3'h4 ; */\r
-/*description: touch sensor slope control. 3-bit for each touch panel default 100.*/\r
-#define RTC_IO_TOUCH_PAD2_DAC 0x00000007\r
-#define RTC_IO_TOUCH_PAD2_DAC_M ((RTC_IO_TOUCH_PAD2_DAC_V)<<(RTC_IO_TOUCH_PAD2_DAC_S))\r
-#define RTC_IO_TOUCH_PAD2_DAC_V 0x7\r
-#define RTC_IO_TOUCH_PAD2_DAC_S 23\r
-/* RTC_IO_TOUCH_PAD2_START : R/W ;bitpos:[22] ;default: 1'd0 ; */\r
-/*description: start touch sensor.*/\r
-#define RTC_IO_TOUCH_PAD2_START (BIT(22))\r
-#define RTC_IO_TOUCH_PAD2_START_M (BIT(22))\r
-#define RTC_IO_TOUCH_PAD2_START_V 0x1\r
-#define RTC_IO_TOUCH_PAD2_START_S 22\r
-/* RTC_IO_TOUCH_PAD2_TIE_OPT : R/W ;bitpos:[21] ;default: 1'd0 ; */\r
-/*description: default touch sensor tie option. 0: tie low 1: tie high.*/\r
-#define RTC_IO_TOUCH_PAD2_TIE_OPT (BIT(21))\r
-#define RTC_IO_TOUCH_PAD2_TIE_OPT_M (BIT(21))\r
-#define RTC_IO_TOUCH_PAD2_TIE_OPT_V 0x1\r
-#define RTC_IO_TOUCH_PAD2_TIE_OPT_S 21\r
-/* RTC_IO_TOUCH_PAD2_XPD : R/W ;bitpos:[20] ;default: 1'd0 ; */\r
-/*description: touch sensor power on.*/\r
-#define RTC_IO_TOUCH_PAD2_XPD (BIT(20))\r
-#define RTC_IO_TOUCH_PAD2_XPD_M (BIT(20))\r
-#define RTC_IO_TOUCH_PAD2_XPD_V 0x1\r
-#define RTC_IO_TOUCH_PAD2_XPD_S 20\r
-/* RTC_IO_TOUCH_PAD2_MUX_SEL : R/W ;bitpos:[19] ;default: 1'd0 ; */\r
-/*description: Ò1Ó select the digital function Ó0Óslection the rtc function*/\r
-#define RTC_IO_TOUCH_PAD2_MUX_SEL (BIT(19))\r
-#define RTC_IO_TOUCH_PAD2_MUX_SEL_M (BIT(19))\r
-#define RTC_IO_TOUCH_PAD2_MUX_SEL_V 0x1\r
-#define RTC_IO_TOUCH_PAD2_MUX_SEL_S 19\r
-/* RTC_IO_TOUCH_PAD2_FUN_SEL : R/W ;bitpos:[18:17] ;default: 2'd0 ; */\r
-/*description: the functional selection signal of the pad*/\r
-#define RTC_IO_TOUCH_PAD2_FUN_SEL 0x00000003\r
-#define RTC_IO_TOUCH_PAD2_FUN_SEL_M ((RTC_IO_TOUCH_PAD2_FUN_SEL_V)<<(RTC_IO_TOUCH_PAD2_FUN_SEL_S))\r
-#define RTC_IO_TOUCH_PAD2_FUN_SEL_V 0x3\r
-#define RTC_IO_TOUCH_PAD2_FUN_SEL_S 17\r
-/* RTC_IO_TOUCH_PAD2_SLP_SEL : R/W ;bitpos:[16] ;default: 1'd0 ; */\r
-/*description: the sleep status selection signal of the pad*/\r
-#define RTC_IO_TOUCH_PAD2_SLP_SEL (BIT(16))\r
-#define RTC_IO_TOUCH_PAD2_SLP_SEL_M (BIT(16))\r
-#define RTC_IO_TOUCH_PAD2_SLP_SEL_V 0x1\r
-#define RTC_IO_TOUCH_PAD2_SLP_SEL_S 16\r
-/* RTC_IO_TOUCH_PAD2_SLP_IE : R/W ;bitpos:[15] ;default: 1'd0 ; */\r
-/*description: the input enable of the pad in sleep status*/\r
-#define RTC_IO_TOUCH_PAD2_SLP_IE (BIT(15))\r
-#define RTC_IO_TOUCH_PAD2_SLP_IE_M (BIT(15))\r
-#define RTC_IO_TOUCH_PAD2_SLP_IE_V 0x1\r
-#define RTC_IO_TOUCH_PAD2_SLP_IE_S 15\r
-/* RTC_IO_TOUCH_PAD2_SLP_OE : R/W ;bitpos:[14] ;default: 1'd0 ; */\r
-/*description: the output enable of the pad in sleep status*/\r
-#define RTC_IO_TOUCH_PAD2_SLP_OE (BIT(14))\r
-#define RTC_IO_TOUCH_PAD2_SLP_OE_M (BIT(14))\r
-#define RTC_IO_TOUCH_PAD2_SLP_OE_V 0x1\r
-#define RTC_IO_TOUCH_PAD2_SLP_OE_S 14\r
-/* RTC_IO_TOUCH_PAD2_FUN_IE : R/W ;bitpos:[13] ;default: 1'd0 ; */\r
-/*description: the input enable of the pad*/\r
-#define RTC_IO_TOUCH_PAD2_FUN_IE (BIT(13))\r
-#define RTC_IO_TOUCH_PAD2_FUN_IE_M (BIT(13))\r
-#define RTC_IO_TOUCH_PAD2_FUN_IE_V 0x1\r
-#define RTC_IO_TOUCH_PAD2_FUN_IE_S 13\r
-/* RTC_IO_TOUCH_PAD2_TO_GPIO : R/W ;bitpos:[12] ;default: 1'd0 ; */\r
-/*description: connect the rtc pad input to digital pad input Ó0Ó is availbale.GPIO2*/\r
-#define RTC_IO_TOUCH_PAD2_TO_GPIO (BIT(12))\r
-#define RTC_IO_TOUCH_PAD2_TO_GPIO_M (BIT(12))\r
-#define RTC_IO_TOUCH_PAD2_TO_GPIO_V 0x1\r
-#define RTC_IO_TOUCH_PAD2_TO_GPIO_S 12\r
-\r
-#define RTC_IO_TOUCH_PAD3_REG (DR_REG_RTCIO_BASE + 0xa0)\r
-/* RTC_IO_TOUCH_PAD3_HOLD : R/W ;bitpos:[31] ;default: 1'd0 ; */\r
-/*description: hold the current value of the output when setting the hold to Ò1Ó*/\r
-#define RTC_IO_TOUCH_PAD3_HOLD (BIT(31))\r
-#define RTC_IO_TOUCH_PAD3_HOLD_M (BIT(31))\r
-#define RTC_IO_TOUCH_PAD3_HOLD_V 0x1\r
-#define RTC_IO_TOUCH_PAD3_HOLD_S 31\r
-/* RTC_IO_TOUCH_PAD3_DRV : R/W ;bitpos:[30:29] ;default: 2'd2 ; */\r
-/*description: the driver strength of the pad*/\r
-#define RTC_IO_TOUCH_PAD3_DRV 0x00000003\r
-#define RTC_IO_TOUCH_PAD3_DRV_M ((RTC_IO_TOUCH_PAD3_DRV_V)<<(RTC_IO_TOUCH_PAD3_DRV_S))\r
-#define RTC_IO_TOUCH_PAD3_DRV_V 0x3\r
-#define RTC_IO_TOUCH_PAD3_DRV_S 29\r
-/* RTC_IO_TOUCH_PAD3_RDE : R/W ;bitpos:[28] ;default: 1'd0 ; */\r
-/*description: the pull down enable of the pad*/\r
-#define RTC_IO_TOUCH_PAD3_RDE (BIT(28))\r
-#define RTC_IO_TOUCH_PAD3_RDE_M (BIT(28))\r
-#define RTC_IO_TOUCH_PAD3_RDE_V 0x1\r
-#define RTC_IO_TOUCH_PAD3_RDE_S 28\r
-/* RTC_IO_TOUCH_PAD3_RUE : R/W ;bitpos:[27] ;default: 1'd1 ; */\r
-/*description: the pull up enable of the pad*/\r
-#define RTC_IO_TOUCH_PAD3_RUE (BIT(27))\r
-#define RTC_IO_TOUCH_PAD3_RUE_M (BIT(27))\r
-#define RTC_IO_TOUCH_PAD3_RUE_V 0x1\r
-#define RTC_IO_TOUCH_PAD3_RUE_S 27\r
-/* RTC_IO_TOUCH_PAD3_DAC : R/W ;bitpos:[25:23] ;default: 3'h4 ; */\r
-/*description: touch sensor slope control. 3-bit for each touch panel default 100.*/\r
-#define RTC_IO_TOUCH_PAD3_DAC 0x00000007\r
-#define RTC_IO_TOUCH_PAD3_DAC_M ((RTC_IO_TOUCH_PAD3_DAC_V)<<(RTC_IO_TOUCH_PAD3_DAC_S))\r
-#define RTC_IO_TOUCH_PAD3_DAC_V 0x7\r
-#define RTC_IO_TOUCH_PAD3_DAC_S 23\r
-/* RTC_IO_TOUCH_PAD3_START : R/W ;bitpos:[22] ;default: 1'd0 ; */\r
-/*description: start touch sensor.*/\r
-#define RTC_IO_TOUCH_PAD3_START (BIT(22))\r
-#define RTC_IO_TOUCH_PAD3_START_M (BIT(22))\r
-#define RTC_IO_TOUCH_PAD3_START_V 0x1\r
-#define RTC_IO_TOUCH_PAD3_START_S 22\r
-/* RTC_IO_TOUCH_PAD3_TIE_OPT : R/W ;bitpos:[21] ;default: 1'd0 ; */\r
-/*description: default touch sensor tie option. 0: tie low 1: tie high.*/\r
-#define RTC_IO_TOUCH_PAD3_TIE_OPT (BIT(21))\r
-#define RTC_IO_TOUCH_PAD3_TIE_OPT_M (BIT(21))\r
-#define RTC_IO_TOUCH_PAD3_TIE_OPT_V 0x1\r
-#define RTC_IO_TOUCH_PAD3_TIE_OPT_S 21\r
-/* RTC_IO_TOUCH_PAD3_XPD : R/W ;bitpos:[20] ;default: 1'd0 ; */\r
-/*description: touch sensor power on.*/\r
-#define RTC_IO_TOUCH_PAD3_XPD (BIT(20))\r
-#define RTC_IO_TOUCH_PAD3_XPD_M (BIT(20))\r
-#define RTC_IO_TOUCH_PAD3_XPD_V 0x1\r
-#define RTC_IO_TOUCH_PAD3_XPD_S 20\r
-/* RTC_IO_TOUCH_PAD3_MUX_SEL : R/W ;bitpos:[19] ;default: 1'd0 ; */\r
-/*description: Ò1Ó select the digital function Ó0Óslection the rtc function*/\r
-#define RTC_IO_TOUCH_PAD3_MUX_SEL (BIT(19))\r
-#define RTC_IO_TOUCH_PAD3_MUX_SEL_M (BIT(19))\r
-#define RTC_IO_TOUCH_PAD3_MUX_SEL_V 0x1\r
-#define RTC_IO_TOUCH_PAD3_MUX_SEL_S 19\r
-/* RTC_IO_TOUCH_PAD3_FUN_SEL : R/W ;bitpos:[18:17] ;default: 2'd0 ; */\r
-/*description: the functional selection signal of the pad*/\r
-#define RTC_IO_TOUCH_PAD3_FUN_SEL 0x00000003\r
-#define RTC_IO_TOUCH_PAD3_FUN_SEL_M ((RTC_IO_TOUCH_PAD3_FUN_SEL_V)<<(RTC_IO_TOUCH_PAD3_FUN_SEL_S))\r
-#define RTC_IO_TOUCH_PAD3_FUN_SEL_V 0x3\r
-#define RTC_IO_TOUCH_PAD3_FUN_SEL_S 17\r
-/* RTC_IO_TOUCH_PAD3_SLP_SEL : R/W ;bitpos:[16] ;default: 1'd0 ; */\r
-/*description: the sleep status selection signal of the pad*/\r
-#define RTC_IO_TOUCH_PAD3_SLP_SEL (BIT(16))\r
-#define RTC_IO_TOUCH_PAD3_SLP_SEL_M (BIT(16))\r
-#define RTC_IO_TOUCH_PAD3_SLP_SEL_V 0x1\r
-#define RTC_IO_TOUCH_PAD3_SLP_SEL_S 16\r
-/* RTC_IO_TOUCH_PAD3_SLP_IE : R/W ;bitpos:[15] ;default: 1'd0 ; */\r
-/*description: the input enable of the pad in sleep status*/\r
-#define RTC_IO_TOUCH_PAD3_SLP_IE (BIT(15))\r
-#define RTC_IO_TOUCH_PAD3_SLP_IE_M (BIT(15))\r
-#define RTC_IO_TOUCH_PAD3_SLP_IE_V 0x1\r
-#define RTC_IO_TOUCH_PAD3_SLP_IE_S 15\r
-/* RTC_IO_TOUCH_PAD3_SLP_OE : R/W ;bitpos:[14] ;default: 1'd0 ; */\r
-/*description: the output enable of the pad in sleep status*/\r
-#define RTC_IO_TOUCH_PAD3_SLP_OE (BIT(14))\r
-#define RTC_IO_TOUCH_PAD3_SLP_OE_M (BIT(14))\r
-#define RTC_IO_TOUCH_PAD3_SLP_OE_V 0x1\r
-#define RTC_IO_TOUCH_PAD3_SLP_OE_S 14\r
-/* RTC_IO_TOUCH_PAD3_FUN_IE : R/W ;bitpos:[13] ;default: 1'd0 ; */\r
-/*description: the input enable of the pad*/\r
-#define RTC_IO_TOUCH_PAD3_FUN_IE (BIT(13))\r
-#define RTC_IO_TOUCH_PAD3_FUN_IE_M (BIT(13))\r
-#define RTC_IO_TOUCH_PAD3_FUN_IE_V 0x1\r
-#define RTC_IO_TOUCH_PAD3_FUN_IE_S 13\r
-/* RTC_IO_TOUCH_PAD3_TO_GPIO : R/W ;bitpos:[12] ;default: 1'd0 ; */\r
-/*description: connect the rtc pad input to digital pad input Ó0Ó is availbale.MTDO*/\r
-#define RTC_IO_TOUCH_PAD3_TO_GPIO (BIT(12))\r
-#define RTC_IO_TOUCH_PAD3_TO_GPIO_M (BIT(12))\r
-#define RTC_IO_TOUCH_PAD3_TO_GPIO_V 0x1\r
-#define RTC_IO_TOUCH_PAD3_TO_GPIO_S 12\r
-\r
-#define RTC_IO_TOUCH_PAD4_REG (DR_REG_RTCIO_BASE + 0xa4)\r
-/* RTC_IO_TOUCH_PAD4_HOLD : R/W ;bitpos:[31] ;default: 1'd0 ; */\r
-/*description: hold the current value of the output when setting the hold to Ò1Ó*/\r
-#define RTC_IO_TOUCH_PAD4_HOLD (BIT(31))\r
-#define RTC_IO_TOUCH_PAD4_HOLD_M (BIT(31))\r
-#define RTC_IO_TOUCH_PAD4_HOLD_V 0x1\r
-#define RTC_IO_TOUCH_PAD4_HOLD_S 31\r
-/* RTC_IO_TOUCH_PAD4_DRV : R/W ;bitpos:[30:29] ;default: 2'd2 ; */\r
-/*description: the driver strength of the pad*/\r
-#define RTC_IO_TOUCH_PAD4_DRV 0x00000003\r
-#define RTC_IO_TOUCH_PAD4_DRV_M ((RTC_IO_TOUCH_PAD4_DRV_V)<<(RTC_IO_TOUCH_PAD4_DRV_S))\r
-#define RTC_IO_TOUCH_PAD4_DRV_V 0x3\r
-#define RTC_IO_TOUCH_PAD4_DRV_S 29\r
-/* RTC_IO_TOUCH_PAD4_RDE : R/W ;bitpos:[28] ;default: 1'd1 ; */\r
-/*description: the pull down enable of the pad*/\r
-#define RTC_IO_TOUCH_PAD4_RDE (BIT(28))\r
-#define RTC_IO_TOUCH_PAD4_RDE_M (BIT(28))\r
-#define RTC_IO_TOUCH_PAD4_RDE_V 0x1\r
-#define RTC_IO_TOUCH_PAD4_RDE_S 28\r
-/* RTC_IO_TOUCH_PAD4_RUE : R/W ;bitpos:[27] ;default: 1'd0 ; */\r
-/*description: the pull up enable of the pad*/\r
-#define RTC_IO_TOUCH_PAD4_RUE (BIT(27))\r
-#define RTC_IO_TOUCH_PAD4_RUE_M (BIT(27))\r
-#define RTC_IO_TOUCH_PAD4_RUE_V 0x1\r
-#define RTC_IO_TOUCH_PAD4_RUE_S 27\r
-/* RTC_IO_TOUCH_PAD4_DAC : R/W ;bitpos:[25:23] ;default: 3'h4 ; */\r
-/*description: touch sensor slope control. 3-bit for each touch panel default 100.*/\r
-#define RTC_IO_TOUCH_PAD4_DAC 0x00000007\r
-#define RTC_IO_TOUCH_PAD4_DAC_M ((RTC_IO_TOUCH_PAD4_DAC_V)<<(RTC_IO_TOUCH_PAD4_DAC_S))\r
-#define RTC_IO_TOUCH_PAD4_DAC_V 0x7\r
-#define RTC_IO_TOUCH_PAD4_DAC_S 23\r
-/* RTC_IO_TOUCH_PAD4_START : R/W ;bitpos:[22] ;default: 1'd0 ; */\r
-/*description: start touch sensor.*/\r
-#define RTC_IO_TOUCH_PAD4_START (BIT(22))\r
-#define RTC_IO_TOUCH_PAD4_START_M (BIT(22))\r
-#define RTC_IO_TOUCH_PAD4_START_V 0x1\r
-#define RTC_IO_TOUCH_PAD4_START_S 22\r
-/* RTC_IO_TOUCH_PAD4_TIE_OPT : R/W ;bitpos:[21] ;default: 1'd0 ; */\r
-/*description: default touch sensor tie option. 0: tie low 1: tie high.*/\r
-#define RTC_IO_TOUCH_PAD4_TIE_OPT (BIT(21))\r
-#define RTC_IO_TOUCH_PAD4_TIE_OPT_M (BIT(21))\r
-#define RTC_IO_TOUCH_PAD4_TIE_OPT_V 0x1\r
-#define RTC_IO_TOUCH_PAD4_TIE_OPT_S 21\r
-/* RTC_IO_TOUCH_PAD4_XPD : R/W ;bitpos:[20] ;default: 1'd0 ; */\r
-/*description: touch sensor power on.*/\r
-#define RTC_IO_TOUCH_PAD4_XPD (BIT(20))\r
-#define RTC_IO_TOUCH_PAD4_XPD_M (BIT(20))\r
-#define RTC_IO_TOUCH_PAD4_XPD_V 0x1\r
-#define RTC_IO_TOUCH_PAD4_XPD_S 20\r
-/* RTC_IO_TOUCH_PAD4_MUX_SEL : R/W ;bitpos:[19] ;default: 1'd0 ; */\r
-/*description: Ò1Ó select the digital function Ó0Óslection the rtc function*/\r
-#define RTC_IO_TOUCH_PAD4_MUX_SEL (BIT(19))\r
-#define RTC_IO_TOUCH_PAD4_MUX_SEL_M (BIT(19))\r
-#define RTC_IO_TOUCH_PAD4_MUX_SEL_V 0x1\r
-#define RTC_IO_TOUCH_PAD4_MUX_SEL_S 19\r
-/* RTC_IO_TOUCH_PAD4_FUN_SEL : R/W ;bitpos:[18:17] ;default: 2'd0 ; */\r
-/*description: the functional selection signal of the pad*/\r
-#define RTC_IO_TOUCH_PAD4_FUN_SEL 0x00000003\r
-#define RTC_IO_TOUCH_PAD4_FUN_SEL_M ((RTC_IO_TOUCH_PAD4_FUN_SEL_V)<<(RTC_IO_TOUCH_PAD4_FUN_SEL_S))\r
-#define RTC_IO_TOUCH_PAD4_FUN_SEL_V 0x3\r
-#define RTC_IO_TOUCH_PAD4_FUN_SEL_S 17\r
-/* RTC_IO_TOUCH_PAD4_SLP_SEL : R/W ;bitpos:[16] ;default: 1'd0 ; */\r
-/*description: the sleep status selection signal of the pad*/\r
-#define RTC_IO_TOUCH_PAD4_SLP_SEL (BIT(16))\r
-#define RTC_IO_TOUCH_PAD4_SLP_SEL_M (BIT(16))\r
-#define RTC_IO_TOUCH_PAD4_SLP_SEL_V 0x1\r
-#define RTC_IO_TOUCH_PAD4_SLP_SEL_S 16\r
-/* RTC_IO_TOUCH_PAD4_SLP_IE : R/W ;bitpos:[15] ;default: 1'd0 ; */\r
-/*description: the input enable of the pad in sleep status*/\r
-#define RTC_IO_TOUCH_PAD4_SLP_IE (BIT(15))\r
-#define RTC_IO_TOUCH_PAD4_SLP_IE_M (BIT(15))\r
-#define RTC_IO_TOUCH_PAD4_SLP_IE_V 0x1\r
-#define RTC_IO_TOUCH_PAD4_SLP_IE_S 15\r
-/* RTC_IO_TOUCH_PAD4_SLP_OE : R/W ;bitpos:[14] ;default: 1'd0 ; */\r
-/*description: the output enable of the pad in sleep status*/\r
-#define RTC_IO_TOUCH_PAD4_SLP_OE (BIT(14))\r
-#define RTC_IO_TOUCH_PAD4_SLP_OE_M (BIT(14))\r
-#define RTC_IO_TOUCH_PAD4_SLP_OE_V 0x1\r
-#define RTC_IO_TOUCH_PAD4_SLP_OE_S 14\r
-/* RTC_IO_TOUCH_PAD4_FUN_IE : R/W ;bitpos:[13] ;default: 1'd0 ; */\r
-/*description: the input enable of the pad*/\r
-#define RTC_IO_TOUCH_PAD4_FUN_IE (BIT(13))\r
-#define RTC_IO_TOUCH_PAD4_FUN_IE_M (BIT(13))\r
-#define RTC_IO_TOUCH_PAD4_FUN_IE_V 0x1\r
-#define RTC_IO_TOUCH_PAD4_FUN_IE_S 13\r
-/* RTC_IO_TOUCH_PAD4_TO_GPIO : R/W ;bitpos:[12] ;default: 1'd0 ; */\r
-/*description: connect the rtc pad input to digital pad input Ó0Ó is availbale.MTCK*/\r
-#define RTC_IO_TOUCH_PAD4_TO_GPIO (BIT(12))\r
-#define RTC_IO_TOUCH_PAD4_TO_GPIO_M (BIT(12))\r
-#define RTC_IO_TOUCH_PAD4_TO_GPIO_V 0x1\r
-#define RTC_IO_TOUCH_PAD4_TO_GPIO_S 12\r
-\r
-#define RTC_IO_TOUCH_PAD5_REG (DR_REG_RTCIO_BASE + 0xa8)\r
-/* RTC_IO_TOUCH_PAD5_HOLD : R/W ;bitpos:[31] ;default: 1'd0 ; */\r
-/*description: hold the current value of the output when setting the hold to Ò1Ó*/\r
-#define RTC_IO_TOUCH_PAD5_HOLD (BIT(31))\r
-#define RTC_IO_TOUCH_PAD5_HOLD_M (BIT(31))\r
-#define RTC_IO_TOUCH_PAD5_HOLD_V 0x1\r
-#define RTC_IO_TOUCH_PAD5_HOLD_S 31\r
-/* RTC_IO_TOUCH_PAD5_DRV : R/W ;bitpos:[30:29] ;default: 2'd2 ; */\r
-/*description: the driver strength of the pad*/\r
-#define RTC_IO_TOUCH_PAD5_DRV 0x00000003\r
-#define RTC_IO_TOUCH_PAD5_DRV_M ((RTC_IO_TOUCH_PAD5_DRV_V)<<(RTC_IO_TOUCH_PAD5_DRV_S))\r
-#define RTC_IO_TOUCH_PAD5_DRV_V 0x3\r
-#define RTC_IO_TOUCH_PAD5_DRV_S 29\r
-/* RTC_IO_TOUCH_PAD5_RDE : R/W ;bitpos:[28] ;default: 1'd1 ; */\r
-/*description: the pull down enable of the pad*/\r
-#define RTC_IO_TOUCH_PAD5_RDE (BIT(28))\r
-#define RTC_IO_TOUCH_PAD5_RDE_M (BIT(28))\r
-#define RTC_IO_TOUCH_PAD5_RDE_V 0x1\r
-#define RTC_IO_TOUCH_PAD5_RDE_S 28\r
-/* RTC_IO_TOUCH_PAD5_RUE : R/W ;bitpos:[27] ;default: 1'd0 ; */\r
-/*description: the pull up enable of the pad*/\r
-#define RTC_IO_TOUCH_PAD5_RUE (BIT(27))\r
-#define RTC_IO_TOUCH_PAD5_RUE_M (BIT(27))\r
-#define RTC_IO_TOUCH_PAD5_RUE_V 0x1\r
-#define RTC_IO_TOUCH_PAD5_RUE_S 27\r
-/* RTC_IO_TOUCH_PAD5_DAC : R/W ;bitpos:[25:23] ;default: 3'h4 ; */\r
-/*description: touch sensor slope control. 3-bit for each touch panel default 100.*/\r
-#define RTC_IO_TOUCH_PAD5_DAC 0x00000007\r
-#define RTC_IO_TOUCH_PAD5_DAC_M ((RTC_IO_TOUCH_PAD5_DAC_V)<<(RTC_IO_TOUCH_PAD5_DAC_S))\r
-#define RTC_IO_TOUCH_PAD5_DAC_V 0x7\r
-#define RTC_IO_TOUCH_PAD5_DAC_S 23\r
-/* RTC_IO_TOUCH_PAD5_START : R/W ;bitpos:[22] ;default: 1'd0 ; */\r
-/*description: start touch sensor.*/\r
-#define RTC_IO_TOUCH_PAD5_START (BIT(22))\r
-#define RTC_IO_TOUCH_PAD5_START_M (BIT(22))\r
-#define RTC_IO_TOUCH_PAD5_START_V 0x1\r
-#define RTC_IO_TOUCH_PAD5_START_S 22\r
-/* RTC_IO_TOUCH_PAD5_TIE_OPT : R/W ;bitpos:[21] ;default: 1'd0 ; */\r
-/*description: default touch sensor tie option. 0: tie low 1: tie high.*/\r
-#define RTC_IO_TOUCH_PAD5_TIE_OPT (BIT(21))\r
-#define RTC_IO_TOUCH_PAD5_TIE_OPT_M (BIT(21))\r
-#define RTC_IO_TOUCH_PAD5_TIE_OPT_V 0x1\r
-#define RTC_IO_TOUCH_PAD5_TIE_OPT_S 21\r
-/* RTC_IO_TOUCH_PAD5_XPD : R/W ;bitpos:[20] ;default: 1'd0 ; */\r
-/*description: touch sensor power on.*/\r
-#define RTC_IO_TOUCH_PAD5_XPD (BIT(20))\r
-#define RTC_IO_TOUCH_PAD5_XPD_M (BIT(20))\r
-#define RTC_IO_TOUCH_PAD5_XPD_V 0x1\r
-#define RTC_IO_TOUCH_PAD5_XPD_S 20\r
-/* RTC_IO_TOUCH_PAD5_MUX_SEL : R/W ;bitpos:[19] ;default: 1'd0 ; */\r
-/*description: Ò1Ó select the digital function Ó0Óslection the rtc function*/\r
-#define RTC_IO_TOUCH_PAD5_MUX_SEL (BIT(19))\r
-#define RTC_IO_TOUCH_PAD5_MUX_SEL_M (BIT(19))\r
-#define RTC_IO_TOUCH_PAD5_MUX_SEL_V 0x1\r
-#define RTC_IO_TOUCH_PAD5_MUX_SEL_S 19\r
-/* RTC_IO_TOUCH_PAD5_FUN_SEL : R/W ;bitpos:[18:17] ;default: 2'd0 ; */\r
-/*description: the functional selection signal of the pad*/\r
-#define RTC_IO_TOUCH_PAD5_FUN_SEL 0x00000003\r
-#define RTC_IO_TOUCH_PAD5_FUN_SEL_M ((RTC_IO_TOUCH_PAD5_FUN_SEL_V)<<(RTC_IO_TOUCH_PAD5_FUN_SEL_S))\r
-#define RTC_IO_TOUCH_PAD5_FUN_SEL_V 0x3\r
-#define RTC_IO_TOUCH_PAD5_FUN_SEL_S 17\r
-/* RTC_IO_TOUCH_PAD5_SLP_SEL : R/W ;bitpos:[16] ;default: 1'd0 ; */\r
-/*description: the sleep status selection signal of the pad*/\r
-#define RTC_IO_TOUCH_PAD5_SLP_SEL (BIT(16))\r
-#define RTC_IO_TOUCH_PAD5_SLP_SEL_M (BIT(16))\r
-#define RTC_IO_TOUCH_PAD5_SLP_SEL_V 0x1\r
-#define RTC_IO_TOUCH_PAD5_SLP_SEL_S 16\r
-/* RTC_IO_TOUCH_PAD5_SLP_IE : R/W ;bitpos:[15] ;default: 1'd0 ; */\r
-/*description: the input enable of the pad in sleep status*/\r
-#define RTC_IO_TOUCH_PAD5_SLP_IE (BIT(15))\r
-#define RTC_IO_TOUCH_PAD5_SLP_IE_M (BIT(15))\r
-#define RTC_IO_TOUCH_PAD5_SLP_IE_V 0x1\r
-#define RTC_IO_TOUCH_PAD5_SLP_IE_S 15\r
-/* RTC_IO_TOUCH_PAD5_SLP_OE : R/W ;bitpos:[14] ;default: 1'd0 ; */\r
-/*description: the output enable of the pad in sleep status*/\r
-#define RTC_IO_TOUCH_PAD5_SLP_OE (BIT(14))\r
-#define RTC_IO_TOUCH_PAD5_SLP_OE_M (BIT(14))\r
-#define RTC_IO_TOUCH_PAD5_SLP_OE_V 0x1\r
-#define RTC_IO_TOUCH_PAD5_SLP_OE_S 14\r
-/* RTC_IO_TOUCH_PAD5_FUN_IE : R/W ;bitpos:[13] ;default: 1'd0 ; */\r
-/*description: the input enable of the pad*/\r
-#define RTC_IO_TOUCH_PAD5_FUN_IE (BIT(13))\r
-#define RTC_IO_TOUCH_PAD5_FUN_IE_M (BIT(13))\r
-#define RTC_IO_TOUCH_PAD5_FUN_IE_V 0x1\r
-#define RTC_IO_TOUCH_PAD5_FUN_IE_S 13\r
-/* RTC_IO_TOUCH_PAD5_TO_GPIO : R/W ;bitpos:[12] ;default: 1'd0 ; */\r
-/*description: connect the rtc pad input to digital pad input Ó0Ó is availbale.MTDI*/\r
-#define RTC_IO_TOUCH_PAD5_TO_GPIO (BIT(12))\r
-#define RTC_IO_TOUCH_PAD5_TO_GPIO_M (BIT(12))\r
-#define RTC_IO_TOUCH_PAD5_TO_GPIO_V 0x1\r
-#define RTC_IO_TOUCH_PAD5_TO_GPIO_S 12\r
-\r
-#define RTC_IO_TOUCH_PAD6_REG (DR_REG_RTCIO_BASE + 0xac)\r
-/* RTC_IO_TOUCH_PAD6_HOLD : R/W ;bitpos:[31] ;default: 1'd0 ; */\r
-/*description: hold the current value of the output when setting the hold to Ò1Ó*/\r
-#define RTC_IO_TOUCH_PAD6_HOLD (BIT(31))\r
-#define RTC_IO_TOUCH_PAD6_HOLD_M (BIT(31))\r
-#define RTC_IO_TOUCH_PAD6_HOLD_V 0x1\r
-#define RTC_IO_TOUCH_PAD6_HOLD_S 31\r
-/* RTC_IO_TOUCH_PAD6_DRV : R/W ;bitpos:[30:29] ;default: 2'd2 ; */\r
-/*description: the driver strength of the pad*/\r
-#define RTC_IO_TOUCH_PAD6_DRV 0x00000003\r
-#define RTC_IO_TOUCH_PAD6_DRV_M ((RTC_IO_TOUCH_PAD6_DRV_V)<<(RTC_IO_TOUCH_PAD6_DRV_S))\r
-#define RTC_IO_TOUCH_PAD6_DRV_V 0x3\r
-#define RTC_IO_TOUCH_PAD6_DRV_S 29\r
-/* RTC_IO_TOUCH_PAD6_RDE : R/W ;bitpos:[28] ;default: 1'd0 ; */\r
-/*description: the pull down enable of the pad*/\r
-#define RTC_IO_TOUCH_PAD6_RDE (BIT(28))\r
-#define RTC_IO_TOUCH_PAD6_RDE_M (BIT(28))\r
-#define RTC_IO_TOUCH_PAD6_RDE_V 0x1\r
-#define RTC_IO_TOUCH_PAD6_RDE_S 28\r
-/* RTC_IO_TOUCH_PAD6_RUE : R/W ;bitpos:[27] ;default: 1'd1 ; */\r
-/*description: the pull up enable of the pad*/\r
-#define RTC_IO_TOUCH_PAD6_RUE (BIT(27))\r
-#define RTC_IO_TOUCH_PAD6_RUE_M (BIT(27))\r
-#define RTC_IO_TOUCH_PAD6_RUE_V 0x1\r
-#define RTC_IO_TOUCH_PAD6_RUE_S 27\r
-/* RTC_IO_TOUCH_PAD6_DAC : R/W ;bitpos:[25:23] ;default: 3'h4 ; */\r
-/*description: touch sensor slope control. 3-bit for each touch panel default 100.*/\r
-#define RTC_IO_TOUCH_PAD6_DAC 0x00000007\r
-#define RTC_IO_TOUCH_PAD6_DAC_M ((RTC_IO_TOUCH_PAD6_DAC_V)<<(RTC_IO_TOUCH_PAD6_DAC_S))\r
-#define RTC_IO_TOUCH_PAD6_DAC_V 0x7\r
-#define RTC_IO_TOUCH_PAD6_DAC_S 23\r
-/* RTC_IO_TOUCH_PAD6_START : R/W ;bitpos:[22] ;default: 1'd0 ; */\r
-/*description: start touch sensor.*/\r
-#define RTC_IO_TOUCH_PAD6_START (BIT(22))\r
-#define RTC_IO_TOUCH_PAD6_START_M (BIT(22))\r
-#define RTC_IO_TOUCH_PAD6_START_V 0x1\r
-#define RTC_IO_TOUCH_PAD6_START_S 22\r
-/* RTC_IO_TOUCH_PAD6_TIE_OPT : R/W ;bitpos:[21] ;default: 1'd0 ; */\r
-/*description: default touch sensor tie option. 0: tie low 1: tie high.*/\r
-#define RTC_IO_TOUCH_PAD6_TIE_OPT (BIT(21))\r
-#define RTC_IO_TOUCH_PAD6_TIE_OPT_M (BIT(21))\r
-#define RTC_IO_TOUCH_PAD6_TIE_OPT_V 0x1\r
-#define RTC_IO_TOUCH_PAD6_TIE_OPT_S 21\r
-/* RTC_IO_TOUCH_PAD6_XPD : R/W ;bitpos:[20] ;default: 1'd0 ; */\r
-/*description: touch sensor power on.*/\r
-#define RTC_IO_TOUCH_PAD6_XPD (BIT(20))\r
-#define RTC_IO_TOUCH_PAD6_XPD_M (BIT(20))\r
-#define RTC_IO_TOUCH_PAD6_XPD_V 0x1\r
-#define RTC_IO_TOUCH_PAD6_XPD_S 20\r
-/* RTC_IO_TOUCH_PAD6_MUX_SEL : R/W ;bitpos:[19] ;default: 1'd0 ; */\r
-/*description: Ò1Ó select the digital function Ó0Óslection the rtc function*/\r
-#define RTC_IO_TOUCH_PAD6_MUX_SEL (BIT(19))\r
-#define RTC_IO_TOUCH_PAD6_MUX_SEL_M (BIT(19))\r
-#define RTC_IO_TOUCH_PAD6_MUX_SEL_V 0x1\r
-#define RTC_IO_TOUCH_PAD6_MUX_SEL_S 19\r
-/* RTC_IO_TOUCH_PAD6_FUN_SEL : R/W ;bitpos:[18:17] ;default: 2'd0 ; */\r
-/*description: the functional selection signal of the pad*/\r
-#define RTC_IO_TOUCH_PAD6_FUN_SEL 0x00000003\r
-#define RTC_IO_TOUCH_PAD6_FUN_SEL_M ((RTC_IO_TOUCH_PAD6_FUN_SEL_V)<<(RTC_IO_TOUCH_PAD6_FUN_SEL_S))\r
-#define RTC_IO_TOUCH_PAD6_FUN_SEL_V 0x3\r
-#define RTC_IO_TOUCH_PAD6_FUN_SEL_S 17\r
-/* RTC_IO_TOUCH_PAD6_SLP_SEL : R/W ;bitpos:[16] ;default: 1'd0 ; */\r
-/*description: the sleep status selection signal of the pad*/\r
-#define RTC_IO_TOUCH_PAD6_SLP_SEL (BIT(16))\r
-#define RTC_IO_TOUCH_PAD6_SLP_SEL_M (BIT(16))\r
-#define RTC_IO_TOUCH_PAD6_SLP_SEL_V 0x1\r
-#define RTC_IO_TOUCH_PAD6_SLP_SEL_S 16\r
-/* RTC_IO_TOUCH_PAD6_SLP_IE : R/W ;bitpos:[15] ;default: 1'd0 ; */\r
-/*description: the input enable of the pad in sleep status*/\r
-#define RTC_IO_TOUCH_PAD6_SLP_IE (BIT(15))\r
-#define RTC_IO_TOUCH_PAD6_SLP_IE_M (BIT(15))\r
-#define RTC_IO_TOUCH_PAD6_SLP_IE_V 0x1\r
-#define RTC_IO_TOUCH_PAD6_SLP_IE_S 15\r
-/* RTC_IO_TOUCH_PAD6_SLP_OE : R/W ;bitpos:[14] ;default: 1'd0 ; */\r
-/*description: the output enable of the pad in sleep status*/\r
-#define RTC_IO_TOUCH_PAD6_SLP_OE (BIT(14))\r
-#define RTC_IO_TOUCH_PAD6_SLP_OE_M (BIT(14))\r
-#define RTC_IO_TOUCH_PAD6_SLP_OE_V 0x1\r
-#define RTC_IO_TOUCH_PAD6_SLP_OE_S 14\r
-/* RTC_IO_TOUCH_PAD6_FUN_IE : R/W ;bitpos:[13] ;default: 1'd0 ; */\r
-/*description: the input enable of the pad*/\r
-#define RTC_IO_TOUCH_PAD6_FUN_IE (BIT(13))\r
-#define RTC_IO_TOUCH_PAD6_FUN_IE_M (BIT(13))\r
-#define RTC_IO_TOUCH_PAD6_FUN_IE_V 0x1\r
-#define RTC_IO_TOUCH_PAD6_FUN_IE_S 13\r
-/* RTC_IO_TOUCH_PAD6_TO_GPIO : R/W ;bitpos:[12] ;default: 1'd0 ; */\r
-/*description: connect the rtc pad input to digital pad input Ó0Ó is availbale.MTMS*/\r
-#define RTC_IO_TOUCH_PAD6_TO_GPIO (BIT(12))\r
-#define RTC_IO_TOUCH_PAD6_TO_GPIO_M (BIT(12))\r
-#define RTC_IO_TOUCH_PAD6_TO_GPIO_V 0x1\r
-#define RTC_IO_TOUCH_PAD6_TO_GPIO_S 12\r
-\r
-#define RTC_IO_TOUCH_PAD7_REG (DR_REG_RTCIO_BASE + 0xb0)\r
-/* RTC_IO_TOUCH_PAD7_HOLD : R/W ;bitpos:[31] ;default: 1'd0 ; */\r
-/*description: hold the current value of the output when setting the hold to Ò1Ó*/\r
-#define RTC_IO_TOUCH_PAD7_HOLD (BIT(31))\r
-#define RTC_IO_TOUCH_PAD7_HOLD_M (BIT(31))\r
-#define RTC_IO_TOUCH_PAD7_HOLD_V 0x1\r
-#define RTC_IO_TOUCH_PAD7_HOLD_S 31\r
-/* RTC_IO_TOUCH_PAD7_DRV : R/W ;bitpos:[30:29] ;default: 2'd2 ; */\r
-/*description: the driver strength of the pad*/\r
-#define RTC_IO_TOUCH_PAD7_DRV 0x00000003\r
-#define RTC_IO_TOUCH_PAD7_DRV_M ((RTC_IO_TOUCH_PAD7_DRV_V)<<(RTC_IO_TOUCH_PAD7_DRV_S))\r
-#define RTC_IO_TOUCH_PAD7_DRV_V 0x3\r
-#define RTC_IO_TOUCH_PAD7_DRV_S 29\r
-/* RTC_IO_TOUCH_PAD7_RDE : R/W ;bitpos:[28] ;default: 1'd0 ; */\r
-/*description: the pull down enable of the pad*/\r
-#define RTC_IO_TOUCH_PAD7_RDE (BIT(28))\r
-#define RTC_IO_TOUCH_PAD7_RDE_M (BIT(28))\r
-#define RTC_IO_TOUCH_PAD7_RDE_V 0x1\r
-#define RTC_IO_TOUCH_PAD7_RDE_S 28\r
-/* RTC_IO_TOUCH_PAD7_RUE : R/W ;bitpos:[27] ;default: 1'd0 ; */\r
-/*description: the pull up enable of the pad*/\r
-#define RTC_IO_TOUCH_PAD7_RUE (BIT(27))\r
-#define RTC_IO_TOUCH_PAD7_RUE_M (BIT(27))\r
-#define RTC_IO_TOUCH_PAD7_RUE_V 0x1\r
-#define RTC_IO_TOUCH_PAD7_RUE_S 27\r
-/* RTC_IO_TOUCH_PAD7_DAC : R/W ;bitpos:[25:23] ;default: 3'h4 ; */\r
-/*description: touch sensor slope control. 3-bit for each touch panel default 100.*/\r
-#define RTC_IO_TOUCH_PAD7_DAC 0x00000007\r
-#define RTC_IO_TOUCH_PAD7_DAC_M ((RTC_IO_TOUCH_PAD7_DAC_V)<<(RTC_IO_TOUCH_PAD7_DAC_S))\r
-#define RTC_IO_TOUCH_PAD7_DAC_V 0x7\r
-#define RTC_IO_TOUCH_PAD7_DAC_S 23\r
-/* RTC_IO_TOUCH_PAD7_START : R/W ;bitpos:[22] ;default: 1'd0 ; */\r
-/*description: start touch sensor.*/\r
-#define RTC_IO_TOUCH_PAD7_START (BIT(22))\r
-#define RTC_IO_TOUCH_PAD7_START_M (BIT(22))\r
-#define RTC_IO_TOUCH_PAD7_START_V 0x1\r
-#define RTC_IO_TOUCH_PAD7_START_S 22\r
-/* RTC_IO_TOUCH_PAD7_TIE_OPT : R/W ;bitpos:[21] ;default: 1'd0 ; */\r
-/*description: default touch sensor tie option. 0: tie low 1: tie high.*/\r
-#define RTC_IO_TOUCH_PAD7_TIE_OPT (BIT(21))\r
-#define RTC_IO_TOUCH_PAD7_TIE_OPT_M (BIT(21))\r
-#define RTC_IO_TOUCH_PAD7_TIE_OPT_V 0x1\r
-#define RTC_IO_TOUCH_PAD7_TIE_OPT_S 21\r
-/* RTC_IO_TOUCH_PAD7_XPD : R/W ;bitpos:[20] ;default: 1'd0 ; */\r
-/*description: touch sensor power on.*/\r
-#define RTC_IO_TOUCH_PAD7_XPD (BIT(20))\r
-#define RTC_IO_TOUCH_PAD7_XPD_M (BIT(20))\r
-#define RTC_IO_TOUCH_PAD7_XPD_V 0x1\r
-#define RTC_IO_TOUCH_PAD7_XPD_S 20\r
-/* RTC_IO_TOUCH_PAD7_MUX_SEL : R/W ;bitpos:[19] ;default: 1'd0 ; */\r
-/*description: Ò1Ó select the digital function Ó0Óslection the rtc function*/\r
-#define RTC_IO_TOUCH_PAD7_MUX_SEL (BIT(19))\r
-#define RTC_IO_TOUCH_PAD7_MUX_SEL_M (BIT(19))\r
-#define RTC_IO_TOUCH_PAD7_MUX_SEL_V 0x1\r
-#define RTC_IO_TOUCH_PAD7_MUX_SEL_S 19\r
-/* RTC_IO_TOUCH_PAD7_FUN_SEL : R/W ;bitpos:[18:17] ;default: 2'd0 ; */\r
-/*description: the functional selection signal of the pad*/\r
-#define RTC_IO_TOUCH_PAD7_FUN_SEL 0x00000003\r
-#define RTC_IO_TOUCH_PAD7_FUN_SEL_M ((RTC_IO_TOUCH_PAD7_FUN_SEL_V)<<(RTC_IO_TOUCH_PAD7_FUN_SEL_S))\r
-#define RTC_IO_TOUCH_PAD7_FUN_SEL_V 0x3\r
-#define RTC_IO_TOUCH_PAD7_FUN_SEL_S 17\r
-/* RTC_IO_TOUCH_PAD7_SLP_SEL : R/W ;bitpos:[16] ;default: 1'd0 ; */\r
-/*description: the sleep status selection signal of the pad*/\r
-#define RTC_IO_TOUCH_PAD7_SLP_SEL (BIT(16))\r
-#define RTC_IO_TOUCH_PAD7_SLP_SEL_M (BIT(16))\r
-#define RTC_IO_TOUCH_PAD7_SLP_SEL_V 0x1\r
-#define RTC_IO_TOUCH_PAD7_SLP_SEL_S 16\r
-/* RTC_IO_TOUCH_PAD7_SLP_IE : R/W ;bitpos:[15] ;default: 1'd0 ; */\r
-/*description: the input enable of the pad in sleep status*/\r
-#define RTC_IO_TOUCH_PAD7_SLP_IE (BIT(15))\r
-#define RTC_IO_TOUCH_PAD7_SLP_IE_M (BIT(15))\r
-#define RTC_IO_TOUCH_PAD7_SLP_IE_V 0x1\r
-#define RTC_IO_TOUCH_PAD7_SLP_IE_S 15\r
-/* RTC_IO_TOUCH_PAD7_SLP_OE : R/W ;bitpos:[14] ;default: 1'd0 ; */\r
-/*description: the output enable of the pad in sleep status*/\r
-#define RTC_IO_TOUCH_PAD7_SLP_OE (BIT(14))\r
-#define RTC_IO_TOUCH_PAD7_SLP_OE_M (BIT(14))\r
-#define RTC_IO_TOUCH_PAD7_SLP_OE_V 0x1\r
-#define RTC_IO_TOUCH_PAD7_SLP_OE_S 14\r
-/* RTC_IO_TOUCH_PAD7_FUN_IE : R/W ;bitpos:[13] ;default: 1'd0 ; */\r
-/*description: the input enable of the pad*/\r
-#define RTC_IO_TOUCH_PAD7_FUN_IE (BIT(13))\r
-#define RTC_IO_TOUCH_PAD7_FUN_IE_M (BIT(13))\r
-#define RTC_IO_TOUCH_PAD7_FUN_IE_V 0x1\r
-#define RTC_IO_TOUCH_PAD7_FUN_IE_S 13\r
-/* RTC_IO_TOUCH_PAD7_TO_GPIO : R/W ;bitpos:[12] ;default: 1'd0 ; */\r
-/*description: connect the rtc pad input to digital pad input Ó0Ó is availbale.GPIO27*/\r
-#define RTC_IO_TOUCH_PAD7_TO_GPIO (BIT(12))\r
-#define RTC_IO_TOUCH_PAD7_TO_GPIO_M (BIT(12))\r
-#define RTC_IO_TOUCH_PAD7_TO_GPIO_V 0x1\r
-#define RTC_IO_TOUCH_PAD7_TO_GPIO_S 12\r
-\r
-#define RTC_IO_TOUCH_PAD8_REG (DR_REG_RTCIO_BASE + 0xb4)\r
-/* RTC_IO_TOUCH_PAD8_DAC : R/W ;bitpos:[25:23] ;default: 3'h4 ; */\r
-/*description: touch sensor slope control. 3-bit for each touch panel default 100.*/\r
-#define RTC_IO_TOUCH_PAD8_DAC 0x00000007\r
-#define RTC_IO_TOUCH_PAD8_DAC_M ((RTC_IO_TOUCH_PAD8_DAC_V)<<(RTC_IO_TOUCH_PAD8_DAC_S))\r
-#define RTC_IO_TOUCH_PAD8_DAC_V 0x7\r
-#define RTC_IO_TOUCH_PAD8_DAC_S 23\r
-/* RTC_IO_TOUCH_PAD8_START : R/W ;bitpos:[22] ;default: 1'd0 ; */\r
-/*description: start touch sensor.*/\r
-#define RTC_IO_TOUCH_PAD8_START (BIT(22))\r
-#define RTC_IO_TOUCH_PAD8_START_M (BIT(22))\r
-#define RTC_IO_TOUCH_PAD8_START_V 0x1\r
-#define RTC_IO_TOUCH_PAD8_START_S 22\r
-/* RTC_IO_TOUCH_PAD8_TIE_OPT : R/W ;bitpos:[21] ;default: 1'd0 ; */\r
-/*description: default touch sensor tie option. 0: tie low 1: tie high.*/\r
-#define RTC_IO_TOUCH_PAD8_TIE_OPT (BIT(21))\r
-#define RTC_IO_TOUCH_PAD8_TIE_OPT_M (BIT(21))\r
-#define RTC_IO_TOUCH_PAD8_TIE_OPT_V 0x1\r
-#define RTC_IO_TOUCH_PAD8_TIE_OPT_S 21\r
-/* RTC_IO_TOUCH_PAD8_XPD : R/W ;bitpos:[20] ;default: 1'd0 ; */\r
-/*description: touch sensor power on.*/\r
-#define RTC_IO_TOUCH_PAD8_XPD (BIT(20))\r
-#define RTC_IO_TOUCH_PAD8_XPD_M (BIT(20))\r
-#define RTC_IO_TOUCH_PAD8_XPD_V 0x1\r
-#define RTC_IO_TOUCH_PAD8_XPD_S 20\r
-/* RTC_IO_TOUCH_PAD8_TO_GPIO : R/W ;bitpos:[19] ;default: 1'd0 ; */\r
-/*description: connect the rtc pad input to digital pad input Ó0Ó is availbale*/\r
-#define RTC_IO_TOUCH_PAD8_TO_GPIO (BIT(19))\r
-#define RTC_IO_TOUCH_PAD8_TO_GPIO_M (BIT(19))\r
-#define RTC_IO_TOUCH_PAD8_TO_GPIO_V 0x1\r
-#define RTC_IO_TOUCH_PAD8_TO_GPIO_S 19\r
-\r
-#define RTC_IO_TOUCH_PAD9_REG (DR_REG_RTCIO_BASE + 0xb8)\r
-/* RTC_IO_TOUCH_PAD9_DAC : R/W ;bitpos:[25:23] ;default: 3'h4 ; */\r
-/*description: touch sensor slope control. 3-bit for each touch panel default 100.*/\r
-#define RTC_IO_TOUCH_PAD9_DAC 0x00000007\r
-#define RTC_IO_TOUCH_PAD9_DAC_M ((RTC_IO_TOUCH_PAD9_DAC_V)<<(RTC_IO_TOUCH_PAD9_DAC_S))\r
-#define RTC_IO_TOUCH_PAD9_DAC_V 0x7\r
-#define RTC_IO_TOUCH_PAD9_DAC_S 23\r
-/* RTC_IO_TOUCH_PAD9_START : R/W ;bitpos:[22] ;default: 1'd0 ; */\r
-/*description: start touch sensor.*/\r
-#define RTC_IO_TOUCH_PAD9_START (BIT(22))\r
-#define RTC_IO_TOUCH_PAD9_START_M (BIT(22))\r
-#define RTC_IO_TOUCH_PAD9_START_V 0x1\r
-#define RTC_IO_TOUCH_PAD9_START_S 22\r
-/* RTC_IO_TOUCH_PAD9_TIE_OPT : R/W ;bitpos:[21] ;default: 1'd0 ; */\r
-/*description: default touch sensor tie option. 0: tie low 1: tie high.*/\r
-#define RTC_IO_TOUCH_PAD9_TIE_OPT (BIT(21))\r
-#define RTC_IO_TOUCH_PAD9_TIE_OPT_M (BIT(21))\r
-#define RTC_IO_TOUCH_PAD9_TIE_OPT_V 0x1\r
-#define RTC_IO_TOUCH_PAD9_TIE_OPT_S 21\r
-/* RTC_IO_TOUCH_PAD9_XPD : R/W ;bitpos:[20] ;default: 1'd0 ; */\r
-/*description: touch sensor power on.*/\r
-#define RTC_IO_TOUCH_PAD9_XPD (BIT(20))\r
-#define RTC_IO_TOUCH_PAD9_XPD_M (BIT(20))\r
-#define RTC_IO_TOUCH_PAD9_XPD_V 0x1\r
-#define RTC_IO_TOUCH_PAD9_XPD_S 20\r
-/* RTC_IO_TOUCH_PAD9_TO_GPIO : R/W ;bitpos:[19] ;default: 1'd0 ; */\r
-/*description: connect the rtc pad input to digital pad input Ó0Ó is availbale*/\r
-#define RTC_IO_TOUCH_PAD9_TO_GPIO (BIT(19))\r
-#define RTC_IO_TOUCH_PAD9_TO_GPIO_M (BIT(19))\r
-#define RTC_IO_TOUCH_PAD9_TO_GPIO_V 0x1\r
-#define RTC_IO_TOUCH_PAD9_TO_GPIO_S 19\r
-\r
-#define RTC_IO_EXT_WAKEUP0_REG (DR_REG_RTCIO_BASE + 0xbc)\r
-/* RTC_IO_EXT_WAKEUP0_SEL : R/W ;bitpos:[31:27] ;default: 5'd0 ; */\r
-/*description: select the wakeup source Ó0Ó select GPIO0 Ó1Ó select GPIO2 ...Ò17Ó select GPIO17*/\r
-#define RTC_IO_EXT_WAKEUP0_SEL 0x0000001F\r
-#define RTC_IO_EXT_WAKEUP0_SEL_M ((RTC_IO_EXT_WAKEUP0_SEL_V)<<(RTC_IO_EXT_WAKEUP0_SEL_S))\r
-#define RTC_IO_EXT_WAKEUP0_SEL_V 0x1F\r
-#define RTC_IO_EXT_WAKEUP0_SEL_S 27\r
-\r
-#define RTC_IO_XTL_EXT_CTR_REG (DR_REG_RTCIO_BASE + 0xc0)\r
-/* RTC_IO_XTL_EXT_CTR_SEL : R/W ;bitpos:[31:27] ;default: 5'd0 ; */\r
-/*description: select the external xtl power source Ó0Ó select GPIO0 Ó1Ó select\r
- GPIO2 ...Ò17Ó select GPIO17*/\r
-#define RTC_IO_XTL_EXT_CTR_SEL 0x0000001F\r
-#define RTC_IO_XTL_EXT_CTR_SEL_M ((RTC_IO_XTL_EXT_CTR_SEL_V)<<(RTC_IO_XTL_EXT_CTR_SEL_S))\r
-#define RTC_IO_XTL_EXT_CTR_SEL_V 0x1F\r
-#define RTC_IO_XTL_EXT_CTR_SEL_S 27\r
-\r
-#define RTC_IO_SAR_I2C_IO_REG (DR_REG_RTCIO_BASE + 0xc4)\r
-/* RTC_IO_SAR_I2C_SDA_SEL : R/W ;bitpos:[31:30] ;default: 2'd0 ; */\r
-/*description: Ò0Ó using TOUCH_PAD[1] as i2c sda Ò1Ó using TOUCH_PAD[3] as i2c sda*/\r
-#define RTC_IO_SAR_I2C_SDA_SEL 0x00000003\r
-#define RTC_IO_SAR_I2C_SDA_SEL_M ((RTC_IO_SAR_I2C_SDA_SEL_V)<<(RTC_IO_SAR_I2C_SDA_SEL_S))\r
-#define RTC_IO_SAR_I2C_SDA_SEL_V 0x3\r
-#define RTC_IO_SAR_I2C_SDA_SEL_S 30\r
-/* RTC_IO_SAR_I2C_SCL_SEL : R/W ;bitpos:[29:28] ;default: 2'd0 ; */\r
-/*description: Ò0Ó using TOUCH_PAD[0] as i2c clk Ò1Ó using TOUCH_PAD[2] as i2c clk*/\r
-#define RTC_IO_SAR_I2C_SCL_SEL 0x00000003\r
-#define RTC_IO_SAR_I2C_SCL_SEL_M ((RTC_IO_SAR_I2C_SCL_SEL_V)<<(RTC_IO_SAR_I2C_SCL_SEL_S))\r
-#define RTC_IO_SAR_I2C_SCL_SEL_V 0x3\r
-#define RTC_IO_SAR_I2C_SCL_SEL_S 28\r
-/* RTC_IO_SAR_DEBUG_BIT_SEL : R/W ;bitpos:[27:23] ;default: 5'h0 ; */\r
-/*description: */\r
-#define RTC_IO_SAR_DEBUG_BIT_SEL 0x0000001F\r
-#define RTC_IO_SAR_DEBUG_BIT_SEL_M ((RTC_IO_SAR_DEBUG_BIT_SEL_V)<<(RTC_IO_SAR_DEBUG_BIT_SEL_S))\r
-#define RTC_IO_SAR_DEBUG_BIT_SEL_V 0x1F\r
-#define RTC_IO_SAR_DEBUG_BIT_SEL_S 23\r
-\r
-#define RTC_IO_DATE_REG (DR_REG_RTCIO_BASE + 0xc8)\r
-/* RTC_IO_IO_DATE : R/W ;bitpos:[27:0] ;default: 28'h1603160 ; */\r
-/*description: date*/\r
-#define RTC_IO_IO_DATE 0x0FFFFFFF\r
-#define RTC_IO_IO_DATE_M ((RTC_IO_IO_DATE_V)<<(RTC_IO_IO_DATE_S))\r
-#define RTC_IO_IO_DATE_V 0xFFFFFFF\r
-#define RTC_IO_IO_DATE_S 0\r
-#define RTC_IO_RTC_IO_DATE_VERSION 0x1703160\r
-\r
-\r
-\r
-\r
-#endif /*_SOC_RTC_IO_REG_H_ */\r
-\r
-\r
+// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+#ifndef _SOC_RTC_IO_REG_H_
+#define _SOC_RTC_IO_REG_H_
+
+
+#include "soc.h"
+#define RTC_GPIO_OUT_REG (DR_REG_RTCIO_BASE + 0x0)
+/* RTC_GPIO_OUT_DATA : R/W ;bitpos:[31:14] ;default: 0 ; */
+/*description: GPIO0~17 output value*/
+#define RTC_GPIO_OUT_DATA 0x0003FFFF
+#define RTC_GPIO_OUT_DATA_M ((RTC_GPIO_OUT_DATA_V)<<(RTC_GPIO_OUT_DATA_S))
+#define RTC_GPIO_OUT_DATA_V 0x3FFFF
+#define RTC_GPIO_OUT_DATA_S 14
+
+#define RTC_GPIO_OUT_W1TS_REG (DR_REG_RTCIO_BASE + 0x4)
+/* RTC_GPIO_OUT_DATA_W1TS : WO ;bitpos:[31:14] ;default: 0 ; */
+/*description: GPIO0~17 output value write 1 to set*/
+#define RTC_GPIO_OUT_DATA_W1TS 0x0003FFFF
+#define RTC_GPIO_OUT_DATA_W1TS_M ((RTC_GPIO_OUT_DATA_W1TS_V)<<(RTC_GPIO_OUT_DATA_W1TS_S))
+#define RTC_GPIO_OUT_DATA_W1TS_V 0x3FFFF
+#define RTC_GPIO_OUT_DATA_W1TS_S 14
+
+#define RTC_GPIO_OUT_W1TC_REG (DR_REG_RTCIO_BASE + 0x8)
+/* RTC_GPIO_OUT_DATA_W1TC : WO ;bitpos:[31:14] ;default: 0 ; */
+/*description: GPIO0~17 output value write 1 to clear*/
+#define RTC_GPIO_OUT_DATA_W1TC 0x0003FFFF
+#define RTC_GPIO_OUT_DATA_W1TC_M ((RTC_GPIO_OUT_DATA_W1TC_V)<<(RTC_GPIO_OUT_DATA_W1TC_S))
+#define RTC_GPIO_OUT_DATA_W1TC_V 0x3FFFF
+#define RTC_GPIO_OUT_DATA_W1TC_S 14
+
+#define RTC_GPIO_ENABLE_REG (DR_REG_RTCIO_BASE + 0xc)
+/* RTC_GPIO_ENABLE : R/W ;bitpos:[31:14] ;default: 0 ; */
+/*description: GPIO0~17 output enable*/
+#define RTC_GPIO_ENABLE 0x0003FFFF
+#define RTC_GPIO_ENABLE_M ((RTC_GPIO_ENABLE_V)<<(RTC_GPIO_ENABLE_S))
+#define RTC_GPIO_ENABLE_V 0x3FFFF
+#define RTC_GPIO_ENABLE_S 14
+
+#define RTC_GPIO_ENABLE_W1TS_REG (DR_REG_RTCIO_BASE + 0x10)
+/* RTC_GPIO_ENABLE_W1TS : WO ;bitpos:[31:14] ;default: 0 ; */
+/*description: GPIO0~17 output enable write 1 to set*/
+#define RTC_GPIO_ENABLE_W1TS 0x0003FFFF
+#define RTC_GPIO_ENABLE_W1TS_M ((RTC_GPIO_ENABLE_W1TS_V)<<(RTC_GPIO_ENABLE_W1TS_S))
+#define RTC_GPIO_ENABLE_W1TS_V 0x3FFFF
+#define RTC_GPIO_ENABLE_W1TS_S 14
+
+#define RTC_GPIO_ENABLE_W1TC_REG (DR_REG_RTCIO_BASE + 0x14)
+/* RTC_GPIO_ENABLE_W1TC : WO ;bitpos:[31:14] ;default: 0 ; */
+/*description: GPIO0~17 output enable write 1 to clear*/
+#define RTC_GPIO_ENABLE_W1TC 0x0003FFFF
+#define RTC_GPIO_ENABLE_W1TC_M ((RTC_GPIO_ENABLE_W1TC_V)<<(RTC_GPIO_ENABLE_W1TC_S))
+#define RTC_GPIO_ENABLE_W1TC_V 0x3FFFF
+#define RTC_GPIO_ENABLE_W1TC_S 14
+
+#define RTC_GPIO_STATUS_REG (DR_REG_RTCIO_BASE + 0x18)
+/* RTC_GPIO_STATUS_INT : R/W ;bitpos:[31:14] ;default: 0 ; */
+/*description: GPIO0~17 interrupt status*/
+#define RTC_GPIO_STATUS_INT 0x0003FFFF
+#define RTC_GPIO_STATUS_INT_M ((RTC_GPIO_STATUS_INT_V)<<(RTC_GPIO_STATUS_INT_S))
+#define RTC_GPIO_STATUS_INT_V 0x3FFFF
+#define RTC_GPIO_STATUS_INT_S 14
+
+#define RTC_GPIO_STATUS_W1TS_REG (DR_REG_RTCIO_BASE + 0x1c)
+/* RTC_GPIO_STATUS_INT_W1TS : WO ;bitpos:[31:14] ;default: 0 ; */
+/*description: GPIO0~17 interrupt status write 1 to set*/
+#define RTC_GPIO_STATUS_INT_W1TS 0x0003FFFF
+#define RTC_GPIO_STATUS_INT_W1TS_M ((RTC_GPIO_STATUS_INT_W1TS_V)<<(RTC_GPIO_STATUS_INT_W1TS_S))
+#define RTC_GPIO_STATUS_INT_W1TS_V 0x3FFFF
+#define RTC_GPIO_STATUS_INT_W1TS_S 14
+
+#define RTC_GPIO_STATUS_W1TC_REG (DR_REG_RTCIO_BASE + 0x20)
+/* RTC_GPIO_STATUS_INT_W1TC : WO ;bitpos:[31:14] ;default: 0 ; */
+/*description: GPIO0~17 interrupt status write 1 to clear*/
+#define RTC_GPIO_STATUS_INT_W1TC 0x0003FFFF
+#define RTC_GPIO_STATUS_INT_W1TC_M ((RTC_GPIO_STATUS_INT_W1TC_V)<<(RTC_GPIO_STATUS_INT_W1TC_S))
+#define RTC_GPIO_STATUS_INT_W1TC_V 0x3FFFF
+#define RTC_GPIO_STATUS_INT_W1TC_S 14
+
+#define RTC_GPIO_IN_REG (DR_REG_RTCIO_BASE + 0x24)
+/* RTC_GPIO_IN_NEXT : RO ;bitpos:[31:14] ;default: ; */
+/*description: GPIO0~17 input value*/
+#define RTC_GPIO_IN_NEXT 0x0003FFFF
+#define RTC_GPIO_IN_NEXT_M ((RTC_GPIO_IN_NEXT_V)<<(RTC_GPIO_IN_NEXT_S))
+#define RTC_GPIO_IN_NEXT_V 0x3FFFF
+#define RTC_GPIO_IN_NEXT_S 14
+
+#define RTC_GPIO_PIN0_REG (DR_REG_RTCIO_BASE + 0x28)
+/* RTC_GPIO_PIN0_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */
+/*description: GPIO wake up enable only available in light sleep*/
+#define RTC_GPIO_PIN0_WAKEUP_ENABLE (BIT(10))
+#define RTC_GPIO_PIN0_WAKEUP_ENABLE_M (BIT(10))
+#define RTC_GPIO_PIN0_WAKEUP_ENABLE_V 0x1
+#define RTC_GPIO_PIN0_WAKEUP_ENABLE_S 10
+/* RTC_GPIO_PIN0_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */
+/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge
+ trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/
+#define RTC_GPIO_PIN0_INT_TYPE 0x00000007
+#define RTC_GPIO_PIN0_INT_TYPE_M ((RTC_GPIO_PIN0_INT_TYPE_V)<<(RTC_GPIO_PIN0_INT_TYPE_S))
+#define RTC_GPIO_PIN0_INT_TYPE_V 0x7
+#define RTC_GPIO_PIN0_INT_TYPE_S 7
+/* RTC_GPIO_PIN0_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */
+/*description: if set to 0: normal output if set to 1: open drain*/
+#define RTC_GPIO_PIN0_PAD_DRIVER (BIT(2))
+#define RTC_GPIO_PIN0_PAD_DRIVER_M (BIT(2))
+#define RTC_GPIO_PIN0_PAD_DRIVER_V 0x1
+#define RTC_GPIO_PIN0_PAD_DRIVER_S 2
+
+#define RTC_GPIO_PIN1_REG (DR_REG_RTCIO_BASE + 0x2c)
+/* RTC_GPIO_PIN1_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */
+/*description: GPIO wake up enable only available in light sleep*/
+#define RTC_GPIO_PIN1_WAKEUP_ENABLE (BIT(10))
+#define RTC_GPIO_PIN1_WAKEUP_ENABLE_M (BIT(10))
+#define RTC_GPIO_PIN1_WAKEUP_ENABLE_V 0x1
+#define RTC_GPIO_PIN1_WAKEUP_ENABLE_S 10
+/* RTC_GPIO_PIN1_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */
+/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge
+ trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/
+#define RTC_GPIO_PIN1_INT_TYPE 0x00000007
+#define RTC_GPIO_PIN1_INT_TYPE_M ((RTC_GPIO_PIN1_INT_TYPE_V)<<(RTC_GPIO_PIN1_INT_TYPE_S))
+#define RTC_GPIO_PIN1_INT_TYPE_V 0x7
+#define RTC_GPIO_PIN1_INT_TYPE_S 7
+/* RTC_GPIO_PIN1_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */
+/*description: if set to 0: normal output if set to 1: open drain*/
+#define RTC_GPIO_PIN1_PAD_DRIVER (BIT(2))
+#define RTC_GPIO_PIN1_PAD_DRIVER_M (BIT(2))
+#define RTC_GPIO_PIN1_PAD_DRIVER_V 0x1
+#define RTC_GPIO_PIN1_PAD_DRIVER_S 2
+
+#define RTC_GPIO_PIN2_REG (DR_REG_RTCIO_BASE + 0x30)
+/* RTC_GPIO_PIN2_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */
+/*description: GPIO wake up enable only available in light sleep*/
+#define RTC_GPIO_PIN2_WAKEUP_ENABLE (BIT(10))
+#define RTC_GPIO_PIN2_WAKEUP_ENABLE_M (BIT(10))
+#define RTC_GPIO_PIN2_WAKEUP_ENABLE_V 0x1
+#define RTC_GPIO_PIN2_WAKEUP_ENABLE_S 10
+/* RTC_GPIO_PIN2_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */
+/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge
+ trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/
+#define RTC_GPIO_PIN2_INT_TYPE 0x00000007
+#define RTC_GPIO_PIN2_INT_TYPE_M ((RTC_GPIO_PIN2_INT_TYPE_V)<<(RTC_GPIO_PIN2_INT_TYPE_S))
+#define RTC_GPIO_PIN2_INT_TYPE_V 0x7
+#define RTC_GPIO_PIN2_INT_TYPE_S 7
+/* RTC_GPIO_PIN2_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */
+/*description: if set to 0: normal output if set to 1: open drain*/
+#define RTC_GPIO_PIN2_PAD_DRIVER (BIT(2))
+#define RTC_GPIO_PIN2_PAD_DRIVER_M (BIT(2))
+#define RTC_GPIO_PIN2_PAD_DRIVER_V 0x1
+#define RTC_GPIO_PIN2_PAD_DRIVER_S 2
+
+#define RTC_GPIO_PIN3_REG (DR_REG_RTCIO_BASE + 0x34)
+/* RTC_GPIO_PIN3_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */
+/*description: GPIO wake up enable only available in light sleep*/
+#define RTC_GPIO_PIN3_WAKEUP_ENABLE (BIT(10))
+#define RTC_GPIO_PIN3_WAKEUP_ENABLE_M (BIT(10))
+#define RTC_GPIO_PIN3_WAKEUP_ENABLE_V 0x1
+#define RTC_GPIO_PIN3_WAKEUP_ENABLE_S 10
+/* RTC_GPIO_PIN3_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */
+/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge
+ trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/
+#define RTC_GPIO_PIN3_INT_TYPE 0x00000007
+#define RTC_GPIO_PIN3_INT_TYPE_M ((RTC_GPIO_PIN3_INT_TYPE_V)<<(RTC_GPIO_PIN3_INT_TYPE_S))
+#define RTC_GPIO_PIN3_INT_TYPE_V 0x7
+#define RTC_GPIO_PIN3_INT_TYPE_S 7
+/* RTC_GPIO_PIN3_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */
+/*description: if set to 0: normal output if set to 1: open drain*/
+#define RTC_GPIO_PIN3_PAD_DRIVER (BIT(2))
+#define RTC_GPIO_PIN3_PAD_DRIVER_M (BIT(2))
+#define RTC_GPIO_PIN3_PAD_DRIVER_V 0x1
+#define RTC_GPIO_PIN3_PAD_DRIVER_S 2
+
+#define RTC_GPIO_PIN4_REG (DR_REG_RTCIO_BASE + 0x38)
+/* RTC_GPIO_PIN4_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */
+/*description: GPIO wake up enable only available in light sleep*/
+#define RTC_GPIO_PIN4_WAKEUP_ENABLE (BIT(10))
+#define RTC_GPIO_PIN4_WAKEUP_ENABLE_M (BIT(10))
+#define RTC_GPIO_PIN4_WAKEUP_ENABLE_V 0x1
+#define RTC_GPIO_PIN4_WAKEUP_ENABLE_S 10
+/* RTC_GPIO_PIN4_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */
+/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge
+ trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/
+#define RTC_GPIO_PIN4_INT_TYPE 0x00000007
+#define RTC_GPIO_PIN4_INT_TYPE_M ((RTC_GPIO_PIN4_INT_TYPE_V)<<(RTC_GPIO_PIN4_INT_TYPE_S))
+#define RTC_GPIO_PIN4_INT_TYPE_V 0x7
+#define RTC_GPIO_PIN4_INT_TYPE_S 7
+/* RTC_GPIO_PIN4_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */
+/*description: if set to 0: normal output if set to 1: open drain*/
+#define RTC_GPIO_PIN4_PAD_DRIVER (BIT(2))
+#define RTC_GPIO_PIN4_PAD_DRIVER_M (BIT(2))
+#define RTC_GPIO_PIN4_PAD_DRIVER_V 0x1
+#define RTC_GPIO_PIN4_PAD_DRIVER_S 2
+
+#define RTC_GPIO_PIN5_REG (DR_REG_RTCIO_BASE + 0x3c)
+/* RTC_GPIO_PIN5_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */
+/*description: GPIO wake up enable only available in light sleep*/
+#define RTC_GPIO_PIN5_WAKEUP_ENABLE (BIT(10))
+#define RTC_GPIO_PIN5_WAKEUP_ENABLE_M (BIT(10))
+#define RTC_GPIO_PIN5_WAKEUP_ENABLE_V 0x1
+#define RTC_GPIO_PIN5_WAKEUP_ENABLE_S 10
+/* RTC_GPIO_PIN5_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */
+/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge
+ trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/
+#define RTC_GPIO_PIN5_INT_TYPE 0x00000007
+#define RTC_GPIO_PIN5_INT_TYPE_M ((RTC_GPIO_PIN5_INT_TYPE_V)<<(RTC_GPIO_PIN5_INT_TYPE_S))
+#define RTC_GPIO_PIN5_INT_TYPE_V 0x7
+#define RTC_GPIO_PIN5_INT_TYPE_S 7
+/* RTC_GPIO_PIN5_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */
+/*description: if set to 0: normal output if set to 1: open drain*/
+#define RTC_GPIO_PIN5_PAD_DRIVER (BIT(2))
+#define RTC_GPIO_PIN5_PAD_DRIVER_M (BIT(2))
+#define RTC_GPIO_PIN5_PAD_DRIVER_V 0x1
+#define RTC_GPIO_PIN5_PAD_DRIVER_S 2
+
+#define RTC_GPIO_PIN6_REG (DR_REG_RTCIO_BASE + 0x40)
+/* RTC_GPIO_PIN6_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */
+/*description: GPIO wake up enable only available in light sleep*/
+#define RTC_GPIO_PIN6_WAKEUP_ENABLE (BIT(10))
+#define RTC_GPIO_PIN6_WAKEUP_ENABLE_M (BIT(10))
+#define RTC_GPIO_PIN6_WAKEUP_ENABLE_V 0x1
+#define RTC_GPIO_PIN6_WAKEUP_ENABLE_S 10
+/* RTC_GPIO_PIN6_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */
+/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge
+ trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/
+#define RTC_GPIO_PIN6_INT_TYPE 0x00000007
+#define RTC_GPIO_PIN6_INT_TYPE_M ((RTC_GPIO_PIN6_INT_TYPE_V)<<(RTC_GPIO_PIN6_INT_TYPE_S))
+#define RTC_GPIO_PIN6_INT_TYPE_V 0x7
+#define RTC_GPIO_PIN6_INT_TYPE_S 7
+/* RTC_GPIO_PIN6_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */
+/*description: if set to 0: normal output if set to 1: open drain*/
+#define RTC_GPIO_PIN6_PAD_DRIVER (BIT(2))
+#define RTC_GPIO_PIN6_PAD_DRIVER_M (BIT(2))
+#define RTC_GPIO_PIN6_PAD_DRIVER_V 0x1
+#define RTC_GPIO_PIN6_PAD_DRIVER_S 2
+
+#define RTC_GPIO_PIN7_REG (DR_REG_RTCIO_BASE + 0x44)
+/* RTC_GPIO_PIN7_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */
+/*description: GPIO wake up enable only available in light sleep*/
+#define RTC_GPIO_PIN7_WAKEUP_ENABLE (BIT(10))
+#define RTC_GPIO_PIN7_WAKEUP_ENABLE_M (BIT(10))
+#define RTC_GPIO_PIN7_WAKEUP_ENABLE_V 0x1
+#define RTC_GPIO_PIN7_WAKEUP_ENABLE_S 10
+/* RTC_GPIO_PIN7_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */
+/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge
+ trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/
+#define RTC_GPIO_PIN7_INT_TYPE 0x00000007
+#define RTC_GPIO_PIN7_INT_TYPE_M ((RTC_GPIO_PIN7_INT_TYPE_V)<<(RTC_GPIO_PIN7_INT_TYPE_S))
+#define RTC_GPIO_PIN7_INT_TYPE_V 0x7
+#define RTC_GPIO_PIN7_INT_TYPE_S 7
+/* RTC_GPIO_PIN7_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */
+/*description: if set to 0: normal output if set to 1: open drain*/
+#define RTC_GPIO_PIN7_PAD_DRIVER (BIT(2))
+#define RTC_GPIO_PIN7_PAD_DRIVER_M (BIT(2))
+#define RTC_GPIO_PIN7_PAD_DRIVER_V 0x1
+#define RTC_GPIO_PIN7_PAD_DRIVER_S 2
+
+#define RTC_GPIO_PIN8_REG (DR_REG_RTCIO_BASE + 0x48)
+/* RTC_GPIO_PIN8_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */
+/*description: GPIO wake up enable only available in light sleep*/
+#define RTC_GPIO_PIN8_WAKEUP_ENABLE (BIT(10))
+#define RTC_GPIO_PIN8_WAKEUP_ENABLE_M (BIT(10))
+#define RTC_GPIO_PIN8_WAKEUP_ENABLE_V 0x1
+#define RTC_GPIO_PIN8_WAKEUP_ENABLE_S 10
+/* RTC_GPIO_PIN8_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */
+/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge
+ trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/
+#define RTC_GPIO_PIN8_INT_TYPE 0x00000007
+#define RTC_GPIO_PIN8_INT_TYPE_M ((RTC_GPIO_PIN8_INT_TYPE_V)<<(RTC_GPIO_PIN8_INT_TYPE_S))
+#define RTC_GPIO_PIN8_INT_TYPE_V 0x7
+#define RTC_GPIO_PIN8_INT_TYPE_S 7
+/* RTC_GPIO_PIN8_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */
+/*description: if set to 0: normal output if set to 1: open drain*/
+#define RTC_GPIO_PIN8_PAD_DRIVER (BIT(2))
+#define RTC_GPIO_PIN8_PAD_DRIVER_M (BIT(2))
+#define RTC_GPIO_PIN8_PAD_DRIVER_V 0x1
+#define RTC_GPIO_PIN8_PAD_DRIVER_S 2
+
+#define RTC_GPIO_PIN9_REG (DR_REG_RTCIO_BASE + 0x4c)
+/* RTC_GPIO_PIN9_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */
+/*description: GPIO wake up enable only available in light sleep*/
+#define RTC_GPIO_PIN9_WAKEUP_ENABLE (BIT(10))
+#define RTC_GPIO_PIN9_WAKEUP_ENABLE_M (BIT(10))
+#define RTC_GPIO_PIN9_WAKEUP_ENABLE_V 0x1
+#define RTC_GPIO_PIN9_WAKEUP_ENABLE_S 10
+/* RTC_GPIO_PIN9_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */
+/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge
+ trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/
+#define RTC_GPIO_PIN9_INT_TYPE 0x00000007
+#define RTC_GPIO_PIN9_INT_TYPE_M ((RTC_GPIO_PIN9_INT_TYPE_V)<<(RTC_GPIO_PIN9_INT_TYPE_S))
+#define RTC_GPIO_PIN9_INT_TYPE_V 0x7
+#define RTC_GPIO_PIN9_INT_TYPE_S 7
+/* RTC_GPIO_PIN9_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */
+/*description: if set to 0: normal output if set to 1: open drain*/
+#define RTC_GPIO_PIN9_PAD_DRIVER (BIT(2))
+#define RTC_GPIO_PIN9_PAD_DRIVER_M (BIT(2))
+#define RTC_GPIO_PIN9_PAD_DRIVER_V 0x1
+#define RTC_GPIO_PIN9_PAD_DRIVER_S 2
+
+#define RTC_GPIO_PIN10_REG (DR_REG_RTCIO_BASE + 0x50)
+/* RTC_GPIO_PIN10_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */
+/*description: GPIO wake up enable only available in light sleep*/
+#define RTC_GPIO_PIN10_WAKEUP_ENABLE (BIT(10))
+#define RTC_GPIO_PIN10_WAKEUP_ENABLE_M (BIT(10))
+#define RTC_GPIO_PIN10_WAKEUP_ENABLE_V 0x1
+#define RTC_GPIO_PIN10_WAKEUP_ENABLE_S 10
+/* RTC_GPIO_PIN10_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */
+/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge
+ trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/
+#define RTC_GPIO_PIN10_INT_TYPE 0x00000007
+#define RTC_GPIO_PIN10_INT_TYPE_M ((RTC_GPIO_PIN10_INT_TYPE_V)<<(RTC_GPIO_PIN10_INT_TYPE_S))
+#define RTC_GPIO_PIN10_INT_TYPE_V 0x7
+#define RTC_GPIO_PIN10_INT_TYPE_S 7
+/* RTC_GPIO_PIN10_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */
+/*description: if set to 0: normal output if set to 1: open drain*/
+#define RTC_GPIO_PIN10_PAD_DRIVER (BIT(2))
+#define RTC_GPIO_PIN10_PAD_DRIVER_M (BIT(2))
+#define RTC_GPIO_PIN10_PAD_DRIVER_V 0x1
+#define RTC_GPIO_PIN10_PAD_DRIVER_S 2
+
+#define RTC_GPIO_PIN11_REG (DR_REG_RTCIO_BASE + 0x54)
+/* RTC_GPIO_PIN11_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */
+/*description: GPIO wake up enable only available in light sleep*/
+#define RTC_GPIO_PIN11_WAKEUP_ENABLE (BIT(10))
+#define RTC_GPIO_PIN11_WAKEUP_ENABLE_M (BIT(10))
+#define RTC_GPIO_PIN11_WAKEUP_ENABLE_V 0x1
+#define RTC_GPIO_PIN11_WAKEUP_ENABLE_S 10
+/* RTC_GPIO_PIN11_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */
+/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge
+ trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/
+#define RTC_GPIO_PIN11_INT_TYPE 0x00000007
+#define RTC_GPIO_PIN11_INT_TYPE_M ((RTC_GPIO_PIN11_INT_TYPE_V)<<(RTC_GPIO_PIN11_INT_TYPE_S))
+#define RTC_GPIO_PIN11_INT_TYPE_V 0x7
+#define RTC_GPIO_PIN11_INT_TYPE_S 7
+/* RTC_GPIO_PIN11_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */
+/*description: if set to 0: normal output if set to 1: open drain*/
+#define RTC_GPIO_PIN11_PAD_DRIVER (BIT(2))
+#define RTC_GPIO_PIN11_PAD_DRIVER_M (BIT(2))
+#define RTC_GPIO_PIN11_PAD_DRIVER_V 0x1
+#define RTC_GPIO_PIN11_PAD_DRIVER_S 2
+
+#define RTC_GPIO_PIN12_REG (DR_REG_RTCIO_BASE + 0x58)
+/* RTC_GPIO_PIN12_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */
+/*description: GPIO wake up enable only available in light sleep*/
+#define RTC_GPIO_PIN12_WAKEUP_ENABLE (BIT(10))
+#define RTC_GPIO_PIN12_WAKEUP_ENABLE_M (BIT(10))
+#define RTC_GPIO_PIN12_WAKEUP_ENABLE_V 0x1
+#define RTC_GPIO_PIN12_WAKEUP_ENABLE_S 10
+/* RTC_GPIO_PIN12_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */
+/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge
+ trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/
+#define RTC_GPIO_PIN12_INT_TYPE 0x00000007
+#define RTC_GPIO_PIN12_INT_TYPE_M ((RTC_GPIO_PIN12_INT_TYPE_V)<<(RTC_GPIO_PIN12_INT_TYPE_S))
+#define RTC_GPIO_PIN12_INT_TYPE_V 0x7
+#define RTC_GPIO_PIN12_INT_TYPE_S 7
+/* RTC_GPIO_PIN12_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */
+/*description: if set to 0: normal output if set to 1: open drain*/
+#define RTC_GPIO_PIN12_PAD_DRIVER (BIT(2))
+#define RTC_GPIO_PIN12_PAD_DRIVER_M (BIT(2))
+#define RTC_GPIO_PIN12_PAD_DRIVER_V 0x1
+#define RTC_GPIO_PIN12_PAD_DRIVER_S 2
+
+#define RTC_GPIO_PIN13_REG (DR_REG_RTCIO_BASE + 0x5c)
+/* RTC_GPIO_PIN13_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */
+/*description: GPIO wake up enable only available in light sleep*/
+#define RTC_GPIO_PIN13_WAKEUP_ENABLE (BIT(10))
+#define RTC_GPIO_PIN13_WAKEUP_ENABLE_M (BIT(10))
+#define RTC_GPIO_PIN13_WAKEUP_ENABLE_V 0x1
+#define RTC_GPIO_PIN13_WAKEUP_ENABLE_S 10
+/* RTC_GPIO_PIN13_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */
+/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge
+ trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/
+#define RTC_GPIO_PIN13_INT_TYPE 0x00000007
+#define RTC_GPIO_PIN13_INT_TYPE_M ((RTC_GPIO_PIN13_INT_TYPE_V)<<(RTC_GPIO_PIN13_INT_TYPE_S))
+#define RTC_GPIO_PIN13_INT_TYPE_V 0x7
+#define RTC_GPIO_PIN13_INT_TYPE_S 7
+/* RTC_GPIO_PIN13_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */
+/*description: if set to 0: normal output if set to 1: open drain*/
+#define RTC_GPIO_PIN13_PAD_DRIVER (BIT(2))
+#define RTC_GPIO_PIN13_PAD_DRIVER_M (BIT(2))
+#define RTC_GPIO_PIN13_PAD_DRIVER_V 0x1
+#define RTC_GPIO_PIN13_PAD_DRIVER_S 2
+
+#define RTC_GPIO_PIN14_REG (DR_REG_RTCIO_BASE + 0x60)
+/* RTC_GPIO_PIN14_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */
+/*description: GPIO wake up enable only available in light sleep*/
+#define RTC_GPIO_PIN14_WAKEUP_ENABLE (BIT(10))
+#define RTC_GPIO_PIN14_WAKEUP_ENABLE_M (BIT(10))
+#define RTC_GPIO_PIN14_WAKEUP_ENABLE_V 0x1
+#define RTC_GPIO_PIN14_WAKEUP_ENABLE_S 10
+/* RTC_GPIO_PIN14_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */
+/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge
+ trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/
+#define RTC_GPIO_PIN14_INT_TYPE 0x00000007
+#define RTC_GPIO_PIN14_INT_TYPE_M ((RTC_GPIO_PIN14_INT_TYPE_V)<<(RTC_GPIO_PIN14_INT_TYPE_S))
+#define RTC_GPIO_PIN14_INT_TYPE_V 0x7
+#define RTC_GPIO_PIN14_INT_TYPE_S 7
+/* RTC_GPIO_PIN14_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */
+/*description: if set to 0: normal output if set to 1: open drain*/
+#define RTC_GPIO_PIN14_PAD_DRIVER (BIT(2))
+#define RTC_GPIO_PIN14_PAD_DRIVER_M (BIT(2))
+#define RTC_GPIO_PIN14_PAD_DRIVER_V 0x1
+#define RTC_GPIO_PIN14_PAD_DRIVER_S 2
+
+#define RTC_GPIO_PIN15_REG (DR_REG_RTCIO_BASE + 0x64)
+/* RTC_GPIO_PIN15_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */
+/*description: GPIO wake up enable only available in light sleep*/
+#define RTC_GPIO_PIN15_WAKEUP_ENABLE (BIT(10))
+#define RTC_GPIO_PIN15_WAKEUP_ENABLE_M (BIT(10))
+#define RTC_GPIO_PIN15_WAKEUP_ENABLE_V 0x1
+#define RTC_GPIO_PIN15_WAKEUP_ENABLE_S 10
+/* RTC_GPIO_PIN15_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */
+/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge
+ trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/
+#define RTC_GPIO_PIN15_INT_TYPE 0x00000007
+#define RTC_GPIO_PIN15_INT_TYPE_M ((RTC_GPIO_PIN15_INT_TYPE_V)<<(RTC_GPIO_PIN15_INT_TYPE_S))
+#define RTC_GPIO_PIN15_INT_TYPE_V 0x7
+#define RTC_GPIO_PIN15_INT_TYPE_S 7
+/* RTC_GPIO_PIN15_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */
+/*description: if set to 0: normal output if set to 1: open drain*/
+#define RTC_GPIO_PIN15_PAD_DRIVER (BIT(2))
+#define RTC_GPIO_PIN15_PAD_DRIVER_M (BIT(2))
+#define RTC_GPIO_PIN15_PAD_DRIVER_V 0x1
+#define RTC_GPIO_PIN15_PAD_DRIVER_S 2
+
+#define RTC_GPIO_PIN16_REG (DR_REG_RTCIO_BASE + 0x68)
+/* RTC_GPIO_PIN16_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */
+/*description: GPIO wake up enable only available in light sleep*/
+#define RTC_GPIO_PIN16_WAKEUP_ENABLE (BIT(10))
+#define RTC_GPIO_PIN16_WAKEUP_ENABLE_M (BIT(10))
+#define RTC_GPIO_PIN16_WAKEUP_ENABLE_V 0x1
+#define RTC_GPIO_PIN16_WAKEUP_ENABLE_S 10
+/* RTC_GPIO_PIN16_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */
+/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge
+ trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/
+#define RTC_GPIO_PIN16_INT_TYPE 0x00000007
+#define RTC_GPIO_PIN16_INT_TYPE_M ((RTC_GPIO_PIN16_INT_TYPE_V)<<(RTC_GPIO_PIN16_INT_TYPE_S))
+#define RTC_GPIO_PIN16_INT_TYPE_V 0x7
+#define RTC_GPIO_PIN16_INT_TYPE_S 7
+/* RTC_GPIO_PIN16_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */
+/*description: if set to 0: normal output if set to 1: open drain*/
+#define RTC_GPIO_PIN16_PAD_DRIVER (BIT(2))
+#define RTC_GPIO_PIN16_PAD_DRIVER_M (BIT(2))
+#define RTC_GPIO_PIN16_PAD_DRIVER_V 0x1
+#define RTC_GPIO_PIN16_PAD_DRIVER_S 2
+
+#define RTC_GPIO_PIN17_REG (DR_REG_RTCIO_BASE + 0x6c)
+/* RTC_GPIO_PIN17_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */
+/*description: GPIO wake up enable only available in light sleep*/
+#define RTC_GPIO_PIN17_WAKEUP_ENABLE (BIT(10))
+#define RTC_GPIO_PIN17_WAKEUP_ENABLE_M (BIT(10))
+#define RTC_GPIO_PIN17_WAKEUP_ENABLE_V 0x1
+#define RTC_GPIO_PIN17_WAKEUP_ENABLE_S 10
+/* RTC_GPIO_PIN17_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */
+/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge
+ trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/
+#define RTC_GPIO_PIN17_INT_TYPE 0x00000007
+#define RTC_GPIO_PIN17_INT_TYPE_M ((RTC_GPIO_PIN17_INT_TYPE_V)<<(RTC_GPIO_PIN17_INT_TYPE_S))
+#define RTC_GPIO_PIN17_INT_TYPE_V 0x7
+#define RTC_GPIO_PIN17_INT_TYPE_S 7
+/* RTC_GPIO_PIN17_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */
+/*description: if set to 0: normal output if set to 1: open drain*/
+#define RTC_GPIO_PIN17_PAD_DRIVER (BIT(2))
+#define RTC_GPIO_PIN17_PAD_DRIVER_M (BIT(2))
+#define RTC_GPIO_PIN17_PAD_DRIVER_V 0x1
+#define RTC_GPIO_PIN17_PAD_DRIVER_S 2
+
+#define RTC_IO_RTC_DEBUG_SEL_REG (DR_REG_RTCIO_BASE + 0x70)
+/* RTC_IO_DEBUG_12M_NO_GATING : R/W ;bitpos:[25] ;default: 1'd0 ; */
+/*description: */
+#define RTC_IO_DEBUG_12M_NO_GATING (BIT(25))
+#define RTC_IO_DEBUG_12M_NO_GATING_M (BIT(25))
+#define RTC_IO_DEBUG_12M_NO_GATING_V 0x1
+#define RTC_IO_DEBUG_12M_NO_GATING_S 25
+/* RTC_IO_DEBUG_SEL4 : R/W ;bitpos:[24:20] ;default: 5'd0 ; */
+/*description: */
+#define RTC_IO_DEBUG_SEL4 0x0000001F
+#define RTC_IO_DEBUG_SEL4_M ((RTC_IO_DEBUG_SEL4_V)<<(RTC_IO_DEBUG_SEL4_S))
+#define RTC_IO_DEBUG_SEL4_V 0x1F
+#define RTC_IO_DEBUG_SEL4_S 20
+/* RTC_IO_DEBUG_SEL3 : R/W ;bitpos:[19:15] ;default: 5'd0 ; */
+/*description: */
+#define RTC_IO_DEBUG_SEL3 0x0000001F
+#define RTC_IO_DEBUG_SEL3_M ((RTC_IO_DEBUG_SEL3_V)<<(RTC_IO_DEBUG_SEL3_S))
+#define RTC_IO_DEBUG_SEL3_V 0x1F
+#define RTC_IO_DEBUG_SEL3_S 15
+/* RTC_IO_DEBUG_SEL2 : R/W ;bitpos:[14:10] ;default: 5'd0 ; */
+/*description: */
+#define RTC_IO_DEBUG_SEL2 0x0000001F
+#define RTC_IO_DEBUG_SEL2_M ((RTC_IO_DEBUG_SEL2_V)<<(RTC_IO_DEBUG_SEL2_S))
+#define RTC_IO_DEBUG_SEL2_V 0x1F
+#define RTC_IO_DEBUG_SEL2_S 10
+/* RTC_IO_DEBUG_SEL1 : R/W ;bitpos:[9:5] ;default: 5'd0 ; */
+/*description: */
+#define RTC_IO_DEBUG_SEL1 0x0000001F
+#define RTC_IO_DEBUG_SEL1_M ((RTC_IO_DEBUG_SEL1_V)<<(RTC_IO_DEBUG_SEL1_S))
+#define RTC_IO_DEBUG_SEL1_V 0x1F
+#define RTC_IO_DEBUG_SEL1_S 5
+/* RTC_IO_DEBUG_SEL0 : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
+/*description: */
+#define RTC_IO_DEBUG_SEL0 0x0000001F
+#define RTC_IO_DEBUG_SEL0_M ((RTC_IO_DEBUG_SEL0_V)<<(RTC_IO_DEBUG_SEL0_S))
+#define RTC_IO_DEBUG_SEL0_V 0x1F
+#define RTC_IO_DEBUG_SEL0_S 0
+
+#define RTC_IO_DIG_PAD_HOLD_REG (DR_REG_RTCIO_BASE + 0x74)
+/* RTC_IO_DIG_PAD_HOLD : R/W ;bitpos:[31:0] ;default: 1'd0 ; */
+/*description: select the digital pad hold value.*/
+#define RTC_IO_DIG_PAD_HOLD 0xFFFFFFFF
+#define RTC_IO_DIG_PAD_HOLD_M ((RTC_IO_DIG_PAD_HOLD_V)<<(RTC_IO_DIG_PAD_HOLD_S))
+#define RTC_IO_DIG_PAD_HOLD_V 0xFFFFFFFF
+#define RTC_IO_DIG_PAD_HOLD_S 0
+
+#define RTC_IO_HALL_SENS_REG (DR_REG_RTCIO_BASE + 0x78)
+/* RTC_IO_XPD_HALL : R/W ;bitpos:[31] ;default: 1'd0 ; */
+/*description: Power on hall sensor and connect to VP and VN*/
+#define RTC_IO_XPD_HALL (BIT(31))
+#define RTC_IO_XPD_HALL_M (BIT(31))
+#define RTC_IO_XPD_HALL_V 0x1
+#define RTC_IO_XPD_HALL_S 31
+/* RTC_IO_HALL_PHASE : R/W ;bitpos:[30] ;default: 1'd0 ; */
+/*description: Reverse phase of hall sensor*/
+#define RTC_IO_HALL_PHASE (BIT(30))
+#define RTC_IO_HALL_PHASE_M (BIT(30))
+#define RTC_IO_HALL_PHASE_V 0x1
+#define RTC_IO_HALL_PHASE_S 30
+
+#define RTC_IO_SENSOR_PADS_REG (DR_REG_RTCIO_BASE + 0x7c)
+/* RTC_IO_SENSE1_HOLD : R/W ;bitpos:[31] ;default: 1'd0 ; */
+/*description: hold the current value of the output when setting the hold to Ò1Ó*/
+#define RTC_IO_SENSE1_HOLD (BIT(31))
+#define RTC_IO_SENSE1_HOLD_M (BIT(31))
+#define RTC_IO_SENSE1_HOLD_V 0x1
+#define RTC_IO_SENSE1_HOLD_S 31
+/* RTC_IO_SENSE2_HOLD : R/W ;bitpos:[30] ;default: 1'd0 ; */
+/*description: hold the current value of the output when setting the hold to Ò1Ó*/
+#define RTC_IO_SENSE2_HOLD (BIT(30))
+#define RTC_IO_SENSE2_HOLD_M (BIT(30))
+#define RTC_IO_SENSE2_HOLD_V 0x1
+#define RTC_IO_SENSE2_HOLD_S 30
+/* RTC_IO_SENSE3_HOLD : R/W ;bitpos:[29] ;default: 1'd0 ; */
+/*description: hold the current value of the output when setting the hold to Ò1Ó*/
+#define RTC_IO_SENSE3_HOLD (BIT(29))
+#define RTC_IO_SENSE3_HOLD_M (BIT(29))
+#define RTC_IO_SENSE3_HOLD_V 0x1
+#define RTC_IO_SENSE3_HOLD_S 29
+/* RTC_IO_SENSE4_HOLD : R/W ;bitpos:[28] ;default: 1'd0 ; */
+/*description: hold the current value of the output when setting the hold to Ò1Ó*/
+#define RTC_IO_SENSE4_HOLD (BIT(28))
+#define RTC_IO_SENSE4_HOLD_M (BIT(28))
+#define RTC_IO_SENSE4_HOLD_V 0x1
+#define RTC_IO_SENSE4_HOLD_S 28
+/* RTC_IO_SENSE1_MUX_SEL : R/W ;bitpos:[27] ;default: 1'd0 ; */
+/*description: Ò1Ó select the digital function Ó0Óslection the rtc function*/
+#define RTC_IO_SENSE1_MUX_SEL (BIT(27))
+#define RTC_IO_SENSE1_MUX_SEL_M (BIT(27))
+#define RTC_IO_SENSE1_MUX_SEL_V 0x1
+#define RTC_IO_SENSE1_MUX_SEL_S 27
+/* RTC_IO_SENSE2_MUX_SEL : R/W ;bitpos:[26] ;default: 1'd0 ; */
+/*description: Ò1Ó select the digital function Ó0Óslection the rtc function*/
+#define RTC_IO_SENSE2_MUX_SEL (BIT(26))
+#define RTC_IO_SENSE2_MUX_SEL_M (BIT(26))
+#define RTC_IO_SENSE2_MUX_SEL_V 0x1
+#define RTC_IO_SENSE2_MUX_SEL_S 26
+/* RTC_IO_SENSE3_MUX_SEL : R/W ;bitpos:[25] ;default: 1'd0 ; */
+/*description: Ò1Ó select the digital function Ó0Óslection the rtc function*/
+#define RTC_IO_SENSE3_MUX_SEL (BIT(25))
+#define RTC_IO_SENSE3_MUX_SEL_M (BIT(25))
+#define RTC_IO_SENSE3_MUX_SEL_V 0x1
+#define RTC_IO_SENSE3_MUX_SEL_S 25
+/* RTC_IO_SENSE4_MUX_SEL : R/W ;bitpos:[24] ;default: 1'd0 ; */
+/*description: Ò1Ó select the digital function Ó0Óslection the rtc function*/
+#define RTC_IO_SENSE4_MUX_SEL (BIT(24))
+#define RTC_IO_SENSE4_MUX_SEL_M (BIT(24))
+#define RTC_IO_SENSE4_MUX_SEL_V 0x1
+#define RTC_IO_SENSE4_MUX_SEL_S 24
+/* RTC_IO_SENSE1_FUN_SEL : R/W ;bitpos:[23:22] ;default: 2'd0 ; */
+/*description: the functional selection signal of the pad*/
+#define RTC_IO_SENSE1_FUN_SEL 0x00000003
+#define RTC_IO_SENSE1_FUN_SEL_M ((RTC_IO_SENSE1_FUN_SEL_V)<<(RTC_IO_SENSE1_FUN_SEL_S))
+#define RTC_IO_SENSE1_FUN_SEL_V 0x3
+#define RTC_IO_SENSE1_FUN_SEL_S 22
+/* RTC_IO_SENSE1_SLP_SEL : R/W ;bitpos:[21] ;default: 1'd0 ; */
+/*description: the sleep status selection signal of the pad*/
+#define RTC_IO_SENSE1_SLP_SEL (BIT(21))
+#define RTC_IO_SENSE1_SLP_SEL_M (BIT(21))
+#define RTC_IO_SENSE1_SLP_SEL_V 0x1
+#define RTC_IO_SENSE1_SLP_SEL_S 21
+/* RTC_IO_SENSE1_SLP_IE : R/W ;bitpos:[20] ;default: 1'd0 ; */
+/*description: the input enable of the pad in sleep status*/
+#define RTC_IO_SENSE1_SLP_IE (BIT(20))
+#define RTC_IO_SENSE1_SLP_IE_M (BIT(20))
+#define RTC_IO_SENSE1_SLP_IE_V 0x1
+#define RTC_IO_SENSE1_SLP_IE_S 20
+/* RTC_IO_SENSE1_FUN_IE : R/W ;bitpos:[19] ;default: 1'd0 ; */
+/*description: the input enable of the pad*/
+#define RTC_IO_SENSE1_FUN_IE (BIT(19))
+#define RTC_IO_SENSE1_FUN_IE_M (BIT(19))
+#define RTC_IO_SENSE1_FUN_IE_V 0x1
+#define RTC_IO_SENSE1_FUN_IE_S 19
+/* RTC_IO_SENSE2_FUN_SEL : R/W ;bitpos:[18:17] ;default: 2'd0 ; */
+/*description: the functional selection signal of the pad*/
+#define RTC_IO_SENSE2_FUN_SEL 0x00000003
+#define RTC_IO_SENSE2_FUN_SEL_M ((RTC_IO_SENSE2_FUN_SEL_V)<<(RTC_IO_SENSE2_FUN_SEL_S))
+#define RTC_IO_SENSE2_FUN_SEL_V 0x3
+#define RTC_IO_SENSE2_FUN_SEL_S 17
+/* RTC_IO_SENSE2_SLP_SEL : R/W ;bitpos:[16] ;default: 1'd0 ; */
+/*description: the sleep status selection signal of the pad*/
+#define RTC_IO_SENSE2_SLP_SEL (BIT(16))
+#define RTC_IO_SENSE2_SLP_SEL_M (BIT(16))
+#define RTC_IO_SENSE2_SLP_SEL_V 0x1
+#define RTC_IO_SENSE2_SLP_SEL_S 16
+/* RTC_IO_SENSE2_SLP_IE : R/W ;bitpos:[15] ;default: 1'd0 ; */
+/*description: the input enable of the pad in sleep status*/
+#define RTC_IO_SENSE2_SLP_IE (BIT(15))
+#define RTC_IO_SENSE2_SLP_IE_M (BIT(15))
+#define RTC_IO_SENSE2_SLP_IE_V 0x1
+#define RTC_IO_SENSE2_SLP_IE_S 15
+/* RTC_IO_SENSE2_FUN_IE : R/W ;bitpos:[14] ;default: 1'd0 ; */
+/*description: the input enable of the pad*/
+#define RTC_IO_SENSE2_FUN_IE (BIT(14))
+#define RTC_IO_SENSE2_FUN_IE_M (BIT(14))
+#define RTC_IO_SENSE2_FUN_IE_V 0x1
+#define RTC_IO_SENSE2_FUN_IE_S 14
+/* RTC_IO_SENSE3_FUN_SEL : R/W ;bitpos:[13:12] ;default: 2'd0 ; */
+/*description: the functional selection signal of the pad*/
+#define RTC_IO_SENSE3_FUN_SEL 0x00000003
+#define RTC_IO_SENSE3_FUN_SEL_M ((RTC_IO_SENSE3_FUN_SEL_V)<<(RTC_IO_SENSE3_FUN_SEL_S))
+#define RTC_IO_SENSE3_FUN_SEL_V 0x3
+#define RTC_IO_SENSE3_FUN_SEL_S 12
+/* RTC_IO_SENSE3_SLP_SEL : R/W ;bitpos:[11] ;default: 1'd0 ; */
+/*description: the sleep status selection signal of the pad*/
+#define RTC_IO_SENSE3_SLP_SEL (BIT(11))
+#define RTC_IO_SENSE3_SLP_SEL_M (BIT(11))
+#define RTC_IO_SENSE3_SLP_SEL_V 0x1
+#define RTC_IO_SENSE3_SLP_SEL_S 11
+/* RTC_IO_SENSE3_SLP_IE : R/W ;bitpos:[10] ;default: 1'd0 ; */
+/*description: the input enable of the pad in sleep status*/
+#define RTC_IO_SENSE3_SLP_IE (BIT(10))
+#define RTC_IO_SENSE3_SLP_IE_M (BIT(10))
+#define RTC_IO_SENSE3_SLP_IE_V 0x1
+#define RTC_IO_SENSE3_SLP_IE_S 10
+/* RTC_IO_SENSE3_FUN_IE : R/W ;bitpos:[9] ;default: 1'd0 ; */
+/*description: the input enable of the pad*/
+#define RTC_IO_SENSE3_FUN_IE (BIT(9))
+#define RTC_IO_SENSE3_FUN_IE_M (BIT(9))
+#define RTC_IO_SENSE3_FUN_IE_V 0x1
+#define RTC_IO_SENSE3_FUN_IE_S 9
+/* RTC_IO_SENSE4_FUN_SEL : R/W ;bitpos:[8:7] ;default: 2'd0 ; */
+/*description: the functional selection signal of the pad*/
+#define RTC_IO_SENSE4_FUN_SEL 0x00000003
+#define RTC_IO_SENSE4_FUN_SEL_M ((RTC_IO_SENSE4_FUN_SEL_V)<<(RTC_IO_SENSE4_FUN_SEL_S))
+#define RTC_IO_SENSE4_FUN_SEL_V 0x3
+#define RTC_IO_SENSE4_FUN_SEL_S 7
+/* RTC_IO_SENSE4_SLP_SEL : R/W ;bitpos:[6] ;default: 1'd0 ; */
+/*description: the sleep status selection signal of the pad*/
+#define RTC_IO_SENSE4_SLP_SEL (BIT(6))
+#define RTC_IO_SENSE4_SLP_SEL_M (BIT(6))
+#define RTC_IO_SENSE4_SLP_SEL_V 0x1
+#define RTC_IO_SENSE4_SLP_SEL_S 6
+/* RTC_IO_SENSE4_SLP_IE : R/W ;bitpos:[5] ;default: 1'd0 ; */
+/*description: the input enable of the pad in sleep status*/
+#define RTC_IO_SENSE4_SLP_IE (BIT(5))
+#define RTC_IO_SENSE4_SLP_IE_M (BIT(5))
+#define RTC_IO_SENSE4_SLP_IE_V 0x1
+#define RTC_IO_SENSE4_SLP_IE_S 5
+/* RTC_IO_SENSE4_FUN_IE : R/W ;bitpos:[4] ;default: 1'd0 ; */
+/*description: the input enable of the pad*/
+#define RTC_IO_SENSE4_FUN_IE (BIT(4))
+#define RTC_IO_SENSE4_FUN_IE_M (BIT(4))
+#define RTC_IO_SENSE4_FUN_IE_V 0x1
+#define RTC_IO_SENSE4_FUN_IE_S 4
+
+#define RTC_IO_ADC_PAD_REG (DR_REG_RTCIO_BASE + 0x80)
+/* RTC_IO_ADC1_HOLD : R/W ;bitpos:[31] ;default: 1'd0 ; */
+/*description: hold the current value of the output when setting the hold to Ò1Ó*/
+#define RTC_IO_ADC1_HOLD (BIT(31))
+#define RTC_IO_ADC1_HOLD_M (BIT(31))
+#define RTC_IO_ADC1_HOLD_V 0x1
+#define RTC_IO_ADC1_HOLD_S 31
+/* RTC_IO_ADC2_HOLD : R/W ;bitpos:[30] ;default: 1'd0 ; */
+/*description: hold the current value of the output when setting the hold to Ò1Ó*/
+#define RTC_IO_ADC2_HOLD (BIT(30))
+#define RTC_IO_ADC2_HOLD_M (BIT(30))
+#define RTC_IO_ADC2_HOLD_V 0x1
+#define RTC_IO_ADC2_HOLD_S 30
+/* RTC_IO_ADC1_MUX_SEL : R/W ;bitpos:[29] ;default: 1'd0 ; */
+/*description: Ò1Ó select the digital function Ó0Óslection the rtc function*/
+#define RTC_IO_ADC1_MUX_SEL (BIT(29))
+#define RTC_IO_ADC1_MUX_SEL_M (BIT(29))
+#define RTC_IO_ADC1_MUX_SEL_V 0x1
+#define RTC_IO_ADC1_MUX_SEL_S 29
+/* RTC_IO_ADC2_MUX_SEL : R/W ;bitpos:[28] ;default: 1'd0 ; */
+/*description: Ò1Ó select the digital function Ó0Óslection the rtc function*/
+#define RTC_IO_ADC2_MUX_SEL (BIT(28))
+#define RTC_IO_ADC2_MUX_SEL_M (BIT(28))
+#define RTC_IO_ADC2_MUX_SEL_V 0x1
+#define RTC_IO_ADC2_MUX_SEL_S 28
+/* RTC_IO_ADC1_FUN_SEL : R/W ;bitpos:[27:26] ;default: 2'd0 ; */
+/*description: the functional selection signal of the pad*/
+#define RTC_IO_ADC1_FUN_SEL 0x00000003
+#define RTC_IO_ADC1_FUN_SEL_M ((RTC_IO_ADC1_FUN_SEL_V)<<(RTC_IO_ADC1_FUN_SEL_S))
+#define RTC_IO_ADC1_FUN_SEL_V 0x3
+#define RTC_IO_ADC1_FUN_SEL_S 26
+/* RTC_IO_ADC1_SLP_SEL : R/W ;bitpos:[25] ;default: 1'd0 ; */
+/*description: the sleep status selection signal of the pad*/
+#define RTC_IO_ADC1_SLP_SEL (BIT(25))
+#define RTC_IO_ADC1_SLP_SEL_M (BIT(25))
+#define RTC_IO_ADC1_SLP_SEL_V 0x1
+#define RTC_IO_ADC1_SLP_SEL_S 25
+/* RTC_IO_ADC1_SLP_IE : R/W ;bitpos:[24] ;default: 1'd0 ; */
+/*description: the input enable of the pad in sleep status*/
+#define RTC_IO_ADC1_SLP_IE (BIT(24))
+#define RTC_IO_ADC1_SLP_IE_M (BIT(24))
+#define RTC_IO_ADC1_SLP_IE_V 0x1
+#define RTC_IO_ADC1_SLP_IE_S 24
+/* RTC_IO_ADC1_FUN_IE : R/W ;bitpos:[23] ;default: 1'd0 ; */
+/*description: the input enable of the pad*/
+#define RTC_IO_ADC1_FUN_IE (BIT(23))
+#define RTC_IO_ADC1_FUN_IE_M (BIT(23))
+#define RTC_IO_ADC1_FUN_IE_V 0x1
+#define RTC_IO_ADC1_FUN_IE_S 23
+/* RTC_IO_ADC2_FUN_SEL : R/W ;bitpos:[22:21] ;default: 2'd0 ; */
+/*description: the functional selection signal of the pad*/
+#define RTC_IO_ADC2_FUN_SEL 0x00000003
+#define RTC_IO_ADC2_FUN_SEL_M ((RTC_IO_ADC2_FUN_SEL_V)<<(RTC_IO_ADC2_FUN_SEL_S))
+#define RTC_IO_ADC2_FUN_SEL_V 0x3
+#define RTC_IO_ADC2_FUN_SEL_S 21
+/* RTC_IO_ADC2_SLP_SEL : R/W ;bitpos:[20] ;default: 1'd0 ; */
+/*description: the sleep status selection signal of the pad*/
+#define RTC_IO_ADC2_SLP_SEL (BIT(20))
+#define RTC_IO_ADC2_SLP_SEL_M (BIT(20))
+#define RTC_IO_ADC2_SLP_SEL_V 0x1
+#define RTC_IO_ADC2_SLP_SEL_S 20
+/* RTC_IO_ADC2_SLP_IE : R/W ;bitpos:[19] ;default: 1'd0 ; */
+/*description: the input enable of the pad in sleep status*/
+#define RTC_IO_ADC2_SLP_IE (BIT(19))
+#define RTC_IO_ADC2_SLP_IE_M (BIT(19))
+#define RTC_IO_ADC2_SLP_IE_V 0x1
+#define RTC_IO_ADC2_SLP_IE_S 19
+/* RTC_IO_ADC2_FUN_IE : R/W ;bitpos:[18] ;default: 1'd0 ; */
+/*description: the input enable of the pad*/
+#define RTC_IO_ADC2_FUN_IE (BIT(18))
+#define RTC_IO_ADC2_FUN_IE_M (BIT(18))
+#define RTC_IO_ADC2_FUN_IE_V 0x1
+#define RTC_IO_ADC2_FUN_IE_S 18
+
+#define RTC_IO_PAD_DAC1_REG (DR_REG_RTCIO_BASE + 0x84)
+/* RTC_IO_PDAC1_DRV : R/W ;bitpos:[31:30] ;default: 2'd2 ; */
+/*description: the driver strength of the pad*/
+#define RTC_IO_PDAC1_DRV 0x00000003
+#define RTC_IO_PDAC1_DRV_M ((RTC_IO_PDAC1_DRV_V)<<(RTC_IO_PDAC1_DRV_S))
+#define RTC_IO_PDAC1_DRV_V 0x3
+#define RTC_IO_PDAC1_DRV_S 30
+/* RTC_IO_PDAC1_HOLD : R/W ;bitpos:[29] ;default: 1'd0 ; */
+/*description: hold the current value of the output when setting the hold to Ò1Ó*/
+#define RTC_IO_PDAC1_HOLD (BIT(29))
+#define RTC_IO_PDAC1_HOLD_M (BIT(29))
+#define RTC_IO_PDAC1_HOLD_V 0x1
+#define RTC_IO_PDAC1_HOLD_S 29
+/* RTC_IO_PDAC1_RDE : R/W ;bitpos:[28] ;default: 1'd0 ; */
+/*description: the pull down enable of the pad*/
+#define RTC_IO_PDAC1_RDE (BIT(28))
+#define RTC_IO_PDAC1_RDE_M (BIT(28))
+#define RTC_IO_PDAC1_RDE_V 0x1
+#define RTC_IO_PDAC1_RDE_S 28
+/* RTC_IO_PDAC1_RUE : R/W ;bitpos:[27] ;default: 1'd0 ; */
+/*description: the pull up enable of the pad*/
+#define RTC_IO_PDAC1_RUE (BIT(27))
+#define RTC_IO_PDAC1_RUE_M (BIT(27))
+#define RTC_IO_PDAC1_RUE_V 0x1
+#define RTC_IO_PDAC1_RUE_S 27
+/* RTC_IO_PDAC1_DAC : R/W ;bitpos:[26:19] ;default: 8'd0 ; */
+/*description: PAD DAC1 control code.*/
+#define RTC_IO_PDAC1_DAC 0x000000FF
+#define RTC_IO_PDAC1_DAC_M ((RTC_IO_PDAC1_DAC_V)<<(RTC_IO_PDAC1_DAC_S))
+#define RTC_IO_PDAC1_DAC_V 0xFF
+#define RTC_IO_PDAC1_DAC_S 19
+/* RTC_IO_PDAC1_XPD_DAC : R/W ;bitpos:[18] ;default: 1'd0 ; */
+/*description: Power on DAC1. Usually we need to tristate PDAC1 if we power
+ on the DAC i.e. IE=0 OE=0 RDE=0 RUE=0*/
+#define RTC_IO_PDAC1_XPD_DAC (BIT(18))
+#define RTC_IO_PDAC1_XPD_DAC_M (BIT(18))
+#define RTC_IO_PDAC1_XPD_DAC_V 0x1
+#define RTC_IO_PDAC1_XPD_DAC_S 18
+/* RTC_IO_PDAC1_MUX_SEL : R/W ;bitpos:[17] ;default: 1'd0 ; */
+/*description: Ò1Ó select the digital function Ó0Óslection the rtc function*/
+#define RTC_IO_PDAC1_MUX_SEL (BIT(17))
+#define RTC_IO_PDAC1_MUX_SEL_M (BIT(17))
+#define RTC_IO_PDAC1_MUX_SEL_V 0x1
+#define RTC_IO_PDAC1_MUX_SEL_S 17
+/* RTC_IO_PDAC1_FUN_SEL : R/W ;bitpos:[16:15] ;default: 2'd0 ; */
+/*description: the functional selection signal of the pad*/
+#define RTC_IO_PDAC1_FUN_SEL 0x00000003
+#define RTC_IO_PDAC1_FUN_SEL_M ((RTC_IO_PDAC1_FUN_SEL_V)<<(RTC_IO_PDAC1_FUN_SEL_S))
+#define RTC_IO_PDAC1_FUN_SEL_V 0x3
+#define RTC_IO_PDAC1_FUN_SEL_S 15
+/* RTC_IO_PDAC1_SLP_SEL : R/W ;bitpos:[14] ;default: 1'd0 ; */
+/*description: the sleep status selection signal of the pad*/
+#define RTC_IO_PDAC1_SLP_SEL (BIT(14))
+#define RTC_IO_PDAC1_SLP_SEL_M (BIT(14))
+#define RTC_IO_PDAC1_SLP_SEL_V 0x1
+#define RTC_IO_PDAC1_SLP_SEL_S 14
+/* RTC_IO_PDAC1_SLP_IE : R/W ;bitpos:[13] ;default: 1'd0 ; */
+/*description: the input enable of the pad in sleep status*/
+#define RTC_IO_PDAC1_SLP_IE (BIT(13))
+#define RTC_IO_PDAC1_SLP_IE_M (BIT(13))
+#define RTC_IO_PDAC1_SLP_IE_V 0x1
+#define RTC_IO_PDAC1_SLP_IE_S 13
+/* RTC_IO_PDAC1_SLP_OE : R/W ;bitpos:[12] ;default: 1'd0 ; */
+/*description: the output enable of the pad in sleep status*/
+#define RTC_IO_PDAC1_SLP_OE (BIT(12))
+#define RTC_IO_PDAC1_SLP_OE_M (BIT(12))
+#define RTC_IO_PDAC1_SLP_OE_V 0x1
+#define RTC_IO_PDAC1_SLP_OE_S 12
+/* RTC_IO_PDAC1_FUN_IE : R/W ;bitpos:[11] ;default: 1'd0 ; */
+/*description: the input enable of the pad*/
+#define RTC_IO_PDAC1_FUN_IE (BIT(11))
+#define RTC_IO_PDAC1_FUN_IE_M (BIT(11))
+#define RTC_IO_PDAC1_FUN_IE_V 0x1
+#define RTC_IO_PDAC1_FUN_IE_S 11
+/* RTC_IO_PDAC1_DAC_XPD_FORCE : R/W ;bitpos:[10] ;default: 1'd0 ; */
+/*description: Power on DAC1. Usually we need to tristate PDAC1 if we power
+ on the DAC i.e. IE=0 OE=0 RDE=0 RUE=0*/
+#define RTC_IO_PDAC1_DAC_XPD_FORCE (BIT(10))
+#define RTC_IO_PDAC1_DAC_XPD_FORCE_M (BIT(10))
+#define RTC_IO_PDAC1_DAC_XPD_FORCE_V 0x1
+#define RTC_IO_PDAC1_DAC_XPD_FORCE_S 10
+
+#define RTC_IO_PAD_DAC2_REG (DR_REG_RTCIO_BASE + 0x88)
+/* RTC_IO_PDAC2_DRV : R/W ;bitpos:[31:30] ;default: 2'd2 ; */
+/*description: the driver strength of the pad*/
+#define RTC_IO_PDAC2_DRV 0x00000003
+#define RTC_IO_PDAC2_DRV_M ((RTC_IO_PDAC2_DRV_V)<<(RTC_IO_PDAC2_DRV_S))
+#define RTC_IO_PDAC2_DRV_V 0x3
+#define RTC_IO_PDAC2_DRV_S 30
+/* RTC_IO_PDAC2_HOLD : R/W ;bitpos:[29] ;default: 1'd0 ; */
+/*description: hold the current value of the output when setting the hold to Ò1Ó*/
+#define RTC_IO_PDAC2_HOLD (BIT(29))
+#define RTC_IO_PDAC2_HOLD_M (BIT(29))
+#define RTC_IO_PDAC2_HOLD_V 0x1
+#define RTC_IO_PDAC2_HOLD_S 29
+/* RTC_IO_PDAC2_RDE : R/W ;bitpos:[28] ;default: 1'd0 ; */
+/*description: the pull down enable of the pad*/
+#define RTC_IO_PDAC2_RDE (BIT(28))
+#define RTC_IO_PDAC2_RDE_M (BIT(28))
+#define RTC_IO_PDAC2_RDE_V 0x1
+#define RTC_IO_PDAC2_RDE_S 28
+/* RTC_IO_PDAC2_RUE : R/W ;bitpos:[27] ;default: 1'd0 ; */
+/*description: the pull up enable of the pad*/
+#define RTC_IO_PDAC2_RUE (BIT(27))
+#define RTC_IO_PDAC2_RUE_M (BIT(27))
+#define RTC_IO_PDAC2_RUE_V 0x1
+#define RTC_IO_PDAC2_RUE_S 27
+/* RTC_IO_PDAC2_DAC : R/W ;bitpos:[26:19] ;default: 8'd0 ; */
+/*description: PAD DAC2 control code.*/
+#define RTC_IO_PDAC2_DAC 0x000000FF
+#define RTC_IO_PDAC2_DAC_M ((RTC_IO_PDAC2_DAC_V)<<(RTC_IO_PDAC2_DAC_S))
+#define RTC_IO_PDAC2_DAC_V 0xFF
+#define RTC_IO_PDAC2_DAC_S 19
+/* RTC_IO_PDAC2_XPD_DAC : R/W ;bitpos:[18] ;default: 1'd0 ; */
+/*description: Power on DAC2. Usually we need to tristate PDAC1 if we power
+ on the DAC i.e. IE=0 OE=0 RDE=0 RUE=0*/
+#define RTC_IO_PDAC2_XPD_DAC (BIT(18))
+#define RTC_IO_PDAC2_XPD_DAC_M (BIT(18))
+#define RTC_IO_PDAC2_XPD_DAC_V 0x1
+#define RTC_IO_PDAC2_XPD_DAC_S 18
+/* RTC_IO_PDAC2_MUX_SEL : R/W ;bitpos:[17] ;default: 1'd0 ; */
+/*description: Ò1Ó select the digital function Ó0Óslection the rtc function*/
+#define RTC_IO_PDAC2_MUX_SEL (BIT(17))
+#define RTC_IO_PDAC2_MUX_SEL_M (BIT(17))
+#define RTC_IO_PDAC2_MUX_SEL_V 0x1
+#define RTC_IO_PDAC2_MUX_SEL_S 17
+/* RTC_IO_PDAC2_FUN_SEL : R/W ;bitpos:[16:15] ;default: 2'd0 ; */
+/*description: the functional selection signal of the pad*/
+#define RTC_IO_PDAC2_FUN_SEL 0x00000003
+#define RTC_IO_PDAC2_FUN_SEL_M ((RTC_IO_PDAC2_FUN_SEL_V)<<(RTC_IO_PDAC2_FUN_SEL_S))
+#define RTC_IO_PDAC2_FUN_SEL_V 0x3
+#define RTC_IO_PDAC2_FUN_SEL_S 15
+/* RTC_IO_PDAC2_SLP_SEL : R/W ;bitpos:[14] ;default: 1'd0 ; */
+/*description: the sleep status selection signal of the pad*/
+#define RTC_IO_PDAC2_SLP_SEL (BIT(14))
+#define RTC_IO_PDAC2_SLP_SEL_M (BIT(14))
+#define RTC_IO_PDAC2_SLP_SEL_V 0x1
+#define RTC_IO_PDAC2_SLP_SEL_S 14
+/* RTC_IO_PDAC2_SLP_IE : R/W ;bitpos:[13] ;default: 1'd0 ; */
+/*description: the input enable of the pad in sleep status*/
+#define RTC_IO_PDAC2_SLP_IE (BIT(13))
+#define RTC_IO_PDAC2_SLP_IE_M (BIT(13))
+#define RTC_IO_PDAC2_SLP_IE_V 0x1
+#define RTC_IO_PDAC2_SLP_IE_S 13
+/* RTC_IO_PDAC2_SLP_OE : R/W ;bitpos:[12] ;default: 1'd0 ; */
+/*description: the output enable of the pad in sleep status*/
+#define RTC_IO_PDAC2_SLP_OE (BIT(12))
+#define RTC_IO_PDAC2_SLP_OE_M (BIT(12))
+#define RTC_IO_PDAC2_SLP_OE_V 0x1
+#define RTC_IO_PDAC2_SLP_OE_S 12
+/* RTC_IO_PDAC2_FUN_IE : R/W ;bitpos:[11] ;default: 1'd0 ; */
+/*description: the input enable of the pad*/
+#define RTC_IO_PDAC2_FUN_IE (BIT(11))
+#define RTC_IO_PDAC2_FUN_IE_M (BIT(11))
+#define RTC_IO_PDAC2_FUN_IE_V 0x1
+#define RTC_IO_PDAC2_FUN_IE_S 11
+/* RTC_IO_PDAC2_DAC_XPD_FORCE : R/W ;bitpos:[10] ;default: 1'd0 ; */
+/*description: Power on DAC2. Usually we need to tristate PDAC2 if we power
+ on the DAC i.e. IE=0 OE=0 RDE=0 RUE=0*/
+#define RTC_IO_PDAC2_DAC_XPD_FORCE (BIT(10))
+#define RTC_IO_PDAC2_DAC_XPD_FORCE_M (BIT(10))
+#define RTC_IO_PDAC2_DAC_XPD_FORCE_V 0x1
+#define RTC_IO_PDAC2_DAC_XPD_FORCE_S 10
+
+#define RTC_IO_XTAL_32K_PAD_REG (DR_REG_RTCIO_BASE + 0x8c)
+/* RTC_IO_X32N_DRV : R/W ;bitpos:[31:30] ;default: 2'd2 ; */
+/*description: the driver strength of the pad*/
+#define RTC_IO_X32N_DRV 0x00000003
+#define RTC_IO_X32N_DRV_M ((RTC_IO_X32N_DRV_V)<<(RTC_IO_X32N_DRV_S))
+#define RTC_IO_X32N_DRV_V 0x3
+#define RTC_IO_X32N_DRV_S 30
+/* RTC_IO_X32N_HOLD : R/W ;bitpos:[29] ;default: 1'd0 ; */
+/*description: hold the current value of the output when setting the hold to Ò1Ó*/
+#define RTC_IO_X32N_HOLD (BIT(29))
+#define RTC_IO_X32N_HOLD_M (BIT(29))
+#define RTC_IO_X32N_HOLD_V 0x1
+#define RTC_IO_X32N_HOLD_S 29
+/* RTC_IO_X32N_RDE : R/W ;bitpos:[28] ;default: 1'd0 ; */
+/*description: the pull down enable of the pad*/
+#define RTC_IO_X32N_RDE (BIT(28))
+#define RTC_IO_X32N_RDE_M (BIT(28))
+#define RTC_IO_X32N_RDE_V 0x1
+#define RTC_IO_X32N_RDE_S 28
+/* RTC_IO_X32N_RUE : R/W ;bitpos:[27] ;default: 1'd0 ; */
+/*description: the pull up enable of the pad*/
+#define RTC_IO_X32N_RUE (BIT(27))
+#define RTC_IO_X32N_RUE_M (BIT(27))
+#define RTC_IO_X32N_RUE_V 0x1
+#define RTC_IO_X32N_RUE_S 27
+/* RTC_IO_X32P_DRV : R/W ;bitpos:[26:25] ;default: 2'd2 ; */
+/*description: the driver strength of the pad*/
+#define RTC_IO_X32P_DRV 0x00000003
+#define RTC_IO_X32P_DRV_M ((RTC_IO_X32P_DRV_V)<<(RTC_IO_X32P_DRV_S))
+#define RTC_IO_X32P_DRV_V 0x3
+#define RTC_IO_X32P_DRV_S 25
+/* RTC_IO_X32P_HOLD : R/W ;bitpos:[24] ;default: 1'd0 ; */
+/*description: hold the current value of the output when setting the hold to Ò1Ó*/
+#define RTC_IO_X32P_HOLD (BIT(24))
+#define RTC_IO_X32P_HOLD_M (BIT(24))
+#define RTC_IO_X32P_HOLD_V 0x1
+#define RTC_IO_X32P_HOLD_S 24
+/* RTC_IO_X32P_RDE : R/W ;bitpos:[23] ;default: 1'd0 ; */
+/*description: the pull down enable of the pad*/
+#define RTC_IO_X32P_RDE (BIT(23))
+#define RTC_IO_X32P_RDE_M (BIT(23))
+#define RTC_IO_X32P_RDE_V 0x1
+#define RTC_IO_X32P_RDE_S 23
+/* RTC_IO_X32P_RUE : R/W ;bitpos:[22] ;default: 1'd0 ; */
+/*description: the pull up enable of the pad*/
+#define RTC_IO_X32P_RUE (BIT(22))
+#define RTC_IO_X32P_RUE_M (BIT(22))
+#define RTC_IO_X32P_RUE_V 0x1
+#define RTC_IO_X32P_RUE_S 22
+/* RTC_IO_DAC_XTAL_32K : R/W ;bitpos:[21:20] ;default: 2'b01 ; */
+/*description: 32K XTAL bias current DAC.*/
+#define RTC_IO_DAC_XTAL_32K 0x00000003
+#define RTC_IO_DAC_XTAL_32K_M ((RTC_IO_DAC_XTAL_32K_V)<<(RTC_IO_DAC_XTAL_32K_S))
+#define RTC_IO_DAC_XTAL_32K_V 0x3
+#define RTC_IO_DAC_XTAL_32K_S 20
+/* RTC_IO_XPD_XTAL_32K : R/W ;bitpos:[19] ;default: 1'd0 ; */
+/*description: Power up 32kHz crystal oscillator*/
+#define RTC_IO_XPD_XTAL_32K (BIT(19))
+#define RTC_IO_XPD_XTAL_32K_M (BIT(19))
+#define RTC_IO_XPD_XTAL_32K_V 0x1
+#define RTC_IO_XPD_XTAL_32K_S 19
+/* RTC_IO_X32N_MUX_SEL : R/W ;bitpos:[18] ;default: 1'd0 ; */
+/*description: Ò1Ó select the digital function Ó0Óslection the rtc function*/
+#define RTC_IO_X32N_MUX_SEL (BIT(18))
+#define RTC_IO_X32N_MUX_SEL_M (BIT(18))
+#define RTC_IO_X32N_MUX_SEL_V 0x1
+#define RTC_IO_X32N_MUX_SEL_S 18
+/* RTC_IO_X32P_MUX_SEL : R/W ;bitpos:[17] ;default: 1'd0 ; */
+/*description: Ò1Ó select the digital function Ó0Óslection the rtc function*/
+#define RTC_IO_X32P_MUX_SEL (BIT(17))
+#define RTC_IO_X32P_MUX_SEL_M (BIT(17))
+#define RTC_IO_X32P_MUX_SEL_V 0x1
+#define RTC_IO_X32P_MUX_SEL_S 17
+/* RTC_IO_X32N_FUN_SEL : R/W ;bitpos:[16:15] ;default: 2'd0 ; */
+/*description: the functional selection signal of the pad*/
+#define RTC_IO_X32N_FUN_SEL 0x00000003
+#define RTC_IO_X32N_FUN_SEL_M ((RTC_IO_X32N_FUN_SEL_V)<<(RTC_IO_X32N_FUN_SEL_S))
+#define RTC_IO_X32N_FUN_SEL_V 0x3
+#define RTC_IO_X32N_FUN_SEL_S 15
+/* RTC_IO_X32N_SLP_SEL : R/W ;bitpos:[14] ;default: 1'd0 ; */
+/*description: the sleep status selection signal of the pad*/
+#define RTC_IO_X32N_SLP_SEL (BIT(14))
+#define RTC_IO_X32N_SLP_SEL_M (BIT(14))
+#define RTC_IO_X32N_SLP_SEL_V 0x1
+#define RTC_IO_X32N_SLP_SEL_S 14
+/* RTC_IO_X32N_SLP_IE : R/W ;bitpos:[13] ;default: 1'd0 ; */
+/*description: the input enable of the pad in sleep status*/
+#define RTC_IO_X32N_SLP_IE (BIT(13))
+#define RTC_IO_X32N_SLP_IE_M (BIT(13))
+#define RTC_IO_X32N_SLP_IE_V 0x1
+#define RTC_IO_X32N_SLP_IE_S 13
+/* RTC_IO_X32N_SLP_OE : R/W ;bitpos:[12] ;default: 1'd0 ; */
+/*description: the output enable of the pad in sleep status*/
+#define RTC_IO_X32N_SLP_OE (BIT(12))
+#define RTC_IO_X32N_SLP_OE_M (BIT(12))
+#define RTC_IO_X32N_SLP_OE_V 0x1
+#define RTC_IO_X32N_SLP_OE_S 12
+/* RTC_IO_X32N_FUN_IE : R/W ;bitpos:[11] ;default: 1'd0 ; */
+/*description: the input enable of the pad*/
+#define RTC_IO_X32N_FUN_IE (BIT(11))
+#define RTC_IO_X32N_FUN_IE_M (BIT(11))
+#define RTC_IO_X32N_FUN_IE_V 0x1
+#define RTC_IO_X32N_FUN_IE_S 11
+/* RTC_IO_X32P_FUN_SEL : R/W ;bitpos:[10:9] ;default: 2'd0 ; */
+/*description: the functional selection signal of the pad*/
+#define RTC_IO_X32P_FUN_SEL 0x00000003
+#define RTC_IO_X32P_FUN_SEL_M ((RTC_IO_X32P_FUN_SEL_V)<<(RTC_IO_X32P_FUN_SEL_S))
+#define RTC_IO_X32P_FUN_SEL_V 0x3
+#define RTC_IO_X32P_FUN_SEL_S 9
+/* RTC_IO_X32P_SLP_SEL : R/W ;bitpos:[8] ;default: 1'd0 ; */
+/*description: the sleep status selection signal of the pad*/
+#define RTC_IO_X32P_SLP_SEL (BIT(8))
+#define RTC_IO_X32P_SLP_SEL_M (BIT(8))
+#define RTC_IO_X32P_SLP_SEL_V 0x1
+#define RTC_IO_X32P_SLP_SEL_S 8
+/* RTC_IO_X32P_SLP_IE : R/W ;bitpos:[7] ;default: 1'd0 ; */
+/*description: the input enable of the pad in sleep status*/
+#define RTC_IO_X32P_SLP_IE (BIT(7))
+#define RTC_IO_X32P_SLP_IE_M (BIT(7))
+#define RTC_IO_X32P_SLP_IE_V 0x1
+#define RTC_IO_X32P_SLP_IE_S 7
+/* RTC_IO_X32P_SLP_OE : R/W ;bitpos:[6] ;default: 1'd0 ; */
+/*description: the output enable of the pad in sleep status*/
+#define RTC_IO_X32P_SLP_OE (BIT(6))
+#define RTC_IO_X32P_SLP_OE_M (BIT(6))
+#define RTC_IO_X32P_SLP_OE_V 0x1
+#define RTC_IO_X32P_SLP_OE_S 6
+/* RTC_IO_X32P_FUN_IE : R/W ;bitpos:[5] ;default: 1'd0 ; */
+/*description: the input enable of the pad*/
+#define RTC_IO_X32P_FUN_IE (BIT(5))
+#define RTC_IO_X32P_FUN_IE_M (BIT(5))
+#define RTC_IO_X32P_FUN_IE_V 0x1
+#define RTC_IO_X32P_FUN_IE_S 5
+/* RTC_IO_DRES_XTAL_32K : R/W ;bitpos:[4:3] ;default: 2'b10 ; */
+/*description: 32K XTAL resistor bias control.*/
+#define RTC_IO_DRES_XTAL_32K 0x00000003
+#define RTC_IO_DRES_XTAL_32K_M ((RTC_IO_DRES_XTAL_32K_V)<<(RTC_IO_DRES_XTAL_32K_S))
+#define RTC_IO_DRES_XTAL_32K_V 0x3
+#define RTC_IO_DRES_XTAL_32K_S 3
+/* RTC_IO_DBIAS_XTAL_32K : R/W ;bitpos:[2:1] ;default: 2'b00 ; */
+/*description: 32K XTAL self-bias reference control.*/
+#define RTC_IO_DBIAS_XTAL_32K 0x00000003
+#define RTC_IO_DBIAS_XTAL_32K_M ((RTC_IO_DBIAS_XTAL_32K_V)<<(RTC_IO_DBIAS_XTAL_32K_S))
+#define RTC_IO_DBIAS_XTAL_32K_V 0x3
+#define RTC_IO_DBIAS_XTAL_32K_S 1
+
+#define RTC_IO_TOUCH_CFG_REG (DR_REG_RTCIO_BASE + 0x90)
+/* RTC_IO_TOUCH_XPD_BIAS : R/W ;bitpos:[31] ;default: 1'd0 ; */
+/*description: touch sensor bias power on.*/
+#define RTC_IO_TOUCH_XPD_BIAS (BIT(31))
+#define RTC_IO_TOUCH_XPD_BIAS_M (BIT(31))
+#define RTC_IO_TOUCH_XPD_BIAS_V 0x1
+#define RTC_IO_TOUCH_XPD_BIAS_S 31
+/* RTC_IO_TOUCH_DREFH : R/W ;bitpos:[30:29] ;default: 2'b11 ; */
+/*description: touch sensor saw wave top voltage.*/
+#define RTC_IO_TOUCH_DREFH 0x00000003
+#define RTC_IO_TOUCH_DREFH_M ((RTC_IO_TOUCH_DREFH_V)<<(RTC_IO_TOUCH_DREFH_S))
+#define RTC_IO_TOUCH_DREFH_V 0x3
+#define RTC_IO_TOUCH_DREFH_S 29
+/* RTC_IO_TOUCH_DREFL : R/W ;bitpos:[28:27] ;default: 2'b00 ; */
+/*description: touch sensor saw wave bottom voltage.*/
+#define RTC_IO_TOUCH_DREFL 0x00000003
+#define RTC_IO_TOUCH_DREFL_M ((RTC_IO_TOUCH_DREFL_V)<<(RTC_IO_TOUCH_DREFL_S))
+#define RTC_IO_TOUCH_DREFL_V 0x3
+#define RTC_IO_TOUCH_DREFL_S 27
+/* RTC_IO_TOUCH_DRANGE : R/W ;bitpos:[26:25] ;default: 2'b11 ; */
+/*description: touch sensor saw wave voltage range.*/
+#define RTC_IO_TOUCH_DRANGE 0x00000003
+#define RTC_IO_TOUCH_DRANGE_M ((RTC_IO_TOUCH_DRANGE_V)<<(RTC_IO_TOUCH_DRANGE_S))
+#define RTC_IO_TOUCH_DRANGE_V 0x3
+#define RTC_IO_TOUCH_DRANGE_S 25
+/* RTC_IO_TOUCH_DCUR : R/W ;bitpos:[24:23] ;default: 2'b00 ; */
+/*description: touch sensor bias current. Should have option to tie with BIAS_SLEEP(When
+ BIAS_SLEEP this setting is available*/
+#define RTC_IO_TOUCH_DCUR 0x00000003
+#define RTC_IO_TOUCH_DCUR_M ((RTC_IO_TOUCH_DCUR_V)<<(RTC_IO_TOUCH_DCUR_S))
+#define RTC_IO_TOUCH_DCUR_V 0x3
+#define RTC_IO_TOUCH_DCUR_S 23
+
+#define RTC_IO_TOUCH_PAD0_REG (DR_REG_RTCIO_BASE + 0x94)
+/* RTC_IO_TOUCH_PAD0_HOLD : R/W ;bitpos:[31] ;default: 1'd0 ; */
+/*description: hold the current value of the output when setting the hold to Ò1Ó*/
+#define RTC_IO_TOUCH_PAD0_HOLD (BIT(31))
+#define RTC_IO_TOUCH_PAD0_HOLD_M (BIT(31))
+#define RTC_IO_TOUCH_PAD0_HOLD_V 0x1
+#define RTC_IO_TOUCH_PAD0_HOLD_S 31
+/* RTC_IO_TOUCH_PAD0_DRV : R/W ;bitpos:[30:29] ;default: 2'd2 ; */
+/*description: the driver strength of the pad*/
+#define RTC_IO_TOUCH_PAD0_DRV 0x00000003
+#define RTC_IO_TOUCH_PAD0_DRV_M ((RTC_IO_TOUCH_PAD0_DRV_V)<<(RTC_IO_TOUCH_PAD0_DRV_S))
+#define RTC_IO_TOUCH_PAD0_DRV_V 0x3
+#define RTC_IO_TOUCH_PAD0_DRV_S 29
+/* RTC_IO_TOUCH_PAD0_RDE : R/W ;bitpos:[28] ;default: 1'd1 ; */
+/*description: the pull down enable of the pad*/
+#define RTC_IO_TOUCH_PAD0_RDE (BIT(28))
+#define RTC_IO_TOUCH_PAD0_RDE_M (BIT(28))
+#define RTC_IO_TOUCH_PAD0_RDE_V 0x1
+#define RTC_IO_TOUCH_PAD0_RDE_S 28
+/* RTC_IO_TOUCH_PAD0_RUE : R/W ;bitpos:[27] ;default: 1'd0 ; */
+/*description: the pull up enable of the pad*/
+#define RTC_IO_TOUCH_PAD0_RUE (BIT(27))
+#define RTC_IO_TOUCH_PAD0_RUE_M (BIT(27))
+#define RTC_IO_TOUCH_PAD0_RUE_V 0x1
+#define RTC_IO_TOUCH_PAD0_RUE_S 27
+/* RTC_IO_TOUCH_PAD0_DAC : R/W ;bitpos:[25:23] ;default: 3'h4 ; */
+/*description: touch sensor slope control. 3-bit for each touch panel default 100.*/
+#define RTC_IO_TOUCH_PAD0_DAC 0x00000007
+#define RTC_IO_TOUCH_PAD0_DAC_M ((RTC_IO_TOUCH_PAD0_DAC_V)<<(RTC_IO_TOUCH_PAD0_DAC_S))
+#define RTC_IO_TOUCH_PAD0_DAC_V 0x7
+#define RTC_IO_TOUCH_PAD0_DAC_S 23
+/* RTC_IO_TOUCH_PAD0_START : R/W ;bitpos:[22] ;default: 1'd0 ; */
+/*description: start touch sensor.*/
+#define RTC_IO_TOUCH_PAD0_START (BIT(22))
+#define RTC_IO_TOUCH_PAD0_START_M (BIT(22))
+#define RTC_IO_TOUCH_PAD0_START_V 0x1
+#define RTC_IO_TOUCH_PAD0_START_S 22
+/* RTC_IO_TOUCH_PAD0_TIE_OPT : R/W ;bitpos:[21] ;default: 1'd0 ; */
+/*description: default touch sensor tie option. 0: tie low 1: tie high.*/
+#define RTC_IO_TOUCH_PAD0_TIE_OPT (BIT(21))
+#define RTC_IO_TOUCH_PAD0_TIE_OPT_M (BIT(21))
+#define RTC_IO_TOUCH_PAD0_TIE_OPT_V 0x1
+#define RTC_IO_TOUCH_PAD0_TIE_OPT_S 21
+/* RTC_IO_TOUCH_PAD0_XPD : R/W ;bitpos:[20] ;default: 1'd0 ; */
+/*description: touch sensor power on.*/
+#define RTC_IO_TOUCH_PAD0_XPD (BIT(20))
+#define RTC_IO_TOUCH_PAD0_XPD_M (BIT(20))
+#define RTC_IO_TOUCH_PAD0_XPD_V 0x1
+#define RTC_IO_TOUCH_PAD0_XPD_S 20
+/* RTC_IO_TOUCH_PAD0_MUX_SEL : R/W ;bitpos:[19] ;default: 1'd0 ; */
+/*description: Ò1Ó select the digital function Ó0Óslection the rtc function*/
+#define RTC_IO_TOUCH_PAD0_MUX_SEL (BIT(19))
+#define RTC_IO_TOUCH_PAD0_MUX_SEL_M (BIT(19))
+#define RTC_IO_TOUCH_PAD0_MUX_SEL_V 0x1
+#define RTC_IO_TOUCH_PAD0_MUX_SEL_S 19
+/* RTC_IO_TOUCH_PAD0_FUN_SEL : R/W ;bitpos:[18:17] ;default: 2'd0 ; */
+/*description: the functional selection signal of the pad*/
+#define RTC_IO_TOUCH_PAD0_FUN_SEL 0x00000003
+#define RTC_IO_TOUCH_PAD0_FUN_SEL_M ((RTC_IO_TOUCH_PAD0_FUN_SEL_V)<<(RTC_IO_TOUCH_PAD0_FUN_SEL_S))
+#define RTC_IO_TOUCH_PAD0_FUN_SEL_V 0x3
+#define RTC_IO_TOUCH_PAD0_FUN_SEL_S 17
+/* RTC_IO_TOUCH_PAD0_SLP_SEL : R/W ;bitpos:[16] ;default: 1'd0 ; */
+/*description: the sleep status selection signal of the pad*/
+#define RTC_IO_TOUCH_PAD0_SLP_SEL (BIT(16))
+#define RTC_IO_TOUCH_PAD0_SLP_SEL_M (BIT(16))
+#define RTC_IO_TOUCH_PAD0_SLP_SEL_V 0x1
+#define RTC_IO_TOUCH_PAD0_SLP_SEL_S 16
+/* RTC_IO_TOUCH_PAD0_SLP_IE : R/W ;bitpos:[15] ;default: 1'd0 ; */
+/*description: the input enable of the pad in sleep status*/
+#define RTC_IO_TOUCH_PAD0_SLP_IE (BIT(15))
+#define RTC_IO_TOUCH_PAD0_SLP_IE_M (BIT(15))
+#define RTC_IO_TOUCH_PAD0_SLP_IE_V 0x1
+#define RTC_IO_TOUCH_PAD0_SLP_IE_S 15
+/* RTC_IO_TOUCH_PAD0_SLP_OE : R/W ;bitpos:[14] ;default: 1'd0 ; */
+/*description: the output enable of the pad in sleep status*/
+#define RTC_IO_TOUCH_PAD0_SLP_OE (BIT(14))
+#define RTC_IO_TOUCH_PAD0_SLP_OE_M (BIT(14))
+#define RTC_IO_TOUCH_PAD0_SLP_OE_V 0x1
+#define RTC_IO_TOUCH_PAD0_SLP_OE_S 14
+/* RTC_IO_TOUCH_PAD0_FUN_IE : R/W ;bitpos:[13] ;default: 1'd0 ; */
+/*description: the input enable of the pad*/
+#define RTC_IO_TOUCH_PAD0_FUN_IE (BIT(13))
+#define RTC_IO_TOUCH_PAD0_FUN_IE_M (BIT(13))
+#define RTC_IO_TOUCH_PAD0_FUN_IE_V 0x1
+#define RTC_IO_TOUCH_PAD0_FUN_IE_S 13
+/* RTC_IO_TOUCH_PAD0_TO_GPIO : R/W ;bitpos:[12] ;default: 1'd0 ; */
+/*description: connect the rtc pad input to digital pad input Ó0Ó is availbale GPIO4*/
+#define RTC_IO_TOUCH_PAD0_TO_GPIO (BIT(12))
+#define RTC_IO_TOUCH_PAD0_TO_GPIO_M (BIT(12))
+#define RTC_IO_TOUCH_PAD0_TO_GPIO_V 0x1
+#define RTC_IO_TOUCH_PAD0_TO_GPIO_S 12
+
+#define RTC_IO_TOUCH_PAD1_REG (DR_REG_RTCIO_BASE + 0x98)
+/* RTC_IO_TOUCH_PAD1_HOLD : R/W ;bitpos:[31] ;default: 1'd0 ; */
+/*description: */
+#define RTC_IO_TOUCH_PAD1_HOLD (BIT(31))
+#define RTC_IO_TOUCH_PAD1_HOLD_M (BIT(31))
+#define RTC_IO_TOUCH_PAD1_HOLD_V 0x1
+#define RTC_IO_TOUCH_PAD1_HOLD_S 31
+/* RTC_IO_TOUCH_PAD1_DRV : R/W ;bitpos:[30:29] ;default: 2'd2 ; */
+/*description: the driver strength of the pad*/
+#define RTC_IO_TOUCH_PAD1_DRV 0x00000003
+#define RTC_IO_TOUCH_PAD1_DRV_M ((RTC_IO_TOUCH_PAD1_DRV_V)<<(RTC_IO_TOUCH_PAD1_DRV_S))
+#define RTC_IO_TOUCH_PAD1_DRV_V 0x3
+#define RTC_IO_TOUCH_PAD1_DRV_S 29
+/* RTC_IO_TOUCH_PAD1_RDE : R/W ;bitpos:[28] ;default: 1'd0 ; */
+/*description: the pull down enable of the pad*/
+#define RTC_IO_TOUCH_PAD1_RDE (BIT(28))
+#define RTC_IO_TOUCH_PAD1_RDE_M (BIT(28))
+#define RTC_IO_TOUCH_PAD1_RDE_V 0x1
+#define RTC_IO_TOUCH_PAD1_RDE_S 28
+/* RTC_IO_TOUCH_PAD1_RUE : R/W ;bitpos:[27] ;default: 1'd1 ; */
+/*description: the pull up enable of the pad*/
+#define RTC_IO_TOUCH_PAD1_RUE (BIT(27))
+#define RTC_IO_TOUCH_PAD1_RUE_M (BIT(27))
+#define RTC_IO_TOUCH_PAD1_RUE_V 0x1
+#define RTC_IO_TOUCH_PAD1_RUE_S 27
+/* RTC_IO_TOUCH_PAD1_DAC : R/W ;bitpos:[25:23] ;default: 3'h4 ; */
+/*description: touch sensor slope control. 3-bit for each touch panel default 100.*/
+#define RTC_IO_TOUCH_PAD1_DAC 0x00000007
+#define RTC_IO_TOUCH_PAD1_DAC_M ((RTC_IO_TOUCH_PAD1_DAC_V)<<(RTC_IO_TOUCH_PAD1_DAC_S))
+#define RTC_IO_TOUCH_PAD1_DAC_V 0x7
+#define RTC_IO_TOUCH_PAD1_DAC_S 23
+/* RTC_IO_TOUCH_PAD1_START : R/W ;bitpos:[22] ;default: 1'd0 ; */
+/*description: start touch sensor.*/
+#define RTC_IO_TOUCH_PAD1_START (BIT(22))
+#define RTC_IO_TOUCH_PAD1_START_M (BIT(22))
+#define RTC_IO_TOUCH_PAD1_START_V 0x1
+#define RTC_IO_TOUCH_PAD1_START_S 22
+/* RTC_IO_TOUCH_PAD1_TIE_OPT : R/W ;bitpos:[21] ;default: 1'd0 ; */
+/*description: default touch sensor tie option. 0: tie low 1: tie high.*/
+#define RTC_IO_TOUCH_PAD1_TIE_OPT (BIT(21))
+#define RTC_IO_TOUCH_PAD1_TIE_OPT_M (BIT(21))
+#define RTC_IO_TOUCH_PAD1_TIE_OPT_V 0x1
+#define RTC_IO_TOUCH_PAD1_TIE_OPT_S 21
+/* RTC_IO_TOUCH_PAD1_XPD : R/W ;bitpos:[20] ;default: 1'd0 ; */
+/*description: touch sensor power on.*/
+#define RTC_IO_TOUCH_PAD1_XPD (BIT(20))
+#define RTC_IO_TOUCH_PAD1_XPD_M (BIT(20))
+#define RTC_IO_TOUCH_PAD1_XPD_V 0x1
+#define RTC_IO_TOUCH_PAD1_XPD_S 20
+/* RTC_IO_TOUCH_PAD1_MUX_SEL : R/W ;bitpos:[19] ;default: 1'd0 ; */
+/*description: Ò1Ó select the digital function Ó0Óslection the rtc function*/
+#define RTC_IO_TOUCH_PAD1_MUX_SEL (BIT(19))
+#define RTC_IO_TOUCH_PAD1_MUX_SEL_M (BIT(19))
+#define RTC_IO_TOUCH_PAD1_MUX_SEL_V 0x1
+#define RTC_IO_TOUCH_PAD1_MUX_SEL_S 19
+/* RTC_IO_TOUCH_PAD1_FUN_SEL : R/W ;bitpos:[18:17] ;default: 2'd0 ; */
+/*description: the functional selection signal of the pad*/
+#define RTC_IO_TOUCH_PAD1_FUN_SEL 0x00000003
+#define RTC_IO_TOUCH_PAD1_FUN_SEL_M ((RTC_IO_TOUCH_PAD1_FUN_SEL_V)<<(RTC_IO_TOUCH_PAD1_FUN_SEL_S))
+#define RTC_IO_TOUCH_PAD1_FUN_SEL_V 0x3
+#define RTC_IO_TOUCH_PAD1_FUN_SEL_S 17
+/* RTC_IO_TOUCH_PAD1_SLP_SEL : R/W ;bitpos:[16] ;default: 1'd0 ; */
+/*description: the sleep status selection signal of the pad*/
+#define RTC_IO_TOUCH_PAD1_SLP_SEL (BIT(16))
+#define RTC_IO_TOUCH_PAD1_SLP_SEL_M (BIT(16))
+#define RTC_IO_TOUCH_PAD1_SLP_SEL_V 0x1
+#define RTC_IO_TOUCH_PAD1_SLP_SEL_S 16
+/* RTC_IO_TOUCH_PAD1_SLP_IE : R/W ;bitpos:[15] ;default: 1'd0 ; */
+/*description: the input enable of the pad in sleep status*/
+#define RTC_IO_TOUCH_PAD1_SLP_IE (BIT(15))
+#define RTC_IO_TOUCH_PAD1_SLP_IE_M (BIT(15))
+#define RTC_IO_TOUCH_PAD1_SLP_IE_V 0x1
+#define RTC_IO_TOUCH_PAD1_SLP_IE_S 15
+/* RTC_IO_TOUCH_PAD1_SLP_OE : R/W ;bitpos:[14] ;default: 1'd0 ; */
+/*description: the output enable of the pad in sleep status*/
+#define RTC_IO_TOUCH_PAD1_SLP_OE (BIT(14))
+#define RTC_IO_TOUCH_PAD1_SLP_OE_M (BIT(14))
+#define RTC_IO_TOUCH_PAD1_SLP_OE_V 0x1
+#define RTC_IO_TOUCH_PAD1_SLP_OE_S 14
+/* RTC_IO_TOUCH_PAD1_FUN_IE : R/W ;bitpos:[13] ;default: 1'd0 ; */
+/*description: the input enable of the pad*/
+#define RTC_IO_TOUCH_PAD1_FUN_IE (BIT(13))
+#define RTC_IO_TOUCH_PAD1_FUN_IE_M (BIT(13))
+#define RTC_IO_TOUCH_PAD1_FUN_IE_V 0x1
+#define RTC_IO_TOUCH_PAD1_FUN_IE_S 13
+/* RTC_IO_TOUCH_PAD1_TO_GPIO : R/W ;bitpos:[12] ;default: 1'd0 ; */
+/*description: connect the rtc pad input to digital pad input Ó0Ó is availbale.GPIO0*/
+#define RTC_IO_TOUCH_PAD1_TO_GPIO (BIT(12))
+#define RTC_IO_TOUCH_PAD1_TO_GPIO_M (BIT(12))
+#define RTC_IO_TOUCH_PAD1_TO_GPIO_V 0x1
+#define RTC_IO_TOUCH_PAD1_TO_GPIO_S 12
+
+#define RTC_IO_TOUCH_PAD2_REG (DR_REG_RTCIO_BASE + 0x9c)
+/* RTC_IO_TOUCH_PAD2_HOLD : R/W ;bitpos:[31] ;default: 1'd0 ; */
+/*description: hold the current value of the output when setting the hold to Ò1Ó*/
+#define RTC_IO_TOUCH_PAD2_HOLD (BIT(31))
+#define RTC_IO_TOUCH_PAD2_HOLD_M (BIT(31))
+#define RTC_IO_TOUCH_PAD2_HOLD_V 0x1
+#define RTC_IO_TOUCH_PAD2_HOLD_S 31
+/* RTC_IO_TOUCH_PAD2_DRV : R/W ;bitpos:[30:29] ;default: 2'd2 ; */
+/*description: the driver strength of the pad*/
+#define RTC_IO_TOUCH_PAD2_DRV 0x00000003
+#define RTC_IO_TOUCH_PAD2_DRV_M ((RTC_IO_TOUCH_PAD2_DRV_V)<<(RTC_IO_TOUCH_PAD2_DRV_S))
+#define RTC_IO_TOUCH_PAD2_DRV_V 0x3
+#define RTC_IO_TOUCH_PAD2_DRV_S 29
+/* RTC_IO_TOUCH_PAD2_RDE : R/W ;bitpos:[28] ;default: 1'd1 ; */
+/*description: the pull down enable of the pad*/
+#define RTC_IO_TOUCH_PAD2_RDE (BIT(28))
+#define RTC_IO_TOUCH_PAD2_RDE_M (BIT(28))
+#define RTC_IO_TOUCH_PAD2_RDE_V 0x1
+#define RTC_IO_TOUCH_PAD2_RDE_S 28
+/* RTC_IO_TOUCH_PAD2_RUE : R/W ;bitpos:[27] ;default: 1'd0 ; */
+/*description: the pull up enable of the pad*/
+#define RTC_IO_TOUCH_PAD2_RUE (BIT(27))
+#define RTC_IO_TOUCH_PAD2_RUE_M (BIT(27))
+#define RTC_IO_TOUCH_PAD2_RUE_V 0x1
+#define RTC_IO_TOUCH_PAD2_RUE_S 27
+/* RTC_IO_TOUCH_PAD2_DAC : R/W ;bitpos:[25:23] ;default: 3'h4 ; */
+/*description: touch sensor slope control. 3-bit for each touch panel default 100.*/
+#define RTC_IO_TOUCH_PAD2_DAC 0x00000007
+#define RTC_IO_TOUCH_PAD2_DAC_M ((RTC_IO_TOUCH_PAD2_DAC_V)<<(RTC_IO_TOUCH_PAD2_DAC_S))
+#define RTC_IO_TOUCH_PAD2_DAC_V 0x7
+#define RTC_IO_TOUCH_PAD2_DAC_S 23
+/* RTC_IO_TOUCH_PAD2_START : R/W ;bitpos:[22] ;default: 1'd0 ; */
+/*description: start touch sensor.*/
+#define RTC_IO_TOUCH_PAD2_START (BIT(22))
+#define RTC_IO_TOUCH_PAD2_START_M (BIT(22))
+#define RTC_IO_TOUCH_PAD2_START_V 0x1
+#define RTC_IO_TOUCH_PAD2_START_S 22
+/* RTC_IO_TOUCH_PAD2_TIE_OPT : R/W ;bitpos:[21] ;default: 1'd0 ; */
+/*description: default touch sensor tie option. 0: tie low 1: tie high.*/
+#define RTC_IO_TOUCH_PAD2_TIE_OPT (BIT(21))
+#define RTC_IO_TOUCH_PAD2_TIE_OPT_M (BIT(21))
+#define RTC_IO_TOUCH_PAD2_TIE_OPT_V 0x1
+#define RTC_IO_TOUCH_PAD2_TIE_OPT_S 21
+/* RTC_IO_TOUCH_PAD2_XPD : R/W ;bitpos:[20] ;default: 1'd0 ; */
+/*description: touch sensor power on.*/
+#define RTC_IO_TOUCH_PAD2_XPD (BIT(20))
+#define RTC_IO_TOUCH_PAD2_XPD_M (BIT(20))
+#define RTC_IO_TOUCH_PAD2_XPD_V 0x1
+#define RTC_IO_TOUCH_PAD2_XPD_S 20
+/* RTC_IO_TOUCH_PAD2_MUX_SEL : R/W ;bitpos:[19] ;default: 1'd0 ; */
+/*description: Ò1Ó select the digital function Ó0Óslection the rtc function*/
+#define RTC_IO_TOUCH_PAD2_MUX_SEL (BIT(19))
+#define RTC_IO_TOUCH_PAD2_MUX_SEL_M (BIT(19))
+#define RTC_IO_TOUCH_PAD2_MUX_SEL_V 0x1
+#define RTC_IO_TOUCH_PAD2_MUX_SEL_S 19
+/* RTC_IO_TOUCH_PAD2_FUN_SEL : R/W ;bitpos:[18:17] ;default: 2'd0 ; */
+/*description: the functional selection signal of the pad*/
+#define RTC_IO_TOUCH_PAD2_FUN_SEL 0x00000003
+#define RTC_IO_TOUCH_PAD2_FUN_SEL_M ((RTC_IO_TOUCH_PAD2_FUN_SEL_V)<<(RTC_IO_TOUCH_PAD2_FUN_SEL_S))
+#define RTC_IO_TOUCH_PAD2_FUN_SEL_V 0x3
+#define RTC_IO_TOUCH_PAD2_FUN_SEL_S 17
+/* RTC_IO_TOUCH_PAD2_SLP_SEL : R/W ;bitpos:[16] ;default: 1'd0 ; */
+/*description: the sleep status selection signal of the pad*/
+#define RTC_IO_TOUCH_PAD2_SLP_SEL (BIT(16))
+#define RTC_IO_TOUCH_PAD2_SLP_SEL_M (BIT(16))
+#define RTC_IO_TOUCH_PAD2_SLP_SEL_V 0x1
+#define RTC_IO_TOUCH_PAD2_SLP_SEL_S 16
+/* RTC_IO_TOUCH_PAD2_SLP_IE : R/W ;bitpos:[15] ;default: 1'd0 ; */
+/*description: the input enable of the pad in sleep status*/
+#define RTC_IO_TOUCH_PAD2_SLP_IE (BIT(15))
+#define RTC_IO_TOUCH_PAD2_SLP_IE_M (BIT(15))
+#define RTC_IO_TOUCH_PAD2_SLP_IE_V 0x1
+#define RTC_IO_TOUCH_PAD2_SLP_IE_S 15
+/* RTC_IO_TOUCH_PAD2_SLP_OE : R/W ;bitpos:[14] ;default: 1'd0 ; */
+/*description: the output enable of the pad in sleep status*/
+#define RTC_IO_TOUCH_PAD2_SLP_OE (BIT(14))
+#define RTC_IO_TOUCH_PAD2_SLP_OE_M (BIT(14))
+#define RTC_IO_TOUCH_PAD2_SLP_OE_V 0x1
+#define RTC_IO_TOUCH_PAD2_SLP_OE_S 14
+/* RTC_IO_TOUCH_PAD2_FUN_IE : R/W ;bitpos:[13] ;default: 1'd0 ; */
+/*description: the input enable of the pad*/
+#define RTC_IO_TOUCH_PAD2_FUN_IE (BIT(13))
+#define RTC_IO_TOUCH_PAD2_FUN_IE_M (BIT(13))
+#define RTC_IO_TOUCH_PAD2_FUN_IE_V 0x1
+#define RTC_IO_TOUCH_PAD2_FUN_IE_S 13
+/* RTC_IO_TOUCH_PAD2_TO_GPIO : R/W ;bitpos:[12] ;default: 1'd0 ; */
+/*description: connect the rtc pad input to digital pad input Ó0Ó is availbale.GPIO2*/
+#define RTC_IO_TOUCH_PAD2_TO_GPIO (BIT(12))
+#define RTC_IO_TOUCH_PAD2_TO_GPIO_M (BIT(12))
+#define RTC_IO_TOUCH_PAD2_TO_GPIO_V 0x1
+#define RTC_IO_TOUCH_PAD2_TO_GPIO_S 12
+
+#define RTC_IO_TOUCH_PAD3_REG (DR_REG_RTCIO_BASE + 0xa0)
+/* RTC_IO_TOUCH_PAD3_HOLD : R/W ;bitpos:[31] ;default: 1'd0 ; */
+/*description: hold the current value of the output when setting the hold to Ò1Ó*/
+#define RTC_IO_TOUCH_PAD3_HOLD (BIT(31))
+#define RTC_IO_TOUCH_PAD3_HOLD_M (BIT(31))
+#define RTC_IO_TOUCH_PAD3_HOLD_V 0x1
+#define RTC_IO_TOUCH_PAD3_HOLD_S 31
+/* RTC_IO_TOUCH_PAD3_DRV : R/W ;bitpos:[30:29] ;default: 2'd2 ; */
+/*description: the driver strength of the pad*/
+#define RTC_IO_TOUCH_PAD3_DRV 0x00000003
+#define RTC_IO_TOUCH_PAD3_DRV_M ((RTC_IO_TOUCH_PAD3_DRV_V)<<(RTC_IO_TOUCH_PAD3_DRV_S))
+#define RTC_IO_TOUCH_PAD3_DRV_V 0x3
+#define RTC_IO_TOUCH_PAD3_DRV_S 29
+/* RTC_IO_TOUCH_PAD3_RDE : R/W ;bitpos:[28] ;default: 1'd0 ; */
+/*description: the pull down enable of the pad*/
+#define RTC_IO_TOUCH_PAD3_RDE (BIT(28))
+#define RTC_IO_TOUCH_PAD3_RDE_M (BIT(28))
+#define RTC_IO_TOUCH_PAD3_RDE_V 0x1
+#define RTC_IO_TOUCH_PAD3_RDE_S 28
+/* RTC_IO_TOUCH_PAD3_RUE : R/W ;bitpos:[27] ;default: 1'd1 ; */
+/*description: the pull up enable of the pad*/
+#define RTC_IO_TOUCH_PAD3_RUE (BIT(27))
+#define RTC_IO_TOUCH_PAD3_RUE_M (BIT(27))
+#define RTC_IO_TOUCH_PAD3_RUE_V 0x1
+#define RTC_IO_TOUCH_PAD3_RUE_S 27
+/* RTC_IO_TOUCH_PAD3_DAC : R/W ;bitpos:[25:23] ;default: 3'h4 ; */
+/*description: touch sensor slope control. 3-bit for each touch panel default 100.*/
+#define RTC_IO_TOUCH_PAD3_DAC 0x00000007
+#define RTC_IO_TOUCH_PAD3_DAC_M ((RTC_IO_TOUCH_PAD3_DAC_V)<<(RTC_IO_TOUCH_PAD3_DAC_S))
+#define RTC_IO_TOUCH_PAD3_DAC_V 0x7
+#define RTC_IO_TOUCH_PAD3_DAC_S 23
+/* RTC_IO_TOUCH_PAD3_START : R/W ;bitpos:[22] ;default: 1'd0 ; */
+/*description: start touch sensor.*/
+#define RTC_IO_TOUCH_PAD3_START (BIT(22))
+#define RTC_IO_TOUCH_PAD3_START_M (BIT(22))
+#define RTC_IO_TOUCH_PAD3_START_V 0x1
+#define RTC_IO_TOUCH_PAD3_START_S 22
+/* RTC_IO_TOUCH_PAD3_TIE_OPT : R/W ;bitpos:[21] ;default: 1'd0 ; */
+/*description: default touch sensor tie option. 0: tie low 1: tie high.*/
+#define RTC_IO_TOUCH_PAD3_TIE_OPT (BIT(21))
+#define RTC_IO_TOUCH_PAD3_TIE_OPT_M (BIT(21))
+#define RTC_IO_TOUCH_PAD3_TIE_OPT_V 0x1
+#define RTC_IO_TOUCH_PAD3_TIE_OPT_S 21
+/* RTC_IO_TOUCH_PAD3_XPD : R/W ;bitpos:[20] ;default: 1'd0 ; */
+/*description: touch sensor power on.*/
+#define RTC_IO_TOUCH_PAD3_XPD (BIT(20))
+#define RTC_IO_TOUCH_PAD3_XPD_M (BIT(20))
+#define RTC_IO_TOUCH_PAD3_XPD_V 0x1
+#define RTC_IO_TOUCH_PAD3_XPD_S 20
+/* RTC_IO_TOUCH_PAD3_MUX_SEL : R/W ;bitpos:[19] ;default: 1'd0 ; */
+/*description: Ò1Ó select the digital function Ó0Óslection the rtc function*/
+#define RTC_IO_TOUCH_PAD3_MUX_SEL (BIT(19))
+#define RTC_IO_TOUCH_PAD3_MUX_SEL_M (BIT(19))
+#define RTC_IO_TOUCH_PAD3_MUX_SEL_V 0x1
+#define RTC_IO_TOUCH_PAD3_MUX_SEL_S 19
+/* RTC_IO_TOUCH_PAD3_FUN_SEL : R/W ;bitpos:[18:17] ;default: 2'd0 ; */
+/*description: the functional selection signal of the pad*/
+#define RTC_IO_TOUCH_PAD3_FUN_SEL 0x00000003
+#define RTC_IO_TOUCH_PAD3_FUN_SEL_M ((RTC_IO_TOUCH_PAD3_FUN_SEL_V)<<(RTC_IO_TOUCH_PAD3_FUN_SEL_S))
+#define RTC_IO_TOUCH_PAD3_FUN_SEL_V 0x3
+#define RTC_IO_TOUCH_PAD3_FUN_SEL_S 17
+/* RTC_IO_TOUCH_PAD3_SLP_SEL : R/W ;bitpos:[16] ;default: 1'd0 ; */
+/*description: the sleep status selection signal of the pad*/
+#define RTC_IO_TOUCH_PAD3_SLP_SEL (BIT(16))
+#define RTC_IO_TOUCH_PAD3_SLP_SEL_M (BIT(16))
+#define RTC_IO_TOUCH_PAD3_SLP_SEL_V 0x1
+#define RTC_IO_TOUCH_PAD3_SLP_SEL_S 16
+/* RTC_IO_TOUCH_PAD3_SLP_IE : R/W ;bitpos:[15] ;default: 1'd0 ; */
+/*description: the input enable of the pad in sleep status*/
+#define RTC_IO_TOUCH_PAD3_SLP_IE (BIT(15))
+#define RTC_IO_TOUCH_PAD3_SLP_IE_M (BIT(15))
+#define RTC_IO_TOUCH_PAD3_SLP_IE_V 0x1
+#define RTC_IO_TOUCH_PAD3_SLP_IE_S 15
+/* RTC_IO_TOUCH_PAD3_SLP_OE : R/W ;bitpos:[14] ;default: 1'd0 ; */
+/*description: the output enable of the pad in sleep status*/
+#define RTC_IO_TOUCH_PAD3_SLP_OE (BIT(14))
+#define RTC_IO_TOUCH_PAD3_SLP_OE_M (BIT(14))
+#define RTC_IO_TOUCH_PAD3_SLP_OE_V 0x1
+#define RTC_IO_TOUCH_PAD3_SLP_OE_S 14
+/* RTC_IO_TOUCH_PAD3_FUN_IE : R/W ;bitpos:[13] ;default: 1'd0 ; */
+/*description: the input enable of the pad*/
+#define RTC_IO_TOUCH_PAD3_FUN_IE (BIT(13))
+#define RTC_IO_TOUCH_PAD3_FUN_IE_M (BIT(13))
+#define RTC_IO_TOUCH_PAD3_FUN_IE_V 0x1
+#define RTC_IO_TOUCH_PAD3_FUN_IE_S 13
+/* RTC_IO_TOUCH_PAD3_TO_GPIO : R/W ;bitpos:[12] ;default: 1'd0 ; */
+/*description: connect the rtc pad input to digital pad input Ó0Ó is availbale.MTDO*/
+#define RTC_IO_TOUCH_PAD3_TO_GPIO (BIT(12))
+#define RTC_IO_TOUCH_PAD3_TO_GPIO_M (BIT(12))
+#define RTC_IO_TOUCH_PAD3_TO_GPIO_V 0x1
+#define RTC_IO_TOUCH_PAD3_TO_GPIO_S 12
+
+#define RTC_IO_TOUCH_PAD4_REG (DR_REG_RTCIO_BASE + 0xa4)
+/* RTC_IO_TOUCH_PAD4_HOLD : R/W ;bitpos:[31] ;default: 1'd0 ; */
+/*description: hold the current value of the output when setting the hold to Ò1Ó*/
+#define RTC_IO_TOUCH_PAD4_HOLD (BIT(31))
+#define RTC_IO_TOUCH_PAD4_HOLD_M (BIT(31))
+#define RTC_IO_TOUCH_PAD4_HOLD_V 0x1
+#define RTC_IO_TOUCH_PAD4_HOLD_S 31
+/* RTC_IO_TOUCH_PAD4_DRV : R/W ;bitpos:[30:29] ;default: 2'd2 ; */
+/*description: the driver strength of the pad*/
+#define RTC_IO_TOUCH_PAD4_DRV 0x00000003
+#define RTC_IO_TOUCH_PAD4_DRV_M ((RTC_IO_TOUCH_PAD4_DRV_V)<<(RTC_IO_TOUCH_PAD4_DRV_S))
+#define RTC_IO_TOUCH_PAD4_DRV_V 0x3
+#define RTC_IO_TOUCH_PAD4_DRV_S 29
+/* RTC_IO_TOUCH_PAD4_RDE : R/W ;bitpos:[28] ;default: 1'd1 ; */
+/*description: the pull down enable of the pad*/
+#define RTC_IO_TOUCH_PAD4_RDE (BIT(28))
+#define RTC_IO_TOUCH_PAD4_RDE_M (BIT(28))
+#define RTC_IO_TOUCH_PAD4_RDE_V 0x1
+#define RTC_IO_TOUCH_PAD4_RDE_S 28
+/* RTC_IO_TOUCH_PAD4_RUE : R/W ;bitpos:[27] ;default: 1'd0 ; */
+/*description: the pull up enable of the pad*/
+#define RTC_IO_TOUCH_PAD4_RUE (BIT(27))
+#define RTC_IO_TOUCH_PAD4_RUE_M (BIT(27))
+#define RTC_IO_TOUCH_PAD4_RUE_V 0x1
+#define RTC_IO_TOUCH_PAD4_RUE_S 27
+/* RTC_IO_TOUCH_PAD4_DAC : R/W ;bitpos:[25:23] ;default: 3'h4 ; */
+/*description: touch sensor slope control. 3-bit for each touch panel default 100.*/
+#define RTC_IO_TOUCH_PAD4_DAC 0x00000007
+#define RTC_IO_TOUCH_PAD4_DAC_M ((RTC_IO_TOUCH_PAD4_DAC_V)<<(RTC_IO_TOUCH_PAD4_DAC_S))
+#define RTC_IO_TOUCH_PAD4_DAC_V 0x7
+#define RTC_IO_TOUCH_PAD4_DAC_S 23
+/* RTC_IO_TOUCH_PAD4_START : R/W ;bitpos:[22] ;default: 1'd0 ; */
+/*description: start touch sensor.*/
+#define RTC_IO_TOUCH_PAD4_START (BIT(22))
+#define RTC_IO_TOUCH_PAD4_START_M (BIT(22))
+#define RTC_IO_TOUCH_PAD4_START_V 0x1
+#define RTC_IO_TOUCH_PAD4_START_S 22
+/* RTC_IO_TOUCH_PAD4_TIE_OPT : R/W ;bitpos:[21] ;default: 1'd0 ; */
+/*description: default touch sensor tie option. 0: tie low 1: tie high.*/
+#define RTC_IO_TOUCH_PAD4_TIE_OPT (BIT(21))
+#define RTC_IO_TOUCH_PAD4_TIE_OPT_M (BIT(21))
+#define RTC_IO_TOUCH_PAD4_TIE_OPT_V 0x1
+#define RTC_IO_TOUCH_PAD4_TIE_OPT_S 21
+/* RTC_IO_TOUCH_PAD4_XPD : R/W ;bitpos:[20] ;default: 1'd0 ; */
+/*description: touch sensor power on.*/
+#define RTC_IO_TOUCH_PAD4_XPD (BIT(20))
+#define RTC_IO_TOUCH_PAD4_XPD_M (BIT(20))
+#define RTC_IO_TOUCH_PAD4_XPD_V 0x1
+#define RTC_IO_TOUCH_PAD4_XPD_S 20
+/* RTC_IO_TOUCH_PAD4_MUX_SEL : R/W ;bitpos:[19] ;default: 1'd0 ; */
+/*description: Ò1Ó select the digital function Ó0Óslection the rtc function*/
+#define RTC_IO_TOUCH_PAD4_MUX_SEL (BIT(19))
+#define RTC_IO_TOUCH_PAD4_MUX_SEL_M (BIT(19))
+#define RTC_IO_TOUCH_PAD4_MUX_SEL_V 0x1
+#define RTC_IO_TOUCH_PAD4_MUX_SEL_S 19
+/* RTC_IO_TOUCH_PAD4_FUN_SEL : R/W ;bitpos:[18:17] ;default: 2'd0 ; */
+/*description: the functional selection signal of the pad*/
+#define RTC_IO_TOUCH_PAD4_FUN_SEL 0x00000003
+#define RTC_IO_TOUCH_PAD4_FUN_SEL_M ((RTC_IO_TOUCH_PAD4_FUN_SEL_V)<<(RTC_IO_TOUCH_PAD4_FUN_SEL_S))
+#define RTC_IO_TOUCH_PAD4_FUN_SEL_V 0x3
+#define RTC_IO_TOUCH_PAD4_FUN_SEL_S 17
+/* RTC_IO_TOUCH_PAD4_SLP_SEL : R/W ;bitpos:[16] ;default: 1'd0 ; */
+/*description: the sleep status selection signal of the pad*/
+#define RTC_IO_TOUCH_PAD4_SLP_SEL (BIT(16))
+#define RTC_IO_TOUCH_PAD4_SLP_SEL_M (BIT(16))
+#define RTC_IO_TOUCH_PAD4_SLP_SEL_V 0x1
+#define RTC_IO_TOUCH_PAD4_SLP_SEL_S 16
+/* RTC_IO_TOUCH_PAD4_SLP_IE : R/W ;bitpos:[15] ;default: 1'd0 ; */
+/*description: the input enable of the pad in sleep status*/
+#define RTC_IO_TOUCH_PAD4_SLP_IE (BIT(15))
+#define RTC_IO_TOUCH_PAD4_SLP_IE_M (BIT(15))
+#define RTC_IO_TOUCH_PAD4_SLP_IE_V 0x1
+#define RTC_IO_TOUCH_PAD4_SLP_IE_S 15
+/* RTC_IO_TOUCH_PAD4_SLP_OE : R/W ;bitpos:[14] ;default: 1'd0 ; */
+/*description: the output enable of the pad in sleep status*/
+#define RTC_IO_TOUCH_PAD4_SLP_OE (BIT(14))
+#define RTC_IO_TOUCH_PAD4_SLP_OE_M (BIT(14))
+#define RTC_IO_TOUCH_PAD4_SLP_OE_V 0x1
+#define RTC_IO_TOUCH_PAD4_SLP_OE_S 14
+/* RTC_IO_TOUCH_PAD4_FUN_IE : R/W ;bitpos:[13] ;default: 1'd0 ; */
+/*description: the input enable of the pad*/
+#define RTC_IO_TOUCH_PAD4_FUN_IE (BIT(13))
+#define RTC_IO_TOUCH_PAD4_FUN_IE_M (BIT(13))
+#define RTC_IO_TOUCH_PAD4_FUN_IE_V 0x1
+#define RTC_IO_TOUCH_PAD4_FUN_IE_S 13
+/* RTC_IO_TOUCH_PAD4_TO_GPIO : R/W ;bitpos:[12] ;default: 1'd0 ; */
+/*description: connect the rtc pad input to digital pad input Ó0Ó is availbale.MTCK*/
+#define RTC_IO_TOUCH_PAD4_TO_GPIO (BIT(12))
+#define RTC_IO_TOUCH_PAD4_TO_GPIO_M (BIT(12))
+#define RTC_IO_TOUCH_PAD4_TO_GPIO_V 0x1
+#define RTC_IO_TOUCH_PAD4_TO_GPIO_S 12
+
+#define RTC_IO_TOUCH_PAD5_REG (DR_REG_RTCIO_BASE + 0xa8)
+/* RTC_IO_TOUCH_PAD5_HOLD : R/W ;bitpos:[31] ;default: 1'd0 ; */
+/*description: hold the current value of the output when setting the hold to Ò1Ó*/
+#define RTC_IO_TOUCH_PAD5_HOLD (BIT(31))
+#define RTC_IO_TOUCH_PAD5_HOLD_M (BIT(31))
+#define RTC_IO_TOUCH_PAD5_HOLD_V 0x1
+#define RTC_IO_TOUCH_PAD5_HOLD_S 31
+/* RTC_IO_TOUCH_PAD5_DRV : R/W ;bitpos:[30:29] ;default: 2'd2 ; */
+/*description: the driver strength of the pad*/
+#define RTC_IO_TOUCH_PAD5_DRV 0x00000003
+#define RTC_IO_TOUCH_PAD5_DRV_M ((RTC_IO_TOUCH_PAD5_DRV_V)<<(RTC_IO_TOUCH_PAD5_DRV_S))
+#define RTC_IO_TOUCH_PAD5_DRV_V 0x3
+#define RTC_IO_TOUCH_PAD5_DRV_S 29
+/* RTC_IO_TOUCH_PAD5_RDE : R/W ;bitpos:[28] ;default: 1'd1 ; */
+/*description: the pull down enable of the pad*/
+#define RTC_IO_TOUCH_PAD5_RDE (BIT(28))
+#define RTC_IO_TOUCH_PAD5_RDE_M (BIT(28))
+#define RTC_IO_TOUCH_PAD5_RDE_V 0x1
+#define RTC_IO_TOUCH_PAD5_RDE_S 28
+/* RTC_IO_TOUCH_PAD5_RUE : R/W ;bitpos:[27] ;default: 1'd0 ; */
+/*description: the pull up enable of the pad*/
+#define RTC_IO_TOUCH_PAD5_RUE (BIT(27))
+#define RTC_IO_TOUCH_PAD5_RUE_M (BIT(27))
+#define RTC_IO_TOUCH_PAD5_RUE_V 0x1
+#define RTC_IO_TOUCH_PAD5_RUE_S 27
+/* RTC_IO_TOUCH_PAD5_DAC : R/W ;bitpos:[25:23] ;default: 3'h4 ; */
+/*description: touch sensor slope control. 3-bit for each touch panel default 100.*/
+#define RTC_IO_TOUCH_PAD5_DAC 0x00000007
+#define RTC_IO_TOUCH_PAD5_DAC_M ((RTC_IO_TOUCH_PAD5_DAC_V)<<(RTC_IO_TOUCH_PAD5_DAC_S))
+#define RTC_IO_TOUCH_PAD5_DAC_V 0x7
+#define RTC_IO_TOUCH_PAD5_DAC_S 23
+/* RTC_IO_TOUCH_PAD5_START : R/W ;bitpos:[22] ;default: 1'd0 ; */
+/*description: start touch sensor.*/
+#define RTC_IO_TOUCH_PAD5_START (BIT(22))
+#define RTC_IO_TOUCH_PAD5_START_M (BIT(22))
+#define RTC_IO_TOUCH_PAD5_START_V 0x1
+#define RTC_IO_TOUCH_PAD5_START_S 22
+/* RTC_IO_TOUCH_PAD5_TIE_OPT : R/W ;bitpos:[21] ;default: 1'd0 ; */
+/*description: default touch sensor tie option. 0: tie low 1: tie high.*/
+#define RTC_IO_TOUCH_PAD5_TIE_OPT (BIT(21))
+#define RTC_IO_TOUCH_PAD5_TIE_OPT_M (BIT(21))
+#define RTC_IO_TOUCH_PAD5_TIE_OPT_V 0x1
+#define RTC_IO_TOUCH_PAD5_TIE_OPT_S 21
+/* RTC_IO_TOUCH_PAD5_XPD : R/W ;bitpos:[20] ;default: 1'd0 ; */
+/*description: touch sensor power on.*/
+#define RTC_IO_TOUCH_PAD5_XPD (BIT(20))
+#define RTC_IO_TOUCH_PAD5_XPD_M (BIT(20))
+#define RTC_IO_TOUCH_PAD5_XPD_V 0x1
+#define RTC_IO_TOUCH_PAD5_XPD_S 20
+/* RTC_IO_TOUCH_PAD5_MUX_SEL : R/W ;bitpos:[19] ;default: 1'd0 ; */
+/*description: Ò1Ó select the digital function Ó0Óslection the rtc function*/
+#define RTC_IO_TOUCH_PAD5_MUX_SEL (BIT(19))
+#define RTC_IO_TOUCH_PAD5_MUX_SEL_M (BIT(19))
+#define RTC_IO_TOUCH_PAD5_MUX_SEL_V 0x1
+#define RTC_IO_TOUCH_PAD5_MUX_SEL_S 19
+/* RTC_IO_TOUCH_PAD5_FUN_SEL : R/W ;bitpos:[18:17] ;default: 2'd0 ; */
+/*description: the functional selection signal of the pad*/
+#define RTC_IO_TOUCH_PAD5_FUN_SEL 0x00000003
+#define RTC_IO_TOUCH_PAD5_FUN_SEL_M ((RTC_IO_TOUCH_PAD5_FUN_SEL_V)<<(RTC_IO_TOUCH_PAD5_FUN_SEL_S))
+#define RTC_IO_TOUCH_PAD5_FUN_SEL_V 0x3
+#define RTC_IO_TOUCH_PAD5_FUN_SEL_S 17
+/* RTC_IO_TOUCH_PAD5_SLP_SEL : R/W ;bitpos:[16] ;default: 1'd0 ; */
+/*description: the sleep status selection signal of the pad*/
+#define RTC_IO_TOUCH_PAD5_SLP_SEL (BIT(16))
+#define RTC_IO_TOUCH_PAD5_SLP_SEL_M (BIT(16))
+#define RTC_IO_TOUCH_PAD5_SLP_SEL_V 0x1
+#define RTC_IO_TOUCH_PAD5_SLP_SEL_S 16
+/* RTC_IO_TOUCH_PAD5_SLP_IE : R/W ;bitpos:[15] ;default: 1'd0 ; */
+/*description: the input enable of the pad in sleep status*/
+#define RTC_IO_TOUCH_PAD5_SLP_IE (BIT(15))
+#define RTC_IO_TOUCH_PAD5_SLP_IE_M (BIT(15))
+#define RTC_IO_TOUCH_PAD5_SLP_IE_V 0x1
+#define RTC_IO_TOUCH_PAD5_SLP_IE_S 15
+/* RTC_IO_TOUCH_PAD5_SLP_OE : R/W ;bitpos:[14] ;default: 1'd0 ; */
+/*description: the output enable of the pad in sleep status*/
+#define RTC_IO_TOUCH_PAD5_SLP_OE (BIT(14))
+#define RTC_IO_TOUCH_PAD5_SLP_OE_M (BIT(14))
+#define RTC_IO_TOUCH_PAD5_SLP_OE_V 0x1
+#define RTC_IO_TOUCH_PAD5_SLP_OE_S 14
+/* RTC_IO_TOUCH_PAD5_FUN_IE : R/W ;bitpos:[13] ;default: 1'd0 ; */
+/*description: the input enable of the pad*/
+#define RTC_IO_TOUCH_PAD5_FUN_IE (BIT(13))
+#define RTC_IO_TOUCH_PAD5_FUN_IE_M (BIT(13))
+#define RTC_IO_TOUCH_PAD5_FUN_IE_V 0x1
+#define RTC_IO_TOUCH_PAD5_FUN_IE_S 13
+/* RTC_IO_TOUCH_PAD5_TO_GPIO : R/W ;bitpos:[12] ;default: 1'd0 ; */
+/*description: connect the rtc pad input to digital pad input Ó0Ó is availbale.MTDI*/
+#define RTC_IO_TOUCH_PAD5_TO_GPIO (BIT(12))
+#define RTC_IO_TOUCH_PAD5_TO_GPIO_M (BIT(12))
+#define RTC_IO_TOUCH_PAD5_TO_GPIO_V 0x1
+#define RTC_IO_TOUCH_PAD5_TO_GPIO_S 12
+
+#define RTC_IO_TOUCH_PAD6_REG (DR_REG_RTCIO_BASE + 0xac)
+/* RTC_IO_TOUCH_PAD6_HOLD : R/W ;bitpos:[31] ;default: 1'd0 ; */
+/*description: hold the current value of the output when setting the hold to Ò1Ó*/
+#define RTC_IO_TOUCH_PAD6_HOLD (BIT(31))
+#define RTC_IO_TOUCH_PAD6_HOLD_M (BIT(31))
+#define RTC_IO_TOUCH_PAD6_HOLD_V 0x1
+#define RTC_IO_TOUCH_PAD6_HOLD_S 31
+/* RTC_IO_TOUCH_PAD6_DRV : R/W ;bitpos:[30:29] ;default: 2'd2 ; */
+/*description: the driver strength of the pad*/
+#define RTC_IO_TOUCH_PAD6_DRV 0x00000003
+#define RTC_IO_TOUCH_PAD6_DRV_M ((RTC_IO_TOUCH_PAD6_DRV_V)<<(RTC_IO_TOUCH_PAD6_DRV_S))
+#define RTC_IO_TOUCH_PAD6_DRV_V 0x3
+#define RTC_IO_TOUCH_PAD6_DRV_S 29
+/* RTC_IO_TOUCH_PAD6_RDE : R/W ;bitpos:[28] ;default: 1'd0 ; */
+/*description: the pull down enable of the pad*/
+#define RTC_IO_TOUCH_PAD6_RDE (BIT(28))
+#define RTC_IO_TOUCH_PAD6_RDE_M (BIT(28))
+#define RTC_IO_TOUCH_PAD6_RDE_V 0x1
+#define RTC_IO_TOUCH_PAD6_RDE_S 28
+/* RTC_IO_TOUCH_PAD6_RUE : R/W ;bitpos:[27] ;default: 1'd1 ; */
+/*description: the pull up enable of the pad*/
+#define RTC_IO_TOUCH_PAD6_RUE (BIT(27))
+#define RTC_IO_TOUCH_PAD6_RUE_M (BIT(27))
+#define RTC_IO_TOUCH_PAD6_RUE_V 0x1
+#define RTC_IO_TOUCH_PAD6_RUE_S 27
+/* RTC_IO_TOUCH_PAD6_DAC : R/W ;bitpos:[25:23] ;default: 3'h4 ; */
+/*description: touch sensor slope control. 3-bit for each touch panel default 100.*/
+#define RTC_IO_TOUCH_PAD6_DAC 0x00000007
+#define RTC_IO_TOUCH_PAD6_DAC_M ((RTC_IO_TOUCH_PAD6_DAC_V)<<(RTC_IO_TOUCH_PAD6_DAC_S))
+#define RTC_IO_TOUCH_PAD6_DAC_V 0x7
+#define RTC_IO_TOUCH_PAD6_DAC_S 23
+/* RTC_IO_TOUCH_PAD6_START : R/W ;bitpos:[22] ;default: 1'd0 ; */
+/*description: start touch sensor.*/
+#define RTC_IO_TOUCH_PAD6_START (BIT(22))
+#define RTC_IO_TOUCH_PAD6_START_M (BIT(22))
+#define RTC_IO_TOUCH_PAD6_START_V 0x1
+#define RTC_IO_TOUCH_PAD6_START_S 22
+/* RTC_IO_TOUCH_PAD6_TIE_OPT : R/W ;bitpos:[21] ;default: 1'd0 ; */
+/*description: default touch sensor tie option. 0: tie low 1: tie high.*/
+#define RTC_IO_TOUCH_PAD6_TIE_OPT (BIT(21))
+#define RTC_IO_TOUCH_PAD6_TIE_OPT_M (BIT(21))
+#define RTC_IO_TOUCH_PAD6_TIE_OPT_V 0x1
+#define RTC_IO_TOUCH_PAD6_TIE_OPT_S 21
+/* RTC_IO_TOUCH_PAD6_XPD : R/W ;bitpos:[20] ;default: 1'd0 ; */
+/*description: touch sensor power on.*/
+#define RTC_IO_TOUCH_PAD6_XPD (BIT(20))
+#define RTC_IO_TOUCH_PAD6_XPD_M (BIT(20))
+#define RTC_IO_TOUCH_PAD6_XPD_V 0x1
+#define RTC_IO_TOUCH_PAD6_XPD_S 20
+/* RTC_IO_TOUCH_PAD6_MUX_SEL : R/W ;bitpos:[19] ;default: 1'd0 ; */
+/*description: Ò1Ó select the digital function Ó0Óslection the rtc function*/
+#define RTC_IO_TOUCH_PAD6_MUX_SEL (BIT(19))
+#define RTC_IO_TOUCH_PAD6_MUX_SEL_M (BIT(19))
+#define RTC_IO_TOUCH_PAD6_MUX_SEL_V 0x1
+#define RTC_IO_TOUCH_PAD6_MUX_SEL_S 19
+/* RTC_IO_TOUCH_PAD6_FUN_SEL : R/W ;bitpos:[18:17] ;default: 2'd0 ; */
+/*description: the functional selection signal of the pad*/
+#define RTC_IO_TOUCH_PAD6_FUN_SEL 0x00000003
+#define RTC_IO_TOUCH_PAD6_FUN_SEL_M ((RTC_IO_TOUCH_PAD6_FUN_SEL_V)<<(RTC_IO_TOUCH_PAD6_FUN_SEL_S))
+#define RTC_IO_TOUCH_PAD6_FUN_SEL_V 0x3
+#define RTC_IO_TOUCH_PAD6_FUN_SEL_S 17
+/* RTC_IO_TOUCH_PAD6_SLP_SEL : R/W ;bitpos:[16] ;default: 1'd0 ; */
+/*description: the sleep status selection signal of the pad*/
+#define RTC_IO_TOUCH_PAD6_SLP_SEL (BIT(16))
+#define RTC_IO_TOUCH_PAD6_SLP_SEL_M (BIT(16))
+#define RTC_IO_TOUCH_PAD6_SLP_SEL_V 0x1
+#define RTC_IO_TOUCH_PAD6_SLP_SEL_S 16
+/* RTC_IO_TOUCH_PAD6_SLP_IE : R/W ;bitpos:[15] ;default: 1'd0 ; */
+/*description: the input enable of the pad in sleep status*/
+#define RTC_IO_TOUCH_PAD6_SLP_IE (BIT(15))
+#define RTC_IO_TOUCH_PAD6_SLP_IE_M (BIT(15))
+#define RTC_IO_TOUCH_PAD6_SLP_IE_V 0x1
+#define RTC_IO_TOUCH_PAD6_SLP_IE_S 15
+/* RTC_IO_TOUCH_PAD6_SLP_OE : R/W ;bitpos:[14] ;default: 1'd0 ; */
+/*description: the output enable of the pad in sleep status*/
+#define RTC_IO_TOUCH_PAD6_SLP_OE (BIT(14))
+#define RTC_IO_TOUCH_PAD6_SLP_OE_M (BIT(14))
+#define RTC_IO_TOUCH_PAD6_SLP_OE_V 0x1
+#define RTC_IO_TOUCH_PAD6_SLP_OE_S 14
+/* RTC_IO_TOUCH_PAD6_FUN_IE : R/W ;bitpos:[13] ;default: 1'd0 ; */
+/*description: the input enable of the pad*/
+#define RTC_IO_TOUCH_PAD6_FUN_IE (BIT(13))
+#define RTC_IO_TOUCH_PAD6_FUN_IE_M (BIT(13))
+#define RTC_IO_TOUCH_PAD6_FUN_IE_V 0x1
+#define RTC_IO_TOUCH_PAD6_FUN_IE_S 13
+/* RTC_IO_TOUCH_PAD6_TO_GPIO : R/W ;bitpos:[12] ;default: 1'd0 ; */
+/*description: connect the rtc pad input to digital pad input Ó0Ó is availbale.MTMS*/
+#define RTC_IO_TOUCH_PAD6_TO_GPIO (BIT(12))
+#define RTC_IO_TOUCH_PAD6_TO_GPIO_M (BIT(12))
+#define RTC_IO_TOUCH_PAD6_TO_GPIO_V 0x1
+#define RTC_IO_TOUCH_PAD6_TO_GPIO_S 12
+
+#define RTC_IO_TOUCH_PAD7_REG (DR_REG_RTCIO_BASE + 0xb0)
+/* RTC_IO_TOUCH_PAD7_HOLD : R/W ;bitpos:[31] ;default: 1'd0 ; */
+/*description: hold the current value of the output when setting the hold to Ò1Ó*/
+#define RTC_IO_TOUCH_PAD7_HOLD (BIT(31))
+#define RTC_IO_TOUCH_PAD7_HOLD_M (BIT(31))
+#define RTC_IO_TOUCH_PAD7_HOLD_V 0x1
+#define RTC_IO_TOUCH_PAD7_HOLD_S 31
+/* RTC_IO_TOUCH_PAD7_DRV : R/W ;bitpos:[30:29] ;default: 2'd2 ; */
+/*description: the driver strength of the pad*/
+#define RTC_IO_TOUCH_PAD7_DRV 0x00000003
+#define RTC_IO_TOUCH_PAD7_DRV_M ((RTC_IO_TOUCH_PAD7_DRV_V)<<(RTC_IO_TOUCH_PAD7_DRV_S))
+#define RTC_IO_TOUCH_PAD7_DRV_V 0x3
+#define RTC_IO_TOUCH_PAD7_DRV_S 29
+/* RTC_IO_TOUCH_PAD7_RDE : R/W ;bitpos:[28] ;default: 1'd0 ; */
+/*description: the pull down enable of the pad*/
+#define RTC_IO_TOUCH_PAD7_RDE (BIT(28))
+#define RTC_IO_TOUCH_PAD7_RDE_M (BIT(28))
+#define RTC_IO_TOUCH_PAD7_RDE_V 0x1
+#define RTC_IO_TOUCH_PAD7_RDE_S 28
+/* RTC_IO_TOUCH_PAD7_RUE : R/W ;bitpos:[27] ;default: 1'd0 ; */
+/*description: the pull up enable of the pad*/
+#define RTC_IO_TOUCH_PAD7_RUE (BIT(27))
+#define RTC_IO_TOUCH_PAD7_RUE_M (BIT(27))
+#define RTC_IO_TOUCH_PAD7_RUE_V 0x1
+#define RTC_IO_TOUCH_PAD7_RUE_S 27
+/* RTC_IO_TOUCH_PAD7_DAC : R/W ;bitpos:[25:23] ;default: 3'h4 ; */
+/*description: touch sensor slope control. 3-bit for each touch panel default 100.*/
+#define RTC_IO_TOUCH_PAD7_DAC 0x00000007
+#define RTC_IO_TOUCH_PAD7_DAC_M ((RTC_IO_TOUCH_PAD7_DAC_V)<<(RTC_IO_TOUCH_PAD7_DAC_S))
+#define RTC_IO_TOUCH_PAD7_DAC_V 0x7
+#define RTC_IO_TOUCH_PAD7_DAC_S 23
+/* RTC_IO_TOUCH_PAD7_START : R/W ;bitpos:[22] ;default: 1'd0 ; */
+/*description: start touch sensor.*/
+#define RTC_IO_TOUCH_PAD7_START (BIT(22))
+#define RTC_IO_TOUCH_PAD7_START_M (BIT(22))
+#define RTC_IO_TOUCH_PAD7_START_V 0x1
+#define RTC_IO_TOUCH_PAD7_START_S 22
+/* RTC_IO_TOUCH_PAD7_TIE_OPT : R/W ;bitpos:[21] ;default: 1'd0 ; */
+/*description: default touch sensor tie option. 0: tie low 1: tie high.*/
+#define RTC_IO_TOUCH_PAD7_TIE_OPT (BIT(21))
+#define RTC_IO_TOUCH_PAD7_TIE_OPT_M (BIT(21))
+#define RTC_IO_TOUCH_PAD7_TIE_OPT_V 0x1
+#define RTC_IO_TOUCH_PAD7_TIE_OPT_S 21
+/* RTC_IO_TOUCH_PAD7_XPD : R/W ;bitpos:[20] ;default: 1'd0 ; */
+/*description: touch sensor power on.*/
+#define RTC_IO_TOUCH_PAD7_XPD (BIT(20))
+#define RTC_IO_TOUCH_PAD7_XPD_M (BIT(20))
+#define RTC_IO_TOUCH_PAD7_XPD_V 0x1
+#define RTC_IO_TOUCH_PAD7_XPD_S 20
+/* RTC_IO_TOUCH_PAD7_MUX_SEL : R/W ;bitpos:[19] ;default: 1'd0 ; */
+/*description: Ò1Ó select the digital function Ó0Óslection the rtc function*/
+#define RTC_IO_TOUCH_PAD7_MUX_SEL (BIT(19))
+#define RTC_IO_TOUCH_PAD7_MUX_SEL_M (BIT(19))
+#define RTC_IO_TOUCH_PAD7_MUX_SEL_V 0x1
+#define RTC_IO_TOUCH_PAD7_MUX_SEL_S 19
+/* RTC_IO_TOUCH_PAD7_FUN_SEL : R/W ;bitpos:[18:17] ;default: 2'd0 ; */
+/*description: the functional selection signal of the pad*/
+#define RTC_IO_TOUCH_PAD7_FUN_SEL 0x00000003
+#define RTC_IO_TOUCH_PAD7_FUN_SEL_M ((RTC_IO_TOUCH_PAD7_FUN_SEL_V)<<(RTC_IO_TOUCH_PAD7_FUN_SEL_S))
+#define RTC_IO_TOUCH_PAD7_FUN_SEL_V 0x3
+#define RTC_IO_TOUCH_PAD7_FUN_SEL_S 17
+/* RTC_IO_TOUCH_PAD7_SLP_SEL : R/W ;bitpos:[16] ;default: 1'd0 ; */
+/*description: the sleep status selection signal of the pad*/
+#define RTC_IO_TOUCH_PAD7_SLP_SEL (BIT(16))
+#define RTC_IO_TOUCH_PAD7_SLP_SEL_M (BIT(16))
+#define RTC_IO_TOUCH_PAD7_SLP_SEL_V 0x1
+#define RTC_IO_TOUCH_PAD7_SLP_SEL_S 16
+/* RTC_IO_TOUCH_PAD7_SLP_IE : R/W ;bitpos:[15] ;default: 1'd0 ; */
+/*description: the input enable of the pad in sleep status*/
+#define RTC_IO_TOUCH_PAD7_SLP_IE (BIT(15))
+#define RTC_IO_TOUCH_PAD7_SLP_IE_M (BIT(15))
+#define RTC_IO_TOUCH_PAD7_SLP_IE_V 0x1
+#define RTC_IO_TOUCH_PAD7_SLP_IE_S 15
+/* RTC_IO_TOUCH_PAD7_SLP_OE : R/W ;bitpos:[14] ;default: 1'd0 ; */
+/*description: the output enable of the pad in sleep status*/
+#define RTC_IO_TOUCH_PAD7_SLP_OE (BIT(14))
+#define RTC_IO_TOUCH_PAD7_SLP_OE_M (BIT(14))
+#define RTC_IO_TOUCH_PAD7_SLP_OE_V 0x1
+#define RTC_IO_TOUCH_PAD7_SLP_OE_S 14
+/* RTC_IO_TOUCH_PAD7_FUN_IE : R/W ;bitpos:[13] ;default: 1'd0 ; */
+/*description: the input enable of the pad*/
+#define RTC_IO_TOUCH_PAD7_FUN_IE (BIT(13))
+#define RTC_IO_TOUCH_PAD7_FUN_IE_M (BIT(13))
+#define RTC_IO_TOUCH_PAD7_FUN_IE_V 0x1
+#define RTC_IO_TOUCH_PAD7_FUN_IE_S 13
+/* RTC_IO_TOUCH_PAD7_TO_GPIO : R/W ;bitpos:[12] ;default: 1'd0 ; */
+/*description: connect the rtc pad input to digital pad input Ó0Ó is availbale.GPIO27*/
+#define RTC_IO_TOUCH_PAD7_TO_GPIO (BIT(12))
+#define RTC_IO_TOUCH_PAD7_TO_GPIO_M (BIT(12))
+#define RTC_IO_TOUCH_PAD7_TO_GPIO_V 0x1
+#define RTC_IO_TOUCH_PAD7_TO_GPIO_S 12
+
+#define RTC_IO_TOUCH_PAD8_REG (DR_REG_RTCIO_BASE + 0xb4)
+/* RTC_IO_TOUCH_PAD8_DAC : R/W ;bitpos:[25:23] ;default: 3'h4 ; */
+/*description: touch sensor slope control. 3-bit for each touch panel default 100.*/
+#define RTC_IO_TOUCH_PAD8_DAC 0x00000007
+#define RTC_IO_TOUCH_PAD8_DAC_M ((RTC_IO_TOUCH_PAD8_DAC_V)<<(RTC_IO_TOUCH_PAD8_DAC_S))
+#define RTC_IO_TOUCH_PAD8_DAC_V 0x7
+#define RTC_IO_TOUCH_PAD8_DAC_S 23
+/* RTC_IO_TOUCH_PAD8_START : R/W ;bitpos:[22] ;default: 1'd0 ; */
+/*description: start touch sensor.*/
+#define RTC_IO_TOUCH_PAD8_START (BIT(22))
+#define RTC_IO_TOUCH_PAD8_START_M (BIT(22))
+#define RTC_IO_TOUCH_PAD8_START_V 0x1
+#define RTC_IO_TOUCH_PAD8_START_S 22
+/* RTC_IO_TOUCH_PAD8_TIE_OPT : R/W ;bitpos:[21] ;default: 1'd0 ; */
+/*description: default touch sensor tie option. 0: tie low 1: tie high.*/
+#define RTC_IO_TOUCH_PAD8_TIE_OPT (BIT(21))
+#define RTC_IO_TOUCH_PAD8_TIE_OPT_M (BIT(21))
+#define RTC_IO_TOUCH_PAD8_TIE_OPT_V 0x1
+#define RTC_IO_TOUCH_PAD8_TIE_OPT_S 21
+/* RTC_IO_TOUCH_PAD8_XPD : R/W ;bitpos:[20] ;default: 1'd0 ; */
+/*description: touch sensor power on.*/
+#define RTC_IO_TOUCH_PAD8_XPD (BIT(20))
+#define RTC_IO_TOUCH_PAD8_XPD_M (BIT(20))
+#define RTC_IO_TOUCH_PAD8_XPD_V 0x1
+#define RTC_IO_TOUCH_PAD8_XPD_S 20
+/* RTC_IO_TOUCH_PAD8_TO_GPIO : R/W ;bitpos:[19] ;default: 1'd0 ; */
+/*description: connect the rtc pad input to digital pad input Ó0Ó is availbale*/
+#define RTC_IO_TOUCH_PAD8_TO_GPIO (BIT(19))
+#define RTC_IO_TOUCH_PAD8_TO_GPIO_M (BIT(19))
+#define RTC_IO_TOUCH_PAD8_TO_GPIO_V 0x1
+#define RTC_IO_TOUCH_PAD8_TO_GPIO_S 19
+
+#define RTC_IO_TOUCH_PAD9_REG (DR_REG_RTCIO_BASE + 0xb8)
+/* RTC_IO_TOUCH_PAD9_DAC : R/W ;bitpos:[25:23] ;default: 3'h4 ; */
+/*description: touch sensor slope control. 3-bit for each touch panel default 100.*/
+#define RTC_IO_TOUCH_PAD9_DAC 0x00000007
+#define RTC_IO_TOUCH_PAD9_DAC_M ((RTC_IO_TOUCH_PAD9_DAC_V)<<(RTC_IO_TOUCH_PAD9_DAC_S))
+#define RTC_IO_TOUCH_PAD9_DAC_V 0x7
+#define RTC_IO_TOUCH_PAD9_DAC_S 23
+/* RTC_IO_TOUCH_PAD9_START : R/W ;bitpos:[22] ;default: 1'd0 ; */
+/*description: start touch sensor.*/
+#define RTC_IO_TOUCH_PAD9_START (BIT(22))
+#define RTC_IO_TOUCH_PAD9_START_M (BIT(22))
+#define RTC_IO_TOUCH_PAD9_START_V 0x1
+#define RTC_IO_TOUCH_PAD9_START_S 22
+/* RTC_IO_TOUCH_PAD9_TIE_OPT : R/W ;bitpos:[21] ;default: 1'd0 ; */
+/*description: default touch sensor tie option. 0: tie low 1: tie high.*/
+#define RTC_IO_TOUCH_PAD9_TIE_OPT (BIT(21))
+#define RTC_IO_TOUCH_PAD9_TIE_OPT_M (BIT(21))
+#define RTC_IO_TOUCH_PAD9_TIE_OPT_V 0x1
+#define RTC_IO_TOUCH_PAD9_TIE_OPT_S 21
+/* RTC_IO_TOUCH_PAD9_XPD : R/W ;bitpos:[20] ;default: 1'd0 ; */
+/*description: touch sensor power on.*/
+#define RTC_IO_TOUCH_PAD9_XPD (BIT(20))
+#define RTC_IO_TOUCH_PAD9_XPD_M (BIT(20))
+#define RTC_IO_TOUCH_PAD9_XPD_V 0x1
+#define RTC_IO_TOUCH_PAD9_XPD_S 20
+/* RTC_IO_TOUCH_PAD9_TO_GPIO : R/W ;bitpos:[19] ;default: 1'd0 ; */
+/*description: connect the rtc pad input to digital pad input Ó0Ó is availbale*/
+#define RTC_IO_TOUCH_PAD9_TO_GPIO (BIT(19))
+#define RTC_IO_TOUCH_PAD9_TO_GPIO_M (BIT(19))
+#define RTC_IO_TOUCH_PAD9_TO_GPIO_V 0x1
+#define RTC_IO_TOUCH_PAD9_TO_GPIO_S 19
+
+#define RTC_IO_EXT_WAKEUP0_REG (DR_REG_RTCIO_BASE + 0xbc)
+/* RTC_IO_EXT_WAKEUP0_SEL : R/W ;bitpos:[31:27] ;default: 5'd0 ; */
+/*description: select the wakeup source Ó0Ó select GPIO0 Ó1Ó select GPIO2 ...Ò17Ó select GPIO17*/
+#define RTC_IO_EXT_WAKEUP0_SEL 0x0000001F
+#define RTC_IO_EXT_WAKEUP0_SEL_M ((RTC_IO_EXT_WAKEUP0_SEL_V)<<(RTC_IO_EXT_WAKEUP0_SEL_S))
+#define RTC_IO_EXT_WAKEUP0_SEL_V 0x1F
+#define RTC_IO_EXT_WAKEUP0_SEL_S 27
+
+#define RTC_IO_XTL_EXT_CTR_REG (DR_REG_RTCIO_BASE + 0xc0)
+/* RTC_IO_XTL_EXT_CTR_SEL : R/W ;bitpos:[31:27] ;default: 5'd0 ; */
+/*description: select the external xtl power source Ó0Ó select GPIO0 Ó1Ó select
+ GPIO2 ...Ò17Ó select GPIO17*/
+#define RTC_IO_XTL_EXT_CTR_SEL 0x0000001F
+#define RTC_IO_XTL_EXT_CTR_SEL_M ((RTC_IO_XTL_EXT_CTR_SEL_V)<<(RTC_IO_XTL_EXT_CTR_SEL_S))
+#define RTC_IO_XTL_EXT_CTR_SEL_V 0x1F
+#define RTC_IO_XTL_EXT_CTR_SEL_S 27
+
+#define RTC_IO_SAR_I2C_IO_REG (DR_REG_RTCIO_BASE + 0xc4)
+/* RTC_IO_SAR_I2C_SDA_SEL : R/W ;bitpos:[31:30] ;default: 2'd0 ; */
+/*description: Ò0Ó using TOUCH_PAD[1] as i2c sda Ò1Ó using TOUCH_PAD[3] as i2c sda*/
+#define RTC_IO_SAR_I2C_SDA_SEL 0x00000003
+#define RTC_IO_SAR_I2C_SDA_SEL_M ((RTC_IO_SAR_I2C_SDA_SEL_V)<<(RTC_IO_SAR_I2C_SDA_SEL_S))
+#define RTC_IO_SAR_I2C_SDA_SEL_V 0x3
+#define RTC_IO_SAR_I2C_SDA_SEL_S 30
+/* RTC_IO_SAR_I2C_SCL_SEL : R/W ;bitpos:[29:28] ;default: 2'd0 ; */
+/*description: Ò0Ó using TOUCH_PAD[0] as i2c clk Ò1Ó using TOUCH_PAD[2] as i2c clk*/
+#define RTC_IO_SAR_I2C_SCL_SEL 0x00000003
+#define RTC_IO_SAR_I2C_SCL_SEL_M ((RTC_IO_SAR_I2C_SCL_SEL_V)<<(RTC_IO_SAR_I2C_SCL_SEL_S))
+#define RTC_IO_SAR_I2C_SCL_SEL_V 0x3
+#define RTC_IO_SAR_I2C_SCL_SEL_S 28
+/* RTC_IO_SAR_DEBUG_BIT_SEL : R/W ;bitpos:[27:23] ;default: 5'h0 ; */
+/*description: */
+#define RTC_IO_SAR_DEBUG_BIT_SEL 0x0000001F
+#define RTC_IO_SAR_DEBUG_BIT_SEL_M ((RTC_IO_SAR_DEBUG_BIT_SEL_V)<<(RTC_IO_SAR_DEBUG_BIT_SEL_S))
+#define RTC_IO_SAR_DEBUG_BIT_SEL_V 0x1F
+#define RTC_IO_SAR_DEBUG_BIT_SEL_S 23
+
+#define RTC_IO_DATE_REG (DR_REG_RTCIO_BASE + 0xc8)
+/* RTC_IO_IO_DATE : R/W ;bitpos:[27:0] ;default: 28'h1603160 ; */
+/*description: date*/
+#define RTC_IO_IO_DATE 0x0FFFFFFF
+#define RTC_IO_IO_DATE_M ((RTC_IO_IO_DATE_V)<<(RTC_IO_IO_DATE_S))
+#define RTC_IO_IO_DATE_V 0xFFFFFFF
+#define RTC_IO_IO_DATE_S 0
+#define RTC_IO_RTC_IO_DATE_VERSION 0x1703160
+
+
+
+
+#endif /*_SOC_RTC_IO_REG_H_ */
+
+
-// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD\r
-//\r
-// Licensed under the Apache License, Version 2.0 (the "License");\r
-// you may not use this file except in compliance with the License.\r
-// You may obtain a copy of the License at\r
-\r
-// http://www.apache.org/licenses/LICENSE-2.0\r
-//\r
-// Unless required by applicable law or agreed to in writing, software\r
-// distributed under the License is distributed on an "AS IS" BASIS,\r
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
-// See the License for the specific language governing permissions and\r
-// limitations under the License.\r
-#ifndef __SPI_REG_H__\r
-#define __SPI_REG_H__\r
-\r
-\r
-#include "soc.h"\r
-#define REG_SPI_BASE(i) (DR_REG_SPI1_BASE + (((i)>1) ? (((i)* 0x1000) + 0x20000) : (((~(i)) & 1)* 0x1000 )))\r
-\r
-#define SPI_CMD_REG(i) (REG_SPI_BASE(i) + 0x0)\r
-/* SPI_FLASH_READ : R/W ;bitpos:[31] ;default: 1'b0 ; */\r
-/*description: Read flash enable. Read flash operation will be triggered when\r
- the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.*/\r
-#define SPI_FLASH_READ (BIT(31))\r
-#define SPI_FLASH_READ_M (BIT(31))\r
-#define SPI_FLASH_READ_V 0x1\r
-#define SPI_FLASH_READ_S 31\r
-/* SPI_FLASH_WREN : R/W ;bitpos:[30] ;default: 1'b0 ; */\r
-/*description: Write flash enable. Write enable command will be sent when the\r
- bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.*/\r
-#define SPI_FLASH_WREN (BIT(30))\r
-#define SPI_FLASH_WREN_M (BIT(30))\r
-#define SPI_FLASH_WREN_V 0x1\r
-#define SPI_FLASH_WREN_S 30\r
-/* SPI_FLASH_WRDI : R/W ;bitpos:[29] ;default: 1'b0 ; */\r
-/*description: Write flash disable. Write disable command will be sent when\r
- the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.*/\r
-#define SPI_FLASH_WRDI (BIT(29))\r
-#define SPI_FLASH_WRDI_M (BIT(29))\r
-#define SPI_FLASH_WRDI_V 0x1\r
-#define SPI_FLASH_WRDI_S 29\r
-/* SPI_FLASH_RDID : R/W ;bitpos:[28] ;default: 1'b0 ; */\r
-/*description: Read JEDEC ID . Read ID command will be sent when the bit is\r
- set. The bit will be cleared once the operation done. 1: enable 0: disable.*/\r
-#define SPI_FLASH_RDID (BIT(28))\r
-#define SPI_FLASH_RDID_M (BIT(28))\r
-#define SPI_FLASH_RDID_V 0x1\r
-#define SPI_FLASH_RDID_S 28\r
-/* SPI_FLASH_RDSR : R/W ;bitpos:[27] ;default: 1'b0 ; */\r
-/*description: Read status register-1. Read status operation will be triggered\r
- when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/\r
-#define SPI_FLASH_RDSR (BIT(27))\r
-#define SPI_FLASH_RDSR_M (BIT(27))\r
-#define SPI_FLASH_RDSR_V 0x1\r
-#define SPI_FLASH_RDSR_S 27\r
-/* SPI_FLASH_WRSR : R/W ;bitpos:[26] ;default: 1'b0 ; */\r
-/*description: Write status register enable. Write status operation will\r
- be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/\r
-#define SPI_FLASH_WRSR (BIT(26))\r
-#define SPI_FLASH_WRSR_M (BIT(26))\r
-#define SPI_FLASH_WRSR_V 0x1\r
-#define SPI_FLASH_WRSR_S 26\r
-/* SPI_FLASH_PP : R/W ;bitpos:[25] ;default: 1'b0 ; */\r
-/*description: Page program enable(1 byte ~256 bytes data to be programmed).\r
- Page program operation will be triggered when the bit is set. The bit will be cleared once the operation done .1: enable 0: disable.*/\r
-#define SPI_FLASH_PP (BIT(25))\r
-#define SPI_FLASH_PP_M (BIT(25))\r
-#define SPI_FLASH_PP_V 0x1\r
-#define SPI_FLASH_PP_S 25\r
-/* SPI_FLASH_SE : R/W ;bitpos:[24] ;default: 1'b0 ; */\r
-/*description: Sector erase enable. A 4KB sector is erased via SPI command 20H. Sector erase operation will be triggered\r
- when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/\r
-#define SPI_FLASH_SE (BIT(24))\r
-#define SPI_FLASH_SE_M (BIT(24))\r
-#define SPI_FLASH_SE_V 0x1\r
-#define SPI_FLASH_SE_S 24\r
-/* SPI_FLASH_BE : R/W ;bitpos:[23] ;default: 1'b0 ; */\r
-/*description: Block erase enable. A 64KB block is erased via SPI command D8H. Block erase operation will be triggered\r
- when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/\r
-#define SPI_FLASH_BE (BIT(23))\r
-#define SPI_FLASH_BE_M (BIT(23))\r
-#define SPI_FLASH_BE_V 0x1\r
-#define SPI_FLASH_BE_S 23\r
-/* SPI_FLASH_CE : R/W ;bitpos:[22] ;default: 1'b0 ; */\r
-/*description: Chip erase enable. Chip erase operation will be triggered when\r
- the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/\r
-#define SPI_FLASH_CE (BIT(22))\r
-#define SPI_FLASH_CE_M (BIT(22))\r
-#define SPI_FLASH_CE_V 0x1\r
-#define SPI_FLASH_CE_S 22\r
-/* SPI_FLASH_DP : R/W ;bitpos:[21] ;default: 1'b0 ; */\r
-/*description: Drive Flash into power down. An operation will be triggered\r
- when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/\r
-#define SPI_FLASH_DP (BIT(21))\r
-#define SPI_FLASH_DP_M (BIT(21))\r
-#define SPI_FLASH_DP_V 0x1\r
-#define SPI_FLASH_DP_S 21\r
-/* SPI_FLASH_RES : R/W ;bitpos:[20] ;default: 1'b0 ; */\r
-/*description: This bit combined with reg_resandres bit releases Flash from\r
- the power-down state or high performance mode and obtains the devices ID. The bit will be cleared once the operation done.1: enable 0: disable.*/\r
-#define SPI_FLASH_RES (BIT(20))\r
-#define SPI_FLASH_RES_M (BIT(20))\r
-#define SPI_FLASH_RES_V 0x1\r
-#define SPI_FLASH_RES_S 20\r
-/* SPI_FLASH_HPM : R/W ;bitpos:[19] ;default: 1'b0 ; */\r
-/*description: Drive Flash into high performance mode. The bit will be cleared\r
- once the operation done.1: enable 0: disable.*/\r
-#define SPI_FLASH_HPM (BIT(19))\r
-#define SPI_FLASH_HPM_M (BIT(19))\r
-#define SPI_FLASH_HPM_V 0x1\r
-#define SPI_FLASH_HPM_S 19\r
-/* SPI_USR : R/W ;bitpos:[18] ;default: 1'b0 ; */\r
-/*description: User define command enable. An operation will be triggered when\r
- the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/\r
-#define SPI_USR (BIT(18))\r
-#define SPI_USR_M (BIT(18))\r
-#define SPI_USR_V 0x1\r
-#define SPI_USR_S 18\r
-/* SPI_FLASH_PES : R/W ;bitpos:[17] ;default: 1'b0 ; */\r
-/*description: program erase suspend bit program erase suspend operation will\r
- be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/\r
-#define SPI_FLASH_PES (BIT(17))\r
-#define SPI_FLASH_PES_M (BIT(17))\r
-#define SPI_FLASH_PES_V 0x1\r
-#define SPI_FLASH_PES_S 17\r
-/* SPI_FLASH_PER : R/W ;bitpos:[16] ;default: 1'b0 ; */\r
-/*description: program erase resume bit program erase suspend operation will\r
- be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/\r
-#define SPI_FLASH_PER (BIT(16))\r
-#define SPI_FLASH_PER_M (BIT(16))\r
-#define SPI_FLASH_PER_V 0x1\r
-#define SPI_FLASH_PER_S 16\r
-\r
-#define SPI_ADDR_REG(i) (REG_SPI_BASE(i) + 0x4)\r
+// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+#ifndef __SPI_REG_H__
+#define __SPI_REG_H__
+
+
+#include "soc.h"
+#define REG_SPI_BASE(i) (DR_REG_SPI1_BASE + (((i)>1) ? (((i)* 0x1000) + 0x20000) : (((~(i)) & 1)* 0x1000 )))
+
+#define SPI_CMD_REG(i) (REG_SPI_BASE(i) + 0x0)
+/* SPI_FLASH_READ : R/W ;bitpos:[31] ;default: 1'b0 ; */
+/*description: Read flash enable. Read flash operation will be triggered when
+ the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.*/
+#define SPI_FLASH_READ (BIT(31))
+#define SPI_FLASH_READ_M (BIT(31))
+#define SPI_FLASH_READ_V 0x1
+#define SPI_FLASH_READ_S 31
+/* SPI_FLASH_WREN : R/W ;bitpos:[30] ;default: 1'b0 ; */
+/*description: Write flash enable. Write enable command will be sent when the
+ bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.*/
+#define SPI_FLASH_WREN (BIT(30))
+#define SPI_FLASH_WREN_M (BIT(30))
+#define SPI_FLASH_WREN_V 0x1
+#define SPI_FLASH_WREN_S 30
+/* SPI_FLASH_WRDI : R/W ;bitpos:[29] ;default: 1'b0 ; */
+/*description: Write flash disable. Write disable command will be sent when
+ the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.*/
+#define SPI_FLASH_WRDI (BIT(29))
+#define SPI_FLASH_WRDI_M (BIT(29))
+#define SPI_FLASH_WRDI_V 0x1
+#define SPI_FLASH_WRDI_S 29
+/* SPI_FLASH_RDID : R/W ;bitpos:[28] ;default: 1'b0 ; */
+/*description: Read JEDEC ID . Read ID command will be sent when the bit is
+ set. The bit will be cleared once the operation done. 1: enable 0: disable.*/
+#define SPI_FLASH_RDID (BIT(28))
+#define SPI_FLASH_RDID_M (BIT(28))
+#define SPI_FLASH_RDID_V 0x1
+#define SPI_FLASH_RDID_S 28
+/* SPI_FLASH_RDSR : R/W ;bitpos:[27] ;default: 1'b0 ; */
+/*description: Read status register-1. Read status operation will be triggered
+ when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/
+#define SPI_FLASH_RDSR (BIT(27))
+#define SPI_FLASH_RDSR_M (BIT(27))
+#define SPI_FLASH_RDSR_V 0x1
+#define SPI_FLASH_RDSR_S 27
+/* SPI_FLASH_WRSR : R/W ;bitpos:[26] ;default: 1'b0 ; */
+/*description: Write status register enable. Write status operation will
+ be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/
+#define SPI_FLASH_WRSR (BIT(26))
+#define SPI_FLASH_WRSR_M (BIT(26))
+#define SPI_FLASH_WRSR_V 0x1
+#define SPI_FLASH_WRSR_S 26
+/* SPI_FLASH_PP : R/W ;bitpos:[25] ;default: 1'b0 ; */
+/*description: Page program enable(1 byte ~256 bytes data to be programmed).
+ Page program operation will be triggered when the bit is set. The bit will be cleared once the operation done .1: enable 0: disable.*/
+#define SPI_FLASH_PP (BIT(25))
+#define SPI_FLASH_PP_M (BIT(25))
+#define SPI_FLASH_PP_V 0x1
+#define SPI_FLASH_PP_S 25
+/* SPI_FLASH_SE : R/W ;bitpos:[24] ;default: 1'b0 ; */
+/*description: Sector erase enable. A 4KB sector is erased via SPI command 20H. Sector erase operation will be triggered
+ when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/
+#define SPI_FLASH_SE (BIT(24))
+#define SPI_FLASH_SE_M (BIT(24))
+#define SPI_FLASH_SE_V 0x1
+#define SPI_FLASH_SE_S 24
+/* SPI_FLASH_BE : R/W ;bitpos:[23] ;default: 1'b0 ; */
+/*description: Block erase enable. A 64KB block is erased via SPI command D8H. Block erase operation will be triggered
+ when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/
+#define SPI_FLASH_BE (BIT(23))
+#define SPI_FLASH_BE_M (BIT(23))
+#define SPI_FLASH_BE_V 0x1
+#define SPI_FLASH_BE_S 23
+/* SPI_FLASH_CE : R/W ;bitpos:[22] ;default: 1'b0 ; */
+/*description: Chip erase enable. Chip erase operation will be triggered when
+ the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/
+#define SPI_FLASH_CE (BIT(22))
+#define SPI_FLASH_CE_M (BIT(22))
+#define SPI_FLASH_CE_V 0x1
+#define SPI_FLASH_CE_S 22
+/* SPI_FLASH_DP : R/W ;bitpos:[21] ;default: 1'b0 ; */
+/*description: Drive Flash into power down. An operation will be triggered
+ when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/
+#define SPI_FLASH_DP (BIT(21))
+#define SPI_FLASH_DP_M (BIT(21))
+#define SPI_FLASH_DP_V 0x1
+#define SPI_FLASH_DP_S 21
+/* SPI_FLASH_RES : R/W ;bitpos:[20] ;default: 1'b0 ; */
+/*description: This bit combined with reg_resandres bit releases Flash from
+ the power-down state or high performance mode and obtains the devices ID. The bit will be cleared once the operation done.1: enable 0: disable.*/
+#define SPI_FLASH_RES (BIT(20))
+#define SPI_FLASH_RES_M (BIT(20))
+#define SPI_FLASH_RES_V 0x1
+#define SPI_FLASH_RES_S 20
+/* SPI_FLASH_HPM : R/W ;bitpos:[19] ;default: 1'b0 ; */
+/*description: Drive Flash into high performance mode. The bit will be cleared
+ once the operation done.1: enable 0: disable.*/
+#define SPI_FLASH_HPM (BIT(19))
+#define SPI_FLASH_HPM_M (BIT(19))
+#define SPI_FLASH_HPM_V 0x1
+#define SPI_FLASH_HPM_S 19
+/* SPI_USR : R/W ;bitpos:[18] ;default: 1'b0 ; */
+/*description: User define command enable. An operation will be triggered when
+ the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/
+#define SPI_USR (BIT(18))
+#define SPI_USR_M (BIT(18))
+#define SPI_USR_V 0x1
+#define SPI_USR_S 18
+/* SPI_FLASH_PES : R/W ;bitpos:[17] ;default: 1'b0 ; */
+/*description: program erase suspend bit program erase suspend operation will
+ be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/
+#define SPI_FLASH_PES (BIT(17))
+#define SPI_FLASH_PES_M (BIT(17))
+#define SPI_FLASH_PES_V 0x1
+#define SPI_FLASH_PES_S 17
+/* SPI_FLASH_PER : R/W ;bitpos:[16] ;default: 1'b0 ; */
+/*description: program erase resume bit program erase suspend operation will
+ be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/
+#define SPI_FLASH_PER (BIT(16))
+#define SPI_FLASH_PER_M (BIT(16))
+#define SPI_FLASH_PER_V 0x1
+#define SPI_FLASH_PER_S 16
+
+#define SPI_ADDR_REG(i) (REG_SPI_BASE(i) + 0x4)
//The CSV actually is wrong here. It indicates that the lower 8 bits of this register are reserved. This is not true,
//all 32 bits of SPI_ADDR_REG are usable/used.
-\r
-#define SPI_CTRL_REG(i) (REG_SPI_BASE(i) + 0x8)\r
-/* SPI_WR_BIT_ORDER : R/W ;bitpos:[26] ;default: 1'b0 ; */\r
-/*description: In command address write-data (MOSI) phases 1: LSB firs 0: MSB first*/\r
-#define SPI_WR_BIT_ORDER (BIT(26))\r
-#define SPI_WR_BIT_ORDER_M (BIT(26))\r
-#define SPI_WR_BIT_ORDER_V 0x1\r
-#define SPI_WR_BIT_ORDER_S 26\r
-/* SPI_RD_BIT_ORDER : R/W ;bitpos:[25] ;default: 1'b0 ; */\r
-/*description: In read-data (MISO) phase 1: LSB first 0: MSB first*/\r
-#define SPI_RD_BIT_ORDER (BIT(25))\r
-#define SPI_RD_BIT_ORDER_M (BIT(25))\r
-#define SPI_RD_BIT_ORDER_V 0x1\r
-#define SPI_RD_BIT_ORDER_S 25\r
-/* SPI_FREAD_QIO : R/W ;bitpos:[24] ;default: 1'b0 ; */\r
-/*description: In the read operations address phase and read-data phase apply\r
- 4 signals. 1: enable 0: disable.*/\r
-#define SPI_FREAD_QIO (BIT(24))\r
-#define SPI_FREAD_QIO_M (BIT(24))\r
-#define SPI_FREAD_QIO_V 0x1\r
-#define SPI_FREAD_QIO_S 24\r
-/* SPI_FREAD_DIO : R/W ;bitpos:[23] ;default: 1'b0 ; */\r
-/*description: In the read operations address phase and read-data phase apply\r
- 2 signals. 1: enable 0: disable.*/\r
-#define SPI_FREAD_DIO (BIT(23))\r
-#define SPI_FREAD_DIO_M (BIT(23))\r
-#define SPI_FREAD_DIO_V 0x1\r
-#define SPI_FREAD_DIO_S 23\r
-/* SPI_WRSR_2B : R/W ;bitpos:[22] ;default: 1'b0 ; */\r
-/*description: two bytes data will be written to status register when it is\r
- set. 1: enable 0: disable.*/\r
-#define SPI_WRSR_2B (BIT(22))\r
-#define SPI_WRSR_2B_M (BIT(22))\r
-#define SPI_WRSR_2B_V 0x1\r
-#define SPI_WRSR_2B_S 22\r
-/* SPI_WP_REG : R/W ;bitpos:[21] ;default: 1'b1 ; */\r
-/*description: Write protect signal output when SPI is idle. 1: output high 0: output low.*/\r
-#define SPI_WP_REG (BIT(21))\r
-#define SPI_WP_REG_M (BIT(21))\r
-#define SPI_WP_REG_V 0x1\r
-#define SPI_WP_REG_S 21\r
-/* SPI_FREAD_QUAD : R/W ;bitpos:[20] ;default: 1'b0 ; */\r
-/*description: In the read operations read-data phase apply 4 signals. 1: enable 0: disable.*/\r
-#define SPI_FREAD_QUAD (BIT(20))\r
-#define SPI_FREAD_QUAD_M (BIT(20))\r
-#define SPI_FREAD_QUAD_V 0x1\r
-#define SPI_FREAD_QUAD_S 20\r
-/* SPI_RESANDRES : R/W ;bitpos:[15] ;default: 1'b1 ; */\r
-/*description: The Device ID is read out to SPI_RD_STATUS register, this bit\r
- combine with spi_flash_res bit. 1: enable 0: disable.*/\r
-#define SPI_RESANDRES (BIT(15))\r
-#define SPI_RESANDRES_M (BIT(15))\r
-#define SPI_RESANDRES_V 0x1\r
-#define SPI_RESANDRES_S 15\r
-/* SPI_FREAD_DUAL : R/W ;bitpos:[14] ;default: 1'b0 ; */\r
-/*description: In the read operations read-data phase apply 2 signals. 1: enable 0: disable.*/\r
-#define SPI_FREAD_DUAL (BIT(14))\r
-#define SPI_FREAD_DUAL_M (BIT(14))\r
-#define SPI_FREAD_DUAL_V 0x1\r
-#define SPI_FREAD_DUAL_S 14\r
-/* SPI_FASTRD_MODE : R/W ;bitpos:[13] ;default: 1'b1 ; */\r
-/*description: This bit enable the bits: spi_fread_qio spi_fread_dio spi_fread_qout\r
- and spi_fread_dout. 1: enable 0: disable.*/\r
-#define SPI_FASTRD_MODE (BIT(13))\r
-#define SPI_FASTRD_MODE_M (BIT(13))\r
-#define SPI_FASTRD_MODE_V 0x1\r
-#define SPI_FASTRD_MODE_S 13\r
-/* SPI_WAIT_FLASH_IDLE_EN : R/W ;bitpos:[12] ;default: 1'b0 ; */\r
-/*description: wait flash idle when program flash or erase flash. 1: enable 0: disable.*/\r
-#define SPI_WAIT_FLASH_IDLE_EN (BIT(12))\r
-#define SPI_WAIT_FLASH_IDLE_EN_M (BIT(12))\r
-#define SPI_WAIT_FLASH_IDLE_EN_V 0x1\r
-#define SPI_WAIT_FLASH_IDLE_EN_S 12\r
-/* SPI_TX_CRC_EN : R/W ;bitpos:[11] ;default: 1'b0 ; */\r
-/*description: For SPI1 enable crc32 when writing encrypted data to flash.\r
- 1: enable 0:disable*/\r
-#define SPI_TX_CRC_EN (BIT(11))\r
-#define SPI_TX_CRC_EN_M (BIT(11))\r
-#define SPI_TX_CRC_EN_V 0x1\r
-#define SPI_TX_CRC_EN_S 11\r
-/* SPI_FCS_CRC_EN : R/W ;bitpos:[10] ;default: 1'b1 ; */\r
-/*description: For SPI1 initialize crc32 module before writing encrypted data\r
- to flash. Active low.*/\r
-#define SPI_FCS_CRC_EN (BIT(10))\r
-#define SPI_FCS_CRC_EN_M (BIT(10))\r
-#define SPI_FCS_CRC_EN_V 0x1\r
-#define SPI_FCS_CRC_EN_S 10\r
-\r
-#define SPI_CTRL1_REG(i) (REG_SPI_BASE(i) + 0xC)\r
-/* SPI_CS_HOLD_DELAY : R/W ;bitpos:[31:28] ;default: 4'h5 ; */\r
-/*description: SPI cs signal is delayed by spi clock cycles*/\r
-#define SPI_CS_HOLD_DELAY 0x0000000F\r
-#define SPI_CS_HOLD_DELAY_M ((SPI_CS_HOLD_DELAY_V)<<(SPI_CS_HOLD_DELAY_S))\r
-#define SPI_CS_HOLD_DELAY_V 0xF\r
-#define SPI_CS_HOLD_DELAY_S 28\r
-/* SPI_CS_HOLD_DELAY_RES : R/W ;bitpos:[27:16] ;default: 12'hfff ; */\r
-/*description: Delay cycles of resume Flash when resume Flash is enable by spi clock.*/\r
-#define SPI_CS_HOLD_DELAY_RES 0x00000FFF\r
-#define SPI_CS_HOLD_DELAY_RES_M ((SPI_CS_HOLD_DELAY_RES_V)<<(SPI_CS_HOLD_DELAY_RES_S))\r
-#define SPI_CS_HOLD_DELAY_RES_V 0xFFF\r
-#define SPI_CS_HOLD_DELAY_RES_S 16\r
-\r
-#define SPI_RD_STATUS_REG(i) (REG_SPI_BASE(i) + 0x10)\r
-/* SPI_STATUS_EXT : R/W ;bitpos:[31:24] ;default: 8'h00 ; */\r
-/*description: In the slave mode,it is the status for master to read out.*/\r
-#define SPI_STATUS_EXT 0x000000FF\r
-#define SPI_STATUS_EXT_M ((SPI_STATUS_EXT_V)<<(SPI_STATUS_EXT_S))\r
-#define SPI_STATUS_EXT_V 0xFF\r
-#define SPI_STATUS_EXT_S 24\r
-/* SPI_WB_MODE : R/W ;bitpos:[23:16] ;default: 8'h00 ; */\r
-/*description: Mode bits in the flash fast read mode, it is combined with spi_fastrd_mode bit.*/\r
-#define SPI_WB_MODE 0x000000FF\r
-#define SPI_WB_MODE_M ((SPI_WB_MODE_V)<<(SPI_WB_MODE_S))\r
-#define SPI_WB_MODE_V 0xFF\r
-#define SPI_WB_MODE_S 16\r
-/* SPI_STATUS : R/W ;bitpos:[15:0] ;default: 16'b0 ; */\r
-/*description: In the slave mode, it is the status for master to read out.*/\r
-#define SPI_STATUS 0x0000FFFF\r
-#define SPI_STATUS_M ((SPI_STATUS_V)<<(SPI_STATUS_S))\r
-#define SPI_STATUS_V 0xFFFF\r
-#define SPI_STATUS_S 0\r
-\r
-#define SPI_CTRL2_REG(i) (REG_SPI_BASE(i) + 0x14)\r
-/* SPI_CS_DELAY_NUM : R/W ;bitpos:[31:28] ;default: 4'h0 ; */\r
-/*description: spi_cs signal is delayed by system clock cycles*/\r
-#define SPI_CS_DELAY_NUM 0x0000000F\r
-#define SPI_CS_DELAY_NUM_M ((SPI_CS_DELAY_NUM_V)<<(SPI_CS_DELAY_NUM_S))\r
-#define SPI_CS_DELAY_NUM_V 0xF\r
-#define SPI_CS_DELAY_NUM_S 28\r
-/* SPI_CS_DELAY_MODE : R/W ;bitpos:[27:26] ;default: 2'h0 ; */\r
-/*description: spi_cs signal is delayed by spi_clk . 0: zero 1: if spi_ck_out_edge\r
- or spi_ck_i_edge is set 1 delayed by half cycle else delayed by one cycle 2: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by one cycle else delayed by half cycle 3: delayed one cycle*/\r
-#define SPI_CS_DELAY_MODE 0x00000003\r
-#define SPI_CS_DELAY_MODE_M ((SPI_CS_DELAY_MODE_V)<<(SPI_CS_DELAY_MODE_S))\r
-#define SPI_CS_DELAY_MODE_V 0x3\r
-#define SPI_CS_DELAY_MODE_S 26\r
-/* SPI_MOSI_DELAY_NUM : R/W ;bitpos:[25:23] ;default: 3'h0 ; */\r
-/*description: MOSI signals are delayed by system clock cycles*/\r
-#define SPI_MOSI_DELAY_NUM 0x00000007\r
-#define SPI_MOSI_DELAY_NUM_M ((SPI_MOSI_DELAY_NUM_V)<<(SPI_MOSI_DELAY_NUM_S))\r
-#define SPI_MOSI_DELAY_NUM_V 0x7\r
-#define SPI_MOSI_DELAY_NUM_S 23\r
-/* SPI_MOSI_DELAY_MODE : R/W ;bitpos:[22:21] ;default: 2'h0 ; */\r
-/*description: MOSI signals are delayed by spi_clk. 0: zero 1: if spi_ck_out_edge\r
- or spi_ck_i_edge is set 1 delayed by half cycle else delayed by one cycle 2: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by one cycle else delayed by half cycle 3: delayed one cycle*/\r
-#define SPI_MOSI_DELAY_MODE 0x00000003\r
-#define SPI_MOSI_DELAY_MODE_M ((SPI_MOSI_DELAY_MODE_V)<<(SPI_MOSI_DELAY_MODE_S))\r
-#define SPI_MOSI_DELAY_MODE_V 0x3\r
-#define SPI_MOSI_DELAY_MODE_S 21\r
-/* SPI_MISO_DELAY_NUM : R/W ;bitpos:[20:18] ;default: 3'h0 ; */\r
-/*description: MISO signals are delayed by system clock cycles*/\r
-#define SPI_MISO_DELAY_NUM 0x00000007\r
-#define SPI_MISO_DELAY_NUM_M ((SPI_MISO_DELAY_NUM_V)<<(SPI_MISO_DELAY_NUM_S))\r
-#define SPI_MISO_DELAY_NUM_V 0x7\r
-#define SPI_MISO_DELAY_NUM_S 18\r
-/* SPI_MISO_DELAY_MODE : R/W ;bitpos:[17:16] ;default: 2'h0 ; */\r
-/*description: MISO signals are delayed by spi_clk. 0: zero 1: if spi_ck_out_edge\r
- or spi_ck_i_edge is set 1 delayed by half cycle else delayed by one cycle 2: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by one cycle else delayed by half cycle 3: delayed one cycle*/\r
-#define SPI_MISO_DELAY_MODE 0x00000003\r
-#define SPI_MISO_DELAY_MODE_M ((SPI_MISO_DELAY_MODE_V)<<(SPI_MISO_DELAY_MODE_S))\r
-#define SPI_MISO_DELAY_MODE_V 0x3\r
-#define SPI_MISO_DELAY_MODE_S 16\r
-/* SPI_CK_OUT_HIGH_MODE : R/W ;bitpos:[15:12] ;default: 4'h0 ; */\r
-/*description: modify spi clock duty ratio when the value is lager than 8,\r
- the bits are combined with spi_clkcnt_N bits and spi_clkcnt_H bits.*/\r
-#define SPI_CK_OUT_HIGH_MODE 0x0000000F\r
-#define SPI_CK_OUT_HIGH_MODE_M ((SPI_CK_OUT_HIGH_MODE_V)<<(SPI_CK_OUT_HIGH_MODE_S))\r
-#define SPI_CK_OUT_HIGH_MODE_V 0xF\r
-#define SPI_CK_OUT_HIGH_MODE_S 12\r
-/* SPI_CK_OUT_LOW_MODE : R/W ;bitpos:[11:8] ;default: 4'h0 ; */\r
-/*description: modify spi clock duty ratio when the value is lager than 8,\r
- the bits are combined with spi_clkcnt_N bits and spi_clkcnt_L bits.*/\r
-#define SPI_CK_OUT_LOW_MODE 0x0000000F\r
-#define SPI_CK_OUT_LOW_MODE_M ((SPI_CK_OUT_LOW_MODE_V)<<(SPI_CK_OUT_LOW_MODE_S))\r
-#define SPI_CK_OUT_LOW_MODE_V 0xF\r
-#define SPI_CK_OUT_LOW_MODE_S 8\r
-/* SPI_HOLD_TIME : R/W ;bitpos:[7:4] ;default: 4'h1 ; */\r
-/*description: delay cycles of cs pin by spi clock, this bits combined with spi_cs_hold bit.*/\r
-#define SPI_HOLD_TIME 0x0000000F\r
-#define SPI_HOLD_TIME_M ((SPI_HOLD_TIME_V)<<(SPI_HOLD_TIME_S))\r
-#define SPI_HOLD_TIME_V 0xF\r
-#define SPI_HOLD_TIME_S 4\r
-/* SPI_SETUP_TIME : R/W ;bitpos:[3:0] ;default: 4'h1 ; */\r
-/*description: (cycles-1) of ¡°prepare¡± phase by spi clock, this bits combined\r
- with spi_cs_setup bit.*/\r
-#define SPI_SETUP_TIME 0x0000000F\r
-#define SPI_SETUP_TIME_M ((SPI_SETUP_TIME_V)<<(SPI_SETUP_TIME_S))\r
-#define SPI_SETUP_TIME_V 0xF\r
-#define SPI_SETUP_TIME_S 0\r
-\r
-#define SPI_CLOCK_REG(i) (REG_SPI_BASE(i) + 0x18)\r
-/* SPI_CLK_EQU_SYSCLK : R/W ;bitpos:[31] ;default: 1'b1 ; */\r
-/*description: In the master mode 1: spi_clk is eqaul to system 0: spi_clk is\r
- divided from system clock.*/\r
-#define SPI_CLK_EQU_SYSCLK (BIT(31))\r
-#define SPI_CLK_EQU_SYSCLK_M (BIT(31))\r
-#define SPI_CLK_EQU_SYSCLK_V 0x1\r
-#define SPI_CLK_EQU_SYSCLK_S 31\r
-/* SPI_CLKDIV_PRE : R/W ;bitpos:[30:18] ;default: 13'b0 ; */\r
-/*description: In the master mode it is pre-divider of spi_clk.*/\r
-#define SPI_CLKDIV_PRE 0x00001FFF\r
-#define SPI_CLKDIV_PRE_M ((SPI_CLKDIV_PRE_V)<<(SPI_CLKDIV_PRE_S))\r
-#define SPI_CLKDIV_PRE_V 0x1FFF\r
-#define SPI_CLKDIV_PRE_S 18\r
-/* SPI_CLKCNT_N : R/W ;bitpos:[17:12] ;default: 6'h3 ; */\r
-/*description: In the master mode it is the divider of spi_clk. So spi_clk frequency\r
- is system/(spi_clkdiv_pre+1)/(spi_clkcnt_N+1)*/\r
-#define SPI_CLKCNT_N 0x0000003F\r
-#define SPI_CLKCNT_N_M ((SPI_CLKCNT_N_V)<<(SPI_CLKCNT_N_S))\r
-#define SPI_CLKCNT_N_V 0x3F\r
-#define SPI_CLKCNT_N_S 12\r
-/* SPI_CLKCNT_H : R/W ;bitpos:[11:6] ;default: 6'h1 ; */\r
-/*description: In the master mode it must be floor((spi_clkcnt_N+1)/2-1). In\r
- the slave mode it must be 0.*/\r
-#define SPI_CLKCNT_H 0x0000003F\r
-#define SPI_CLKCNT_H_M ((SPI_CLKCNT_H_V)<<(SPI_CLKCNT_H_S))\r
-#define SPI_CLKCNT_H_V 0x3F\r
-#define SPI_CLKCNT_H_S 6\r
-/* SPI_CLKCNT_L : R/W ;bitpos:[5:0] ;default: 6'h3 ; */\r
-/*description: In the master mode it must be equal to spi_clkcnt_N. In the slave\r
- mode it must be 0.*/\r
-#define SPI_CLKCNT_L 0x0000003F\r
-#define SPI_CLKCNT_L_M ((SPI_CLKCNT_L_V)<<(SPI_CLKCNT_L_S))\r
-#define SPI_CLKCNT_L_V 0x3F\r
-#define SPI_CLKCNT_L_S 0\r
-\r
-#define SPI_USER_REG(i) (REG_SPI_BASE(i) + 0x1C)\r
-/* SPI_USR_COMMAND : R/W ;bitpos:[31] ;default: 1'b1 ; */\r
-/*description: This bit enable the command phase of an operation.*/\r
-#define SPI_USR_COMMAND (BIT(31))\r
-#define SPI_USR_COMMAND_M (BIT(31))\r
-#define SPI_USR_COMMAND_V 0x1\r
-#define SPI_USR_COMMAND_S 31\r
-/* SPI_USR_ADDR : R/W ;bitpos:[30] ;default: 1'b0 ; */\r
-/*description: This bit enable the address phase of an operation.*/\r
-#define SPI_USR_ADDR (BIT(30))\r
-#define SPI_USR_ADDR_M (BIT(30))\r
-#define SPI_USR_ADDR_V 0x1\r
-#define SPI_USR_ADDR_S 30\r
-/* SPI_USR_DUMMY : R/W ;bitpos:[29] ;default: 1'b0 ; */\r
-/*description: This bit enable the dummy phase of an operation.*/\r
-#define SPI_USR_DUMMY (BIT(29))\r
-#define SPI_USR_DUMMY_M (BIT(29))\r
-#define SPI_USR_DUMMY_V 0x1\r
-#define SPI_USR_DUMMY_S 29\r
-/* SPI_USR_MISO : R/W ;bitpos:[28] ;default: 1'b0 ; */\r
-/*description: This bit enable the read-data phase of an operation.*/\r
-#define SPI_USR_MISO (BIT(28))\r
-#define SPI_USR_MISO_M (BIT(28))\r
-#define SPI_USR_MISO_V 0x1\r
-#define SPI_USR_MISO_S 28\r
-/* SPI_USR_MOSI : R/W ;bitpos:[27] ;default: 1'b0 ; */\r
-/*description: This bit enable the write-data phase of an operation.*/\r
-#define SPI_USR_MOSI (BIT(27))\r
-#define SPI_USR_MOSI_M (BIT(27))\r
-#define SPI_USR_MOSI_V 0x1\r
-#define SPI_USR_MOSI_S 27\r
-/* SPI_USR_DUMMY_IDLE : R/W ;bitpos:[26] ;default: 1'b0 ; */\r
-/*description: spi clock is disable in dummy phase when the bit is enable.*/\r
-#define SPI_USR_DUMMY_IDLE (BIT(26))\r
-#define SPI_USR_DUMMY_IDLE_M (BIT(26))\r
-#define SPI_USR_DUMMY_IDLE_V 0x1\r
-#define SPI_USR_DUMMY_IDLE_S 26\r
-/* SPI_USR_MOSI_HIGHPART : R/W ;bitpos:[25] ;default: 1'b0 ; */\r
-/*description: write-data phase only access to high-part of the buffer spi_w8~spi_w15.\r
- 1: enable 0: disable.*/\r
-#define SPI_USR_MOSI_HIGHPART (BIT(25))\r
-#define SPI_USR_MOSI_HIGHPART_M (BIT(25))\r
-#define SPI_USR_MOSI_HIGHPART_V 0x1\r
-#define SPI_USR_MOSI_HIGHPART_S 25\r
-/* SPI_USR_MISO_HIGHPART : R/W ;bitpos:[24] ;default: 1'b0 ; */\r
-/*description: read-data phase only access to high-part of the buffer spi_w8~spi_w15.\r
- 1: enable 0: disable.*/\r
-#define SPI_USR_MISO_HIGHPART (BIT(24))\r
-#define SPI_USR_MISO_HIGHPART_M (BIT(24))\r
-#define SPI_USR_MISO_HIGHPART_V 0x1\r
-#define SPI_USR_MISO_HIGHPART_S 24\r
-/* SPI_USR_PREP_HOLD : R/W ;bitpos:[23] ;default: 1'b0 ; */\r
-/*description: spi is hold at prepare state the bit combined with spi_usr_hold_pol bit.*/\r
-#define SPI_USR_PREP_HOLD (BIT(23))\r
-#define SPI_USR_PREP_HOLD_M (BIT(23))\r
-#define SPI_USR_PREP_HOLD_V 0x1\r
-#define SPI_USR_PREP_HOLD_S 23\r
-/* SPI_USR_CMD_HOLD : R/W ;bitpos:[22] ;default: 1'b0 ; */\r
-/*description: spi is hold at command state the bit combined with spi_usr_hold_pol bit.*/\r
-#define SPI_USR_CMD_HOLD (BIT(22))\r
-#define SPI_USR_CMD_HOLD_M (BIT(22))\r
-#define SPI_USR_CMD_HOLD_V 0x1\r
-#define SPI_USR_CMD_HOLD_S 22\r
-/* SPI_USR_ADDR_HOLD : R/W ;bitpos:[21] ;default: 1'b0 ; */\r
-/*description: spi is hold at address state the bit combined with spi_usr_hold_pol bit.*/\r
-#define SPI_USR_ADDR_HOLD (BIT(21))\r
-#define SPI_USR_ADDR_HOLD_M (BIT(21))\r
-#define SPI_USR_ADDR_HOLD_V 0x1\r
-#define SPI_USR_ADDR_HOLD_S 21\r
-/* SPI_USR_DUMMY_HOLD : R/W ;bitpos:[20] ;default: 1'b0 ; */\r
-/*description: spi is hold at dummy state the bit combined with spi_usr_hold_pol bit.*/\r
-#define SPI_USR_DUMMY_HOLD (BIT(20))\r
-#define SPI_USR_DUMMY_HOLD_M (BIT(20))\r
-#define SPI_USR_DUMMY_HOLD_V 0x1\r
-#define SPI_USR_DUMMY_HOLD_S 20\r
-/* SPI_USR_DIN_HOLD : R/W ;bitpos:[19] ;default: 1'b0 ; */\r
-/*description: spi is hold at data in state the bit combined with spi_usr_hold_pol bit.*/\r
-#define SPI_USR_DIN_HOLD (BIT(19))\r
-#define SPI_USR_DIN_HOLD_M (BIT(19))\r
-#define SPI_USR_DIN_HOLD_V 0x1\r
-#define SPI_USR_DIN_HOLD_S 19\r
-/* SPI_USR_DOUT_HOLD : R/W ;bitpos:[18] ;default: 1'b0 ; */\r
-/*description: spi is hold at data out state the bit combined with spi_usr_hold_pol bit.*/\r
-#define SPI_USR_DOUT_HOLD (BIT(18))\r
-#define SPI_USR_DOUT_HOLD_M (BIT(18))\r
-#define SPI_USR_DOUT_HOLD_V 0x1\r
-#define SPI_USR_DOUT_HOLD_S 18\r
-/* SPI_USR_HOLD_POL : R/W ;bitpos:[17] ;default: 1'b0 ; */\r
-/*description: It is combined with hold bits to set the polarity of spi hold\r
- line 1: spi will be held when spi hold line is high 0: spi will be held when spi hold line is low*/\r
-#define SPI_USR_HOLD_POL (BIT(17))\r
-#define SPI_USR_HOLD_POL_M (BIT(17))\r
-#define SPI_USR_HOLD_POL_V 0x1\r
-#define SPI_USR_HOLD_POL_S 17\r
-/* SPI_SIO : R/W ;bitpos:[16] ;default: 1'b0 ; */\r
-/*description: Set the bit to enable 3-line half duplex communication mosi\r
- and miso signals share the same pin. 1: enable 0: disable.*/\r
-#define SPI_SIO (BIT(16))\r
-#define SPI_SIO_M (BIT(16))\r
-#define SPI_SIO_V 0x1\r
-#define SPI_SIO_S 16\r
-/* SPI_FWRITE_QIO : R/W ;bitpos:[15] ;default: 1'b0 ; */\r
-/*description: In the write operations address phase and read-data phase apply 4 signals.*/\r
-#define SPI_FWRITE_QIO (BIT(15))\r
-#define SPI_FWRITE_QIO_M (BIT(15))\r
-#define SPI_FWRITE_QIO_V 0x1\r
-#define SPI_FWRITE_QIO_S 15\r
-/* SPI_FWRITE_DIO : R/W ;bitpos:[14] ;default: 1'b0 ; */\r
-/*description: In the write operations address phase and read-data phase apply 2 signals.*/\r
-#define SPI_FWRITE_DIO (BIT(14))\r
-#define SPI_FWRITE_DIO_M (BIT(14))\r
-#define SPI_FWRITE_DIO_V 0x1\r
-#define SPI_FWRITE_DIO_S 14\r
-/* SPI_FWRITE_QUAD : R/W ;bitpos:[13] ;default: 1'b0 ; */\r
-/*description: In the write operations read-data phase apply 4 signals*/\r
-#define SPI_FWRITE_QUAD (BIT(13))\r
-#define SPI_FWRITE_QUAD_M (BIT(13))\r
-#define SPI_FWRITE_QUAD_V 0x1\r
-#define SPI_FWRITE_QUAD_S 13\r
-/* SPI_FWRITE_DUAL : R/W ;bitpos:[12] ;default: 1'b0 ; */\r
-/*description: In the write operations read-data phase apply 2 signals*/\r
-#define SPI_FWRITE_DUAL (BIT(12))\r
-#define SPI_FWRITE_DUAL_M (BIT(12))\r
-#define SPI_FWRITE_DUAL_V 0x1\r
-#define SPI_FWRITE_DUAL_S 12\r
-/* SPI_WR_BYTE_ORDER : R/W ;bitpos:[11] ;default: 1'b0 ; */\r
-/*description: In command address write-data (MOSI) phases 1: big-endian 0: litte_endian*/\r
-#define SPI_WR_BYTE_ORDER (BIT(11))\r
-#define SPI_WR_BYTE_ORDER_M (BIT(11))\r
-#define SPI_WR_BYTE_ORDER_V 0x1\r
-#define SPI_WR_BYTE_ORDER_S 11\r
-/* SPI_RD_BYTE_ORDER : R/W ;bitpos:[10] ;default: 1'b0 ; */\r
-/*description: In read-data (MISO) phase 1: big-endian 0: little_endian*/\r
-#define SPI_RD_BYTE_ORDER (BIT(10))\r
-#define SPI_RD_BYTE_ORDER_M (BIT(10))\r
-#define SPI_RD_BYTE_ORDER_V 0x1\r
-#define SPI_RD_BYTE_ORDER_S 10\r
-/* SPI_CK_OUT_EDGE : R/W ;bitpos:[7] ;default: 1'b0 ; */\r
-/*description: the bit combined with spi_mosi_delay_mode bits to set mosi signal delay mode.*/\r
-#define SPI_CK_OUT_EDGE (BIT(7))\r
-#define SPI_CK_OUT_EDGE_M (BIT(7))\r
-#define SPI_CK_OUT_EDGE_V 0x1\r
-#define SPI_CK_OUT_EDGE_S 7\r
-/* SPI_CK_I_EDGE : R/W ;bitpos:[6] ;default: 1'b1 ; */\r
-/*description: In the slave mode the bit is same as spi_ck_out_edge in master\r
- mode. It is combined with spi_miso_delay_mode bits.*/\r
-#define SPI_CK_I_EDGE (BIT(6))\r
-#define SPI_CK_I_EDGE_M (BIT(6))\r
-#define SPI_CK_I_EDGE_V 0x1\r
-#define SPI_CK_I_EDGE_S 6\r
-/* SPI_CS_SETUP : R/W ;bitpos:[5] ;default: 1'b0 ; */\r
-/*description: spi cs is enable when spi is in ¡°prepare¡± phase. 1: enable 0: disable.*/\r
-#define SPI_CS_SETUP (BIT(5))\r
-#define SPI_CS_SETUP_M (BIT(5))\r
-#define SPI_CS_SETUP_V 0x1\r
-#define SPI_CS_SETUP_S 5\r
-/* SPI_CS_HOLD : R/W ;bitpos:[4] ;default: 1'b0 ; */\r
-/*description: spi cs keep low when spi is in ¡°done¡± phase. 1: enable 0: disable.*/\r
-#define SPI_CS_HOLD (BIT(4))\r
-#define SPI_CS_HOLD_M (BIT(4))\r
-#define SPI_CS_HOLD_V 0x1\r
-#define SPI_CS_HOLD_S 4\r
-/* SPI_DOUTDIN : R/W ;bitpos:[0] ;default: 1'b0 ; */\r
-/*description: Set the bit to enable full duplex communication. 1: enable 0: disable.*/\r
-#define SPI_DOUTDIN (BIT(0))\r
-#define SPI_DOUTDIN_M (BIT(0))\r
-#define SPI_DOUTDIN_V 0x1\r
-#define SPI_DOUTDIN_S 0\r
-\r
-#define SPI_USER1_REG(i) (REG_SPI_BASE(i) + 0x20)\r
-/* SPI_USR_ADDR_BITLEN : RO ;bitpos:[31:26] ;default: 6'd23 ; */\r
-/*description: The length in bits of address phase. The register value shall be (bit_num-1).*/\r
-#define SPI_USR_ADDR_BITLEN 0x0000003F\r
-#define SPI_USR_ADDR_BITLEN_M ((SPI_USR_ADDR_BITLEN_V)<<(SPI_USR_ADDR_BITLEN_S))\r
-#define SPI_USR_ADDR_BITLEN_V 0x3F\r
-#define SPI_USR_ADDR_BITLEN_S 26\r
-/* SPI_USR_DUMMY_CYCLELEN : R/W ;bitpos:[7:0] ;default: 8'd7 ; */\r
-/*description: The length in spi_clk cycles of dummy phase. The register value\r
- shall be (cycle_num-1).*/\r
-#define SPI_USR_DUMMY_CYCLELEN 0x000000FF\r
-#define SPI_USR_DUMMY_CYCLELEN_M ((SPI_USR_DUMMY_CYCLELEN_V)<<(SPI_USR_DUMMY_CYCLELEN_S))\r
-#define SPI_USR_DUMMY_CYCLELEN_V 0xFF\r
-#define SPI_USR_DUMMY_CYCLELEN_S 0\r
-\r
-#define SPI_USER2_REG(i) (REG_SPI_BASE(i) + 0x24)\r
-/* SPI_USR_COMMAND_BITLEN : R/W ;bitpos:[31:28] ;default: 4'd7 ; */\r
-/*description: The length in bits of command phase. The register value shall be (bit_num-1)*/\r
-#define SPI_USR_COMMAND_BITLEN 0x0000000F\r
-#define SPI_USR_COMMAND_BITLEN_M ((SPI_USR_COMMAND_BITLEN_V)<<(SPI_USR_COMMAND_BITLEN_S))\r
-#define SPI_USR_COMMAND_BITLEN_V 0xF\r
-#define SPI_USR_COMMAND_BITLEN_S 28\r
-/* SPI_USR_COMMAND_VALUE : R/W ;bitpos:[15:0] ;default: 16'b0 ; */\r
-/*description: The value of command.*/\r
-#define SPI_USR_COMMAND_VALUE 0x0000FFFF\r
-#define SPI_USR_COMMAND_VALUE_M ((SPI_USR_COMMAND_VALUE_V)<<(SPI_USR_COMMAND_VALUE_S))\r
-#define SPI_USR_COMMAND_VALUE_V 0xFFFF\r
-#define SPI_USR_COMMAND_VALUE_S 0\r
-\r
-#define SPI_MOSI_DLEN_REG(i) (REG_SPI_BASE(i) + 0x28)\r
-/* SPI_USR_MOSI_DBITLEN : R/W ;bitpos:[23:0] ;default: 24'h0 ; */\r
-/*description: The length in bits of write-data. The register value shall be (bit_num-1).*/\r
-#define SPI_USR_MOSI_DBITLEN 0x00FFFFFF\r
-#define SPI_USR_MOSI_DBITLEN_M ((SPI_USR_MOSI_DBITLEN_V)<<(SPI_USR_MOSI_DBITLEN_S))\r
-#define SPI_USR_MOSI_DBITLEN_V 0xFFFFFF\r
-#define SPI_USR_MOSI_DBITLEN_S 0\r
-\r
-#define SPI_MISO_DLEN_REG(i) (REG_SPI_BASE(i) + 0x2C)\r
-/* SPI_USR_MISO_DBITLEN : R/W ;bitpos:[23:0] ;default: 24'h0 ; */\r
-/*description: The length in bits of read-data. The register value shall be (bit_num-1).*/\r
-#define SPI_USR_MISO_DBITLEN 0x00FFFFFF\r
-#define SPI_USR_MISO_DBITLEN_M ((SPI_USR_MISO_DBITLEN_V)<<(SPI_USR_MISO_DBITLEN_S))\r
-#define SPI_USR_MISO_DBITLEN_V 0xFFFFFF\r
-#define SPI_USR_MISO_DBITLEN_S 0\r
-\r
-#define SPI_SLV_WR_STATUS_REG(i) (REG_SPI_BASE(i) + 0x30)\r
-/* SPI_SLV_WR_ST : R/W ;bitpos:[31:0] ;default: 32'b0 ; */\r
-/*description: In the slave mode this register are the status register for the\r
- master to write into. In the master mode this register are the higher 32bits in the 64 bits address condition.*/\r
-#define SPI_SLV_WR_ST 0xFFFFFFFF\r
-#define SPI_SLV_WR_ST_M ((SPI_SLV_WR_ST_V)<<(SPI_SLV_WR_ST_S))\r
-#define SPI_SLV_WR_ST_V 0xFFFFFFFF\r
-#define SPI_SLV_WR_ST_S 0\r
-\r
-#define SPI_PIN_REG(i) (REG_SPI_BASE(i) + 0x34)\r
-/* SPI_CS_KEEP_ACTIVE : R/W ;bitpos:[30] ;default: 1'b0 ; */\r
-/*description: spi cs line keep low when the bit is set.*/\r
-#define SPI_CS_KEEP_ACTIVE (BIT(30))\r
-#define SPI_CS_KEEP_ACTIVE_M (BIT(30))\r
-#define SPI_CS_KEEP_ACTIVE_V 0x1\r
-#define SPI_CS_KEEP_ACTIVE_S 30\r
-/* SPI_CK_IDLE_EDGE : R/W ;bitpos:[29] ;default: 1'b0 ; */\r
-/*description: 1: spi clk line is high when idle 0: spi clk line is low when idle*/\r
-#define SPI_CK_IDLE_EDGE (BIT(29))\r
-#define SPI_CK_IDLE_EDGE_M (BIT(29))\r
-#define SPI_CK_IDLE_EDGE_V 0x1\r
-#define SPI_CK_IDLE_EDGE_S 29\r
-/* SPI_MASTER_CK_SEL : R/W ;bitpos:[13:11] ;default: 3'b0 ; */\r
-/*description: In the master mode spi cs line is enable as spi clk it is combined\r
- with spi_cs0_dis spi_cs1_dis spi_cs2_dis.*/\r
-#define SPI_MASTER_CK_SEL 0x00000007\r
-#define SPI_MASTER_CK_SEL_M ((SPI_MASTER_CK_SEL_V)<<(SPI_MASTER_CK_SEL_S))\r
-#define SPI_MASTER_CK_SEL_V 0x07\r
-#define SPI_MASTER_CK_SEL_S 11\r
-/* SPI_MASTER_CS_POL : R/W ;bitpos:[8:6] ;default: 3'b0 ; */\r
-/*description: In the master mode the bits are the polarity of spi cs line\r
- the value is equivalent to spi_cs ^ spi_master_cs_pol.*/\r
-#define SPI_MASTER_CS_POL 0x00000007\r
-#define SPI_MASTER_CS_POL_M ((SPI_MASTER_CS_POL_V)<<(SPI_MASTER_CS_POL_S))\r
-#define SPI_MASTER_CS_POL_V 0x7\r
-#define SPI_MASTER_CS_POL_S 6\r
-/* SPI_CK_DIS : R/W ;bitpos:[5] ;default: 1'b0 ; */\r
-/*description: 1: spi clk out disable 0: spi clk out enable*/\r
-#define SPI_CK_DIS (BIT(5))\r
-#define SPI_CK_DIS_M (BIT(5))\r
-#define SPI_CK_DIS_V 0x1\r
-#define SPI_CK_DIS_S 5\r
-/* SPI_CS2_DIS : R/W ;bitpos:[2] ;default: 1'b1 ; */\r
-/*description: SPI CS2 pin enable, 1: disable CS2, 0: spi_cs2 signal is from/to CS2 pin*/\r
-#define SPI_CS2_DIS (BIT(2))\r
-#define SPI_CS2_DIS_M (BIT(2))\r
-#define SPI_CS2_DIS_V 0x1\r
-#define SPI_CS2_DIS_S 2\r
-/* SPI_CS1_DIS : R/W ;bitpos:[1] ;default: 1'b1 ; */\r
-/*description: SPI CS1 pin enable, 1: disable CS1, 0: spi_cs1 signal is from/to CS1 pin*/\r
-#define SPI_CS1_DIS (BIT(1))\r
-#define SPI_CS1_DIS_M (BIT(1))\r
-#define SPI_CS1_DIS_V 0x1\r
-#define SPI_CS1_DIS_S 1\r
-/* SPI_CS0_DIS : R/W ;bitpos:[0] ;default: 1'b0 ; */\r
-/*description: SPI CS0 pin enable, 1: disable CS0, 0: spi_cs0 signal is from/to CS0 pin*/\r
-#define SPI_CS0_DIS (BIT(0))\r
-#define SPI_CS0_DIS_M (BIT(0))\r
-#define SPI_CS0_DIS_V 0x1\r
-#define SPI_CS0_DIS_S 0\r
-\r
-#define SPI_SLAVE_REG(i) (REG_SPI_BASE(i) + 0x38)\r
-/* SPI_SYNC_RESET : R/W ;bitpos:[31] ;default: 1'b0 ; */\r
-/*description: Software reset enable, reset the spi clock line cs line and data lines.*/\r
-#define SPI_SYNC_RESET (BIT(31))\r
-#define SPI_SYNC_RESET_M (BIT(31))\r
-#define SPI_SYNC_RESET_V 0x1\r
-#define SPI_SYNC_RESET_S 31\r
-/* SPI_SLAVE_MODE : R/W ;bitpos:[30] ;default: 1'b0 ; */\r
-/*description: 1: slave mode 0: master mode.*/\r
-#define SPI_SLAVE_MODE (BIT(30))\r
-#define SPI_SLAVE_MODE_M (BIT(30))\r
-#define SPI_SLAVE_MODE_V 0x1\r
-#define SPI_SLAVE_MODE_S 30\r
-/* SPI_SLV_WR_RD_BUF_EN : R/W ;bitpos:[29] ;default: 1'b0 ; */\r
-/*description: write and read buffer enable in the slave mode*/\r
-#define SPI_SLV_WR_RD_BUF_EN (BIT(29))\r
-#define SPI_SLV_WR_RD_BUF_EN_M (BIT(29))\r
-#define SPI_SLV_WR_RD_BUF_EN_V 0x1\r
-#define SPI_SLV_WR_RD_BUF_EN_S 29\r
-/* SPI_SLV_WR_RD_STA_EN : R/W ;bitpos:[28] ;default: 1'b0 ; */\r
-/*description: write and read status enable in the slave mode*/\r
-#define SPI_SLV_WR_RD_STA_EN (BIT(28))\r
-#define SPI_SLV_WR_RD_STA_EN_M (BIT(28))\r
-#define SPI_SLV_WR_RD_STA_EN_V 0x1\r
-#define SPI_SLV_WR_RD_STA_EN_S 28\r
-/* SPI_SLV_CMD_DEFINE : R/W ;bitpos:[27] ;default: 1'b0 ; */\r
-/*description: 1: slave mode commands are defined in SPI_SLAVE3. 0: slave mode\r
- commands are fixed as: 1: write-status 2: write-buffer and 3: read-buffer.*/\r
-#define SPI_SLV_CMD_DEFINE (BIT(27))\r
-#define SPI_SLV_CMD_DEFINE_M (BIT(27))\r
-#define SPI_SLV_CMD_DEFINE_V 0x1\r
-#define SPI_SLV_CMD_DEFINE_S 27\r
-/* SPI_TRANS_CNT : RO ;bitpos:[26:23] ;default: 4'b0 ; */\r
-/*description: The operations counter in both the master mode and the slave\r
- mode. 4: read-status*/\r
-#define SPI_TRANS_CNT 0x0000000F\r
-#define SPI_TRANS_CNT_M ((SPI_TRANS_CNT_V)<<(SPI_TRANS_CNT_S))\r
-#define SPI_TRANS_CNT_V 0xF\r
-#define SPI_TRANS_CNT_S 23\r
-/* SPI_SLV_LAST_STATE : RO ;bitpos:[22:20] ;default: 3'b0 ; */\r
-/*description: In the slave mode it is the state of spi state machine.*/\r
-#define SPI_SLV_LAST_STATE 0x00000007\r
-#define SPI_SLV_LAST_STATE_M ((SPI_SLV_LAST_STATE_V)<<(SPI_SLV_LAST_STATE_S))\r
-#define SPI_SLV_LAST_STATE_V 0x7\r
-#define SPI_SLV_LAST_STATE_S 20\r
-/* SPI_SLV_LAST_COMMAND : RO ;bitpos:[19:17] ;default: 3'b0 ; */\r
-/*description: In the slave mode it is the value of command.*/\r
-#define SPI_SLV_LAST_COMMAND 0x00000007\r
-#define SPI_SLV_LAST_COMMAND_M ((SPI_SLV_LAST_COMMAND_V)<<(SPI_SLV_LAST_COMMAND_S))\r
-#define SPI_SLV_LAST_COMMAND_V 0x7\r
-#define SPI_SLV_LAST_COMMAND_S 17\r
-/* SPI_CS_I_MODE : R/W ;bitpos:[11:10] ;default: 2'b0 ; */\r
-/*description: In the slave mode this bits used to synchronize the input spi\r
- cs signal and eliminate spi cs jitter.*/\r
-#define SPI_CS_I_MODE 0x00000003\r
-#define SPI_CS_I_MODE_M ((SPI_CS_I_MODE_V)<<(SPI_CS_I_MODE_S))\r
-#define SPI_CS_I_MODE_V 0x3\r
-#define SPI_CS_I_MODE_S 10\r
-/* SPI_INT_EN : R/W ;bitpos:[9:5] ;default: 5'b1_0000 ; */\r
-/*description: Interrupt enable bits for the below 5 sources*/\r
-#define SPI_INT_EN 0x0000001F\r
-#define SPI_INT_EN_M ((SPI_INT_EN_V)<<(SPI_INT_EN_S))\r
-#define SPI_INT_EN_V 0x1F\r
-#define SPI_INT_EN_S 5\r
-/* SPI_TRANS_DONE : R/W ;bitpos:[4] ;default: 1'b0 ; */\r
-/*description: The interrupt raw bit for the completion of any operation in\r
- both the master mode and the slave mode.*/\r
-#define SPI_TRANS_DONE (BIT(4))\r
-#define SPI_TRANS_DONE_M (BIT(4))\r
-#define SPI_TRANS_DONE_V 0x1\r
-#define SPI_TRANS_DONE_S 4\r
-/* SPI_SLV_WR_STA_DONE : R/W ;bitpos:[3] ;default: 1'b0 ; */\r
-/*description: The interrupt raw bit for the completion of write-status operation\r
- in the slave mode.*/\r
-#define SPI_SLV_WR_STA_DONE (BIT(3))\r
-#define SPI_SLV_WR_STA_DONE_M (BIT(3))\r
-#define SPI_SLV_WR_STA_DONE_V 0x1\r
-#define SPI_SLV_WR_STA_DONE_S 3\r
-/* SPI_SLV_RD_STA_DONE : R/W ;bitpos:[2] ;default: 1'b0 ; */\r
-/*description: The interrupt raw bit for the completion of read-status operation\r
- in the slave mode.*/\r
-#define SPI_SLV_RD_STA_DONE (BIT(2))\r
-#define SPI_SLV_RD_STA_DONE_M (BIT(2))\r
-#define SPI_SLV_RD_STA_DONE_V 0x1\r
-#define SPI_SLV_RD_STA_DONE_S 2\r
-/* SPI_SLV_WR_BUF_DONE : R/W ;bitpos:[1] ;default: 1'b0 ; */\r
-/*description: The interrupt raw bit for the completion of write-buffer operation\r
- in the slave mode.*/\r
-#define SPI_SLV_WR_BUF_DONE (BIT(1))\r
-#define SPI_SLV_WR_BUF_DONE_M (BIT(1))\r
-#define SPI_SLV_WR_BUF_DONE_V 0x1\r
-#define SPI_SLV_WR_BUF_DONE_S 1\r
-/* SPI_SLV_RD_BUF_DONE : R/W ;bitpos:[0] ;default: 1'b0 ; */\r
-/*description: The interrupt raw bit for the completion of read-buffer operation\r
- in the slave mode.*/\r
-#define SPI_SLV_RD_BUF_DONE (BIT(0))\r
-#define SPI_SLV_RD_BUF_DONE_M (BIT(0))\r
-#define SPI_SLV_RD_BUF_DONE_V 0x1\r
-#define SPI_SLV_RD_BUF_DONE_S 0\r
-\r
-#define SPI_SLAVE1_REG(i) (REG_SPI_BASE(i) + 0x3C)\r
-/* SPI_SLV_STATUS_BITLEN : R/W ;bitpos:[31:27] ;default: 5'b0 ; */\r
-/*description: In the slave mode it is the length of status bit.*/\r
-#define SPI_SLV_STATUS_BITLEN 0x0000001F\r
-#define SPI_SLV_STATUS_BITLEN_M ((SPI_SLV_STATUS_BITLEN_V)<<(SPI_SLV_STATUS_BITLEN_S))\r
-#define SPI_SLV_STATUS_BITLEN_V 0x1F\r
-#define SPI_SLV_STATUS_BITLEN_S 27\r
-/* SPI_SLV_STATUS_FAST_EN : R/W ;bitpos:[26] ;default: 1'b0 ; */\r
-/*description: In the slave mode enable fast read status.*/\r
-#define SPI_SLV_STATUS_FAST_EN (BIT(26))\r
-#define SPI_SLV_STATUS_FAST_EN_M (BIT(26))\r
-#define SPI_SLV_STATUS_FAST_EN_V 0x1\r
-#define SPI_SLV_STATUS_FAST_EN_S 26\r
-/* SPI_SLV_STATUS_READBACK : R/W ;bitpos:[25] ;default: 1'b1 ; */\r
-/*description: In the slave mode 1:read register of SPI_SLV_WR_STATUS 0: read\r
- register of SPI_RD_STATUS.*/\r
-#define SPI_SLV_STATUS_READBACK (BIT(25))\r
-#define SPI_SLV_STATUS_READBACK_M (BIT(25))\r
-#define SPI_SLV_STATUS_READBACK_V 0x1\r
-#define SPI_SLV_STATUS_READBACK_S 25\r
-/* SPI_SLV_RD_ADDR_BITLEN : R/W ;bitpos:[15:10] ;default: 6'h0 ; */\r
-/*description: In the slave mode it is the address length in bits for read-buffer\r
- operation. The register value shall be (bit_num-1).*/\r
-#define SPI_SLV_RD_ADDR_BITLEN 0x0000003F\r
-#define SPI_SLV_RD_ADDR_BITLEN_M ((SPI_SLV_RD_ADDR_BITLEN_V)<<(SPI_SLV_RD_ADDR_BITLEN_S))\r
-#define SPI_SLV_RD_ADDR_BITLEN_V 0x3F\r
-#define SPI_SLV_RD_ADDR_BITLEN_S 10\r
-/* SPI_SLV_WR_ADDR_BITLEN : R/W ;bitpos:[9:4] ;default: 6'h0 ; */\r
-/*description: In the slave mode it is the address length in bits for write-buffer\r
- operation. The register value shall be (bit_num-1).*/\r
-#define SPI_SLV_WR_ADDR_BITLEN 0x0000003F\r
-#define SPI_SLV_WR_ADDR_BITLEN_M ((SPI_SLV_WR_ADDR_BITLEN_V)<<(SPI_SLV_WR_ADDR_BITLEN_S))\r
-#define SPI_SLV_WR_ADDR_BITLEN_V 0x3F\r
-#define SPI_SLV_WR_ADDR_BITLEN_S 4\r
-/* SPI_SLV_WRSTA_DUMMY_EN : R/W ;bitpos:[3] ;default: 1'b0 ; */\r
-/*description: In the slave mode it is the enable bit of dummy phase for write-status\r
- operations.*/\r
-#define SPI_SLV_WRSTA_DUMMY_EN (BIT(3))\r
-#define SPI_SLV_WRSTA_DUMMY_EN_M (BIT(3))\r
-#define SPI_SLV_WRSTA_DUMMY_EN_V 0x1\r
-#define SPI_SLV_WRSTA_DUMMY_EN_S 3\r
-/* SPI_SLV_RDSTA_DUMMY_EN : R/W ;bitpos:[2] ;default: 1'b0 ; */\r
-/*description: In the slave mode it is the enable bit of dummy phase for read-status\r
- operations.*/\r
-#define SPI_SLV_RDSTA_DUMMY_EN (BIT(2))\r
-#define SPI_SLV_RDSTA_DUMMY_EN_M (BIT(2))\r
-#define SPI_SLV_RDSTA_DUMMY_EN_V 0x1\r
-#define SPI_SLV_RDSTA_DUMMY_EN_S 2\r
-/* SPI_SLV_WRBUF_DUMMY_EN : R/W ;bitpos:[1] ;default: 1'b0 ; */\r
-/*description: In the slave mode it is the enable bit of dummy phase for write-buffer\r
- operations.*/\r
-#define SPI_SLV_WRBUF_DUMMY_EN (BIT(1))\r
-#define SPI_SLV_WRBUF_DUMMY_EN_M (BIT(1))\r
-#define SPI_SLV_WRBUF_DUMMY_EN_V 0x1\r
-#define SPI_SLV_WRBUF_DUMMY_EN_S 1\r
-/* SPI_SLV_RDBUF_DUMMY_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */\r
-/*description: In the slave mode it is the enable bit of dummy phase for read-buffer\r
- operations.*/\r
-#define SPI_SLV_RDBUF_DUMMY_EN (BIT(0))\r
-#define SPI_SLV_RDBUF_DUMMY_EN_M (BIT(0))\r
-#define SPI_SLV_RDBUF_DUMMY_EN_V 0x1\r
-#define SPI_SLV_RDBUF_DUMMY_EN_S 0\r
-\r
-#define SPI_SLAVE2_REG(i) (REG_SPI_BASE(i) + 0x40)\r
-/* SPI_SLV_WRBUF_DUMMY_CYCLELEN : R/W ;bitpos:[31:24] ;default: 8'b0 ; */\r
-/*description: In the slave mode it is the length in spi_clk cycles of dummy\r
- phase for write-buffer operations. The register value shall be (cycle_num-1).*/\r
-#define SPI_SLV_WRBUF_DUMMY_CYCLELEN 0x000000FF\r
-#define SPI_SLV_WRBUF_DUMMY_CYCLELEN_M ((SPI_SLV_WRBUF_DUMMY_CYCLELEN_V)<<(SPI_SLV_WRBUF_DUMMY_CYCLELEN_S))\r
-#define SPI_SLV_WRBUF_DUMMY_CYCLELEN_V 0xFF\r
-#define SPI_SLV_WRBUF_DUMMY_CYCLELEN_S 24\r
-/* SPI_SLV_RDBUF_DUMMY_CYCLELEN : R/W ;bitpos:[23:16] ;default: 8'h0 ; */\r
-/*description: In the slave mode it is the length in spi_clk cycles of dummy\r
- phase for read-buffer operations. The register value shall be (cycle_num-1).*/\r
-#define SPI_SLV_RDBUF_DUMMY_CYCLELEN 0x000000FF\r
-#define SPI_SLV_RDBUF_DUMMY_CYCLELEN_M ((SPI_SLV_RDBUF_DUMMY_CYCLELEN_V)<<(SPI_SLV_RDBUF_DUMMY_CYCLELEN_S))\r
-#define SPI_SLV_RDBUF_DUMMY_CYCLELEN_V 0xFF\r
-#define SPI_SLV_RDBUF_DUMMY_CYCLELEN_S 16\r
-/* SPI_SLV_WRSTA_DUMMY_CYCLELEN : R/W ;bitpos:[15:8] ;default: 8'h0 ; */\r
-/*description: In the slave mode it is the length in spi_clk cycles of dummy\r
- phase for write-status operations. The register value shall be (cycle_num-1).*/\r
-#define SPI_SLV_WRSTA_DUMMY_CYCLELEN 0x000000FF\r
-#define SPI_SLV_WRSTA_DUMMY_CYCLELEN_M ((SPI_SLV_WRSTA_DUMMY_CYCLELEN_V)<<(SPI_SLV_WRSTA_DUMMY_CYCLELEN_S))\r
-#define SPI_SLV_WRSTA_DUMMY_CYCLELEN_V 0xFF\r
-#define SPI_SLV_WRSTA_DUMMY_CYCLELEN_S 8\r
-/* SPI_SLV_RDSTA_DUMMY_CYCLELEN : R/W ;bitpos:[7:0] ;default: 8'h0 ; */\r
-/*description: In the slave mode it is the length in spi_clk cycles of dummy\r
- phase for read-status operations. The register value shall be (cycle_num-1).*/\r
-#define SPI_SLV_RDSTA_DUMMY_CYCLELEN 0x000000FF\r
-#define SPI_SLV_RDSTA_DUMMY_CYCLELEN_M ((SPI_SLV_RDSTA_DUMMY_CYCLELEN_V)<<(SPI_SLV_RDSTA_DUMMY_CYCLELEN_S))\r
-#define SPI_SLV_RDSTA_DUMMY_CYCLELEN_V 0xFF\r
-#define SPI_SLV_RDSTA_DUMMY_CYCLELEN_S 0\r
-\r
-#define SPI_SLAVE3_REG(i) (REG_SPI_BASE(i) + 0x44)\r
-/* SPI_SLV_WRSTA_CMD_VALUE : R/W ;bitpos:[31:24] ;default: 8'b0 ; */\r
-/*description: In the slave mode it is the value of write-status command.*/\r
-#define SPI_SLV_WRSTA_CMD_VALUE 0x000000FF\r
-#define SPI_SLV_WRSTA_CMD_VALUE_M ((SPI_SLV_WRSTA_CMD_VALUE_V)<<(SPI_SLV_WRSTA_CMD_VALUE_S))\r
-#define SPI_SLV_WRSTA_CMD_VALUE_V 0xFF\r
-#define SPI_SLV_WRSTA_CMD_VALUE_S 24\r
-/* SPI_SLV_RDSTA_CMD_VALUE : R/W ;bitpos:[23:16] ;default: 8'b0 ; */\r
-/*description: In the slave mode it is the value of read-status command.*/\r
-#define SPI_SLV_RDSTA_CMD_VALUE 0x000000FF\r
-#define SPI_SLV_RDSTA_CMD_VALUE_M ((SPI_SLV_RDSTA_CMD_VALUE_V)<<(SPI_SLV_RDSTA_CMD_VALUE_S))\r
-#define SPI_SLV_RDSTA_CMD_VALUE_V 0xFF\r
-#define SPI_SLV_RDSTA_CMD_VALUE_S 16\r
-/* SPI_SLV_WRBUF_CMD_VALUE : R/W ;bitpos:[15:8] ;default: 8'b0 ; */\r
-/*description: In the slave mode it is the value of write-buffer command.*/\r
-#define SPI_SLV_WRBUF_CMD_VALUE 0x000000FF\r
-#define SPI_SLV_WRBUF_CMD_VALUE_M ((SPI_SLV_WRBUF_CMD_VALUE_V)<<(SPI_SLV_WRBUF_CMD_VALUE_S))\r
-#define SPI_SLV_WRBUF_CMD_VALUE_V 0xFF\r
-#define SPI_SLV_WRBUF_CMD_VALUE_S 8\r
-/* SPI_SLV_RDBUF_CMD_VALUE : R/W ;bitpos:[7:0] ;default: 8'b0 ; */\r
-/*description: In the slave mode it is the value of read-buffer command.*/\r
-#define SPI_SLV_RDBUF_CMD_VALUE 0x000000FF\r
-#define SPI_SLV_RDBUF_CMD_VALUE_M ((SPI_SLV_RDBUF_CMD_VALUE_V)<<(SPI_SLV_RDBUF_CMD_VALUE_S))\r
-#define SPI_SLV_RDBUF_CMD_VALUE_V 0xFF\r
-#define SPI_SLV_RDBUF_CMD_VALUE_S 0\r
-\r
-#define SPI_SLV_WRBUF_DLEN_REG(i) (REG_SPI_BASE(i) + 0x48)\r
-/* SPI_SLV_WRBUF_DBITLEN : R/W ;bitpos:[23:0] ;default: 24'h0 ; */\r
-/*description: In the slave mode it is the length in bits for write-buffer operations.\r
- The register value shall be (bit_num-1).*/\r
-#define SPI_SLV_WRBUF_DBITLEN 0x00FFFFFF\r
-#define SPI_SLV_WRBUF_DBITLEN_M ((SPI_SLV_WRBUF_DBITLEN_V)<<(SPI_SLV_WRBUF_DBITLEN_S))\r
-#define SPI_SLV_WRBUF_DBITLEN_V 0xFFFFFF\r
-#define SPI_SLV_WRBUF_DBITLEN_S 0\r
-\r
-#define SPI_SLV_RDBUF_DLEN_REG(i) (REG_SPI_BASE(i) + 0x4C)\r
-/* SPI_SLV_RDBUF_DBITLEN : R/W ;bitpos:[23:0] ;default: 24'h0 ; */\r
-/*description: In the slave mode it is the length in bits for read-buffer operations.\r
- The register value shall be (bit_num-1).*/\r
-#define SPI_SLV_RDBUF_DBITLEN 0x00FFFFFF\r
-#define SPI_SLV_RDBUF_DBITLEN_M ((SPI_SLV_RDBUF_DBITLEN_V)<<(SPI_SLV_RDBUF_DBITLEN_S))\r
-#define SPI_SLV_RDBUF_DBITLEN_V 0xFFFFFF\r
-#define SPI_SLV_RDBUF_DBITLEN_S 0\r
-\r
-#define SPI_CACHE_FCTRL_REG(i) (REG_SPI_BASE(i) + 0x50)\r
-/* SPI_CACHE_FLASH_PES_EN : R/W ;bitpos:[3] ;default: 1'b0 ; */\r
-/*description: For SPI0 spi1 send suspend command before cache read flash \r
- 1: enable 0:disable.*/\r
-#define SPI_CACHE_FLASH_PES_EN (BIT(3))\r
-#define SPI_CACHE_FLASH_PES_EN_M (BIT(3))\r
-#define SPI_CACHE_FLASH_PES_EN_V 0x1\r
-#define SPI_CACHE_FLASH_PES_EN_S 3\r
-/* SPI_CACHE_FLASH_USR_CMD : R/W ;bitpos:[2] ;default: 1'b0 ; */\r
-/*description: For SPI0 cache read flash for user define command 1: enable 0:disable.*/\r
-#define SPI_CACHE_FLASH_USR_CMD (BIT(2))\r
-#define SPI_CACHE_FLASH_USR_CMD_M (BIT(2))\r
-#define SPI_CACHE_FLASH_USR_CMD_V 0x1\r
-#define SPI_CACHE_FLASH_USR_CMD_S 2\r
-/* SPI_CACHE_USR_CMD_4BYTE : R/W ;bitpos:[1] ;default: 1'b0 ; */\r
-/*description: For SPI0 cache read flash with 4 bytes command 1: enable 0:disable.*/\r
-#define SPI_CACHE_USR_CMD_4BYTE (BIT(1))\r
-#define SPI_CACHE_USR_CMD_4BYTE_M (BIT(1))\r
-#define SPI_CACHE_USR_CMD_4BYTE_V 0x1\r
-#define SPI_CACHE_USR_CMD_4BYTE_S 1\r
-/* SPI_CACHE_REQ_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */\r
-/*description: For SPI0 Cache access enable 1: enable 0:disable.*/\r
-#define SPI_CACHE_REQ_EN (BIT(0))\r
-#define SPI_CACHE_REQ_EN_M (BIT(0))\r
-#define SPI_CACHE_REQ_EN_V 0x1\r
-#define SPI_CACHE_REQ_EN_S 0\r
-\r
-#define SPI_CACHE_SCTRL_REG(i) (REG_SPI_BASE(i) + 0x54)\r
-/* SPI_CACHE_SRAM_USR_WCMD : R/W ;bitpos:[28] ;default: 1'b1 ; */\r
-/*description: For SPI0 In the spi sram mode cache write sram for user define command*/\r
-#define SPI_CACHE_SRAM_USR_WCMD (BIT(28))\r
-#define SPI_CACHE_SRAM_USR_WCMD_M (BIT(28))\r
-#define SPI_CACHE_SRAM_USR_WCMD_V 0x1\r
-#define SPI_CACHE_SRAM_USR_WCMD_S 28\r
-/* SPI_SRAM_ADDR_BITLEN : R/W ;bitpos:[27:22] ;default: 6'd23 ; */\r
-/*description: For SPI0 In the sram mode it is the length in bits of address\r
- phase. The register value shall be (bit_num-1).*/\r
-#define SPI_SRAM_ADDR_BITLEN 0x0000003F\r
-#define SPI_SRAM_ADDR_BITLEN_M ((SPI_SRAM_ADDR_BITLEN_V)<<(SPI_SRAM_ADDR_BITLEN_S))\r
-#define SPI_SRAM_ADDR_BITLEN_V 0x3F\r
-#define SPI_SRAM_ADDR_BITLEN_S 22\r
-/* SPI_SRAM_DUMMY_CYCLELEN : R/W ;bitpos:[21:14] ;default: 8'b1 ; */\r
-/*description: For SPI0 In the sram mode it is the length in bits of address\r
- phase. The register value shall be (bit_num-1).*/\r
-#define SPI_SRAM_DUMMY_CYCLELEN 0x000000FF\r
-#define SPI_SRAM_DUMMY_CYCLELEN_M ((SPI_SRAM_DUMMY_CYCLELEN_V)<<(SPI_SRAM_DUMMY_CYCLELEN_S))\r
-#define SPI_SRAM_DUMMY_CYCLELEN_V 0xFF\r
-#define SPI_SRAM_DUMMY_CYCLELEN_S 14\r
-/* SPI_SRAM_BYTES_LEN : R/W ;bitpos:[13:6] ;default: 8'b32 ; */\r
-/*description: For SPI0 In the sram mode it is the byte length of spi read sram data.*/\r
-#define SPI_SRAM_BYTES_LEN 0x000000FF\r
-#define SPI_SRAM_BYTES_LEN_M ((SPI_SRAM_BYTES_LEN_V)<<(SPI_SRAM_BYTES_LEN_S))\r
-#define SPI_SRAM_BYTES_LEN_V 0xFF\r
-#define SPI_SRAM_BYTES_LEN_S 6\r
-/* SPI_CACHE_SRAM_USR_RCMD : R/W ;bitpos:[5] ;default: 1'b1 ; */\r
-/*description: For SPI0 In the spi sram mode cache read sram for user define command.*/\r
-#define SPI_CACHE_SRAM_USR_RCMD (BIT(5))\r
-#define SPI_CACHE_SRAM_USR_RCMD_M (BIT(5))\r
-#define SPI_CACHE_SRAM_USR_RCMD_V 0x1\r
-#define SPI_CACHE_SRAM_USR_RCMD_S 5\r
-/* SPI_USR_RD_SRAM_DUMMY : R/W ;bitpos:[4] ;default: 1'b1 ; */\r
-/*description: For SPI0 In the spi sram mode it is the enable bit of dummy\r
- phase for read operations.*/\r
-#define SPI_USR_RD_SRAM_DUMMY (BIT(4))\r
-#define SPI_USR_RD_SRAM_DUMMY_M (BIT(4))\r
-#define SPI_USR_RD_SRAM_DUMMY_V 0x1\r
-#define SPI_USR_RD_SRAM_DUMMY_S 4\r
-/* SPI_USR_WR_SRAM_DUMMY : R/W ;bitpos:[3] ;default: 1'b0 ; */\r
-/*description: For SPI0 In the spi sram mode it is the enable bit of dummy\r
- phase for write operations.*/\r
-#define SPI_USR_WR_SRAM_DUMMY (BIT(3))\r
-#define SPI_USR_WR_SRAM_DUMMY_M (BIT(3))\r
-#define SPI_USR_WR_SRAM_DUMMY_V 0x1\r
-#define SPI_USR_WR_SRAM_DUMMY_S 3\r
-/* SPI_USR_SRAM_QIO : R/W ;bitpos:[2] ;default: 1'b0 ; */\r
-/*description: For SPI0 In the spi sram mode spi quad I/O mode enable 1: enable 0:disable*/\r
-#define SPI_USR_SRAM_QIO (BIT(2))\r
-#define SPI_USR_SRAM_QIO_M (BIT(2))\r
-#define SPI_USR_SRAM_QIO_V 0x1\r
-#define SPI_USR_SRAM_QIO_S 2\r
-/* SPI_USR_SRAM_DIO : R/W ;bitpos:[1] ;default: 1'b0 ; */\r
-/*description: For SPI0 In the spi sram mode spi dual I/O mode enable 1: enable 0:disable*/\r
-#define SPI_USR_SRAM_DIO (BIT(1))\r
-#define SPI_USR_SRAM_DIO_M (BIT(1))\r
-#define SPI_USR_SRAM_DIO_V 0x1\r
-#define SPI_USR_SRAM_DIO_S 1\r
-\r
-#define SPI_SRAM_CMD_REG(i) (REG_SPI_BASE(i) + 0x58)\r
-/* SPI_SRAM_RSTIO : R/W ;bitpos:[4] ;default: 1'b0 ; */\r
-/*description: For SPI0 SRAM IO mode reset enable. SRAM IO mode reset operation\r
- will be triggered when the bit is set. The bit will be cleared once the operation done*/\r
-#define SPI_SRAM_RSTIO (BIT(4))\r
-#define SPI_SRAM_RSTIO_M (BIT(4))\r
-#define SPI_SRAM_RSTIO_V 0x1\r
-#define SPI_SRAM_RSTIO_S 4\r
-/* SPI_SRAM_QIO : R/W ;bitpos:[1] ;default: 1'b0 ; */\r
-/*description: For SPI0 SRAM QIO mode enable . SRAM QIO enable command will\r
- be send when the bit is set. The bit will be cleared once the operation done.*/\r
-#define SPI_SRAM_QIO (BIT(1))\r
-#define SPI_SRAM_QIO_M (BIT(1))\r
-#define SPI_SRAM_QIO_V 0x1\r
-#define SPI_SRAM_QIO_S 1\r
-/* SPI_SRAM_DIO : R/W ;bitpos:[0] ;default: 1'b0 ; */\r
-/*description: For SPI0 SRAM DIO mode enable . SRAM DIO enable command will\r
- be send when the bit is set. The bit will be cleared once the operation done.*/\r
-#define SPI_SRAM_DIO (BIT(0))\r
-#define SPI_SRAM_DIO_M (BIT(0))\r
-#define SPI_SRAM_DIO_V 0x1\r
-#define SPI_SRAM_DIO_S 0\r
-\r
-#define SPI_SRAM_DRD_CMD_REG(i) (REG_SPI_BASE(i) + 0x5C)\r
-/* SPI_CACHE_SRAM_USR_RD_CMD_BITLEN : R/W ;bitpos:[31:28] ;default: 4'h0 ; */\r
-/*description: For SPI0 When cache mode is enable it is the length in bits of\r
- command phase for SRAM. The register value shall be (bit_num-1).*/\r
-#define SPI_CACHE_SRAM_USR_RD_CMD_BITLEN 0x0000000F\r
-#define SPI_CACHE_SRAM_USR_RD_CMD_BITLEN_M ((SPI_CACHE_SRAM_USR_RD_CMD_BITLEN_V)<<(SPI_CACHE_SRAM_USR_RD_CMD_BITLEN_S))\r
-#define SPI_CACHE_SRAM_USR_RD_CMD_BITLEN_V 0xF\r
-#define SPI_CACHE_SRAM_USR_RD_CMD_BITLEN_S 28\r
-/* SPI_CACHE_SRAM_USR_RD_CMD_VALUE : R/W ;bitpos:[15:0] ;default: 16'h0 ; */\r
-/*description: For SPI0 When cache mode is enable it is the read command value\r
- of command phase for SRAM.*/\r
-#define SPI_CACHE_SRAM_USR_RD_CMD_VALUE 0x0000FFFF\r
-#define SPI_CACHE_SRAM_USR_RD_CMD_VALUE_M ((SPI_CACHE_SRAM_USR_RD_CMD_VALUE_V)<<(SPI_CACHE_SRAM_USR_RD_CMD_VALUE_S))\r
-#define SPI_CACHE_SRAM_USR_RD_CMD_VALUE_V 0xFFFF\r
-#define SPI_CACHE_SRAM_USR_RD_CMD_VALUE_S 0\r
-\r
-#define SPI_SRAM_DWR_CMD_REG(i) (REG_SPI_BASE(i) + 0x60)\r
-/* SPI_CACHE_SRAM_USR_WR_CMD_BITLEN : R/W ;bitpos:[31:28] ;default: 4'h0 ; */\r
-/*description: For SPI0 When cache mode is enable it is the in bits of command\r
- phase for SRAM. The register value shall be (bit_num-1).*/\r
-#define SPI_CACHE_SRAM_USR_WR_CMD_BITLEN 0x0000000F\r
-#define SPI_CACHE_SRAM_USR_WR_CMD_BITLEN_M ((SPI_CACHE_SRAM_USR_WR_CMD_BITLEN_V)<<(SPI_CACHE_SRAM_USR_WR_CMD_BITLEN_S))\r
-#define SPI_CACHE_SRAM_USR_WR_CMD_BITLEN_V 0xF\r
-#define SPI_CACHE_SRAM_USR_WR_CMD_BITLEN_S 28\r
-/* SPI_CACHE_SRAM_USR_WR_CMD_VALUE : R/W ;bitpos:[15:0] ;default: 16'h0 ; */\r
-/*description: For SPI0 When cache mode is enable it is the write command value\r
- of command phase for SRAM.*/\r
-#define SPI_CACHE_SRAM_USR_WR_CMD_VALUE 0x0000FFFF\r
-#define SPI_CACHE_SRAM_USR_WR_CMD_VALUE_M ((SPI_CACHE_SRAM_USR_WR_CMD_VALUE_V)<<(SPI_CACHE_SRAM_USR_WR_CMD_VALUE_S))\r
-#define SPI_CACHE_SRAM_USR_WR_CMD_VALUE_V 0xFFFF\r
-#define SPI_CACHE_SRAM_USR_WR_CMD_VALUE_S 0\r
-\r
-#define SPI_SLV_RD_BIT_REG(i) (REG_SPI_BASE(i) + 0x64)\r
-/* SPI_SLV_RDATA_BIT : RW ;bitpos:[23:0] ;default: 24'b0 ; */\r
-/*description: In the slave mode it is the bit length of read data. The value\r
- is the length - 1.*/\r
-#define SPI_SLV_RDATA_BIT 0x00FFFFFF\r
-#define SPI_SLV_RDATA_BIT_M ((SPI_SLV_RDATA_BIT_V)<<(SPI_SLV_RDATA_BIT_S))\r
-#define SPI_SLV_RDATA_BIT_V 0xFFFFFF\r
-#define SPI_SLV_RDATA_BIT_S 0\r
-\r
-#define SPI_W0_REG(i) (REG_SPI_BASE(i) + 0x80)\r
-/* SPI_BUF0 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */\r
-/*description: data buffer*/\r
-#define SPI_BUF0 0xFFFFFFFF\r
-#define SPI_BUF0_M ((SPI_BUF0_V)<<(SPI_BUF0_S))\r
-#define SPI_BUF0_V 0xFFFFFFFF\r
-#define SPI_BUF0_S 0\r
-\r
-#define SPI_W1_REG(i) (REG_SPI_BASE(i) + 0x84)\r
-/* SPI_BUF1 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */\r
-/*description: data buffer*/\r
-#define SPI_BUF1 0xFFFFFFFF\r
-#define SPI_BUF1_M ((SPI_BUF1_V)<<(SPI_BUF1_S))\r
-#define SPI_BUF1_V 0xFFFFFFFF\r
-#define SPI_BUF1_S 0\r
-\r
-#define SPI_W2_REG(i) (REG_SPI_BASE(i) + 0x88)\r
-/* SPI_BUF2 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */\r
-/*description: data buffer*/\r
-#define SPI_BUF2 0xFFFFFFFF\r
-#define SPI_BUF2_M ((SPI_BUF2_V)<<(SPI_BUF2_S))\r
-#define SPI_BUF2_V 0xFFFFFFFF\r
-#define SPI_BUF2_S 0\r
-\r
-#define SPI_W3_REG(i) (REG_SPI_BASE(i) + 0x8C)\r
-/* SPI_BUF3 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */\r
-/*description: data buffer*/\r
-#define SPI_BUF3 0xFFFFFFFF\r
-#define SPI_BUF3_M ((SPI_BUF3_V)<<(SPI_BUF3_S))\r
-#define SPI_BUF3_V 0xFFFFFFFF\r
-#define SPI_BUF3_S 0\r
-\r
-#define SPI_W4_REG(i) (REG_SPI_BASE(i) + 0x90)\r
-/* SPI_BUF4 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */\r
-/*description: data buffer*/\r
-#define SPI_BUF4 0xFFFFFFFF\r
-#define SPI_BUF4_M ((SPI_BUF4_V)<<(SPI_BUF4_S))\r
-#define SPI_BUF4_V 0xFFFFFFFF\r
-#define SPI_BUF4_S 0\r
-\r
-#define SPI_W5_REG(i) (REG_SPI_BASE(i) + 0x94)\r
-/* SPI_BUF5 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */\r
-/*description: data buffer*/\r
-#define SPI_BUF5 0xFFFFFFFF\r
-#define SPI_BUF5_M ((SPI_BUF5_V)<<(SPI_BUF5_S))\r
-#define SPI_BUF5_V 0xFFFFFFFF\r
-#define SPI_BUF5_S 0\r
-\r
-#define SPI_W6_REG(i) (REG_SPI_BASE(i) + 0x98)\r
-/* SPI_BUF6 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */\r
-/*description: data buffer*/\r
-#define SPI_BUF6 0xFFFFFFFF\r
-#define SPI_BUF6_M ((SPI_BUF6_V)<<(SPI_BUF6_S))\r
-#define SPI_BUF6_V 0xFFFFFFFF\r
-#define SPI_BUF6_S 0\r
-\r
-#define SPI_W7_REG(i) (REG_SPI_BASE(i) + 0x9C)\r
-/* SPI_BUF7 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */\r
-/*description: data buffer*/\r
-#define SPI_BUF7 0xFFFFFFFF\r
-#define SPI_BUF7_M ((SPI_BUF7_V)<<(SPI_BUF7_S))\r
-#define SPI_BUF7_V 0xFFFFFFFF\r
-#define SPI_BUF7_S 0\r
-\r
-#define SPI_W8_REG(i) (REG_SPI_BASE(i) + 0xA0)\r
-/* SPI_BUF8 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */\r
-/*description: data buffer*/\r
-#define SPI_BUF8 0xFFFFFFFF\r
-#define SPI_BUF8_M ((SPI_BUF8_V)<<(SPI_BUF8_S))\r
-#define SPI_BUF8_V 0xFFFFFFFF\r
-#define SPI_BUF8_S 0\r
-\r
-#define SPI_W9_REG(i) (REG_SPI_BASE(i) + 0xA4)\r
-/* SPI_BUF9 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */\r
-/*description: data buffer*/\r
-#define SPI_BUF9 0xFFFFFFFF\r
-#define SPI_BUF9_M ((SPI_BUF9_V)<<(SPI_BUF9_S))\r
-#define SPI_BUF9_V 0xFFFFFFFF\r
-#define SPI_BUF9_S 0\r
-\r
-#define SPI_W10_REG(i) (REG_SPI_BASE(i) + 0xA8)\r
-/* SPI_BUF10 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */\r
-/*description: data buffer*/\r
-#define SPI_BUF10 0xFFFFFFFF\r
-#define SPI_BUF10_M ((SPI_BUF10_V)<<(SPI_BUF10_S))\r
-#define SPI_BUF10_V 0xFFFFFFFF\r
-#define SPI_BUF10_S 0\r
-\r
-#define SPI_W11_REG(i) (REG_SPI_BASE(i) + 0xAC)\r
-/* SPI_BUF11 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */\r
-/*description: data buffer*/\r
-#define SPI_BUF11 0xFFFFFFFF\r
-#define SPI_BUF11_M ((SPI_BUF11_V)<<(SPI_BUF11_S))\r
-#define SPI_BUF11_V 0xFFFFFFFF\r
-#define SPI_BUF11_S 0\r
-\r
-#define SPI_W12_REG(i) (REG_SPI_BASE(i) + 0xB0)\r
-/* SPI_BUF12 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */\r
-/*description: data buffer*/\r
-#define SPI_BUF12 0xFFFFFFFF\r
-#define SPI_BUF12_M ((SPI_BUF12_V)<<(SPI_BUF12_S))\r
-#define SPI_BUF12_V 0xFFFFFFFF\r
-#define SPI_BUF12_S 0\r
-\r
-#define SPI_W13_REG(i) (REG_SPI_BASE(i) + 0xB4)\r
-/* SPI_BUF13 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */\r
-/*description: data buffer*/\r
-#define SPI_BUF13 0xFFFFFFFF\r
-#define SPI_BUF13_M ((SPI_BUF13_V)<<(SPI_BUF13_S))\r
-#define SPI_BUF13_V 0xFFFFFFFF\r
-#define SPI_BUF13_S 0\r
-\r
-#define SPI_W14_REG(i) (REG_SPI_BASE(i) + 0xB8)\r
-/* SPI_BUF14 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */\r
-/*description: data buffer*/\r
-#define SPI_BUF14 0xFFFFFFFF\r
-#define SPI_BUF14_M ((SPI_BUF14_V)<<(SPI_BUF14_S))\r
-#define SPI_BUF14_V 0xFFFFFFFF\r
-#define SPI_BUF14_S 0\r
-\r
-#define SPI_W15_REG(i) (REG_SPI_BASE(i) + 0xBC)\r
-/* SPI_BUF15 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */\r
-/*description: data buffer*/\r
-#define SPI_BUF15 0xFFFFFFFF\r
-#define SPI_BUF15_M ((SPI_BUF15_V)<<(SPI_BUF15_S))\r
-#define SPI_BUF15_V 0xFFFFFFFF\r
-#define SPI_BUF15_S 0\r
-\r
-#define SPI_TX_CRC_REG(i) (REG_SPI_BASE(i) + 0xC0)\r
-/* SPI_TX_CRC_DATA : R/W ;bitpos:[31:0] ;default: 32'b0 ; */\r
-/*description: For SPI1 the value of crc32 for 256 bits data.*/\r
-#define SPI_TX_CRC_DATA 0xFFFFFFFF\r
-#define SPI_TX_CRC_DATA_M ((SPI_TX_CRC_DATA_V)<<(SPI_TX_CRC_DATA_S))\r
-#define SPI_TX_CRC_DATA_V 0xFFFFFFFF\r
-#define SPI_TX_CRC_DATA_S 0\r
-\r
-#define SPI_EXT0_REG(i) (REG_SPI_BASE(i) + 0xF0)\r
-/* SPI_T_PP_ENA : R/W ;bitpos:[31] ;default: 1'b1 ; */\r
-/*description: page program delay enable.*/\r
-#define SPI_T_PP_ENA (BIT(31))\r
-#define SPI_T_PP_ENA_M (BIT(31))\r
-#define SPI_T_PP_ENA_V 0x1\r
-#define SPI_T_PP_ENA_S 31\r
-/* SPI_T_PP_SHIFT : R/W ;bitpos:[19:16] ;default: 4'd10 ; */\r
-/*description: page program delay time shift .*/\r
-#define SPI_T_PP_SHIFT 0x0000000F\r
-#define SPI_T_PP_SHIFT_M ((SPI_T_PP_SHIFT_V)<<(SPI_T_PP_SHIFT_S))\r
-#define SPI_T_PP_SHIFT_V 0xF\r
-#define SPI_T_PP_SHIFT_S 16\r
-/* SPI_T_PP_TIME : R/W ;bitpos:[11:0] ;default: 12'd80 ; */\r
-/*description: page program delay time by system clock.*/\r
-#define SPI_T_PP_TIME 0x00000FFF\r
-#define SPI_T_PP_TIME_M ((SPI_T_PP_TIME_V)<<(SPI_T_PP_TIME_S))\r
-#define SPI_T_PP_TIME_V 0xFFF\r
-#define SPI_T_PP_TIME_S 0\r
-\r
-#define SPI_EXT1_REG(i) (REG_SPI_BASE(i) + 0xF4)\r
-/* SPI_T_ERASE_ENA : R/W ;bitpos:[31] ;default: 1'b1 ; */\r
-/*description: erase flash delay enable.*/\r
-#define SPI_T_ERASE_ENA (BIT(31))\r
-#define SPI_T_ERASE_ENA_M (BIT(31))\r
-#define SPI_T_ERASE_ENA_V 0x1\r
-#define SPI_T_ERASE_ENA_S 31\r
-/* SPI_T_ERASE_SHIFT : R/W ;bitpos:[19:16] ;default: 4'd15 ; */\r
-/*description: erase flash delay time shift.*/\r
-#define SPI_T_ERASE_SHIFT 0x0000000F\r
-#define SPI_T_ERASE_SHIFT_M ((SPI_T_ERASE_SHIFT_V)<<(SPI_T_ERASE_SHIFT_S))\r
-#define SPI_T_ERASE_SHIFT_V 0xF\r
-#define SPI_T_ERASE_SHIFT_S 16\r
-/* SPI_T_ERASE_TIME : R/W ;bitpos:[11:0] ;default: 12'd0 ; */\r
-/*description: erase flash delay time by system clock.*/\r
-#define SPI_T_ERASE_TIME 0x00000FFF\r
-#define SPI_T_ERASE_TIME_M ((SPI_T_ERASE_TIME_V)<<(SPI_T_ERASE_TIME_S))\r
-#define SPI_T_ERASE_TIME_V 0xFFF\r
-#define SPI_T_ERASE_TIME_S 0\r
-\r
-#define SPI_EXT2_REG(i) (REG_SPI_BASE(i) + 0xF8)\r
-/* SPI_ST : RO ;bitpos:[2:0] ;default: 3'b0 ; */\r
-/*description: The status of spi state machine .*/\r
-#define SPI_ST 0x00000007\r
-#define SPI_ST_M ((SPI_ST_V)<<(SPI_ST_S))\r
-#define SPI_ST_V 0x7\r
-#define SPI_ST_S 0\r
-\r
-#define SPI_EXT3_REG(i) (REG_SPI_BASE(i) + 0xFC)\r
-/* SPI_INT_HOLD_ENA : R/W ;bitpos:[1:0] ;default: 2'b0 ; */\r
-/*description: This register is for two SPI masters to share the same cs clock\r
- and data signals. The bits of one SPI are set if the other SPI is busy the SPI will be hold. 1(3): hold at ¡°idle¡± phase 2: hold at ¡°prepare¡± phase.*/\r
-#define SPI_INT_HOLD_ENA 0x00000003\r
-#define SPI_INT_HOLD_ENA_M ((SPI_INT_HOLD_ENA_V)<<(SPI_INT_HOLD_ENA_S))\r
-#define SPI_INT_HOLD_ENA_V 0x3\r
-#define SPI_INT_HOLD_ENA_S 0\r
-\r
-#define SPI_DMA_CONF_REG(i) (REG_SPI_BASE(i) + 0x100)\r
-/* SPI_DMA_CONTINUE : R/W ;bitpos:[16] ;default: 1'b0 ; */\r
-/*description: spi dma continue tx/rx data.*/\r
-#define SPI_DMA_CONTINUE (BIT(16))\r
-#define SPI_DMA_CONTINUE_M (BIT(16))\r
-#define SPI_DMA_CONTINUE_V 0x1\r
-#define SPI_DMA_CONTINUE_S 16\r
-/* SPI_DMA_TX_STOP : R/W ;bitpos:[15] ;default: 1'b0 ; */\r
-/*description: spi dma write data stop when in continue tx/rx mode.*/\r
-#define SPI_DMA_TX_STOP (BIT(15))\r
-#define SPI_DMA_TX_STOP_M (BIT(15))\r
-#define SPI_DMA_TX_STOP_V 0x1\r
-#define SPI_DMA_TX_STOP_S 15\r
-/* SPI_DMA_RX_STOP : R/W ;bitpos:[14] ;default: 1'b0 ; */\r
-/*description: spi dma read data stop when in continue tx/rx mode.*/\r
-#define SPI_DMA_RX_STOP (BIT(14))\r
-#define SPI_DMA_RX_STOP_M (BIT(14))\r
-#define SPI_DMA_RX_STOP_V 0x1\r
-#define SPI_DMA_RX_STOP_S 14\r
-/* SPI_OUT_DATA_BURST_EN : R/W ;bitpos:[12] ;default: 1'b0 ; */\r
-/*description: spi dma read data from memory in burst mode.*/\r
-#define SPI_OUT_DATA_BURST_EN (BIT(12))\r
-#define SPI_OUT_DATA_BURST_EN_M (BIT(12))\r
-#define SPI_OUT_DATA_BURST_EN_V 0x1\r
-#define SPI_OUT_DATA_BURST_EN_S 12\r
-/* SPI_INDSCR_BURST_EN : R/W ;bitpos:[11] ;default: 1'b0 ; */\r
-/*description: read descriptor use burst mode when write data to memory.*/\r
-#define SPI_INDSCR_BURST_EN (BIT(11))\r
-#define SPI_INDSCR_BURST_EN_M (BIT(11))\r
-#define SPI_INDSCR_BURST_EN_V 0x1\r
-#define SPI_INDSCR_BURST_EN_S 11\r
-/* SPI_OUTDSCR_BURST_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */\r
-/*description: read descriptor use burst mode when read data for memory.*/\r
-#define SPI_OUTDSCR_BURST_EN (BIT(10))\r
-#define SPI_OUTDSCR_BURST_EN_M (BIT(10))\r
-#define SPI_OUTDSCR_BURST_EN_V 0x1\r
-#define SPI_OUTDSCR_BURST_EN_S 10\r
-/* SPI_OUT_EOF_MODE : R/W ;bitpos:[9] ;default: 1'b1 ; */\r
-/*description: out eof flag generation mode . 1: when dma pop all data from\r
- fifo 0:when ahb push all data to fifo.*/\r
-#define SPI_OUT_EOF_MODE (BIT(9))\r
-#define SPI_OUT_EOF_MODE_M (BIT(9))\r
-#define SPI_OUT_EOF_MODE_V 0x1\r
-#define SPI_OUT_EOF_MODE_S 9\r
-/* SPI_OUT_AUTO_WRBACK : R/W ;bitpos:[8] ;default: 1'b0 ; */\r
-/*description: when the link is empty jump to next automatically.*/\r
-#define SPI_OUT_AUTO_WRBACK (BIT(8))\r
-#define SPI_OUT_AUTO_WRBACK_M (BIT(8))\r
-#define SPI_OUT_AUTO_WRBACK_V 0x1\r
-#define SPI_OUT_AUTO_WRBACK_S 8\r
-/* SPI_OUT_LOOP_TEST : R/W ;bitpos:[7] ;default: 1'b0 ; */\r
-/*description: Set bit to test out link.*/\r
-#define SPI_OUT_LOOP_TEST (BIT(7))\r
-#define SPI_OUT_LOOP_TEST_M (BIT(7))\r
-#define SPI_OUT_LOOP_TEST_V 0x1\r
-#define SPI_OUT_LOOP_TEST_S 7\r
-/* SPI_IN_LOOP_TEST : R/W ;bitpos:[6] ;default: 1'b0 ; */\r
-/*description: Set bit to test in link.*/\r
-#define SPI_IN_LOOP_TEST (BIT(6))\r
-#define SPI_IN_LOOP_TEST_M (BIT(6))\r
-#define SPI_IN_LOOP_TEST_V 0x1\r
-#define SPI_IN_LOOP_TEST_S 6\r
-/* SPI_AHBM_RST : R/W ;bitpos:[5] ;default: 1'b0 ; */\r
-/*description: reset spi dma ahb master.*/\r
-#define SPI_AHBM_RST (BIT(5))\r
-#define SPI_AHBM_RST_M (BIT(5))\r
-#define SPI_AHBM_RST_V 0x1\r
-#define SPI_AHBM_RST_S 5\r
-/* SPI_AHBM_FIFO_RST : R/W ;bitpos:[4] ;default: 1'b0 ; */\r
-/*description: reset spi dma ahb master fifo pointer.*/\r
-#define SPI_AHBM_FIFO_RST (BIT(4))\r
-#define SPI_AHBM_FIFO_RST_M (BIT(4))\r
-#define SPI_AHBM_FIFO_RST_V 0x1\r
-#define SPI_AHBM_FIFO_RST_S 4\r
-/* SPI_OUT_RST : R/W ;bitpos:[3] ;default: 1'b0 ; */\r
-/*description: The bit is used to reset out dma fsm and out data fifo pointer.*/\r
-#define SPI_OUT_RST (BIT(3))\r
-#define SPI_OUT_RST_M (BIT(3))\r
-#define SPI_OUT_RST_V 0x1\r
-#define SPI_OUT_RST_S 3\r
-/* SPI_IN_RST : R/W ;bitpos:[2] ;default: 1'b0 ; */\r
-/*description: The bit is used to reset in dma fsm and in data fifo pointer.*/\r
-#define SPI_IN_RST (BIT(2))\r
-#define SPI_IN_RST_M (BIT(2))\r
-#define SPI_IN_RST_V 0x1\r
-#define SPI_IN_RST_S 2\r
-\r
-#define SPI_DMA_OUT_LINK_REG(i) (REG_SPI_BASE(i) + 0x104)\r
-/* SPI_OUTLINK_RESTART : R/W ;bitpos:[30] ;default: 1'b0 ; */\r
-/*description: Set the bit to mount on new outlink descriptors.*/\r
-#define SPI_OUTLINK_RESTART (BIT(30))\r
-#define SPI_OUTLINK_RESTART_M (BIT(30))\r
-#define SPI_OUTLINK_RESTART_V 0x1\r
-#define SPI_OUTLINK_RESTART_S 30\r
-/* SPI_OUTLINK_START : R/W ;bitpos:[29] ;default: 1'b0 ; */\r
-/*description: Set the bit to start to use outlink descriptor.*/\r
-#define SPI_OUTLINK_START (BIT(29))\r
-#define SPI_OUTLINK_START_M (BIT(29))\r
-#define SPI_OUTLINK_START_V 0x1\r
-#define SPI_OUTLINK_START_S 29\r
-/* SPI_OUTLINK_STOP : R/W ;bitpos:[28] ;default: 1'b0 ; */\r
-/*description: Set the bit to stop to use outlink descriptor.*/\r
-#define SPI_OUTLINK_STOP (BIT(28))\r
-#define SPI_OUTLINK_STOP_M (BIT(28))\r
-#define SPI_OUTLINK_STOP_V 0x1\r
-#define SPI_OUTLINK_STOP_S 28\r
-/* SPI_OUTLINK_ADDR : R/W ;bitpos:[19:0] ;default: 20'h0 ; */\r
-/*description: The address of the first outlink descriptor.*/\r
-#define SPI_OUTLINK_ADDR 0x000FFFFF\r
-#define SPI_OUTLINK_ADDR_M ((SPI_OUTLINK_ADDR_V)<<(SPI_OUTLINK_ADDR_S))\r
-#define SPI_OUTLINK_ADDR_V 0xFFFFF\r
-#define SPI_OUTLINK_ADDR_S 0\r
-\r
-#define SPI_DMA_IN_LINK_REG(i) (REG_SPI_BASE(i) + 0x108)\r
-/* SPI_INLINK_RESTART : R/W ;bitpos:[30] ;default: 1'b0 ; */\r
-/*description: Set the bit to mount on new inlink descriptors.*/\r
-#define SPI_INLINK_RESTART (BIT(30))\r
-#define SPI_INLINK_RESTART_M (BIT(30))\r
-#define SPI_INLINK_RESTART_V 0x1\r
-#define SPI_INLINK_RESTART_S 30\r
-/* SPI_INLINK_START : R/W ;bitpos:[29] ;default: 1'b0 ; */\r
-/*description: Set the bit to start to use inlink descriptor.*/\r
-#define SPI_INLINK_START (BIT(29))\r
-#define SPI_INLINK_START_M (BIT(29))\r
-#define SPI_INLINK_START_V 0x1\r
-#define SPI_INLINK_START_S 29\r
-/* SPI_INLINK_STOP : R/W ;bitpos:[28] ;default: 1'b0 ; */\r
-/*description: Set the bit to stop to use inlink descriptor.*/\r
-#define SPI_INLINK_STOP (BIT(28))\r
-#define SPI_INLINK_STOP_M (BIT(28))\r
-#define SPI_INLINK_STOP_V 0x1\r
-#define SPI_INLINK_STOP_S 28\r
-/* SPI_INLINK_AUTO_RET : R/W ;bitpos:[20] ;default: 1'b0 ; */\r
-/*description: when the bit is set inlink descriptor returns to the next descriptor\r
- while a packet is wrong*/\r
-#define SPI_INLINK_AUTO_RET (BIT(20))\r
-#define SPI_INLINK_AUTO_RET_M (BIT(20))\r
-#define SPI_INLINK_AUTO_RET_V 0x1\r
-#define SPI_INLINK_AUTO_RET_S 20\r
-/* SPI_INLINK_ADDR : R/W ;bitpos:[19:0] ;default: 20'h0 ; */\r
-/*description: The address of the first inlink descriptor.*/\r
-#define SPI_INLINK_ADDR 0x000FFFFF\r
-#define SPI_INLINK_ADDR_M ((SPI_INLINK_ADDR_V)<<(SPI_INLINK_ADDR_S))\r
-#define SPI_INLINK_ADDR_V 0xFFFFF\r
-#define SPI_INLINK_ADDR_S 0\r
-\r
-#define SPI_DMA_STATUS_REG(i) (REG_SPI_BASE(i) + 0x10C)\r
-/* SPI_DMA_TX_EN : RO ;bitpos:[1] ;default: 1'b0 ; */\r
-/*description: spi dma write data status bit.*/\r
-#define SPI_DMA_TX_EN (BIT(1))\r
-#define SPI_DMA_TX_EN_M (BIT(1))\r
-#define SPI_DMA_TX_EN_V 0x1\r
-#define SPI_DMA_TX_EN_S 1\r
-/* SPI_DMA_RX_EN : RO ;bitpos:[0] ;default: 1'b0 ; */\r
-/*description: spi dma read data status bit.*/\r
-#define SPI_DMA_RX_EN (BIT(0))\r
-#define SPI_DMA_RX_EN_M (BIT(0))\r
-#define SPI_DMA_RX_EN_V 0x1\r
-#define SPI_DMA_RX_EN_S 0\r
-\r
-#define SPI_DMA_INT_ENA_REG(i) (REG_SPI_BASE(i) + 0x110)\r
-/* SPI_OUT_TOTAL_EOF_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */\r
-/*description: The enable bit for sending all the packets to host done.*/\r
-#define SPI_OUT_TOTAL_EOF_INT_ENA (BIT(8))\r
-#define SPI_OUT_TOTAL_EOF_INT_ENA_M (BIT(8))\r
-#define SPI_OUT_TOTAL_EOF_INT_ENA_V 0x1\r
-#define SPI_OUT_TOTAL_EOF_INT_ENA_S 8\r
-/* SPI_OUT_EOF_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */\r
-/*description: The enable bit for sending a packet to host done.*/\r
-#define SPI_OUT_EOF_INT_ENA (BIT(7))\r
-#define SPI_OUT_EOF_INT_ENA_M (BIT(7))\r
-#define SPI_OUT_EOF_INT_ENA_V 0x1\r
-#define SPI_OUT_EOF_INT_ENA_S 7\r
-/* SPI_OUT_DONE_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */\r
-/*description: The enable bit for completing usage of a outlink descriptor .*/\r
-#define SPI_OUT_DONE_INT_ENA (BIT(6))\r
-#define SPI_OUT_DONE_INT_ENA_M (BIT(6))\r
-#define SPI_OUT_DONE_INT_ENA_V 0x1\r
-#define SPI_OUT_DONE_INT_ENA_S 6\r
-/* SPI_IN_SUC_EOF_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */\r
-/*description: The enable bit for completing receiving all the packets from host.*/\r
-#define SPI_IN_SUC_EOF_INT_ENA (BIT(5))\r
-#define SPI_IN_SUC_EOF_INT_ENA_M (BIT(5))\r
-#define SPI_IN_SUC_EOF_INT_ENA_V 0x1\r
-#define SPI_IN_SUC_EOF_INT_ENA_S 5\r
-/* SPI_IN_ERR_EOF_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */\r
-/*description: The enable bit for receiving error.*/\r
-#define SPI_IN_ERR_EOF_INT_ENA (BIT(4))\r
-#define SPI_IN_ERR_EOF_INT_ENA_M (BIT(4))\r
-#define SPI_IN_ERR_EOF_INT_ENA_V 0x1\r
-#define SPI_IN_ERR_EOF_INT_ENA_S 4\r
-/* SPI_IN_DONE_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */\r
-/*description: The enable bit for completing usage of a inlink descriptor.*/\r
-#define SPI_IN_DONE_INT_ENA (BIT(3))\r
-#define SPI_IN_DONE_INT_ENA_M (BIT(3))\r
-#define SPI_IN_DONE_INT_ENA_V 0x1\r
-#define SPI_IN_DONE_INT_ENA_S 3\r
-/* SPI_INLINK_DSCR_ERROR_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */\r
-/*description: The enable bit for inlink descriptor error.*/\r
-#define SPI_INLINK_DSCR_ERROR_INT_ENA (BIT(2))\r
-#define SPI_INLINK_DSCR_ERROR_INT_ENA_M (BIT(2))\r
-#define SPI_INLINK_DSCR_ERROR_INT_ENA_V 0x1\r
-#define SPI_INLINK_DSCR_ERROR_INT_ENA_S 2\r
-/* SPI_OUTLINK_DSCR_ERROR_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */\r
-/*description: The enable bit for outlink descriptor error.*/\r
-#define SPI_OUTLINK_DSCR_ERROR_INT_ENA (BIT(1))\r
-#define SPI_OUTLINK_DSCR_ERROR_INT_ENA_M (BIT(1))\r
-#define SPI_OUTLINK_DSCR_ERROR_INT_ENA_V 0x1\r
-#define SPI_OUTLINK_DSCR_ERROR_INT_ENA_S 1\r
-/* SPI_INLINK_DSCR_EMPTY_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */\r
-/*description: The enable bit for lack of enough inlink descriptors.*/\r
-#define SPI_INLINK_DSCR_EMPTY_INT_ENA (BIT(0))\r
-#define SPI_INLINK_DSCR_EMPTY_INT_ENA_M (BIT(0))\r
-#define SPI_INLINK_DSCR_EMPTY_INT_ENA_V 0x1\r
-#define SPI_INLINK_DSCR_EMPTY_INT_ENA_S 0\r
-\r
-#define SPI_DMA_INT_RAW_REG(i) (REG_SPI_BASE(i) + 0x114)\r
-/* SPI_OUT_TOTAL_EOF_INT_RAW : RO ;bitpos:[8] ;default: 1'b0 ; */\r
-/*description: The raw bit for sending all the packets to host done.*/\r
-#define SPI_OUT_TOTAL_EOF_INT_RAW (BIT(8))\r
-#define SPI_OUT_TOTAL_EOF_INT_RAW_M (BIT(8))\r
-#define SPI_OUT_TOTAL_EOF_INT_RAW_V 0x1\r
-#define SPI_OUT_TOTAL_EOF_INT_RAW_S 8\r
-/* SPI_OUT_EOF_INT_RAW : RO ;bitpos:[7] ;default: 1'b0 ; */\r
-/*description: The raw bit for sending a packet to host done.*/\r
-#define SPI_OUT_EOF_INT_RAW (BIT(7))\r
-#define SPI_OUT_EOF_INT_RAW_M (BIT(7))\r
-#define SPI_OUT_EOF_INT_RAW_V 0x1\r
-#define SPI_OUT_EOF_INT_RAW_S 7\r
-/* SPI_OUT_DONE_INT_RAW : RO ;bitpos:[6] ;default: 1'b0 ; */\r
-/*description: The raw bit for completing usage of a outlink descriptor.*/\r
-#define SPI_OUT_DONE_INT_RAW (BIT(6))\r
-#define SPI_OUT_DONE_INT_RAW_M (BIT(6))\r
-#define SPI_OUT_DONE_INT_RAW_V 0x1\r
-#define SPI_OUT_DONE_INT_RAW_S 6\r
-/* SPI_IN_SUC_EOF_INT_RAW : RO ;bitpos:[5] ;default: 1'b0 ; */\r
-/*description: The raw bit for completing receiving all the packets from host.*/\r
-#define SPI_IN_SUC_EOF_INT_RAW (BIT(5))\r
-#define SPI_IN_SUC_EOF_INT_RAW_M (BIT(5))\r
-#define SPI_IN_SUC_EOF_INT_RAW_V 0x1\r
-#define SPI_IN_SUC_EOF_INT_RAW_S 5\r
-/* SPI_IN_ERR_EOF_INT_RAW : RO ;bitpos:[4] ;default: 1'b0 ; */\r
-/*description: The raw bit for receiving error.*/\r
-#define SPI_IN_ERR_EOF_INT_RAW (BIT(4))\r
-#define SPI_IN_ERR_EOF_INT_RAW_M (BIT(4))\r
-#define SPI_IN_ERR_EOF_INT_RAW_V 0x1\r
-#define SPI_IN_ERR_EOF_INT_RAW_S 4\r
-/* SPI_IN_DONE_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */\r
-/*description: The raw bit for completing usage of a inlink descriptor.*/\r
-#define SPI_IN_DONE_INT_RAW (BIT(3))\r
-#define SPI_IN_DONE_INT_RAW_M (BIT(3))\r
-#define SPI_IN_DONE_INT_RAW_V 0x1\r
-#define SPI_IN_DONE_INT_RAW_S 3\r
-/* SPI_INLINK_DSCR_ERROR_INT_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */\r
-/*description: The raw bit for inlink descriptor error.*/\r
-#define SPI_INLINK_DSCR_ERROR_INT_RAW (BIT(2))\r
-#define SPI_INLINK_DSCR_ERROR_INT_RAW_M (BIT(2))\r
-#define SPI_INLINK_DSCR_ERROR_INT_RAW_V 0x1\r
-#define SPI_INLINK_DSCR_ERROR_INT_RAW_S 2\r
-/* SPI_OUTLINK_DSCR_ERROR_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */\r
-/*description: The raw bit for outlink descriptor error.*/\r
-#define SPI_OUTLINK_DSCR_ERROR_INT_RAW (BIT(1))\r
-#define SPI_OUTLINK_DSCR_ERROR_INT_RAW_M (BIT(1))\r
-#define SPI_OUTLINK_DSCR_ERROR_INT_RAW_V 0x1\r
-#define SPI_OUTLINK_DSCR_ERROR_INT_RAW_S 1\r
-/* SPI_INLINK_DSCR_EMPTY_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */\r
-/*description: The raw bit for lack of enough inlink descriptors.*/\r
-#define SPI_INLINK_DSCR_EMPTY_INT_RAW (BIT(0))\r
-#define SPI_INLINK_DSCR_EMPTY_INT_RAW_M (BIT(0))\r
-#define SPI_INLINK_DSCR_EMPTY_INT_RAW_V 0x1\r
-#define SPI_INLINK_DSCR_EMPTY_INT_RAW_S 0\r
-\r
-#define SPI_DMA_INT_ST_REG(i) (REG_SPI_BASE(i) + 0x118)\r
-/* SPI_OUT_TOTAL_EOF_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */\r
-/*description: The status bit for sending all the packets to host done.*/\r
-#define SPI_OUT_TOTAL_EOF_INT_ST (BIT(8))\r
-#define SPI_OUT_TOTAL_EOF_INT_ST_M (BIT(8))\r
-#define SPI_OUT_TOTAL_EOF_INT_ST_V 0x1\r
-#define SPI_OUT_TOTAL_EOF_INT_ST_S 8\r
-/* SPI_OUT_EOF_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */\r
-/*description: The status bit for sending a packet to host done.*/\r
-#define SPI_OUT_EOF_INT_ST (BIT(7))\r
-#define SPI_OUT_EOF_INT_ST_M (BIT(7))\r
-#define SPI_OUT_EOF_INT_ST_V 0x1\r
-#define SPI_OUT_EOF_INT_ST_S 7\r
-/* SPI_OUT_DONE_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */\r
-/*description: The status bit for completing usage of a outlink descriptor.*/\r
-#define SPI_OUT_DONE_INT_ST (BIT(6))\r
-#define SPI_OUT_DONE_INT_ST_M (BIT(6))\r
-#define SPI_OUT_DONE_INT_ST_V 0x1\r
-#define SPI_OUT_DONE_INT_ST_S 6\r
-/* SPI_IN_SUC_EOF_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */\r
-/*description: The status bit for completing receiving all the packets from host.*/\r
-#define SPI_IN_SUC_EOF_INT_ST (BIT(5))\r
-#define SPI_IN_SUC_EOF_INT_ST_M (BIT(5))\r
-#define SPI_IN_SUC_EOF_INT_ST_V 0x1\r
-#define SPI_IN_SUC_EOF_INT_ST_S 5\r
-/* SPI_IN_ERR_EOF_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */\r
-/*description: The status bit for receiving error.*/\r
-#define SPI_IN_ERR_EOF_INT_ST (BIT(4))\r
-#define SPI_IN_ERR_EOF_INT_ST_M (BIT(4))\r
-#define SPI_IN_ERR_EOF_INT_ST_V 0x1\r
-#define SPI_IN_ERR_EOF_INT_ST_S 4\r
-/* SPI_IN_DONE_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */\r
-/*description: The status bit for completing usage of a inlink descriptor.*/\r
-#define SPI_IN_DONE_INT_ST (BIT(3))\r
-#define SPI_IN_DONE_INT_ST_M (BIT(3))\r
-#define SPI_IN_DONE_INT_ST_V 0x1\r
-#define SPI_IN_DONE_INT_ST_S 3\r
-/* SPI_INLINK_DSCR_ERROR_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */\r
-/*description: The status bit for inlink descriptor error.*/\r
-#define SPI_INLINK_DSCR_ERROR_INT_ST (BIT(2))\r
-#define SPI_INLINK_DSCR_ERROR_INT_ST_M (BIT(2))\r
-#define SPI_INLINK_DSCR_ERROR_INT_ST_V 0x1\r
-#define SPI_INLINK_DSCR_ERROR_INT_ST_S 2\r
-/* SPI_OUTLINK_DSCR_ERROR_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */\r
-/*description: The status bit for outlink descriptor error.*/\r
-#define SPI_OUTLINK_DSCR_ERROR_INT_ST (BIT(1))\r
-#define SPI_OUTLINK_DSCR_ERROR_INT_ST_M (BIT(1))\r
-#define SPI_OUTLINK_DSCR_ERROR_INT_ST_V 0x1\r
-#define SPI_OUTLINK_DSCR_ERROR_INT_ST_S 1\r
-/* SPI_INLINK_DSCR_EMPTY_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */\r
-/*description: The status bit for lack of enough inlink descriptors.*/\r
-#define SPI_INLINK_DSCR_EMPTY_INT_ST (BIT(0))\r
-#define SPI_INLINK_DSCR_EMPTY_INT_ST_M (BIT(0))\r
-#define SPI_INLINK_DSCR_EMPTY_INT_ST_V 0x1\r
-#define SPI_INLINK_DSCR_EMPTY_INT_ST_S 0\r
-\r
-#define SPI_DMA_INT_CLR_REG(i) (REG_SPI_BASE(i) + 0x11C)\r
-/* SPI_OUT_TOTAL_EOF_INT_CLR : R/W ;bitpos:[8] ;default: 1'b0 ; */\r
-/*description: The clear bit for sending all the packets to host done.*/\r
-#define SPI_OUT_TOTAL_EOF_INT_CLR (BIT(8))\r
-#define SPI_OUT_TOTAL_EOF_INT_CLR_M (BIT(8))\r
-#define SPI_OUT_TOTAL_EOF_INT_CLR_V 0x1\r
-#define SPI_OUT_TOTAL_EOF_INT_CLR_S 8\r
-/* SPI_OUT_EOF_INT_CLR : R/W ;bitpos:[7] ;default: 1'b0 ; */\r
-/*description: The clear bit for sending a packet to host done.*/\r
-#define SPI_OUT_EOF_INT_CLR (BIT(7))\r
-#define SPI_OUT_EOF_INT_CLR_M (BIT(7))\r
-#define SPI_OUT_EOF_INT_CLR_V 0x1\r
-#define SPI_OUT_EOF_INT_CLR_S 7\r
-/* SPI_OUT_DONE_INT_CLR : R/W ;bitpos:[6] ;default: 1'b0 ; */\r
-/*description: The clear bit for completing usage of a outlink descriptor.*/\r
-#define SPI_OUT_DONE_INT_CLR (BIT(6))\r
-#define SPI_OUT_DONE_INT_CLR_M (BIT(6))\r
-#define SPI_OUT_DONE_INT_CLR_V 0x1\r
-#define SPI_OUT_DONE_INT_CLR_S 6\r
-/* SPI_IN_SUC_EOF_INT_CLR : R/W ;bitpos:[5] ;default: 1'b0 ; */\r
-/*description: The clear bit for completing receiving all the packets from host.*/\r
-#define SPI_IN_SUC_EOF_INT_CLR (BIT(5))\r
-#define SPI_IN_SUC_EOF_INT_CLR_M (BIT(5))\r
-#define SPI_IN_SUC_EOF_INT_CLR_V 0x1\r
-#define SPI_IN_SUC_EOF_INT_CLR_S 5\r
-/* SPI_IN_ERR_EOF_INT_CLR : R/W ;bitpos:[4] ;default: 1'b0 ; */\r
-/*description: The clear bit for receiving error.*/\r
-#define SPI_IN_ERR_EOF_INT_CLR (BIT(4))\r
-#define SPI_IN_ERR_EOF_INT_CLR_M (BIT(4))\r
-#define SPI_IN_ERR_EOF_INT_CLR_V 0x1\r
-#define SPI_IN_ERR_EOF_INT_CLR_S 4\r
-/* SPI_IN_DONE_INT_CLR : R/W ;bitpos:[3] ;default: 1'b0 ; */\r
-/*description: The clear bit for completing usage of a inlink descriptor.*/\r
-#define SPI_IN_DONE_INT_CLR (BIT(3))\r
-#define SPI_IN_DONE_INT_CLR_M (BIT(3))\r
-#define SPI_IN_DONE_INT_CLR_V 0x1\r
-#define SPI_IN_DONE_INT_CLR_S 3\r
-/* SPI_INLINK_DSCR_ERROR_INT_CLR : R/W ;bitpos:[2] ;default: 1'b0 ; */\r
-/*description: The clear bit for inlink descriptor error.*/\r
-#define SPI_INLINK_DSCR_ERROR_INT_CLR (BIT(2))\r
-#define SPI_INLINK_DSCR_ERROR_INT_CLR_M (BIT(2))\r
-#define SPI_INLINK_DSCR_ERROR_INT_CLR_V 0x1\r
-#define SPI_INLINK_DSCR_ERROR_INT_CLR_S 2\r
-/* SPI_OUTLINK_DSCR_ERROR_INT_CLR : R/W ;bitpos:[1] ;default: 1'b0 ; */\r
-/*description: The clear bit for outlink descriptor error.*/\r
-#define SPI_OUTLINK_DSCR_ERROR_INT_CLR (BIT(1))\r
-#define SPI_OUTLINK_DSCR_ERROR_INT_CLR_M (BIT(1))\r
-#define SPI_OUTLINK_DSCR_ERROR_INT_CLR_V 0x1\r
-#define SPI_OUTLINK_DSCR_ERROR_INT_CLR_S 1\r
-/* SPI_INLINK_DSCR_EMPTY_INT_CLR : R/W ;bitpos:[0] ;default: 1'b0 ; */\r
-/*description: The clear bit for lack of enough inlink descriptors.*/\r
-#define SPI_INLINK_DSCR_EMPTY_INT_CLR (BIT(0))\r
-#define SPI_INLINK_DSCR_EMPTY_INT_CLR_M (BIT(0))\r
-#define SPI_INLINK_DSCR_EMPTY_INT_CLR_V 0x1\r
-#define SPI_INLINK_DSCR_EMPTY_INT_CLR_S 0\r
-\r
-#define SPI_IN_ERR_EOF_DES_ADDR_REG(i) (REG_SPI_BASE(i) + 0x120)\r
-/* SPI_DMA_IN_ERR_EOF_DES_ADDR : RO ;bitpos:[31:0] ;default: 32'b0 ; */\r
-/*description: The inlink descriptor address when spi dma produce receiving error.*/\r
-#define SPI_DMA_IN_ERR_EOF_DES_ADDR 0xFFFFFFFF\r
-#define SPI_DMA_IN_ERR_EOF_DES_ADDR_M ((SPI_DMA_IN_ERR_EOF_DES_ADDR_V)<<(SPI_DMA_IN_ERR_EOF_DES_ADDR_S))\r
-#define SPI_DMA_IN_ERR_EOF_DES_ADDR_V 0xFFFFFFFF\r
-#define SPI_DMA_IN_ERR_EOF_DES_ADDR_S 0\r
-\r
-#define SPI_IN_SUC_EOF_DES_ADDR_REG(i) (REG_SPI_BASE(i) + 0x124)\r
-/* SPI_DMA_IN_SUC_EOF_DES_ADDR : RO ;bitpos:[31:0] ;default: 32'b0 ; */\r
-/*description: The last inlink descriptor address when spi dma produce from_suc_eof.*/\r
-#define SPI_DMA_IN_SUC_EOF_DES_ADDR 0xFFFFFFFF\r
-#define SPI_DMA_IN_SUC_EOF_DES_ADDR_M ((SPI_DMA_IN_SUC_EOF_DES_ADDR_V)<<(SPI_DMA_IN_SUC_EOF_DES_ADDR_S))\r
-#define SPI_DMA_IN_SUC_EOF_DES_ADDR_V 0xFFFFFFFF\r
-#define SPI_DMA_IN_SUC_EOF_DES_ADDR_S 0\r
-\r
-#define SPI_INLINK_DSCR_REG(i) (REG_SPI_BASE(i) + 0x128)\r
-/* SPI_DMA_INLINK_DSCR : RO ;bitpos:[31:0] ;default: 32'b0 ; */\r
-/*description: The content of current in descriptor pointer.*/\r
-#define SPI_DMA_INLINK_DSCR 0xFFFFFFFF\r
-#define SPI_DMA_INLINK_DSCR_M ((SPI_DMA_INLINK_DSCR_V)<<(SPI_DMA_INLINK_DSCR_S))\r
-#define SPI_DMA_INLINK_DSCR_V 0xFFFFFFFF\r
-#define SPI_DMA_INLINK_DSCR_S 0\r
-\r
-#define SPI_INLINK_DSCR_BF0_REG(i) (REG_SPI_BASE(i) + 0x12C)\r
-/* SPI_DMA_INLINK_DSCR_BF0 : RO ;bitpos:[31:0] ;default: 32'b0 ; */\r
-/*description: The content of next in descriptor pointer.*/\r
-#define SPI_DMA_INLINK_DSCR_BF0 0xFFFFFFFF\r
-#define SPI_DMA_INLINK_DSCR_BF0_M ((SPI_DMA_INLINK_DSCR_BF0_V)<<(SPI_DMA_INLINK_DSCR_BF0_S))\r
-#define SPI_DMA_INLINK_DSCR_BF0_V 0xFFFFFFFF\r
-#define SPI_DMA_INLINK_DSCR_BF0_S 0\r
-\r
-#define SPI_INLINK_DSCR_BF1_REG(i) (REG_SPI_BASE(i) + 0x130)\r
-/* SPI_DMA_INLINK_DSCR_BF1 : RO ;bitpos:[31:0] ;default: 32'b0 ; */\r
-/*description: The content of current in descriptor data buffer pointer.*/\r
-#define SPI_DMA_INLINK_DSCR_BF1 0xFFFFFFFF\r
-#define SPI_DMA_INLINK_DSCR_BF1_M ((SPI_DMA_INLINK_DSCR_BF1_V)<<(SPI_DMA_INLINK_DSCR_BF1_S))\r
-#define SPI_DMA_INLINK_DSCR_BF1_V 0xFFFFFFFF\r
-#define SPI_DMA_INLINK_DSCR_BF1_S 0\r
-\r
-#define SPI_OUT_EOF_BFR_DES_ADDR_REG(i) (REG_SPI_BASE(i) + 0x134)\r
-/* SPI_DMA_OUT_EOF_BFR_DES_ADDR : RO ;bitpos:[31:0] ;default: 32'b0 ; */\r
-/*description: The address of buffer relative to the outlink descriptor that produce eof.*/\r
-#define SPI_DMA_OUT_EOF_BFR_DES_ADDR 0xFFFFFFFF\r
-#define SPI_DMA_OUT_EOF_BFR_DES_ADDR_M ((SPI_DMA_OUT_EOF_BFR_DES_ADDR_V)<<(SPI_DMA_OUT_EOF_BFR_DES_ADDR_S))\r
-#define SPI_DMA_OUT_EOF_BFR_DES_ADDR_V 0xFFFFFFFF\r
-#define SPI_DMA_OUT_EOF_BFR_DES_ADDR_S 0\r
-\r
-#define SPI_OUT_EOF_DES_ADDR_REG(i) (REG_SPI_BASE(i) + 0x138)\r
-/* SPI_DMA_OUT_EOF_DES_ADDR : RO ;bitpos:[31:0] ;default: 32'b0 ; */\r
-/*description: The last outlink descriptor address when spi dma produce to_eof.*/\r
-#define SPI_DMA_OUT_EOF_DES_ADDR 0xFFFFFFFF\r
-#define SPI_DMA_OUT_EOF_DES_ADDR_M ((SPI_DMA_OUT_EOF_DES_ADDR_V)<<(SPI_DMA_OUT_EOF_DES_ADDR_S))\r
-#define SPI_DMA_OUT_EOF_DES_ADDR_V 0xFFFFFFFF\r
-#define SPI_DMA_OUT_EOF_DES_ADDR_S 0\r
-\r
-#define SPI_OUTLINK_DSCR_REG(i) (REG_SPI_BASE(i) + 0x13C)\r
-/* SPI_DMA_OUTLINK_DSCR : RO ;bitpos:[31:0] ;default: 32'b0 ; */\r
-/*description: The content of current out descriptor pointer.*/\r
-#define SPI_DMA_OUTLINK_DSCR 0xFFFFFFFF\r
-#define SPI_DMA_OUTLINK_DSCR_M ((SPI_DMA_OUTLINK_DSCR_V)<<(SPI_DMA_OUTLINK_DSCR_S))\r
-#define SPI_DMA_OUTLINK_DSCR_V 0xFFFFFFFF\r
-#define SPI_DMA_OUTLINK_DSCR_S 0\r
-\r
-#define SPI_OUTLINK_DSCR_BF0_REG(i) (REG_SPI_BASE(i) + 0x140)\r
-/* SPI_DMA_OUTLINK_DSCR_BF0 : RO ;bitpos:[31:0] ;default: 32'b0 ; */\r
-/*description: The content of next out descriptor pointer.*/\r
-#define SPI_DMA_OUTLINK_DSCR_BF0 0xFFFFFFFF\r
-#define SPI_DMA_OUTLINK_DSCR_BF0_M ((SPI_DMA_OUTLINK_DSCR_BF0_V)<<(SPI_DMA_OUTLINK_DSCR_BF0_S))\r
-#define SPI_DMA_OUTLINK_DSCR_BF0_V 0xFFFFFFFF\r
-#define SPI_DMA_OUTLINK_DSCR_BF0_S 0\r
-\r
-#define SPI_OUTLINK_DSCR_BF1_REG(i) (REG_SPI_BASE(i) + 0x144)\r
-/* SPI_DMA_OUTLINK_DSCR_BF1 : RO ;bitpos:[31:0] ;default: 32'b0 ; */\r
-/*description: The content of current out descriptor data buffer pointer.*/\r
-#define SPI_DMA_OUTLINK_DSCR_BF1 0xFFFFFFFF\r
-#define SPI_DMA_OUTLINK_DSCR_BF1_M ((SPI_DMA_OUTLINK_DSCR_BF1_V)<<(SPI_DMA_OUTLINK_DSCR_BF1_S))\r
-#define SPI_DMA_OUTLINK_DSCR_BF1_V 0xFFFFFFFF\r
-#define SPI_DMA_OUTLINK_DSCR_BF1_S 0\r
-\r
-#define SPI_DMA_RSTATUS_REG(i) (REG_SPI_BASE(i) + 0x148)\r
-/* SPI_DMA_OUT_STATUS : RO ;bitpos:[31:0] ;default: 32'b0 ; */\r
-/*description: spi dma read data from memory status.*/\r
-#define SPI_DMA_OUT_STATUS 0xFFFFFFFF\r
-#define SPI_DMA_OUT_STATUS_M ((SPI_DMA_OUT_STATUS_V)<<(SPI_DMA_OUT_STATUS_S))\r
-#define SPI_DMA_OUT_STATUS_V 0xFFFFFFFF\r
-#define SPI_DMA_OUT_STATUS_S 0\r
-\r
-#define SPI_DMA_TSTATUS_REG(i) (REG_SPI_BASE(i) + 0x14C)\r
-/* SPI_DMA_IN_STATUS : RO ;bitpos:[31:0] ;default: 32'b0 ; */\r
-/*description: spi dma write data to memory status.*/\r
-#define SPI_DMA_IN_STATUS 0xFFFFFFFF\r
-#define SPI_DMA_IN_STATUS_M ((SPI_DMA_IN_STATUS_V)<<(SPI_DMA_IN_STATUS_S))\r
-#define SPI_DMA_IN_STATUS_V 0xFFFFFFFF\r
-#define SPI_DMA_IN_STATUS_S 0\r
-\r
-#define SPI_DATE_REG(i) (REG_SPI_BASE(i) + 0x3FC)\r
-/* SPI_DATE : RO ;bitpos:[27:0] ;default: 32'h1604270 ; */\r
-/*description: SPI register version.*/\r
-#define SPI_DATE 0x0FFFFFFF\r
-#define SPI_DATE_M ((SPI_DATE_V)<<(SPI_DATE_S))\r
-#define SPI_DATE_V 0xFFFFFFF\r
-#define SPI_DATE_S 0\r
-\r
-\r
-\r
-\r
-#endif /*__SPI_REG_H__ */\r
-\r
-\r
+
+#define SPI_CTRL_REG(i) (REG_SPI_BASE(i) + 0x8)
+/* SPI_WR_BIT_ORDER : R/W ;bitpos:[26] ;default: 1'b0 ; */
+/*description: In command address write-data (MOSI) phases 1: LSB firs 0: MSB first*/
+#define SPI_WR_BIT_ORDER (BIT(26))
+#define SPI_WR_BIT_ORDER_M (BIT(26))
+#define SPI_WR_BIT_ORDER_V 0x1
+#define SPI_WR_BIT_ORDER_S 26
+/* SPI_RD_BIT_ORDER : R/W ;bitpos:[25] ;default: 1'b0 ; */
+/*description: In read-data (MISO) phase 1: LSB first 0: MSB first*/
+#define SPI_RD_BIT_ORDER (BIT(25))
+#define SPI_RD_BIT_ORDER_M (BIT(25))
+#define SPI_RD_BIT_ORDER_V 0x1
+#define SPI_RD_BIT_ORDER_S 25
+/* SPI_FREAD_QIO : R/W ;bitpos:[24] ;default: 1'b0 ; */
+/*description: In the read operations address phase and read-data phase apply
+ 4 signals. 1: enable 0: disable.*/
+#define SPI_FREAD_QIO (BIT(24))
+#define SPI_FREAD_QIO_M (BIT(24))
+#define SPI_FREAD_QIO_V 0x1
+#define SPI_FREAD_QIO_S 24
+/* SPI_FREAD_DIO : R/W ;bitpos:[23] ;default: 1'b0 ; */
+/*description: In the read operations address phase and read-data phase apply
+ 2 signals. 1: enable 0: disable.*/
+#define SPI_FREAD_DIO (BIT(23))
+#define SPI_FREAD_DIO_M (BIT(23))
+#define SPI_FREAD_DIO_V 0x1
+#define SPI_FREAD_DIO_S 23
+/* SPI_WRSR_2B : R/W ;bitpos:[22] ;default: 1'b0 ; */
+/*description: two bytes data will be written to status register when it is
+ set. 1: enable 0: disable.*/
+#define SPI_WRSR_2B (BIT(22))
+#define SPI_WRSR_2B_M (BIT(22))
+#define SPI_WRSR_2B_V 0x1
+#define SPI_WRSR_2B_S 22
+/* SPI_WP_REG : R/W ;bitpos:[21] ;default: 1'b1 ; */
+/*description: Write protect signal output when SPI is idle. 1: output high 0: output low.*/
+#define SPI_WP_REG (BIT(21))
+#define SPI_WP_REG_M (BIT(21))
+#define SPI_WP_REG_V 0x1
+#define SPI_WP_REG_S 21
+/* SPI_FREAD_QUAD : R/W ;bitpos:[20] ;default: 1'b0 ; */
+/*description: In the read operations read-data phase apply 4 signals. 1: enable 0: disable.*/
+#define SPI_FREAD_QUAD (BIT(20))
+#define SPI_FREAD_QUAD_M (BIT(20))
+#define SPI_FREAD_QUAD_V 0x1
+#define SPI_FREAD_QUAD_S 20
+/* SPI_RESANDRES : R/W ;bitpos:[15] ;default: 1'b1 ; */
+/*description: The Device ID is read out to SPI_RD_STATUS register, this bit
+ combine with spi_flash_res bit. 1: enable 0: disable.*/
+#define SPI_RESANDRES (BIT(15))
+#define SPI_RESANDRES_M (BIT(15))
+#define SPI_RESANDRES_V 0x1
+#define SPI_RESANDRES_S 15
+/* SPI_FREAD_DUAL : R/W ;bitpos:[14] ;default: 1'b0 ; */
+/*description: In the read operations read-data phase apply 2 signals. 1: enable 0: disable.*/
+#define SPI_FREAD_DUAL (BIT(14))
+#define SPI_FREAD_DUAL_M (BIT(14))
+#define SPI_FREAD_DUAL_V 0x1
+#define SPI_FREAD_DUAL_S 14
+/* SPI_FASTRD_MODE : R/W ;bitpos:[13] ;default: 1'b1 ; */
+/*description: This bit enable the bits: spi_fread_qio spi_fread_dio spi_fread_qout
+ and spi_fread_dout. 1: enable 0: disable.*/
+#define SPI_FASTRD_MODE (BIT(13))
+#define SPI_FASTRD_MODE_M (BIT(13))
+#define SPI_FASTRD_MODE_V 0x1
+#define SPI_FASTRD_MODE_S 13
+/* SPI_WAIT_FLASH_IDLE_EN : R/W ;bitpos:[12] ;default: 1'b0 ; */
+/*description: wait flash idle when program flash or erase flash. 1: enable 0: disable.*/
+#define SPI_WAIT_FLASH_IDLE_EN (BIT(12))
+#define SPI_WAIT_FLASH_IDLE_EN_M (BIT(12))
+#define SPI_WAIT_FLASH_IDLE_EN_V 0x1
+#define SPI_WAIT_FLASH_IDLE_EN_S 12
+/* SPI_TX_CRC_EN : R/W ;bitpos:[11] ;default: 1'b0 ; */
+/*description: For SPI1 enable crc32 when writing encrypted data to flash.
+ 1: enable 0:disable*/
+#define SPI_TX_CRC_EN (BIT(11))
+#define SPI_TX_CRC_EN_M (BIT(11))
+#define SPI_TX_CRC_EN_V 0x1
+#define SPI_TX_CRC_EN_S 11
+/* SPI_FCS_CRC_EN : R/W ;bitpos:[10] ;default: 1'b1 ; */
+/*description: For SPI1 initialize crc32 module before writing encrypted data
+ to flash. Active low.*/
+#define SPI_FCS_CRC_EN (BIT(10))
+#define SPI_FCS_CRC_EN_M (BIT(10))
+#define SPI_FCS_CRC_EN_V 0x1
+#define SPI_FCS_CRC_EN_S 10
+
+#define SPI_CTRL1_REG(i) (REG_SPI_BASE(i) + 0xC)
+/* SPI_CS_HOLD_DELAY : R/W ;bitpos:[31:28] ;default: 4'h5 ; */
+/*description: SPI cs signal is delayed by spi clock cycles*/
+#define SPI_CS_HOLD_DELAY 0x0000000F
+#define SPI_CS_HOLD_DELAY_M ((SPI_CS_HOLD_DELAY_V)<<(SPI_CS_HOLD_DELAY_S))
+#define SPI_CS_HOLD_DELAY_V 0xF
+#define SPI_CS_HOLD_DELAY_S 28
+/* SPI_CS_HOLD_DELAY_RES : R/W ;bitpos:[27:16] ;default: 12'hfff ; */
+/*description: Delay cycles of resume Flash when resume Flash is enable by spi clock.*/
+#define SPI_CS_HOLD_DELAY_RES 0x00000FFF
+#define SPI_CS_HOLD_DELAY_RES_M ((SPI_CS_HOLD_DELAY_RES_V)<<(SPI_CS_HOLD_DELAY_RES_S))
+#define SPI_CS_HOLD_DELAY_RES_V 0xFFF
+#define SPI_CS_HOLD_DELAY_RES_S 16
+
+#define SPI_RD_STATUS_REG(i) (REG_SPI_BASE(i) + 0x10)
+/* SPI_STATUS_EXT : R/W ;bitpos:[31:24] ;default: 8'h00 ; */
+/*description: In the slave mode,it is the status for master to read out.*/
+#define SPI_STATUS_EXT 0x000000FF
+#define SPI_STATUS_EXT_M ((SPI_STATUS_EXT_V)<<(SPI_STATUS_EXT_S))
+#define SPI_STATUS_EXT_V 0xFF
+#define SPI_STATUS_EXT_S 24
+/* SPI_WB_MODE : R/W ;bitpos:[23:16] ;default: 8'h00 ; */
+/*description: Mode bits in the flash fast read mode, it is combined with spi_fastrd_mode bit.*/
+#define SPI_WB_MODE 0x000000FF
+#define SPI_WB_MODE_M ((SPI_WB_MODE_V)<<(SPI_WB_MODE_S))
+#define SPI_WB_MODE_V 0xFF
+#define SPI_WB_MODE_S 16
+/* SPI_STATUS : R/W ;bitpos:[15:0] ;default: 16'b0 ; */
+/*description: In the slave mode, it is the status for master to read out.*/
+#define SPI_STATUS 0x0000FFFF
+#define SPI_STATUS_M ((SPI_STATUS_V)<<(SPI_STATUS_S))
+#define SPI_STATUS_V 0xFFFF
+#define SPI_STATUS_S 0
+
+#define SPI_CTRL2_REG(i) (REG_SPI_BASE(i) + 0x14)
+/* SPI_CS_DELAY_NUM : R/W ;bitpos:[31:28] ;default: 4'h0 ; */
+/*description: spi_cs signal is delayed by system clock cycles*/
+#define SPI_CS_DELAY_NUM 0x0000000F
+#define SPI_CS_DELAY_NUM_M ((SPI_CS_DELAY_NUM_V)<<(SPI_CS_DELAY_NUM_S))
+#define SPI_CS_DELAY_NUM_V 0xF
+#define SPI_CS_DELAY_NUM_S 28
+/* SPI_CS_DELAY_MODE : R/W ;bitpos:[27:26] ;default: 2'h0 ; */
+/*description: spi_cs signal is delayed by spi_clk . 0: zero 1: if spi_ck_out_edge
+ or spi_ck_i_edge is set 1 delayed by half cycle else delayed by one cycle 2: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by one cycle else delayed by half cycle 3: delayed one cycle*/
+#define SPI_CS_DELAY_MODE 0x00000003
+#define SPI_CS_DELAY_MODE_M ((SPI_CS_DELAY_MODE_V)<<(SPI_CS_DELAY_MODE_S))
+#define SPI_CS_DELAY_MODE_V 0x3
+#define SPI_CS_DELAY_MODE_S 26
+/* SPI_MOSI_DELAY_NUM : R/W ;bitpos:[25:23] ;default: 3'h0 ; */
+/*description: MOSI signals are delayed by system clock cycles*/
+#define SPI_MOSI_DELAY_NUM 0x00000007
+#define SPI_MOSI_DELAY_NUM_M ((SPI_MOSI_DELAY_NUM_V)<<(SPI_MOSI_DELAY_NUM_S))
+#define SPI_MOSI_DELAY_NUM_V 0x7
+#define SPI_MOSI_DELAY_NUM_S 23
+/* SPI_MOSI_DELAY_MODE : R/W ;bitpos:[22:21] ;default: 2'h0 ; */
+/*description: MOSI signals are delayed by spi_clk. 0: zero 1: if spi_ck_out_edge
+ or spi_ck_i_edge is set 1 delayed by half cycle else delayed by one cycle 2: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by one cycle else delayed by half cycle 3: delayed one cycle*/
+#define SPI_MOSI_DELAY_MODE 0x00000003
+#define SPI_MOSI_DELAY_MODE_M ((SPI_MOSI_DELAY_MODE_V)<<(SPI_MOSI_DELAY_MODE_S))
+#define SPI_MOSI_DELAY_MODE_V 0x3
+#define SPI_MOSI_DELAY_MODE_S 21
+/* SPI_MISO_DELAY_NUM : R/W ;bitpos:[20:18] ;default: 3'h0 ; */
+/*description: MISO signals are delayed by system clock cycles*/
+#define SPI_MISO_DELAY_NUM 0x00000007
+#define SPI_MISO_DELAY_NUM_M ((SPI_MISO_DELAY_NUM_V)<<(SPI_MISO_DELAY_NUM_S))
+#define SPI_MISO_DELAY_NUM_V 0x7
+#define SPI_MISO_DELAY_NUM_S 18
+/* SPI_MISO_DELAY_MODE : R/W ;bitpos:[17:16] ;default: 2'h0 ; */
+/*description: MISO signals are delayed by spi_clk. 0: zero 1: if spi_ck_out_edge
+ or spi_ck_i_edge is set 1 delayed by half cycle else delayed by one cycle 2: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by one cycle else delayed by half cycle 3: delayed one cycle*/
+#define SPI_MISO_DELAY_MODE 0x00000003
+#define SPI_MISO_DELAY_MODE_M ((SPI_MISO_DELAY_MODE_V)<<(SPI_MISO_DELAY_MODE_S))
+#define SPI_MISO_DELAY_MODE_V 0x3
+#define SPI_MISO_DELAY_MODE_S 16
+/* SPI_CK_OUT_HIGH_MODE : R/W ;bitpos:[15:12] ;default: 4'h0 ; */
+/*description: modify spi clock duty ratio when the value is lager than 8,
+ the bits are combined with spi_clkcnt_N bits and spi_clkcnt_H bits.*/
+#define SPI_CK_OUT_HIGH_MODE 0x0000000F
+#define SPI_CK_OUT_HIGH_MODE_M ((SPI_CK_OUT_HIGH_MODE_V)<<(SPI_CK_OUT_HIGH_MODE_S))
+#define SPI_CK_OUT_HIGH_MODE_V 0xF
+#define SPI_CK_OUT_HIGH_MODE_S 12
+/* SPI_CK_OUT_LOW_MODE : R/W ;bitpos:[11:8] ;default: 4'h0 ; */
+/*description: modify spi clock duty ratio when the value is lager than 8,
+ the bits are combined with spi_clkcnt_N bits and spi_clkcnt_L bits.*/
+#define SPI_CK_OUT_LOW_MODE 0x0000000F
+#define SPI_CK_OUT_LOW_MODE_M ((SPI_CK_OUT_LOW_MODE_V)<<(SPI_CK_OUT_LOW_MODE_S))
+#define SPI_CK_OUT_LOW_MODE_V 0xF
+#define SPI_CK_OUT_LOW_MODE_S 8
+/* SPI_HOLD_TIME : R/W ;bitpos:[7:4] ;default: 4'h1 ; */
+/*description: delay cycles of cs pin by spi clock, this bits combined with spi_cs_hold bit.*/
+#define SPI_HOLD_TIME 0x0000000F
+#define SPI_HOLD_TIME_M ((SPI_HOLD_TIME_V)<<(SPI_HOLD_TIME_S))
+#define SPI_HOLD_TIME_V 0xF
+#define SPI_HOLD_TIME_S 4
+/* SPI_SETUP_TIME : R/W ;bitpos:[3:0] ;default: 4'h1 ; */
+/*description: (cycles-1) of ¡°prepare¡± phase by spi clock, this bits combined
+ with spi_cs_setup bit.*/
+#define SPI_SETUP_TIME 0x0000000F
+#define SPI_SETUP_TIME_M ((SPI_SETUP_TIME_V)<<(SPI_SETUP_TIME_S))
+#define SPI_SETUP_TIME_V 0xF
+#define SPI_SETUP_TIME_S 0
+
+#define SPI_CLOCK_REG(i) (REG_SPI_BASE(i) + 0x18)
+/* SPI_CLK_EQU_SYSCLK : R/W ;bitpos:[31] ;default: 1'b1 ; */
+/*description: In the master mode 1: spi_clk is eqaul to system 0: spi_clk is
+ divided from system clock.*/
+#define SPI_CLK_EQU_SYSCLK (BIT(31))
+#define SPI_CLK_EQU_SYSCLK_M (BIT(31))
+#define SPI_CLK_EQU_SYSCLK_V 0x1
+#define SPI_CLK_EQU_SYSCLK_S 31
+/* SPI_CLKDIV_PRE : R/W ;bitpos:[30:18] ;default: 13'b0 ; */
+/*description: In the master mode it is pre-divider of spi_clk.*/
+#define SPI_CLKDIV_PRE 0x00001FFF
+#define SPI_CLKDIV_PRE_M ((SPI_CLKDIV_PRE_V)<<(SPI_CLKDIV_PRE_S))
+#define SPI_CLKDIV_PRE_V 0x1FFF
+#define SPI_CLKDIV_PRE_S 18
+/* SPI_CLKCNT_N : R/W ;bitpos:[17:12] ;default: 6'h3 ; */
+/*description: In the master mode it is the divider of spi_clk. So spi_clk frequency
+ is system/(spi_clkdiv_pre+1)/(spi_clkcnt_N+1)*/
+#define SPI_CLKCNT_N 0x0000003F
+#define SPI_CLKCNT_N_M ((SPI_CLKCNT_N_V)<<(SPI_CLKCNT_N_S))
+#define SPI_CLKCNT_N_V 0x3F
+#define SPI_CLKCNT_N_S 12
+/* SPI_CLKCNT_H : R/W ;bitpos:[11:6] ;default: 6'h1 ; */
+/*description: In the master mode it must be floor((spi_clkcnt_N+1)/2-1). In
+ the slave mode it must be 0.*/
+#define SPI_CLKCNT_H 0x0000003F
+#define SPI_CLKCNT_H_M ((SPI_CLKCNT_H_V)<<(SPI_CLKCNT_H_S))
+#define SPI_CLKCNT_H_V 0x3F
+#define SPI_CLKCNT_H_S 6
+/* SPI_CLKCNT_L : R/W ;bitpos:[5:0] ;default: 6'h3 ; */
+/*description: In the master mode it must be equal to spi_clkcnt_N. In the slave
+ mode it must be 0.*/
+#define SPI_CLKCNT_L 0x0000003F
+#define SPI_CLKCNT_L_M ((SPI_CLKCNT_L_V)<<(SPI_CLKCNT_L_S))
+#define SPI_CLKCNT_L_V 0x3F
+#define SPI_CLKCNT_L_S 0
+
+#define SPI_USER_REG(i) (REG_SPI_BASE(i) + 0x1C)
+/* SPI_USR_COMMAND : R/W ;bitpos:[31] ;default: 1'b1 ; */
+/*description: This bit enable the command phase of an operation.*/
+#define SPI_USR_COMMAND (BIT(31))
+#define SPI_USR_COMMAND_M (BIT(31))
+#define SPI_USR_COMMAND_V 0x1
+#define SPI_USR_COMMAND_S 31
+/* SPI_USR_ADDR : R/W ;bitpos:[30] ;default: 1'b0 ; */
+/*description: This bit enable the address phase of an operation.*/
+#define SPI_USR_ADDR (BIT(30))
+#define SPI_USR_ADDR_M (BIT(30))
+#define SPI_USR_ADDR_V 0x1
+#define SPI_USR_ADDR_S 30
+/* SPI_USR_DUMMY : R/W ;bitpos:[29] ;default: 1'b0 ; */
+/*description: This bit enable the dummy phase of an operation.*/
+#define SPI_USR_DUMMY (BIT(29))
+#define SPI_USR_DUMMY_M (BIT(29))
+#define SPI_USR_DUMMY_V 0x1
+#define SPI_USR_DUMMY_S 29
+/* SPI_USR_MISO : R/W ;bitpos:[28] ;default: 1'b0 ; */
+/*description: This bit enable the read-data phase of an operation.*/
+#define SPI_USR_MISO (BIT(28))
+#define SPI_USR_MISO_M (BIT(28))
+#define SPI_USR_MISO_V 0x1
+#define SPI_USR_MISO_S 28
+/* SPI_USR_MOSI : R/W ;bitpos:[27] ;default: 1'b0 ; */
+/*description: This bit enable the write-data phase of an operation.*/
+#define SPI_USR_MOSI (BIT(27))
+#define SPI_USR_MOSI_M (BIT(27))
+#define SPI_USR_MOSI_V 0x1
+#define SPI_USR_MOSI_S 27
+/* SPI_USR_DUMMY_IDLE : R/W ;bitpos:[26] ;default: 1'b0 ; */
+/*description: spi clock is disable in dummy phase when the bit is enable.*/
+#define SPI_USR_DUMMY_IDLE (BIT(26))
+#define SPI_USR_DUMMY_IDLE_M (BIT(26))
+#define SPI_USR_DUMMY_IDLE_V 0x1
+#define SPI_USR_DUMMY_IDLE_S 26
+/* SPI_USR_MOSI_HIGHPART : R/W ;bitpos:[25] ;default: 1'b0 ; */
+/*description: write-data phase only access to high-part of the buffer spi_w8~spi_w15.
+ 1: enable 0: disable.*/
+#define SPI_USR_MOSI_HIGHPART (BIT(25))
+#define SPI_USR_MOSI_HIGHPART_M (BIT(25))
+#define SPI_USR_MOSI_HIGHPART_V 0x1
+#define SPI_USR_MOSI_HIGHPART_S 25
+/* SPI_USR_MISO_HIGHPART : R/W ;bitpos:[24] ;default: 1'b0 ; */
+/*description: read-data phase only access to high-part of the buffer spi_w8~spi_w15.
+ 1: enable 0: disable.*/
+#define SPI_USR_MISO_HIGHPART (BIT(24))
+#define SPI_USR_MISO_HIGHPART_M (BIT(24))
+#define SPI_USR_MISO_HIGHPART_V 0x1
+#define SPI_USR_MISO_HIGHPART_S 24
+/* SPI_USR_PREP_HOLD : R/W ;bitpos:[23] ;default: 1'b0 ; */
+/*description: spi is hold at prepare state the bit combined with spi_usr_hold_pol bit.*/
+#define SPI_USR_PREP_HOLD (BIT(23))
+#define SPI_USR_PREP_HOLD_M (BIT(23))
+#define SPI_USR_PREP_HOLD_V 0x1
+#define SPI_USR_PREP_HOLD_S 23
+/* SPI_USR_CMD_HOLD : R/W ;bitpos:[22] ;default: 1'b0 ; */
+/*description: spi is hold at command state the bit combined with spi_usr_hold_pol bit.*/
+#define SPI_USR_CMD_HOLD (BIT(22))
+#define SPI_USR_CMD_HOLD_M (BIT(22))
+#define SPI_USR_CMD_HOLD_V 0x1
+#define SPI_USR_CMD_HOLD_S 22
+/* SPI_USR_ADDR_HOLD : R/W ;bitpos:[21] ;default: 1'b0 ; */
+/*description: spi is hold at address state the bit combined with spi_usr_hold_pol bit.*/
+#define SPI_USR_ADDR_HOLD (BIT(21))
+#define SPI_USR_ADDR_HOLD_M (BIT(21))
+#define SPI_USR_ADDR_HOLD_V 0x1
+#define SPI_USR_ADDR_HOLD_S 21
+/* SPI_USR_DUMMY_HOLD : R/W ;bitpos:[20] ;default: 1'b0 ; */
+/*description: spi is hold at dummy state the bit combined with spi_usr_hold_pol bit.*/
+#define SPI_USR_DUMMY_HOLD (BIT(20))
+#define SPI_USR_DUMMY_HOLD_M (BIT(20))
+#define SPI_USR_DUMMY_HOLD_V 0x1
+#define SPI_USR_DUMMY_HOLD_S 20
+/* SPI_USR_DIN_HOLD : R/W ;bitpos:[19] ;default: 1'b0 ; */
+/*description: spi is hold at data in state the bit combined with spi_usr_hold_pol bit.*/
+#define SPI_USR_DIN_HOLD (BIT(19))
+#define SPI_USR_DIN_HOLD_M (BIT(19))
+#define SPI_USR_DIN_HOLD_V 0x1
+#define SPI_USR_DIN_HOLD_S 19
+/* SPI_USR_DOUT_HOLD : R/W ;bitpos:[18] ;default: 1'b0 ; */
+/*description: spi is hold at data out state the bit combined with spi_usr_hold_pol bit.*/
+#define SPI_USR_DOUT_HOLD (BIT(18))
+#define SPI_USR_DOUT_HOLD_M (BIT(18))
+#define SPI_USR_DOUT_HOLD_V 0x1
+#define SPI_USR_DOUT_HOLD_S 18
+/* SPI_USR_HOLD_POL : R/W ;bitpos:[17] ;default: 1'b0 ; */
+/*description: It is combined with hold bits to set the polarity of spi hold
+ line 1: spi will be held when spi hold line is high 0: spi will be held when spi hold line is low*/
+#define SPI_USR_HOLD_POL (BIT(17))
+#define SPI_USR_HOLD_POL_M (BIT(17))
+#define SPI_USR_HOLD_POL_V 0x1
+#define SPI_USR_HOLD_POL_S 17
+/* SPI_SIO : R/W ;bitpos:[16] ;default: 1'b0 ; */
+/*description: Set the bit to enable 3-line half duplex communication mosi
+ and miso signals share the same pin. 1: enable 0: disable.*/
+#define SPI_SIO (BIT(16))
+#define SPI_SIO_M (BIT(16))
+#define SPI_SIO_V 0x1
+#define SPI_SIO_S 16
+/* SPI_FWRITE_QIO : R/W ;bitpos:[15] ;default: 1'b0 ; */
+/*description: In the write operations address phase and read-data phase apply 4 signals.*/
+#define SPI_FWRITE_QIO (BIT(15))
+#define SPI_FWRITE_QIO_M (BIT(15))
+#define SPI_FWRITE_QIO_V 0x1
+#define SPI_FWRITE_QIO_S 15
+/* SPI_FWRITE_DIO : R/W ;bitpos:[14] ;default: 1'b0 ; */
+/*description: In the write operations address phase and read-data phase apply 2 signals.*/
+#define SPI_FWRITE_DIO (BIT(14))
+#define SPI_FWRITE_DIO_M (BIT(14))
+#define SPI_FWRITE_DIO_V 0x1
+#define SPI_FWRITE_DIO_S 14
+/* SPI_FWRITE_QUAD : R/W ;bitpos:[13] ;default: 1'b0 ; */
+/*description: In the write operations read-data phase apply 4 signals*/
+#define SPI_FWRITE_QUAD (BIT(13))
+#define SPI_FWRITE_QUAD_M (BIT(13))
+#define SPI_FWRITE_QUAD_V 0x1
+#define SPI_FWRITE_QUAD_S 13
+/* SPI_FWRITE_DUAL : R/W ;bitpos:[12] ;default: 1'b0 ; */
+/*description: In the write operations read-data phase apply 2 signals*/
+#define SPI_FWRITE_DUAL (BIT(12))
+#define SPI_FWRITE_DUAL_M (BIT(12))
+#define SPI_FWRITE_DUAL_V 0x1
+#define SPI_FWRITE_DUAL_S 12
+/* SPI_WR_BYTE_ORDER : R/W ;bitpos:[11] ;default: 1'b0 ; */
+/*description: In command address write-data (MOSI) phases 1: big-endian 0: litte_endian*/
+#define SPI_WR_BYTE_ORDER (BIT(11))
+#define SPI_WR_BYTE_ORDER_M (BIT(11))
+#define SPI_WR_BYTE_ORDER_V 0x1
+#define SPI_WR_BYTE_ORDER_S 11
+/* SPI_RD_BYTE_ORDER : R/W ;bitpos:[10] ;default: 1'b0 ; */
+/*description: In read-data (MISO) phase 1: big-endian 0: little_endian*/
+#define SPI_RD_BYTE_ORDER (BIT(10))
+#define SPI_RD_BYTE_ORDER_M (BIT(10))
+#define SPI_RD_BYTE_ORDER_V 0x1
+#define SPI_RD_BYTE_ORDER_S 10
+/* SPI_CK_OUT_EDGE : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: the bit combined with spi_mosi_delay_mode bits to set mosi signal delay mode.*/
+#define SPI_CK_OUT_EDGE (BIT(7))
+#define SPI_CK_OUT_EDGE_M (BIT(7))
+#define SPI_CK_OUT_EDGE_V 0x1
+#define SPI_CK_OUT_EDGE_S 7
+/* SPI_CK_I_EDGE : R/W ;bitpos:[6] ;default: 1'b1 ; */
+/*description: In the slave mode the bit is same as spi_ck_out_edge in master
+ mode. It is combined with spi_miso_delay_mode bits.*/
+#define SPI_CK_I_EDGE (BIT(6))
+#define SPI_CK_I_EDGE_M (BIT(6))
+#define SPI_CK_I_EDGE_V 0x1
+#define SPI_CK_I_EDGE_S 6
+/* SPI_CS_SETUP : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: spi cs is enable when spi is in ¡°prepare¡± phase. 1: enable 0: disable.*/
+#define SPI_CS_SETUP (BIT(5))
+#define SPI_CS_SETUP_M (BIT(5))
+#define SPI_CS_SETUP_V 0x1
+#define SPI_CS_SETUP_S 5
+/* SPI_CS_HOLD : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: spi cs keep low when spi is in ¡°done¡± phase. 1: enable 0: disable.*/
+#define SPI_CS_HOLD (BIT(4))
+#define SPI_CS_HOLD_M (BIT(4))
+#define SPI_CS_HOLD_V 0x1
+#define SPI_CS_HOLD_S 4
+/* SPI_DOUTDIN : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: Set the bit to enable full duplex communication. 1: enable 0: disable.*/
+#define SPI_DOUTDIN (BIT(0))
+#define SPI_DOUTDIN_M (BIT(0))
+#define SPI_DOUTDIN_V 0x1
+#define SPI_DOUTDIN_S 0
+
+#define SPI_USER1_REG(i) (REG_SPI_BASE(i) + 0x20)
+/* SPI_USR_ADDR_BITLEN : RO ;bitpos:[31:26] ;default: 6'd23 ; */
+/*description: The length in bits of address phase. The register value shall be (bit_num-1).*/
+#define SPI_USR_ADDR_BITLEN 0x0000003F
+#define SPI_USR_ADDR_BITLEN_M ((SPI_USR_ADDR_BITLEN_V)<<(SPI_USR_ADDR_BITLEN_S))
+#define SPI_USR_ADDR_BITLEN_V 0x3F
+#define SPI_USR_ADDR_BITLEN_S 26
+/* SPI_USR_DUMMY_CYCLELEN : R/W ;bitpos:[7:0] ;default: 8'd7 ; */
+/*description: The length in spi_clk cycles of dummy phase. The register value
+ shall be (cycle_num-1).*/
+#define SPI_USR_DUMMY_CYCLELEN 0x000000FF
+#define SPI_USR_DUMMY_CYCLELEN_M ((SPI_USR_DUMMY_CYCLELEN_V)<<(SPI_USR_DUMMY_CYCLELEN_S))
+#define SPI_USR_DUMMY_CYCLELEN_V 0xFF
+#define SPI_USR_DUMMY_CYCLELEN_S 0
+
+#define SPI_USER2_REG(i) (REG_SPI_BASE(i) + 0x24)
+/* SPI_USR_COMMAND_BITLEN : R/W ;bitpos:[31:28] ;default: 4'd7 ; */
+/*description: The length in bits of command phase. The register value shall be (bit_num-1)*/
+#define SPI_USR_COMMAND_BITLEN 0x0000000F
+#define SPI_USR_COMMAND_BITLEN_M ((SPI_USR_COMMAND_BITLEN_V)<<(SPI_USR_COMMAND_BITLEN_S))
+#define SPI_USR_COMMAND_BITLEN_V 0xF
+#define SPI_USR_COMMAND_BITLEN_S 28
+/* SPI_USR_COMMAND_VALUE : R/W ;bitpos:[15:0] ;default: 16'b0 ; */
+/*description: The value of command.*/
+#define SPI_USR_COMMAND_VALUE 0x0000FFFF
+#define SPI_USR_COMMAND_VALUE_M ((SPI_USR_COMMAND_VALUE_V)<<(SPI_USR_COMMAND_VALUE_S))
+#define SPI_USR_COMMAND_VALUE_V 0xFFFF
+#define SPI_USR_COMMAND_VALUE_S 0
+
+#define SPI_MOSI_DLEN_REG(i) (REG_SPI_BASE(i) + 0x28)
+/* SPI_USR_MOSI_DBITLEN : R/W ;bitpos:[23:0] ;default: 24'h0 ; */
+/*description: The length in bits of write-data. The register value shall be (bit_num-1).*/
+#define SPI_USR_MOSI_DBITLEN 0x00FFFFFF
+#define SPI_USR_MOSI_DBITLEN_M ((SPI_USR_MOSI_DBITLEN_V)<<(SPI_USR_MOSI_DBITLEN_S))
+#define SPI_USR_MOSI_DBITLEN_V 0xFFFFFF
+#define SPI_USR_MOSI_DBITLEN_S 0
+
+#define SPI_MISO_DLEN_REG(i) (REG_SPI_BASE(i) + 0x2C)
+/* SPI_USR_MISO_DBITLEN : R/W ;bitpos:[23:0] ;default: 24'h0 ; */
+/*description: The length in bits of read-data. The register value shall be (bit_num-1).*/
+#define SPI_USR_MISO_DBITLEN 0x00FFFFFF
+#define SPI_USR_MISO_DBITLEN_M ((SPI_USR_MISO_DBITLEN_V)<<(SPI_USR_MISO_DBITLEN_S))
+#define SPI_USR_MISO_DBITLEN_V 0xFFFFFF
+#define SPI_USR_MISO_DBITLEN_S 0
+
+#define SPI_SLV_WR_STATUS_REG(i) (REG_SPI_BASE(i) + 0x30)
+/* SPI_SLV_WR_ST : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: In the slave mode this register are the status register for the
+ master to write into. In the master mode this register are the higher 32bits in the 64 bits address condition.*/
+#define SPI_SLV_WR_ST 0xFFFFFFFF
+#define SPI_SLV_WR_ST_M ((SPI_SLV_WR_ST_V)<<(SPI_SLV_WR_ST_S))
+#define SPI_SLV_WR_ST_V 0xFFFFFFFF
+#define SPI_SLV_WR_ST_S 0
+
+#define SPI_PIN_REG(i) (REG_SPI_BASE(i) + 0x34)
+/* SPI_CS_KEEP_ACTIVE : R/W ;bitpos:[30] ;default: 1'b0 ; */
+/*description: spi cs line keep low when the bit is set.*/
+#define SPI_CS_KEEP_ACTIVE (BIT(30))
+#define SPI_CS_KEEP_ACTIVE_M (BIT(30))
+#define SPI_CS_KEEP_ACTIVE_V 0x1
+#define SPI_CS_KEEP_ACTIVE_S 30
+/* SPI_CK_IDLE_EDGE : R/W ;bitpos:[29] ;default: 1'b0 ; */
+/*description: 1: spi clk line is high when idle 0: spi clk line is low when idle*/
+#define SPI_CK_IDLE_EDGE (BIT(29))
+#define SPI_CK_IDLE_EDGE_M (BIT(29))
+#define SPI_CK_IDLE_EDGE_V 0x1
+#define SPI_CK_IDLE_EDGE_S 29
+/* SPI_MASTER_CK_SEL : R/W ;bitpos:[13:11] ;default: 3'b0 ; */
+/*description: In the master mode spi cs line is enable as spi clk it is combined
+ with spi_cs0_dis spi_cs1_dis spi_cs2_dis.*/
+#define SPI_MASTER_CK_SEL 0x00000007
+#define SPI_MASTER_CK_SEL_M ((SPI_MASTER_CK_SEL_V)<<(SPI_MASTER_CK_SEL_S))
+#define SPI_MASTER_CK_SEL_V 0x07
+#define SPI_MASTER_CK_SEL_S 11
+/* SPI_MASTER_CS_POL : R/W ;bitpos:[8:6] ;default: 3'b0 ; */
+/*description: In the master mode the bits are the polarity of spi cs line
+ the value is equivalent to spi_cs ^ spi_master_cs_pol.*/
+#define SPI_MASTER_CS_POL 0x00000007
+#define SPI_MASTER_CS_POL_M ((SPI_MASTER_CS_POL_V)<<(SPI_MASTER_CS_POL_S))
+#define SPI_MASTER_CS_POL_V 0x7
+#define SPI_MASTER_CS_POL_S 6
+/* SPI_CK_DIS : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: 1: spi clk out disable 0: spi clk out enable*/
+#define SPI_CK_DIS (BIT(5))
+#define SPI_CK_DIS_M (BIT(5))
+#define SPI_CK_DIS_V 0x1
+#define SPI_CK_DIS_S 5
+/* SPI_CS2_DIS : R/W ;bitpos:[2] ;default: 1'b1 ; */
+/*description: SPI CS2 pin enable, 1: disable CS2, 0: spi_cs2 signal is from/to CS2 pin*/
+#define SPI_CS2_DIS (BIT(2))
+#define SPI_CS2_DIS_M (BIT(2))
+#define SPI_CS2_DIS_V 0x1
+#define SPI_CS2_DIS_S 2
+/* SPI_CS1_DIS : R/W ;bitpos:[1] ;default: 1'b1 ; */
+/*description: SPI CS1 pin enable, 1: disable CS1, 0: spi_cs1 signal is from/to CS1 pin*/
+#define SPI_CS1_DIS (BIT(1))
+#define SPI_CS1_DIS_M (BIT(1))
+#define SPI_CS1_DIS_V 0x1
+#define SPI_CS1_DIS_S 1
+/* SPI_CS0_DIS : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: SPI CS0 pin enable, 1: disable CS0, 0: spi_cs0 signal is from/to CS0 pin*/
+#define SPI_CS0_DIS (BIT(0))
+#define SPI_CS0_DIS_M (BIT(0))
+#define SPI_CS0_DIS_V 0x1
+#define SPI_CS0_DIS_S 0
+
+#define SPI_SLAVE_REG(i) (REG_SPI_BASE(i) + 0x38)
+/* SPI_SYNC_RESET : R/W ;bitpos:[31] ;default: 1'b0 ; */
+/*description: Software reset enable, reset the spi clock line cs line and data lines.*/
+#define SPI_SYNC_RESET (BIT(31))
+#define SPI_SYNC_RESET_M (BIT(31))
+#define SPI_SYNC_RESET_V 0x1
+#define SPI_SYNC_RESET_S 31
+/* SPI_SLAVE_MODE : R/W ;bitpos:[30] ;default: 1'b0 ; */
+/*description: 1: slave mode 0: master mode.*/
+#define SPI_SLAVE_MODE (BIT(30))
+#define SPI_SLAVE_MODE_M (BIT(30))
+#define SPI_SLAVE_MODE_V 0x1
+#define SPI_SLAVE_MODE_S 30
+/* SPI_SLV_WR_RD_BUF_EN : R/W ;bitpos:[29] ;default: 1'b0 ; */
+/*description: write and read buffer enable in the slave mode*/
+#define SPI_SLV_WR_RD_BUF_EN (BIT(29))
+#define SPI_SLV_WR_RD_BUF_EN_M (BIT(29))
+#define SPI_SLV_WR_RD_BUF_EN_V 0x1
+#define SPI_SLV_WR_RD_BUF_EN_S 29
+/* SPI_SLV_WR_RD_STA_EN : R/W ;bitpos:[28] ;default: 1'b0 ; */
+/*description: write and read status enable in the slave mode*/
+#define SPI_SLV_WR_RD_STA_EN (BIT(28))
+#define SPI_SLV_WR_RD_STA_EN_M (BIT(28))
+#define SPI_SLV_WR_RD_STA_EN_V 0x1
+#define SPI_SLV_WR_RD_STA_EN_S 28
+/* SPI_SLV_CMD_DEFINE : R/W ;bitpos:[27] ;default: 1'b0 ; */
+/*description: 1: slave mode commands are defined in SPI_SLAVE3. 0: slave mode
+ commands are fixed as: 1: write-status 2: write-buffer and 3: read-buffer.*/
+#define SPI_SLV_CMD_DEFINE (BIT(27))
+#define SPI_SLV_CMD_DEFINE_M (BIT(27))
+#define SPI_SLV_CMD_DEFINE_V 0x1
+#define SPI_SLV_CMD_DEFINE_S 27
+/* SPI_TRANS_CNT : RO ;bitpos:[26:23] ;default: 4'b0 ; */
+/*description: The operations counter in both the master mode and the slave
+ mode. 4: read-status*/
+#define SPI_TRANS_CNT 0x0000000F
+#define SPI_TRANS_CNT_M ((SPI_TRANS_CNT_V)<<(SPI_TRANS_CNT_S))
+#define SPI_TRANS_CNT_V 0xF
+#define SPI_TRANS_CNT_S 23
+/* SPI_SLV_LAST_STATE : RO ;bitpos:[22:20] ;default: 3'b0 ; */
+/*description: In the slave mode it is the state of spi state machine.*/
+#define SPI_SLV_LAST_STATE 0x00000007
+#define SPI_SLV_LAST_STATE_M ((SPI_SLV_LAST_STATE_V)<<(SPI_SLV_LAST_STATE_S))
+#define SPI_SLV_LAST_STATE_V 0x7
+#define SPI_SLV_LAST_STATE_S 20
+/* SPI_SLV_LAST_COMMAND : RO ;bitpos:[19:17] ;default: 3'b0 ; */
+/*description: In the slave mode it is the value of command.*/
+#define SPI_SLV_LAST_COMMAND 0x00000007
+#define SPI_SLV_LAST_COMMAND_M ((SPI_SLV_LAST_COMMAND_V)<<(SPI_SLV_LAST_COMMAND_S))
+#define SPI_SLV_LAST_COMMAND_V 0x7
+#define SPI_SLV_LAST_COMMAND_S 17
+/* SPI_CS_I_MODE : R/W ;bitpos:[11:10] ;default: 2'b0 ; */
+/*description: In the slave mode this bits used to synchronize the input spi
+ cs signal and eliminate spi cs jitter.*/
+#define SPI_CS_I_MODE 0x00000003
+#define SPI_CS_I_MODE_M ((SPI_CS_I_MODE_V)<<(SPI_CS_I_MODE_S))
+#define SPI_CS_I_MODE_V 0x3
+#define SPI_CS_I_MODE_S 10
+/* SPI_INT_EN : R/W ;bitpos:[9:5] ;default: 5'b1_0000 ; */
+/*description: Interrupt enable bits for the below 5 sources*/
+#define SPI_INT_EN 0x0000001F
+#define SPI_INT_EN_M ((SPI_INT_EN_V)<<(SPI_INT_EN_S))
+#define SPI_INT_EN_V 0x1F
+#define SPI_INT_EN_S 5
+/* SPI_TRANS_DONE : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: The interrupt raw bit for the completion of any operation in
+ both the master mode and the slave mode.*/
+#define SPI_TRANS_DONE (BIT(4))
+#define SPI_TRANS_DONE_M (BIT(4))
+#define SPI_TRANS_DONE_V 0x1
+#define SPI_TRANS_DONE_S 4
+/* SPI_SLV_WR_STA_DONE : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: The interrupt raw bit for the completion of write-status operation
+ in the slave mode.*/
+#define SPI_SLV_WR_STA_DONE (BIT(3))
+#define SPI_SLV_WR_STA_DONE_M (BIT(3))
+#define SPI_SLV_WR_STA_DONE_V 0x1
+#define SPI_SLV_WR_STA_DONE_S 3
+/* SPI_SLV_RD_STA_DONE : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: The interrupt raw bit for the completion of read-status operation
+ in the slave mode.*/
+#define SPI_SLV_RD_STA_DONE (BIT(2))
+#define SPI_SLV_RD_STA_DONE_M (BIT(2))
+#define SPI_SLV_RD_STA_DONE_V 0x1
+#define SPI_SLV_RD_STA_DONE_S 2
+/* SPI_SLV_WR_BUF_DONE : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: The interrupt raw bit for the completion of write-buffer operation
+ in the slave mode.*/
+#define SPI_SLV_WR_BUF_DONE (BIT(1))
+#define SPI_SLV_WR_BUF_DONE_M (BIT(1))
+#define SPI_SLV_WR_BUF_DONE_V 0x1
+#define SPI_SLV_WR_BUF_DONE_S 1
+/* SPI_SLV_RD_BUF_DONE : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: The interrupt raw bit for the completion of read-buffer operation
+ in the slave mode.*/
+#define SPI_SLV_RD_BUF_DONE (BIT(0))
+#define SPI_SLV_RD_BUF_DONE_M (BIT(0))
+#define SPI_SLV_RD_BUF_DONE_V 0x1
+#define SPI_SLV_RD_BUF_DONE_S 0
+
+#define SPI_SLAVE1_REG(i) (REG_SPI_BASE(i) + 0x3C)
+/* SPI_SLV_STATUS_BITLEN : R/W ;bitpos:[31:27] ;default: 5'b0 ; */
+/*description: In the slave mode it is the length of status bit.*/
+#define SPI_SLV_STATUS_BITLEN 0x0000001F
+#define SPI_SLV_STATUS_BITLEN_M ((SPI_SLV_STATUS_BITLEN_V)<<(SPI_SLV_STATUS_BITLEN_S))
+#define SPI_SLV_STATUS_BITLEN_V 0x1F
+#define SPI_SLV_STATUS_BITLEN_S 27
+/* SPI_SLV_STATUS_FAST_EN : R/W ;bitpos:[26] ;default: 1'b0 ; */
+/*description: In the slave mode enable fast read status.*/
+#define SPI_SLV_STATUS_FAST_EN (BIT(26))
+#define SPI_SLV_STATUS_FAST_EN_M (BIT(26))
+#define SPI_SLV_STATUS_FAST_EN_V 0x1
+#define SPI_SLV_STATUS_FAST_EN_S 26
+/* SPI_SLV_STATUS_READBACK : R/W ;bitpos:[25] ;default: 1'b1 ; */
+/*description: In the slave mode 1:read register of SPI_SLV_WR_STATUS 0: read
+ register of SPI_RD_STATUS.*/
+#define SPI_SLV_STATUS_READBACK (BIT(25))
+#define SPI_SLV_STATUS_READBACK_M (BIT(25))
+#define SPI_SLV_STATUS_READBACK_V 0x1
+#define SPI_SLV_STATUS_READBACK_S 25
+/* SPI_SLV_RD_ADDR_BITLEN : R/W ;bitpos:[15:10] ;default: 6'h0 ; */
+/*description: In the slave mode it is the address length in bits for read-buffer
+ operation. The register value shall be (bit_num-1).*/
+#define SPI_SLV_RD_ADDR_BITLEN 0x0000003F
+#define SPI_SLV_RD_ADDR_BITLEN_M ((SPI_SLV_RD_ADDR_BITLEN_V)<<(SPI_SLV_RD_ADDR_BITLEN_S))
+#define SPI_SLV_RD_ADDR_BITLEN_V 0x3F
+#define SPI_SLV_RD_ADDR_BITLEN_S 10
+/* SPI_SLV_WR_ADDR_BITLEN : R/W ;bitpos:[9:4] ;default: 6'h0 ; */
+/*description: In the slave mode it is the address length in bits for write-buffer
+ operation. The register value shall be (bit_num-1).*/
+#define SPI_SLV_WR_ADDR_BITLEN 0x0000003F
+#define SPI_SLV_WR_ADDR_BITLEN_M ((SPI_SLV_WR_ADDR_BITLEN_V)<<(SPI_SLV_WR_ADDR_BITLEN_S))
+#define SPI_SLV_WR_ADDR_BITLEN_V 0x3F
+#define SPI_SLV_WR_ADDR_BITLEN_S 4
+/* SPI_SLV_WRSTA_DUMMY_EN : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: In the slave mode it is the enable bit of dummy phase for write-status
+ operations.*/
+#define SPI_SLV_WRSTA_DUMMY_EN (BIT(3))
+#define SPI_SLV_WRSTA_DUMMY_EN_M (BIT(3))
+#define SPI_SLV_WRSTA_DUMMY_EN_V 0x1
+#define SPI_SLV_WRSTA_DUMMY_EN_S 3
+/* SPI_SLV_RDSTA_DUMMY_EN : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: In the slave mode it is the enable bit of dummy phase for read-status
+ operations.*/
+#define SPI_SLV_RDSTA_DUMMY_EN (BIT(2))
+#define SPI_SLV_RDSTA_DUMMY_EN_M (BIT(2))
+#define SPI_SLV_RDSTA_DUMMY_EN_V 0x1
+#define SPI_SLV_RDSTA_DUMMY_EN_S 2
+/* SPI_SLV_WRBUF_DUMMY_EN : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: In the slave mode it is the enable bit of dummy phase for write-buffer
+ operations.*/
+#define SPI_SLV_WRBUF_DUMMY_EN (BIT(1))
+#define SPI_SLV_WRBUF_DUMMY_EN_M (BIT(1))
+#define SPI_SLV_WRBUF_DUMMY_EN_V 0x1
+#define SPI_SLV_WRBUF_DUMMY_EN_S 1
+/* SPI_SLV_RDBUF_DUMMY_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: In the slave mode it is the enable bit of dummy phase for read-buffer
+ operations.*/
+#define SPI_SLV_RDBUF_DUMMY_EN (BIT(0))
+#define SPI_SLV_RDBUF_DUMMY_EN_M (BIT(0))
+#define SPI_SLV_RDBUF_DUMMY_EN_V 0x1
+#define SPI_SLV_RDBUF_DUMMY_EN_S 0
+
+#define SPI_SLAVE2_REG(i) (REG_SPI_BASE(i) + 0x40)
+/* SPI_SLV_WRBUF_DUMMY_CYCLELEN : R/W ;bitpos:[31:24] ;default: 8'b0 ; */
+/*description: In the slave mode it is the length in spi_clk cycles of dummy
+ phase for write-buffer operations. The register value shall be (cycle_num-1).*/
+#define SPI_SLV_WRBUF_DUMMY_CYCLELEN 0x000000FF
+#define SPI_SLV_WRBUF_DUMMY_CYCLELEN_M ((SPI_SLV_WRBUF_DUMMY_CYCLELEN_V)<<(SPI_SLV_WRBUF_DUMMY_CYCLELEN_S))
+#define SPI_SLV_WRBUF_DUMMY_CYCLELEN_V 0xFF
+#define SPI_SLV_WRBUF_DUMMY_CYCLELEN_S 24
+/* SPI_SLV_RDBUF_DUMMY_CYCLELEN : R/W ;bitpos:[23:16] ;default: 8'h0 ; */
+/*description: In the slave mode it is the length in spi_clk cycles of dummy
+ phase for read-buffer operations. The register value shall be (cycle_num-1).*/
+#define SPI_SLV_RDBUF_DUMMY_CYCLELEN 0x000000FF
+#define SPI_SLV_RDBUF_DUMMY_CYCLELEN_M ((SPI_SLV_RDBUF_DUMMY_CYCLELEN_V)<<(SPI_SLV_RDBUF_DUMMY_CYCLELEN_S))
+#define SPI_SLV_RDBUF_DUMMY_CYCLELEN_V 0xFF
+#define SPI_SLV_RDBUF_DUMMY_CYCLELEN_S 16
+/* SPI_SLV_WRSTA_DUMMY_CYCLELEN : R/W ;bitpos:[15:8] ;default: 8'h0 ; */
+/*description: In the slave mode it is the length in spi_clk cycles of dummy
+ phase for write-status operations. The register value shall be (cycle_num-1).*/
+#define SPI_SLV_WRSTA_DUMMY_CYCLELEN 0x000000FF
+#define SPI_SLV_WRSTA_DUMMY_CYCLELEN_M ((SPI_SLV_WRSTA_DUMMY_CYCLELEN_V)<<(SPI_SLV_WRSTA_DUMMY_CYCLELEN_S))
+#define SPI_SLV_WRSTA_DUMMY_CYCLELEN_V 0xFF
+#define SPI_SLV_WRSTA_DUMMY_CYCLELEN_S 8
+/* SPI_SLV_RDSTA_DUMMY_CYCLELEN : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
+/*description: In the slave mode it is the length in spi_clk cycles of dummy
+ phase for read-status operations. The register value shall be (cycle_num-1).*/
+#define SPI_SLV_RDSTA_DUMMY_CYCLELEN 0x000000FF
+#define SPI_SLV_RDSTA_DUMMY_CYCLELEN_M ((SPI_SLV_RDSTA_DUMMY_CYCLELEN_V)<<(SPI_SLV_RDSTA_DUMMY_CYCLELEN_S))
+#define SPI_SLV_RDSTA_DUMMY_CYCLELEN_V 0xFF
+#define SPI_SLV_RDSTA_DUMMY_CYCLELEN_S 0
+
+#define SPI_SLAVE3_REG(i) (REG_SPI_BASE(i) + 0x44)
+/* SPI_SLV_WRSTA_CMD_VALUE : R/W ;bitpos:[31:24] ;default: 8'b0 ; */
+/*description: In the slave mode it is the value of write-status command.*/
+#define SPI_SLV_WRSTA_CMD_VALUE 0x000000FF
+#define SPI_SLV_WRSTA_CMD_VALUE_M ((SPI_SLV_WRSTA_CMD_VALUE_V)<<(SPI_SLV_WRSTA_CMD_VALUE_S))
+#define SPI_SLV_WRSTA_CMD_VALUE_V 0xFF
+#define SPI_SLV_WRSTA_CMD_VALUE_S 24
+/* SPI_SLV_RDSTA_CMD_VALUE : R/W ;bitpos:[23:16] ;default: 8'b0 ; */
+/*description: In the slave mode it is the value of read-status command.*/
+#define SPI_SLV_RDSTA_CMD_VALUE 0x000000FF
+#define SPI_SLV_RDSTA_CMD_VALUE_M ((SPI_SLV_RDSTA_CMD_VALUE_V)<<(SPI_SLV_RDSTA_CMD_VALUE_S))
+#define SPI_SLV_RDSTA_CMD_VALUE_V 0xFF
+#define SPI_SLV_RDSTA_CMD_VALUE_S 16
+/* SPI_SLV_WRBUF_CMD_VALUE : R/W ;bitpos:[15:8] ;default: 8'b0 ; */
+/*description: In the slave mode it is the value of write-buffer command.*/
+#define SPI_SLV_WRBUF_CMD_VALUE 0x000000FF
+#define SPI_SLV_WRBUF_CMD_VALUE_M ((SPI_SLV_WRBUF_CMD_VALUE_V)<<(SPI_SLV_WRBUF_CMD_VALUE_S))
+#define SPI_SLV_WRBUF_CMD_VALUE_V 0xFF
+#define SPI_SLV_WRBUF_CMD_VALUE_S 8
+/* SPI_SLV_RDBUF_CMD_VALUE : R/W ;bitpos:[7:0] ;default: 8'b0 ; */
+/*description: In the slave mode it is the value of read-buffer command.*/
+#define SPI_SLV_RDBUF_CMD_VALUE 0x000000FF
+#define SPI_SLV_RDBUF_CMD_VALUE_M ((SPI_SLV_RDBUF_CMD_VALUE_V)<<(SPI_SLV_RDBUF_CMD_VALUE_S))
+#define SPI_SLV_RDBUF_CMD_VALUE_V 0xFF
+#define SPI_SLV_RDBUF_CMD_VALUE_S 0
+
+#define SPI_SLV_WRBUF_DLEN_REG(i) (REG_SPI_BASE(i) + 0x48)
+/* SPI_SLV_WRBUF_DBITLEN : R/W ;bitpos:[23:0] ;default: 24'h0 ; */
+/*description: In the slave mode it is the length in bits for write-buffer operations.
+ The register value shall be (bit_num-1).*/
+#define SPI_SLV_WRBUF_DBITLEN 0x00FFFFFF
+#define SPI_SLV_WRBUF_DBITLEN_M ((SPI_SLV_WRBUF_DBITLEN_V)<<(SPI_SLV_WRBUF_DBITLEN_S))
+#define SPI_SLV_WRBUF_DBITLEN_V 0xFFFFFF
+#define SPI_SLV_WRBUF_DBITLEN_S 0
+
+#define SPI_SLV_RDBUF_DLEN_REG(i) (REG_SPI_BASE(i) + 0x4C)
+/* SPI_SLV_RDBUF_DBITLEN : R/W ;bitpos:[23:0] ;default: 24'h0 ; */
+/*description: In the slave mode it is the length in bits for read-buffer operations.
+ The register value shall be (bit_num-1).*/
+#define SPI_SLV_RDBUF_DBITLEN 0x00FFFFFF
+#define SPI_SLV_RDBUF_DBITLEN_M ((SPI_SLV_RDBUF_DBITLEN_V)<<(SPI_SLV_RDBUF_DBITLEN_S))
+#define SPI_SLV_RDBUF_DBITLEN_V 0xFFFFFF
+#define SPI_SLV_RDBUF_DBITLEN_S 0
+
+#define SPI_CACHE_FCTRL_REG(i) (REG_SPI_BASE(i) + 0x50)
+/* SPI_CACHE_FLASH_PES_EN : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: For SPI0 spi1 send suspend command before cache read flash
+ 1: enable 0:disable.*/
+#define SPI_CACHE_FLASH_PES_EN (BIT(3))
+#define SPI_CACHE_FLASH_PES_EN_M (BIT(3))
+#define SPI_CACHE_FLASH_PES_EN_V 0x1
+#define SPI_CACHE_FLASH_PES_EN_S 3
+/* SPI_CACHE_FLASH_USR_CMD : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: For SPI0 cache read flash for user define command 1: enable 0:disable.*/
+#define SPI_CACHE_FLASH_USR_CMD (BIT(2))
+#define SPI_CACHE_FLASH_USR_CMD_M (BIT(2))
+#define SPI_CACHE_FLASH_USR_CMD_V 0x1
+#define SPI_CACHE_FLASH_USR_CMD_S 2
+/* SPI_CACHE_USR_CMD_4BYTE : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: For SPI0 cache read flash with 4 bytes command 1: enable 0:disable.*/
+#define SPI_CACHE_USR_CMD_4BYTE (BIT(1))
+#define SPI_CACHE_USR_CMD_4BYTE_M (BIT(1))
+#define SPI_CACHE_USR_CMD_4BYTE_V 0x1
+#define SPI_CACHE_USR_CMD_4BYTE_S 1
+/* SPI_CACHE_REQ_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: For SPI0 Cache access enable 1: enable 0:disable.*/
+#define SPI_CACHE_REQ_EN (BIT(0))
+#define SPI_CACHE_REQ_EN_M (BIT(0))
+#define SPI_CACHE_REQ_EN_V 0x1
+#define SPI_CACHE_REQ_EN_S 0
+
+#define SPI_CACHE_SCTRL_REG(i) (REG_SPI_BASE(i) + 0x54)
+/* SPI_CACHE_SRAM_USR_WCMD : R/W ;bitpos:[28] ;default: 1'b1 ; */
+/*description: For SPI0 In the spi sram mode cache write sram for user define command*/
+#define SPI_CACHE_SRAM_USR_WCMD (BIT(28))
+#define SPI_CACHE_SRAM_USR_WCMD_M (BIT(28))
+#define SPI_CACHE_SRAM_USR_WCMD_V 0x1
+#define SPI_CACHE_SRAM_USR_WCMD_S 28
+/* SPI_SRAM_ADDR_BITLEN : R/W ;bitpos:[27:22] ;default: 6'd23 ; */
+/*description: For SPI0 In the sram mode it is the length in bits of address
+ phase. The register value shall be (bit_num-1).*/
+#define SPI_SRAM_ADDR_BITLEN 0x0000003F
+#define SPI_SRAM_ADDR_BITLEN_M ((SPI_SRAM_ADDR_BITLEN_V)<<(SPI_SRAM_ADDR_BITLEN_S))
+#define SPI_SRAM_ADDR_BITLEN_V 0x3F
+#define SPI_SRAM_ADDR_BITLEN_S 22
+/* SPI_SRAM_DUMMY_CYCLELEN : R/W ;bitpos:[21:14] ;default: 8'b1 ; */
+/*description: For SPI0 In the sram mode it is the length in bits of address
+ phase. The register value shall be (bit_num-1).*/
+#define SPI_SRAM_DUMMY_CYCLELEN 0x000000FF
+#define SPI_SRAM_DUMMY_CYCLELEN_M ((SPI_SRAM_DUMMY_CYCLELEN_V)<<(SPI_SRAM_DUMMY_CYCLELEN_S))
+#define SPI_SRAM_DUMMY_CYCLELEN_V 0xFF
+#define SPI_SRAM_DUMMY_CYCLELEN_S 14
+/* SPI_SRAM_BYTES_LEN : R/W ;bitpos:[13:6] ;default: 8'b32 ; */
+/*description: For SPI0 In the sram mode it is the byte length of spi read sram data.*/
+#define SPI_SRAM_BYTES_LEN 0x000000FF
+#define SPI_SRAM_BYTES_LEN_M ((SPI_SRAM_BYTES_LEN_V)<<(SPI_SRAM_BYTES_LEN_S))
+#define SPI_SRAM_BYTES_LEN_V 0xFF
+#define SPI_SRAM_BYTES_LEN_S 6
+/* SPI_CACHE_SRAM_USR_RCMD : R/W ;bitpos:[5] ;default: 1'b1 ; */
+/*description: For SPI0 In the spi sram mode cache read sram for user define command.*/
+#define SPI_CACHE_SRAM_USR_RCMD (BIT(5))
+#define SPI_CACHE_SRAM_USR_RCMD_M (BIT(5))
+#define SPI_CACHE_SRAM_USR_RCMD_V 0x1
+#define SPI_CACHE_SRAM_USR_RCMD_S 5
+/* SPI_USR_RD_SRAM_DUMMY : R/W ;bitpos:[4] ;default: 1'b1 ; */
+/*description: For SPI0 In the spi sram mode it is the enable bit of dummy
+ phase for read operations.*/
+#define SPI_USR_RD_SRAM_DUMMY (BIT(4))
+#define SPI_USR_RD_SRAM_DUMMY_M (BIT(4))
+#define SPI_USR_RD_SRAM_DUMMY_V 0x1
+#define SPI_USR_RD_SRAM_DUMMY_S 4
+/* SPI_USR_WR_SRAM_DUMMY : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: For SPI0 In the spi sram mode it is the enable bit of dummy
+ phase for write operations.*/
+#define SPI_USR_WR_SRAM_DUMMY (BIT(3))
+#define SPI_USR_WR_SRAM_DUMMY_M (BIT(3))
+#define SPI_USR_WR_SRAM_DUMMY_V 0x1
+#define SPI_USR_WR_SRAM_DUMMY_S 3
+/* SPI_USR_SRAM_QIO : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: For SPI0 In the spi sram mode spi quad I/O mode enable 1: enable 0:disable*/
+#define SPI_USR_SRAM_QIO (BIT(2))
+#define SPI_USR_SRAM_QIO_M (BIT(2))
+#define SPI_USR_SRAM_QIO_V 0x1
+#define SPI_USR_SRAM_QIO_S 2
+/* SPI_USR_SRAM_DIO : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: For SPI0 In the spi sram mode spi dual I/O mode enable 1: enable 0:disable*/
+#define SPI_USR_SRAM_DIO (BIT(1))
+#define SPI_USR_SRAM_DIO_M (BIT(1))
+#define SPI_USR_SRAM_DIO_V 0x1
+#define SPI_USR_SRAM_DIO_S 1
+
+#define SPI_SRAM_CMD_REG(i) (REG_SPI_BASE(i) + 0x58)
+/* SPI_SRAM_RSTIO : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: For SPI0 SRAM IO mode reset enable. SRAM IO mode reset operation
+ will be triggered when the bit is set. The bit will be cleared once the operation done*/
+#define SPI_SRAM_RSTIO (BIT(4))
+#define SPI_SRAM_RSTIO_M (BIT(4))
+#define SPI_SRAM_RSTIO_V 0x1
+#define SPI_SRAM_RSTIO_S 4
+/* SPI_SRAM_QIO : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: For SPI0 SRAM QIO mode enable . SRAM QIO enable command will
+ be send when the bit is set. The bit will be cleared once the operation done.*/
+#define SPI_SRAM_QIO (BIT(1))
+#define SPI_SRAM_QIO_M (BIT(1))
+#define SPI_SRAM_QIO_V 0x1
+#define SPI_SRAM_QIO_S 1
+/* SPI_SRAM_DIO : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: For SPI0 SRAM DIO mode enable . SRAM DIO enable command will
+ be send when the bit is set. The bit will be cleared once the operation done.*/
+#define SPI_SRAM_DIO (BIT(0))
+#define SPI_SRAM_DIO_M (BIT(0))
+#define SPI_SRAM_DIO_V 0x1
+#define SPI_SRAM_DIO_S 0
+
+#define SPI_SRAM_DRD_CMD_REG(i) (REG_SPI_BASE(i) + 0x5C)
+/* SPI_CACHE_SRAM_USR_RD_CMD_BITLEN : R/W ;bitpos:[31:28] ;default: 4'h0 ; */
+/*description: For SPI0 When cache mode is enable it is the length in bits of
+ command phase for SRAM. The register value shall be (bit_num-1).*/
+#define SPI_CACHE_SRAM_USR_RD_CMD_BITLEN 0x0000000F
+#define SPI_CACHE_SRAM_USR_RD_CMD_BITLEN_M ((SPI_CACHE_SRAM_USR_RD_CMD_BITLEN_V)<<(SPI_CACHE_SRAM_USR_RD_CMD_BITLEN_S))
+#define SPI_CACHE_SRAM_USR_RD_CMD_BITLEN_V 0xF
+#define SPI_CACHE_SRAM_USR_RD_CMD_BITLEN_S 28
+/* SPI_CACHE_SRAM_USR_RD_CMD_VALUE : R/W ;bitpos:[15:0] ;default: 16'h0 ; */
+/*description: For SPI0 When cache mode is enable it is the read command value
+ of command phase for SRAM.*/
+#define SPI_CACHE_SRAM_USR_RD_CMD_VALUE 0x0000FFFF
+#define SPI_CACHE_SRAM_USR_RD_CMD_VALUE_M ((SPI_CACHE_SRAM_USR_RD_CMD_VALUE_V)<<(SPI_CACHE_SRAM_USR_RD_CMD_VALUE_S))
+#define SPI_CACHE_SRAM_USR_RD_CMD_VALUE_V 0xFFFF
+#define SPI_CACHE_SRAM_USR_RD_CMD_VALUE_S 0
+
+#define SPI_SRAM_DWR_CMD_REG(i) (REG_SPI_BASE(i) + 0x60)
+/* SPI_CACHE_SRAM_USR_WR_CMD_BITLEN : R/W ;bitpos:[31:28] ;default: 4'h0 ; */
+/*description: For SPI0 When cache mode is enable it is the in bits of command
+ phase for SRAM. The register value shall be (bit_num-1).*/
+#define SPI_CACHE_SRAM_USR_WR_CMD_BITLEN 0x0000000F
+#define SPI_CACHE_SRAM_USR_WR_CMD_BITLEN_M ((SPI_CACHE_SRAM_USR_WR_CMD_BITLEN_V)<<(SPI_CACHE_SRAM_USR_WR_CMD_BITLEN_S))
+#define SPI_CACHE_SRAM_USR_WR_CMD_BITLEN_V 0xF
+#define SPI_CACHE_SRAM_USR_WR_CMD_BITLEN_S 28
+/* SPI_CACHE_SRAM_USR_WR_CMD_VALUE : R/W ;bitpos:[15:0] ;default: 16'h0 ; */
+/*description: For SPI0 When cache mode is enable it is the write command value
+ of command phase for SRAM.*/
+#define SPI_CACHE_SRAM_USR_WR_CMD_VALUE 0x0000FFFF
+#define SPI_CACHE_SRAM_USR_WR_CMD_VALUE_M ((SPI_CACHE_SRAM_USR_WR_CMD_VALUE_V)<<(SPI_CACHE_SRAM_USR_WR_CMD_VALUE_S))
+#define SPI_CACHE_SRAM_USR_WR_CMD_VALUE_V 0xFFFF
+#define SPI_CACHE_SRAM_USR_WR_CMD_VALUE_S 0
+
+#define SPI_SLV_RD_BIT_REG(i) (REG_SPI_BASE(i) + 0x64)
+/* SPI_SLV_RDATA_BIT : RW ;bitpos:[23:0] ;default: 24'b0 ; */
+/*description: In the slave mode it is the bit length of read data. The value
+ is the length - 1.*/
+#define SPI_SLV_RDATA_BIT 0x00FFFFFF
+#define SPI_SLV_RDATA_BIT_M ((SPI_SLV_RDATA_BIT_V)<<(SPI_SLV_RDATA_BIT_S))
+#define SPI_SLV_RDATA_BIT_V 0xFFFFFF
+#define SPI_SLV_RDATA_BIT_S 0
+
+#define SPI_W0_REG(i) (REG_SPI_BASE(i) + 0x80)
+/* SPI_BUF0 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: data buffer*/
+#define SPI_BUF0 0xFFFFFFFF
+#define SPI_BUF0_M ((SPI_BUF0_V)<<(SPI_BUF0_S))
+#define SPI_BUF0_V 0xFFFFFFFF
+#define SPI_BUF0_S 0
+
+#define SPI_W1_REG(i) (REG_SPI_BASE(i) + 0x84)
+/* SPI_BUF1 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: data buffer*/
+#define SPI_BUF1 0xFFFFFFFF
+#define SPI_BUF1_M ((SPI_BUF1_V)<<(SPI_BUF1_S))
+#define SPI_BUF1_V 0xFFFFFFFF
+#define SPI_BUF1_S 0
+
+#define SPI_W2_REG(i) (REG_SPI_BASE(i) + 0x88)
+/* SPI_BUF2 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: data buffer*/
+#define SPI_BUF2 0xFFFFFFFF
+#define SPI_BUF2_M ((SPI_BUF2_V)<<(SPI_BUF2_S))
+#define SPI_BUF2_V 0xFFFFFFFF
+#define SPI_BUF2_S 0
+
+#define SPI_W3_REG(i) (REG_SPI_BASE(i) + 0x8C)
+/* SPI_BUF3 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: data buffer*/
+#define SPI_BUF3 0xFFFFFFFF
+#define SPI_BUF3_M ((SPI_BUF3_V)<<(SPI_BUF3_S))
+#define SPI_BUF3_V 0xFFFFFFFF
+#define SPI_BUF3_S 0
+
+#define SPI_W4_REG(i) (REG_SPI_BASE(i) + 0x90)
+/* SPI_BUF4 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: data buffer*/
+#define SPI_BUF4 0xFFFFFFFF
+#define SPI_BUF4_M ((SPI_BUF4_V)<<(SPI_BUF4_S))
+#define SPI_BUF4_V 0xFFFFFFFF
+#define SPI_BUF4_S 0
+
+#define SPI_W5_REG(i) (REG_SPI_BASE(i) + 0x94)
+/* SPI_BUF5 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: data buffer*/
+#define SPI_BUF5 0xFFFFFFFF
+#define SPI_BUF5_M ((SPI_BUF5_V)<<(SPI_BUF5_S))
+#define SPI_BUF5_V 0xFFFFFFFF
+#define SPI_BUF5_S 0
+
+#define SPI_W6_REG(i) (REG_SPI_BASE(i) + 0x98)
+/* SPI_BUF6 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: data buffer*/
+#define SPI_BUF6 0xFFFFFFFF
+#define SPI_BUF6_M ((SPI_BUF6_V)<<(SPI_BUF6_S))
+#define SPI_BUF6_V 0xFFFFFFFF
+#define SPI_BUF6_S 0
+
+#define SPI_W7_REG(i) (REG_SPI_BASE(i) + 0x9C)
+/* SPI_BUF7 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: data buffer*/
+#define SPI_BUF7 0xFFFFFFFF
+#define SPI_BUF7_M ((SPI_BUF7_V)<<(SPI_BUF7_S))
+#define SPI_BUF7_V 0xFFFFFFFF
+#define SPI_BUF7_S 0
+
+#define SPI_W8_REG(i) (REG_SPI_BASE(i) + 0xA0)
+/* SPI_BUF8 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: data buffer*/
+#define SPI_BUF8 0xFFFFFFFF
+#define SPI_BUF8_M ((SPI_BUF8_V)<<(SPI_BUF8_S))
+#define SPI_BUF8_V 0xFFFFFFFF
+#define SPI_BUF8_S 0
+
+#define SPI_W9_REG(i) (REG_SPI_BASE(i) + 0xA4)
+/* SPI_BUF9 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: data buffer*/
+#define SPI_BUF9 0xFFFFFFFF
+#define SPI_BUF9_M ((SPI_BUF9_V)<<(SPI_BUF9_S))
+#define SPI_BUF9_V 0xFFFFFFFF
+#define SPI_BUF9_S 0
+
+#define SPI_W10_REG(i) (REG_SPI_BASE(i) + 0xA8)
+/* SPI_BUF10 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: data buffer*/
+#define SPI_BUF10 0xFFFFFFFF
+#define SPI_BUF10_M ((SPI_BUF10_V)<<(SPI_BUF10_S))
+#define SPI_BUF10_V 0xFFFFFFFF
+#define SPI_BUF10_S 0
+
+#define SPI_W11_REG(i) (REG_SPI_BASE(i) + 0xAC)
+/* SPI_BUF11 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: data buffer*/
+#define SPI_BUF11 0xFFFFFFFF
+#define SPI_BUF11_M ((SPI_BUF11_V)<<(SPI_BUF11_S))
+#define SPI_BUF11_V 0xFFFFFFFF
+#define SPI_BUF11_S 0
+
+#define SPI_W12_REG(i) (REG_SPI_BASE(i) + 0xB0)
+/* SPI_BUF12 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: data buffer*/
+#define SPI_BUF12 0xFFFFFFFF
+#define SPI_BUF12_M ((SPI_BUF12_V)<<(SPI_BUF12_S))
+#define SPI_BUF12_V 0xFFFFFFFF
+#define SPI_BUF12_S 0
+
+#define SPI_W13_REG(i) (REG_SPI_BASE(i) + 0xB4)
+/* SPI_BUF13 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: data buffer*/
+#define SPI_BUF13 0xFFFFFFFF
+#define SPI_BUF13_M ((SPI_BUF13_V)<<(SPI_BUF13_S))
+#define SPI_BUF13_V 0xFFFFFFFF
+#define SPI_BUF13_S 0
+
+#define SPI_W14_REG(i) (REG_SPI_BASE(i) + 0xB8)
+/* SPI_BUF14 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: data buffer*/
+#define SPI_BUF14 0xFFFFFFFF
+#define SPI_BUF14_M ((SPI_BUF14_V)<<(SPI_BUF14_S))
+#define SPI_BUF14_V 0xFFFFFFFF
+#define SPI_BUF14_S 0
+
+#define SPI_W15_REG(i) (REG_SPI_BASE(i) + 0xBC)
+/* SPI_BUF15 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: data buffer*/
+#define SPI_BUF15 0xFFFFFFFF
+#define SPI_BUF15_M ((SPI_BUF15_V)<<(SPI_BUF15_S))
+#define SPI_BUF15_V 0xFFFFFFFF
+#define SPI_BUF15_S 0
+
+#define SPI_TX_CRC_REG(i) (REG_SPI_BASE(i) + 0xC0)
+/* SPI_TX_CRC_DATA : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: For SPI1 the value of crc32 for 256 bits data.*/
+#define SPI_TX_CRC_DATA 0xFFFFFFFF
+#define SPI_TX_CRC_DATA_M ((SPI_TX_CRC_DATA_V)<<(SPI_TX_CRC_DATA_S))
+#define SPI_TX_CRC_DATA_V 0xFFFFFFFF
+#define SPI_TX_CRC_DATA_S 0
+
+#define SPI_EXT0_REG(i) (REG_SPI_BASE(i) + 0xF0)
+/* SPI_T_PP_ENA : R/W ;bitpos:[31] ;default: 1'b1 ; */
+/*description: page program delay enable.*/
+#define SPI_T_PP_ENA (BIT(31))
+#define SPI_T_PP_ENA_M (BIT(31))
+#define SPI_T_PP_ENA_V 0x1
+#define SPI_T_PP_ENA_S 31
+/* SPI_T_PP_SHIFT : R/W ;bitpos:[19:16] ;default: 4'd10 ; */
+/*description: page program delay time shift .*/
+#define SPI_T_PP_SHIFT 0x0000000F
+#define SPI_T_PP_SHIFT_M ((SPI_T_PP_SHIFT_V)<<(SPI_T_PP_SHIFT_S))
+#define SPI_T_PP_SHIFT_V 0xF
+#define SPI_T_PP_SHIFT_S 16
+/* SPI_T_PP_TIME : R/W ;bitpos:[11:0] ;default: 12'd80 ; */
+/*description: page program delay time by system clock.*/
+#define SPI_T_PP_TIME 0x00000FFF
+#define SPI_T_PP_TIME_M ((SPI_T_PP_TIME_V)<<(SPI_T_PP_TIME_S))
+#define SPI_T_PP_TIME_V 0xFFF
+#define SPI_T_PP_TIME_S 0
+
+#define SPI_EXT1_REG(i) (REG_SPI_BASE(i) + 0xF4)
+/* SPI_T_ERASE_ENA : R/W ;bitpos:[31] ;default: 1'b1 ; */
+/*description: erase flash delay enable.*/
+#define SPI_T_ERASE_ENA (BIT(31))
+#define SPI_T_ERASE_ENA_M (BIT(31))
+#define SPI_T_ERASE_ENA_V 0x1
+#define SPI_T_ERASE_ENA_S 31
+/* SPI_T_ERASE_SHIFT : R/W ;bitpos:[19:16] ;default: 4'd15 ; */
+/*description: erase flash delay time shift.*/
+#define SPI_T_ERASE_SHIFT 0x0000000F
+#define SPI_T_ERASE_SHIFT_M ((SPI_T_ERASE_SHIFT_V)<<(SPI_T_ERASE_SHIFT_S))
+#define SPI_T_ERASE_SHIFT_V 0xF
+#define SPI_T_ERASE_SHIFT_S 16
+/* SPI_T_ERASE_TIME : R/W ;bitpos:[11:0] ;default: 12'd0 ; */
+/*description: erase flash delay time by system clock.*/
+#define SPI_T_ERASE_TIME 0x00000FFF
+#define SPI_T_ERASE_TIME_M ((SPI_T_ERASE_TIME_V)<<(SPI_T_ERASE_TIME_S))
+#define SPI_T_ERASE_TIME_V 0xFFF
+#define SPI_T_ERASE_TIME_S 0
+
+#define SPI_EXT2_REG(i) (REG_SPI_BASE(i) + 0xF8)
+/* SPI_ST : RO ;bitpos:[2:0] ;default: 3'b0 ; */
+/*description: The status of spi state machine .*/
+#define SPI_ST 0x00000007
+#define SPI_ST_M ((SPI_ST_V)<<(SPI_ST_S))
+#define SPI_ST_V 0x7
+#define SPI_ST_S 0
+
+#define SPI_EXT3_REG(i) (REG_SPI_BASE(i) + 0xFC)
+/* SPI_INT_HOLD_ENA : R/W ;bitpos:[1:0] ;default: 2'b0 ; */
+/*description: This register is for two SPI masters to share the same cs clock
+ and data signals. The bits of one SPI are set if the other SPI is busy the SPI will be hold. 1(3): hold at ¡°idle¡± phase 2: hold at ¡°prepare¡± phase.*/
+#define SPI_INT_HOLD_ENA 0x00000003
+#define SPI_INT_HOLD_ENA_M ((SPI_INT_HOLD_ENA_V)<<(SPI_INT_HOLD_ENA_S))
+#define SPI_INT_HOLD_ENA_V 0x3
+#define SPI_INT_HOLD_ENA_S 0
+
+#define SPI_DMA_CONF_REG(i) (REG_SPI_BASE(i) + 0x100)
+/* SPI_DMA_CONTINUE : R/W ;bitpos:[16] ;default: 1'b0 ; */
+/*description: spi dma continue tx/rx data.*/
+#define SPI_DMA_CONTINUE (BIT(16))
+#define SPI_DMA_CONTINUE_M (BIT(16))
+#define SPI_DMA_CONTINUE_V 0x1
+#define SPI_DMA_CONTINUE_S 16
+/* SPI_DMA_TX_STOP : R/W ;bitpos:[15] ;default: 1'b0 ; */
+/*description: spi dma write data stop when in continue tx/rx mode.*/
+#define SPI_DMA_TX_STOP (BIT(15))
+#define SPI_DMA_TX_STOP_M (BIT(15))
+#define SPI_DMA_TX_STOP_V 0x1
+#define SPI_DMA_TX_STOP_S 15
+/* SPI_DMA_RX_STOP : R/W ;bitpos:[14] ;default: 1'b0 ; */
+/*description: spi dma read data stop when in continue tx/rx mode.*/
+#define SPI_DMA_RX_STOP (BIT(14))
+#define SPI_DMA_RX_STOP_M (BIT(14))
+#define SPI_DMA_RX_STOP_V 0x1
+#define SPI_DMA_RX_STOP_S 14
+/* SPI_OUT_DATA_BURST_EN : R/W ;bitpos:[12] ;default: 1'b0 ; */
+/*description: spi dma read data from memory in burst mode.*/
+#define SPI_OUT_DATA_BURST_EN (BIT(12))
+#define SPI_OUT_DATA_BURST_EN_M (BIT(12))
+#define SPI_OUT_DATA_BURST_EN_V 0x1
+#define SPI_OUT_DATA_BURST_EN_S 12
+/* SPI_INDSCR_BURST_EN : R/W ;bitpos:[11] ;default: 1'b0 ; */
+/*description: read descriptor use burst mode when write data to memory.*/
+#define SPI_INDSCR_BURST_EN (BIT(11))
+#define SPI_INDSCR_BURST_EN_M (BIT(11))
+#define SPI_INDSCR_BURST_EN_V 0x1
+#define SPI_INDSCR_BURST_EN_S 11
+/* SPI_OUTDSCR_BURST_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */
+/*description: read descriptor use burst mode when read data for memory.*/
+#define SPI_OUTDSCR_BURST_EN (BIT(10))
+#define SPI_OUTDSCR_BURST_EN_M (BIT(10))
+#define SPI_OUTDSCR_BURST_EN_V 0x1
+#define SPI_OUTDSCR_BURST_EN_S 10
+/* SPI_OUT_EOF_MODE : R/W ;bitpos:[9] ;default: 1'b1 ; */
+/*description: out eof flag generation mode . 1: when dma pop all data from
+ fifo 0:when ahb push all data to fifo.*/
+#define SPI_OUT_EOF_MODE (BIT(9))
+#define SPI_OUT_EOF_MODE_M (BIT(9))
+#define SPI_OUT_EOF_MODE_V 0x1
+#define SPI_OUT_EOF_MODE_S 9
+/* SPI_OUT_AUTO_WRBACK : R/W ;bitpos:[8] ;default: 1'b0 ; */
+/*description: when the link is empty jump to next automatically.*/
+#define SPI_OUT_AUTO_WRBACK (BIT(8))
+#define SPI_OUT_AUTO_WRBACK_M (BIT(8))
+#define SPI_OUT_AUTO_WRBACK_V 0x1
+#define SPI_OUT_AUTO_WRBACK_S 8
+/* SPI_OUT_LOOP_TEST : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: Set bit to test out link.*/
+#define SPI_OUT_LOOP_TEST (BIT(7))
+#define SPI_OUT_LOOP_TEST_M (BIT(7))
+#define SPI_OUT_LOOP_TEST_V 0x1
+#define SPI_OUT_LOOP_TEST_S 7
+/* SPI_IN_LOOP_TEST : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: Set bit to test in link.*/
+#define SPI_IN_LOOP_TEST (BIT(6))
+#define SPI_IN_LOOP_TEST_M (BIT(6))
+#define SPI_IN_LOOP_TEST_V 0x1
+#define SPI_IN_LOOP_TEST_S 6
+/* SPI_AHBM_RST : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: reset spi dma ahb master.*/
+#define SPI_AHBM_RST (BIT(5))
+#define SPI_AHBM_RST_M (BIT(5))
+#define SPI_AHBM_RST_V 0x1
+#define SPI_AHBM_RST_S 5
+/* SPI_AHBM_FIFO_RST : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: reset spi dma ahb master fifo pointer.*/
+#define SPI_AHBM_FIFO_RST (BIT(4))
+#define SPI_AHBM_FIFO_RST_M (BIT(4))
+#define SPI_AHBM_FIFO_RST_V 0x1
+#define SPI_AHBM_FIFO_RST_S 4
+/* SPI_OUT_RST : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: The bit is used to reset out dma fsm and out data fifo pointer.*/
+#define SPI_OUT_RST (BIT(3))
+#define SPI_OUT_RST_M (BIT(3))
+#define SPI_OUT_RST_V 0x1
+#define SPI_OUT_RST_S 3
+/* SPI_IN_RST : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: The bit is used to reset in dma fsm and in data fifo pointer.*/
+#define SPI_IN_RST (BIT(2))
+#define SPI_IN_RST_M (BIT(2))
+#define SPI_IN_RST_V 0x1
+#define SPI_IN_RST_S 2
+
+#define SPI_DMA_OUT_LINK_REG(i) (REG_SPI_BASE(i) + 0x104)
+/* SPI_OUTLINK_RESTART : R/W ;bitpos:[30] ;default: 1'b0 ; */
+/*description: Set the bit to mount on new outlink descriptors.*/
+#define SPI_OUTLINK_RESTART (BIT(30))
+#define SPI_OUTLINK_RESTART_M (BIT(30))
+#define SPI_OUTLINK_RESTART_V 0x1
+#define SPI_OUTLINK_RESTART_S 30
+/* SPI_OUTLINK_START : R/W ;bitpos:[29] ;default: 1'b0 ; */
+/*description: Set the bit to start to use outlink descriptor.*/
+#define SPI_OUTLINK_START (BIT(29))
+#define SPI_OUTLINK_START_M (BIT(29))
+#define SPI_OUTLINK_START_V 0x1
+#define SPI_OUTLINK_START_S 29
+/* SPI_OUTLINK_STOP : R/W ;bitpos:[28] ;default: 1'b0 ; */
+/*description: Set the bit to stop to use outlink descriptor.*/
+#define SPI_OUTLINK_STOP (BIT(28))
+#define SPI_OUTLINK_STOP_M (BIT(28))
+#define SPI_OUTLINK_STOP_V 0x1
+#define SPI_OUTLINK_STOP_S 28
+/* SPI_OUTLINK_ADDR : R/W ;bitpos:[19:0] ;default: 20'h0 ; */
+/*description: The address of the first outlink descriptor.*/
+#define SPI_OUTLINK_ADDR 0x000FFFFF
+#define SPI_OUTLINK_ADDR_M ((SPI_OUTLINK_ADDR_V)<<(SPI_OUTLINK_ADDR_S))
+#define SPI_OUTLINK_ADDR_V 0xFFFFF
+#define SPI_OUTLINK_ADDR_S 0
+
+#define SPI_DMA_IN_LINK_REG(i) (REG_SPI_BASE(i) + 0x108)
+/* SPI_INLINK_RESTART : R/W ;bitpos:[30] ;default: 1'b0 ; */
+/*description: Set the bit to mount on new inlink descriptors.*/
+#define SPI_INLINK_RESTART (BIT(30))
+#define SPI_INLINK_RESTART_M (BIT(30))
+#define SPI_INLINK_RESTART_V 0x1
+#define SPI_INLINK_RESTART_S 30
+/* SPI_INLINK_START : R/W ;bitpos:[29] ;default: 1'b0 ; */
+/*description: Set the bit to start to use inlink descriptor.*/
+#define SPI_INLINK_START (BIT(29))
+#define SPI_INLINK_START_M (BIT(29))
+#define SPI_INLINK_START_V 0x1
+#define SPI_INLINK_START_S 29
+/* SPI_INLINK_STOP : R/W ;bitpos:[28] ;default: 1'b0 ; */
+/*description: Set the bit to stop to use inlink descriptor.*/
+#define SPI_INLINK_STOP (BIT(28))
+#define SPI_INLINK_STOP_M (BIT(28))
+#define SPI_INLINK_STOP_V 0x1
+#define SPI_INLINK_STOP_S 28
+/* SPI_INLINK_AUTO_RET : R/W ;bitpos:[20] ;default: 1'b0 ; */
+/*description: when the bit is set inlink descriptor returns to the next descriptor
+ while a packet is wrong*/
+#define SPI_INLINK_AUTO_RET (BIT(20))
+#define SPI_INLINK_AUTO_RET_M (BIT(20))
+#define SPI_INLINK_AUTO_RET_V 0x1
+#define SPI_INLINK_AUTO_RET_S 20
+/* SPI_INLINK_ADDR : R/W ;bitpos:[19:0] ;default: 20'h0 ; */
+/*description: The address of the first inlink descriptor.*/
+#define SPI_INLINK_ADDR 0x000FFFFF
+#define SPI_INLINK_ADDR_M ((SPI_INLINK_ADDR_V)<<(SPI_INLINK_ADDR_S))
+#define SPI_INLINK_ADDR_V 0xFFFFF
+#define SPI_INLINK_ADDR_S 0
+
+#define SPI_DMA_STATUS_REG(i) (REG_SPI_BASE(i) + 0x10C)
+/* SPI_DMA_TX_EN : RO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: spi dma write data status bit.*/
+#define SPI_DMA_TX_EN (BIT(1))
+#define SPI_DMA_TX_EN_M (BIT(1))
+#define SPI_DMA_TX_EN_V 0x1
+#define SPI_DMA_TX_EN_S 1
+/* SPI_DMA_RX_EN : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: spi dma read data status bit.*/
+#define SPI_DMA_RX_EN (BIT(0))
+#define SPI_DMA_RX_EN_M (BIT(0))
+#define SPI_DMA_RX_EN_V 0x1
+#define SPI_DMA_RX_EN_S 0
+
+#define SPI_DMA_INT_ENA_REG(i) (REG_SPI_BASE(i) + 0x110)
+/* SPI_OUT_TOTAL_EOF_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */
+/*description: The enable bit for sending all the packets to host done.*/
+#define SPI_OUT_TOTAL_EOF_INT_ENA (BIT(8))
+#define SPI_OUT_TOTAL_EOF_INT_ENA_M (BIT(8))
+#define SPI_OUT_TOTAL_EOF_INT_ENA_V 0x1
+#define SPI_OUT_TOTAL_EOF_INT_ENA_S 8
+/* SPI_OUT_EOF_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: The enable bit for sending a packet to host done.*/
+#define SPI_OUT_EOF_INT_ENA (BIT(7))
+#define SPI_OUT_EOF_INT_ENA_M (BIT(7))
+#define SPI_OUT_EOF_INT_ENA_V 0x1
+#define SPI_OUT_EOF_INT_ENA_S 7
+/* SPI_OUT_DONE_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: The enable bit for completing usage of a outlink descriptor .*/
+#define SPI_OUT_DONE_INT_ENA (BIT(6))
+#define SPI_OUT_DONE_INT_ENA_M (BIT(6))
+#define SPI_OUT_DONE_INT_ENA_V 0x1
+#define SPI_OUT_DONE_INT_ENA_S 6
+/* SPI_IN_SUC_EOF_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: The enable bit for completing receiving all the packets from host.*/
+#define SPI_IN_SUC_EOF_INT_ENA (BIT(5))
+#define SPI_IN_SUC_EOF_INT_ENA_M (BIT(5))
+#define SPI_IN_SUC_EOF_INT_ENA_V 0x1
+#define SPI_IN_SUC_EOF_INT_ENA_S 5
+/* SPI_IN_ERR_EOF_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: The enable bit for receiving error.*/
+#define SPI_IN_ERR_EOF_INT_ENA (BIT(4))
+#define SPI_IN_ERR_EOF_INT_ENA_M (BIT(4))
+#define SPI_IN_ERR_EOF_INT_ENA_V 0x1
+#define SPI_IN_ERR_EOF_INT_ENA_S 4
+/* SPI_IN_DONE_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: The enable bit for completing usage of a inlink descriptor.*/
+#define SPI_IN_DONE_INT_ENA (BIT(3))
+#define SPI_IN_DONE_INT_ENA_M (BIT(3))
+#define SPI_IN_DONE_INT_ENA_V 0x1
+#define SPI_IN_DONE_INT_ENA_S 3
+/* SPI_INLINK_DSCR_ERROR_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: The enable bit for inlink descriptor error.*/
+#define SPI_INLINK_DSCR_ERROR_INT_ENA (BIT(2))
+#define SPI_INLINK_DSCR_ERROR_INT_ENA_M (BIT(2))
+#define SPI_INLINK_DSCR_ERROR_INT_ENA_V 0x1
+#define SPI_INLINK_DSCR_ERROR_INT_ENA_S 2
+/* SPI_OUTLINK_DSCR_ERROR_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: The enable bit for outlink descriptor error.*/
+#define SPI_OUTLINK_DSCR_ERROR_INT_ENA (BIT(1))
+#define SPI_OUTLINK_DSCR_ERROR_INT_ENA_M (BIT(1))
+#define SPI_OUTLINK_DSCR_ERROR_INT_ENA_V 0x1
+#define SPI_OUTLINK_DSCR_ERROR_INT_ENA_S 1
+/* SPI_INLINK_DSCR_EMPTY_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: The enable bit for lack of enough inlink descriptors.*/
+#define SPI_INLINK_DSCR_EMPTY_INT_ENA (BIT(0))
+#define SPI_INLINK_DSCR_EMPTY_INT_ENA_M (BIT(0))
+#define SPI_INLINK_DSCR_EMPTY_INT_ENA_V 0x1
+#define SPI_INLINK_DSCR_EMPTY_INT_ENA_S 0
+
+#define SPI_DMA_INT_RAW_REG(i) (REG_SPI_BASE(i) + 0x114)
+/* SPI_OUT_TOTAL_EOF_INT_RAW : RO ;bitpos:[8] ;default: 1'b0 ; */
+/*description: The raw bit for sending all the packets to host done.*/
+#define SPI_OUT_TOTAL_EOF_INT_RAW (BIT(8))
+#define SPI_OUT_TOTAL_EOF_INT_RAW_M (BIT(8))
+#define SPI_OUT_TOTAL_EOF_INT_RAW_V 0x1
+#define SPI_OUT_TOTAL_EOF_INT_RAW_S 8
+/* SPI_OUT_EOF_INT_RAW : RO ;bitpos:[7] ;default: 1'b0 ; */
+/*description: The raw bit for sending a packet to host done.*/
+#define SPI_OUT_EOF_INT_RAW (BIT(7))
+#define SPI_OUT_EOF_INT_RAW_M (BIT(7))
+#define SPI_OUT_EOF_INT_RAW_V 0x1
+#define SPI_OUT_EOF_INT_RAW_S 7
+/* SPI_OUT_DONE_INT_RAW : RO ;bitpos:[6] ;default: 1'b0 ; */
+/*description: The raw bit for completing usage of a outlink descriptor.*/
+#define SPI_OUT_DONE_INT_RAW (BIT(6))
+#define SPI_OUT_DONE_INT_RAW_M (BIT(6))
+#define SPI_OUT_DONE_INT_RAW_V 0x1
+#define SPI_OUT_DONE_INT_RAW_S 6
+/* SPI_IN_SUC_EOF_INT_RAW : RO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: The raw bit for completing receiving all the packets from host.*/
+#define SPI_IN_SUC_EOF_INT_RAW (BIT(5))
+#define SPI_IN_SUC_EOF_INT_RAW_M (BIT(5))
+#define SPI_IN_SUC_EOF_INT_RAW_V 0x1
+#define SPI_IN_SUC_EOF_INT_RAW_S 5
+/* SPI_IN_ERR_EOF_INT_RAW : RO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: The raw bit for receiving error.*/
+#define SPI_IN_ERR_EOF_INT_RAW (BIT(4))
+#define SPI_IN_ERR_EOF_INT_RAW_M (BIT(4))
+#define SPI_IN_ERR_EOF_INT_RAW_V 0x1
+#define SPI_IN_ERR_EOF_INT_RAW_S 4
+/* SPI_IN_DONE_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: The raw bit for completing usage of a inlink descriptor.*/
+#define SPI_IN_DONE_INT_RAW (BIT(3))
+#define SPI_IN_DONE_INT_RAW_M (BIT(3))
+#define SPI_IN_DONE_INT_RAW_V 0x1
+#define SPI_IN_DONE_INT_RAW_S 3
+/* SPI_INLINK_DSCR_ERROR_INT_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */
+/*description: The raw bit for inlink descriptor error.*/
+#define SPI_INLINK_DSCR_ERROR_INT_RAW (BIT(2))
+#define SPI_INLINK_DSCR_ERROR_INT_RAW_M (BIT(2))
+#define SPI_INLINK_DSCR_ERROR_INT_RAW_V 0x1
+#define SPI_INLINK_DSCR_ERROR_INT_RAW_S 2
+/* SPI_OUTLINK_DSCR_ERROR_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: The raw bit for outlink descriptor error.*/
+#define SPI_OUTLINK_DSCR_ERROR_INT_RAW (BIT(1))
+#define SPI_OUTLINK_DSCR_ERROR_INT_RAW_M (BIT(1))
+#define SPI_OUTLINK_DSCR_ERROR_INT_RAW_V 0x1
+#define SPI_OUTLINK_DSCR_ERROR_INT_RAW_S 1
+/* SPI_INLINK_DSCR_EMPTY_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: The raw bit for lack of enough inlink descriptors.*/
+#define SPI_INLINK_DSCR_EMPTY_INT_RAW (BIT(0))
+#define SPI_INLINK_DSCR_EMPTY_INT_RAW_M (BIT(0))
+#define SPI_INLINK_DSCR_EMPTY_INT_RAW_V 0x1
+#define SPI_INLINK_DSCR_EMPTY_INT_RAW_S 0
+
+#define SPI_DMA_INT_ST_REG(i) (REG_SPI_BASE(i) + 0x118)
+/* SPI_OUT_TOTAL_EOF_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */
+/*description: The status bit for sending all the packets to host done.*/
+#define SPI_OUT_TOTAL_EOF_INT_ST (BIT(8))
+#define SPI_OUT_TOTAL_EOF_INT_ST_M (BIT(8))
+#define SPI_OUT_TOTAL_EOF_INT_ST_V 0x1
+#define SPI_OUT_TOTAL_EOF_INT_ST_S 8
+/* SPI_OUT_EOF_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */
+/*description: The status bit for sending a packet to host done.*/
+#define SPI_OUT_EOF_INT_ST (BIT(7))
+#define SPI_OUT_EOF_INT_ST_M (BIT(7))
+#define SPI_OUT_EOF_INT_ST_V 0x1
+#define SPI_OUT_EOF_INT_ST_S 7
+/* SPI_OUT_DONE_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */
+/*description: The status bit for completing usage of a outlink descriptor.*/
+#define SPI_OUT_DONE_INT_ST (BIT(6))
+#define SPI_OUT_DONE_INT_ST_M (BIT(6))
+#define SPI_OUT_DONE_INT_ST_V 0x1
+#define SPI_OUT_DONE_INT_ST_S 6
+/* SPI_IN_SUC_EOF_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: The status bit for completing receiving all the packets from host.*/
+#define SPI_IN_SUC_EOF_INT_ST (BIT(5))
+#define SPI_IN_SUC_EOF_INT_ST_M (BIT(5))
+#define SPI_IN_SUC_EOF_INT_ST_V 0x1
+#define SPI_IN_SUC_EOF_INT_ST_S 5
+/* SPI_IN_ERR_EOF_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: The status bit for receiving error.*/
+#define SPI_IN_ERR_EOF_INT_ST (BIT(4))
+#define SPI_IN_ERR_EOF_INT_ST_M (BIT(4))
+#define SPI_IN_ERR_EOF_INT_ST_V 0x1
+#define SPI_IN_ERR_EOF_INT_ST_S 4
+/* SPI_IN_DONE_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: The status bit for completing usage of a inlink descriptor.*/
+#define SPI_IN_DONE_INT_ST (BIT(3))
+#define SPI_IN_DONE_INT_ST_M (BIT(3))
+#define SPI_IN_DONE_INT_ST_V 0x1
+#define SPI_IN_DONE_INT_ST_S 3
+/* SPI_INLINK_DSCR_ERROR_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */
+/*description: The status bit for inlink descriptor error.*/
+#define SPI_INLINK_DSCR_ERROR_INT_ST (BIT(2))
+#define SPI_INLINK_DSCR_ERROR_INT_ST_M (BIT(2))
+#define SPI_INLINK_DSCR_ERROR_INT_ST_V 0x1
+#define SPI_INLINK_DSCR_ERROR_INT_ST_S 2
+/* SPI_OUTLINK_DSCR_ERROR_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: The status bit for outlink descriptor error.*/
+#define SPI_OUTLINK_DSCR_ERROR_INT_ST (BIT(1))
+#define SPI_OUTLINK_DSCR_ERROR_INT_ST_M (BIT(1))
+#define SPI_OUTLINK_DSCR_ERROR_INT_ST_V 0x1
+#define SPI_OUTLINK_DSCR_ERROR_INT_ST_S 1
+/* SPI_INLINK_DSCR_EMPTY_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: The status bit for lack of enough inlink descriptors.*/
+#define SPI_INLINK_DSCR_EMPTY_INT_ST (BIT(0))
+#define SPI_INLINK_DSCR_EMPTY_INT_ST_M (BIT(0))
+#define SPI_INLINK_DSCR_EMPTY_INT_ST_V 0x1
+#define SPI_INLINK_DSCR_EMPTY_INT_ST_S 0
+
+#define SPI_DMA_INT_CLR_REG(i) (REG_SPI_BASE(i) + 0x11C)
+/* SPI_OUT_TOTAL_EOF_INT_CLR : R/W ;bitpos:[8] ;default: 1'b0 ; */
+/*description: The clear bit for sending all the packets to host done.*/
+#define SPI_OUT_TOTAL_EOF_INT_CLR (BIT(8))
+#define SPI_OUT_TOTAL_EOF_INT_CLR_M (BIT(8))
+#define SPI_OUT_TOTAL_EOF_INT_CLR_V 0x1
+#define SPI_OUT_TOTAL_EOF_INT_CLR_S 8
+/* SPI_OUT_EOF_INT_CLR : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: The clear bit for sending a packet to host done.*/
+#define SPI_OUT_EOF_INT_CLR (BIT(7))
+#define SPI_OUT_EOF_INT_CLR_M (BIT(7))
+#define SPI_OUT_EOF_INT_CLR_V 0x1
+#define SPI_OUT_EOF_INT_CLR_S 7
+/* SPI_OUT_DONE_INT_CLR : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: The clear bit for completing usage of a outlink descriptor.*/
+#define SPI_OUT_DONE_INT_CLR (BIT(6))
+#define SPI_OUT_DONE_INT_CLR_M (BIT(6))
+#define SPI_OUT_DONE_INT_CLR_V 0x1
+#define SPI_OUT_DONE_INT_CLR_S 6
+/* SPI_IN_SUC_EOF_INT_CLR : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: The clear bit for completing receiving all the packets from host.*/
+#define SPI_IN_SUC_EOF_INT_CLR (BIT(5))
+#define SPI_IN_SUC_EOF_INT_CLR_M (BIT(5))
+#define SPI_IN_SUC_EOF_INT_CLR_V 0x1
+#define SPI_IN_SUC_EOF_INT_CLR_S 5
+/* SPI_IN_ERR_EOF_INT_CLR : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: The clear bit for receiving error.*/
+#define SPI_IN_ERR_EOF_INT_CLR (BIT(4))
+#define SPI_IN_ERR_EOF_INT_CLR_M (BIT(4))
+#define SPI_IN_ERR_EOF_INT_CLR_V 0x1
+#define SPI_IN_ERR_EOF_INT_CLR_S 4
+/* SPI_IN_DONE_INT_CLR : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: The clear bit for completing usage of a inlink descriptor.*/
+#define SPI_IN_DONE_INT_CLR (BIT(3))
+#define SPI_IN_DONE_INT_CLR_M (BIT(3))
+#define SPI_IN_DONE_INT_CLR_V 0x1
+#define SPI_IN_DONE_INT_CLR_S 3
+/* SPI_INLINK_DSCR_ERROR_INT_CLR : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: The clear bit for inlink descriptor error.*/
+#define SPI_INLINK_DSCR_ERROR_INT_CLR (BIT(2))
+#define SPI_INLINK_DSCR_ERROR_INT_CLR_M (BIT(2))
+#define SPI_INLINK_DSCR_ERROR_INT_CLR_V 0x1
+#define SPI_INLINK_DSCR_ERROR_INT_CLR_S 2
+/* SPI_OUTLINK_DSCR_ERROR_INT_CLR : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: The clear bit for outlink descriptor error.*/
+#define SPI_OUTLINK_DSCR_ERROR_INT_CLR (BIT(1))
+#define SPI_OUTLINK_DSCR_ERROR_INT_CLR_M (BIT(1))
+#define SPI_OUTLINK_DSCR_ERROR_INT_CLR_V 0x1
+#define SPI_OUTLINK_DSCR_ERROR_INT_CLR_S 1
+/* SPI_INLINK_DSCR_EMPTY_INT_CLR : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: The clear bit for lack of enough inlink descriptors.*/
+#define SPI_INLINK_DSCR_EMPTY_INT_CLR (BIT(0))
+#define SPI_INLINK_DSCR_EMPTY_INT_CLR_M (BIT(0))
+#define SPI_INLINK_DSCR_EMPTY_INT_CLR_V 0x1
+#define SPI_INLINK_DSCR_EMPTY_INT_CLR_S 0
+
+#define SPI_IN_ERR_EOF_DES_ADDR_REG(i) (REG_SPI_BASE(i) + 0x120)
+/* SPI_DMA_IN_ERR_EOF_DES_ADDR : RO ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: The inlink descriptor address when spi dma produce receiving error.*/
+#define SPI_DMA_IN_ERR_EOF_DES_ADDR 0xFFFFFFFF
+#define SPI_DMA_IN_ERR_EOF_DES_ADDR_M ((SPI_DMA_IN_ERR_EOF_DES_ADDR_V)<<(SPI_DMA_IN_ERR_EOF_DES_ADDR_S))
+#define SPI_DMA_IN_ERR_EOF_DES_ADDR_V 0xFFFFFFFF
+#define SPI_DMA_IN_ERR_EOF_DES_ADDR_S 0
+
+#define SPI_IN_SUC_EOF_DES_ADDR_REG(i) (REG_SPI_BASE(i) + 0x124)
+/* SPI_DMA_IN_SUC_EOF_DES_ADDR : RO ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: The last inlink descriptor address when spi dma produce from_suc_eof.*/
+#define SPI_DMA_IN_SUC_EOF_DES_ADDR 0xFFFFFFFF
+#define SPI_DMA_IN_SUC_EOF_DES_ADDR_M ((SPI_DMA_IN_SUC_EOF_DES_ADDR_V)<<(SPI_DMA_IN_SUC_EOF_DES_ADDR_S))
+#define SPI_DMA_IN_SUC_EOF_DES_ADDR_V 0xFFFFFFFF
+#define SPI_DMA_IN_SUC_EOF_DES_ADDR_S 0
+
+#define SPI_INLINK_DSCR_REG(i) (REG_SPI_BASE(i) + 0x128)
+/* SPI_DMA_INLINK_DSCR : RO ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: The content of current in descriptor pointer.*/
+#define SPI_DMA_INLINK_DSCR 0xFFFFFFFF
+#define SPI_DMA_INLINK_DSCR_M ((SPI_DMA_INLINK_DSCR_V)<<(SPI_DMA_INLINK_DSCR_S))
+#define SPI_DMA_INLINK_DSCR_V 0xFFFFFFFF
+#define SPI_DMA_INLINK_DSCR_S 0
+
+#define SPI_INLINK_DSCR_BF0_REG(i) (REG_SPI_BASE(i) + 0x12C)
+/* SPI_DMA_INLINK_DSCR_BF0 : RO ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: The content of next in descriptor pointer.*/
+#define SPI_DMA_INLINK_DSCR_BF0 0xFFFFFFFF
+#define SPI_DMA_INLINK_DSCR_BF0_M ((SPI_DMA_INLINK_DSCR_BF0_V)<<(SPI_DMA_INLINK_DSCR_BF0_S))
+#define SPI_DMA_INLINK_DSCR_BF0_V 0xFFFFFFFF
+#define SPI_DMA_INLINK_DSCR_BF0_S 0
+
+#define SPI_INLINK_DSCR_BF1_REG(i) (REG_SPI_BASE(i) + 0x130)
+/* SPI_DMA_INLINK_DSCR_BF1 : RO ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: The content of current in descriptor data buffer pointer.*/
+#define SPI_DMA_INLINK_DSCR_BF1 0xFFFFFFFF
+#define SPI_DMA_INLINK_DSCR_BF1_M ((SPI_DMA_INLINK_DSCR_BF1_V)<<(SPI_DMA_INLINK_DSCR_BF1_S))
+#define SPI_DMA_INLINK_DSCR_BF1_V 0xFFFFFFFF
+#define SPI_DMA_INLINK_DSCR_BF1_S 0
+
+#define SPI_OUT_EOF_BFR_DES_ADDR_REG(i) (REG_SPI_BASE(i) + 0x134)
+/* SPI_DMA_OUT_EOF_BFR_DES_ADDR : RO ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: The address of buffer relative to the outlink descriptor that produce eof.*/
+#define SPI_DMA_OUT_EOF_BFR_DES_ADDR 0xFFFFFFFF
+#define SPI_DMA_OUT_EOF_BFR_DES_ADDR_M ((SPI_DMA_OUT_EOF_BFR_DES_ADDR_V)<<(SPI_DMA_OUT_EOF_BFR_DES_ADDR_S))
+#define SPI_DMA_OUT_EOF_BFR_DES_ADDR_V 0xFFFFFFFF
+#define SPI_DMA_OUT_EOF_BFR_DES_ADDR_S 0
+
+#define SPI_OUT_EOF_DES_ADDR_REG(i) (REG_SPI_BASE(i) + 0x138)
+/* SPI_DMA_OUT_EOF_DES_ADDR : RO ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: The last outlink descriptor address when spi dma produce to_eof.*/
+#define SPI_DMA_OUT_EOF_DES_ADDR 0xFFFFFFFF
+#define SPI_DMA_OUT_EOF_DES_ADDR_M ((SPI_DMA_OUT_EOF_DES_ADDR_V)<<(SPI_DMA_OUT_EOF_DES_ADDR_S))
+#define SPI_DMA_OUT_EOF_DES_ADDR_V 0xFFFFFFFF
+#define SPI_DMA_OUT_EOF_DES_ADDR_S 0
+
+#define SPI_OUTLINK_DSCR_REG(i) (REG_SPI_BASE(i) + 0x13C)
+/* SPI_DMA_OUTLINK_DSCR : RO ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: The content of current out descriptor pointer.*/
+#define SPI_DMA_OUTLINK_DSCR 0xFFFFFFFF
+#define SPI_DMA_OUTLINK_DSCR_M ((SPI_DMA_OUTLINK_DSCR_V)<<(SPI_DMA_OUTLINK_DSCR_S))
+#define SPI_DMA_OUTLINK_DSCR_V 0xFFFFFFFF
+#define SPI_DMA_OUTLINK_DSCR_S 0
+
+#define SPI_OUTLINK_DSCR_BF0_REG(i) (REG_SPI_BASE(i) + 0x140)
+/* SPI_DMA_OUTLINK_DSCR_BF0 : RO ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: The content of next out descriptor pointer.*/
+#define SPI_DMA_OUTLINK_DSCR_BF0 0xFFFFFFFF
+#define SPI_DMA_OUTLINK_DSCR_BF0_M ((SPI_DMA_OUTLINK_DSCR_BF0_V)<<(SPI_DMA_OUTLINK_DSCR_BF0_S))
+#define SPI_DMA_OUTLINK_DSCR_BF0_V 0xFFFFFFFF
+#define SPI_DMA_OUTLINK_DSCR_BF0_S 0
+
+#define SPI_OUTLINK_DSCR_BF1_REG(i) (REG_SPI_BASE(i) + 0x144)
+/* SPI_DMA_OUTLINK_DSCR_BF1 : RO ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: The content of current out descriptor data buffer pointer.*/
+#define SPI_DMA_OUTLINK_DSCR_BF1 0xFFFFFFFF
+#define SPI_DMA_OUTLINK_DSCR_BF1_M ((SPI_DMA_OUTLINK_DSCR_BF1_V)<<(SPI_DMA_OUTLINK_DSCR_BF1_S))
+#define SPI_DMA_OUTLINK_DSCR_BF1_V 0xFFFFFFFF
+#define SPI_DMA_OUTLINK_DSCR_BF1_S 0
+
+#define SPI_DMA_RSTATUS_REG(i) (REG_SPI_BASE(i) + 0x148)
+/* SPI_DMA_OUT_STATUS : RO ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: spi dma read data from memory status.*/
+#define SPI_DMA_OUT_STATUS 0xFFFFFFFF
+#define SPI_DMA_OUT_STATUS_M ((SPI_DMA_OUT_STATUS_V)<<(SPI_DMA_OUT_STATUS_S))
+#define SPI_DMA_OUT_STATUS_V 0xFFFFFFFF
+#define SPI_DMA_OUT_STATUS_S 0
+
+#define SPI_DMA_TSTATUS_REG(i) (REG_SPI_BASE(i) + 0x14C)
+/* SPI_DMA_IN_STATUS : RO ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: spi dma write data to memory status.*/
+#define SPI_DMA_IN_STATUS 0xFFFFFFFF
+#define SPI_DMA_IN_STATUS_M ((SPI_DMA_IN_STATUS_V)<<(SPI_DMA_IN_STATUS_S))
+#define SPI_DMA_IN_STATUS_V 0xFFFFFFFF
+#define SPI_DMA_IN_STATUS_S 0
+
+#define SPI_DATE_REG(i) (REG_SPI_BASE(i) + 0x3FC)
+/* SPI_DATE : RO ;bitpos:[27:0] ;default: 32'h1604270 ; */
+/*description: SPI register version.*/
+#define SPI_DATE 0x0FFFFFFF
+#define SPI_DATE_M ((SPI_DATE_V)<<(SPI_DATE_S))
+#define SPI_DATE_V 0xFFFFFFF
+#define SPI_DATE_S 0
+
+
+
+
+#endif /*__SPI_REG_H__ */
+
+
-// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD\r
-//\r
-// Licensed under the Apache License, Version 2.0 (the "License");\r
-// you may not use this file except in compliance with the License.\r
-// You may obtain a copy of the License at\r
-\r
-// http://www.apache.org/licenses/LICENSE-2.0\r
-//\r
-// Unless required by applicable law or agreed to in writing, software\r
-// distributed under the License is distributed on an "AS IS" BASIS,\r
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
-// See the License for the specific language governing permissions and\r
-// limitations under the License.\r
-#ifndef __UART_REG_H__\r
-#define __UART_REG_H__\r
-\r
-\r
-#include "soc.h"\r
-\r
-#define REG_UART_BASE( i ) (DR_REG_UART_BASE + (i) * 0x10000 + ( i > 1 ? 0xe000 : 0 ) )\r
-#define REG_UART_AHB_BASE(i) (0x60000000 + (i) * 0x10000 + ( i > 1 ? 0xe000 : 0 ) )\r
-#define UART_FIFO_AHB_REG(i) (REG_UART_AHB_BASE(i) + 0x0)\r
-#define UART_FIFO_REG(i) (REG_UART_BASE(i) + 0x0)\r
-\r
-/* UART_RXFIFO_RD_BYTE : RO ;bitpos:[7:0] ;default: 8'b0 ; */\r
-/*description: This register stores one byte data read by rx fifo.*/\r
-#define UART_RXFIFO_RD_BYTE 0x000000FF\r
-#define UART_RXFIFO_RD_BYTE_M ((UART_RXFIFO_RD_BYTE_V)<<(UART_RXFIFO_RD_BYTE_S))\r
-#define UART_RXFIFO_RD_BYTE_V 0xFF\r
-#define UART_RXFIFO_RD_BYTE_S 0\r
-\r
-#define UART_INT_RAW_REG(i) (REG_UART_BASE(i) + 0x4)\r
-/* UART_AT_CMD_CHAR_DET_INT_RAW : RO ;bitpos:[18] ;default: 1'b0 ; */\r
-/*description: This interrupt raw bit turns to high level when receiver detects\r
- the configured at_cmd chars.*/\r
-#define UART_AT_CMD_CHAR_DET_INT_RAW (BIT(18))\r
-#define UART_AT_CMD_CHAR_DET_INT_RAW_M (BIT(18))\r
-#define UART_AT_CMD_CHAR_DET_INT_RAW_V 0x1\r
-#define UART_AT_CMD_CHAR_DET_INT_RAW_S 18\r
-/* UART_RS485_CLASH_INT_RAW : RO ;bitpos:[17] ;default: 1'b0 ; */\r
-/*description: This interrupt raw bit turns to high level when rs485 detects\r
- the clash between transmitter and receiver.*/\r
-#define UART_RS485_CLASH_INT_RAW (BIT(17))\r
-#define UART_RS485_CLASH_INT_RAW_M (BIT(17))\r
-#define UART_RS485_CLASH_INT_RAW_V 0x1\r
-#define UART_RS485_CLASH_INT_RAW_S 17\r
-/* UART_RS485_FRM_ERR_INT_RAW : RO ;bitpos:[16] ;default: 1'b0 ; */\r
-/*description: This interrupt raw bit turns to high level when rs485 detects\r
- the data frame error.*/\r
-#define UART_RS485_FRM_ERR_INT_RAW (BIT(16))\r
-#define UART_RS485_FRM_ERR_INT_RAW_M (BIT(16))\r
-#define UART_RS485_FRM_ERR_INT_RAW_V 0x1\r
-#define UART_RS485_FRM_ERR_INT_RAW_S 16\r
-/* UART_RS485_PARITY_ERR_INT_RAW : RO ;bitpos:[15] ;default: 1'b0 ; */\r
-/*description: This interrupt raw bit turns to high level when rs485 detects the parity error.*/\r
-#define UART_RS485_PARITY_ERR_INT_RAW (BIT(15))\r
-#define UART_RS485_PARITY_ERR_INT_RAW_M (BIT(15))\r
-#define UART_RS485_PARITY_ERR_INT_RAW_V 0x1\r
-#define UART_RS485_PARITY_ERR_INT_RAW_S 15\r
-/* UART_TX_DONE_INT_RAW : RO ;bitpos:[14] ;default: 1'b0 ; */\r
-/*description: This interrupt raw bit turns to high level when transmitter has\r
- send all the data in fifo.*/\r
-#define UART_TX_DONE_INT_RAW (BIT(14))\r
-#define UART_TX_DONE_INT_RAW_M (BIT(14))\r
-#define UART_TX_DONE_INT_RAW_V 0x1\r
-#define UART_TX_DONE_INT_RAW_S 14\r
-/* UART_TX_BRK_IDLE_DONE_INT_RAW : RO ;bitpos:[13] ;default: 1'b0 ; */\r
-/*description: This interrupt raw bit turns to high level when transmitter has\r
- kept the shortest duration after the last data has been send.*/\r
-#define UART_TX_BRK_IDLE_DONE_INT_RAW (BIT(13))\r
-#define UART_TX_BRK_IDLE_DONE_INT_RAW_M (BIT(13))\r
-#define UART_TX_BRK_IDLE_DONE_INT_RAW_V 0x1\r
-#define UART_TX_BRK_IDLE_DONE_INT_RAW_S 13\r
-/* UART_TX_BRK_DONE_INT_RAW : RO ;bitpos:[12] ;default: 1'b0 ; */\r
-/*description: This interrupt raw bit turns to high level when transmitter completes\r
- sendding 0 after all the datas in transmitter's fifo are send.*/\r
-#define UART_TX_BRK_DONE_INT_RAW (BIT(12))\r
-#define UART_TX_BRK_DONE_INT_RAW_M (BIT(12))\r
-#define UART_TX_BRK_DONE_INT_RAW_V 0x1\r
-#define UART_TX_BRK_DONE_INT_RAW_S 12\r
-/* UART_GLITCH_DET_INT_RAW : RO ;bitpos:[11] ;default: 1'b0 ; */\r
-/*description: This interrupt raw bit turns to high level when receiver detects the start bit.*/\r
-#define UART_GLITCH_DET_INT_RAW (BIT(11))\r
-#define UART_GLITCH_DET_INT_RAW_M (BIT(11))\r
-#define UART_GLITCH_DET_INT_RAW_V 0x1\r
-#define UART_GLITCH_DET_INT_RAW_S 11\r
-/* UART_SW_XOFF_INT_RAW : RO ;bitpos:[10] ;default: 1'b0 ; */\r
-/*description: This interrupt raw bit turns to high level when receiver receives\r
- xon char with uart_sw_flow_con_en is set to 1.*/\r
-#define UART_SW_XOFF_INT_RAW (BIT(10))\r
-#define UART_SW_XOFF_INT_RAW_M (BIT(10))\r
-#define UART_SW_XOFF_INT_RAW_V 0x1\r
-#define UART_SW_XOFF_INT_RAW_S 10\r
-/* UART_SW_XON_INT_RAW : RO ;bitpos:[9] ;default: 1'b0 ; */\r
-/*description: This interrupt raw bit turns to high level when receiver receives\r
- xoff char with uart_sw_flow_con_en is set to 1.*/\r
-#define UART_SW_XON_INT_RAW (BIT(9))\r
-#define UART_SW_XON_INT_RAW_M (BIT(9))\r
-#define UART_SW_XON_INT_RAW_V 0x1\r
-#define UART_SW_XON_INT_RAW_S 9\r
-/* UART_RXFIFO_TOUT_INT_RAW : RO ;bitpos:[8] ;default: 1'b0 ; */\r
-/*description: This interrupt raw bit turns to high level when receiver takes\r
- more time than rx_tout_thrhd to receive a byte.*/\r
-#define UART_RXFIFO_TOUT_INT_RAW (BIT(8))\r
-#define UART_RXFIFO_TOUT_INT_RAW_M (BIT(8))\r
-#define UART_RXFIFO_TOUT_INT_RAW_V 0x1\r
-#define UART_RXFIFO_TOUT_INT_RAW_S 8\r
-/* UART_BRK_DET_INT_RAW : RO ;bitpos:[7] ;default: 1'b0 ; */\r
-/*description: This interrupt raw bit turns to high level when receiver detects\r
- the 0 after the stop bit.*/\r
-#define UART_BRK_DET_INT_RAW (BIT(7))\r
-#define UART_BRK_DET_INT_RAW_M (BIT(7))\r
-#define UART_BRK_DET_INT_RAW_V 0x1\r
-#define UART_BRK_DET_INT_RAW_S 7\r
-/* UART_CTS_CHG_INT_RAW : RO ;bitpos:[6] ;default: 1'b0 ; */\r
-/*description: This interrupt raw bit turns to high level when receiver detects\r
- the edge change of ctsn signal.*/\r
-#define UART_CTS_CHG_INT_RAW (BIT(6))\r
-#define UART_CTS_CHG_INT_RAW_M (BIT(6))\r
-#define UART_CTS_CHG_INT_RAW_V 0x1\r
-#define UART_CTS_CHG_INT_RAW_S 6\r
-/* UART_DSR_CHG_INT_RAW : RO ;bitpos:[5] ;default: 1'b0 ; */\r
-/*description: This interrupt raw bit turns to high level when receiver detects\r
- the edge change of dsrn signal.*/\r
-#define UART_DSR_CHG_INT_RAW (BIT(5))\r
-#define UART_DSR_CHG_INT_RAW_M (BIT(5))\r
-#define UART_DSR_CHG_INT_RAW_V 0x1\r
-#define UART_DSR_CHG_INT_RAW_S 5\r
-/* UART_RXFIFO_OVF_INT_RAW : RO ;bitpos:[4] ;default: 1'b0 ; */\r
-/*description: This interrupt raw bit turns to high level when receiver receives\r
- more data than the fifo can store.*/\r
-#define UART_RXFIFO_OVF_INT_RAW (BIT(4))\r
-#define UART_RXFIFO_OVF_INT_RAW_M (BIT(4))\r
-#define UART_RXFIFO_OVF_INT_RAW_V 0x1\r
-#define UART_RXFIFO_OVF_INT_RAW_S 4\r
-/* UART_FRM_ERR_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */\r
-/*description: This interrupt raw bit turns to high level when receiver detects\r
- data's frame error .*/\r
-#define UART_FRM_ERR_INT_RAW (BIT(3))\r
-#define UART_FRM_ERR_INT_RAW_M (BIT(3))\r
-#define UART_FRM_ERR_INT_RAW_V 0x1\r
-#define UART_FRM_ERR_INT_RAW_S 3\r
-/* UART_PARITY_ERR_INT_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */\r
-/*description: This interrupt raw bit turns to high level when receiver detects\r
- the parity error of data.*/\r
-#define UART_PARITY_ERR_INT_RAW (BIT(2))\r
-#define UART_PARITY_ERR_INT_RAW_M (BIT(2))\r
-#define UART_PARITY_ERR_INT_RAW_V 0x1\r
-#define UART_PARITY_ERR_INT_RAW_S 2\r
-/* UART_TXFIFO_EMPTY_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */\r
-/*description: This interrupt raw bit turns to high level when the amount of\r
- data in transmitter's fifo is less than ((tx_mem_cnttxfifo_cnt) .*/\r
-#define UART_TXFIFO_EMPTY_INT_RAW (BIT(1))\r
-#define UART_TXFIFO_EMPTY_INT_RAW_M (BIT(1))\r
-#define UART_TXFIFO_EMPTY_INT_RAW_V 0x1\r
-#define UART_TXFIFO_EMPTY_INT_RAW_S 1\r
-/* UART_RXFIFO_FULL_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */\r
-/*description: This interrupt raw bit turns to high level when receiver receives\r
- more data than (rx_flow_thrhd_h3 rx_flow_thrhd).*/\r
-#define UART_RXFIFO_FULL_INT_RAW (BIT(0))\r
-#define UART_RXFIFO_FULL_INT_RAW_M (BIT(0))\r
-#define UART_RXFIFO_FULL_INT_RAW_V 0x1\r
-#define UART_RXFIFO_FULL_INT_RAW_S 0\r
-\r
-#define UART_INT_ST_REG(i) (REG_UART_BASE(i) + 0x8)\r
-/* UART_AT_CMD_CHAR_DET_INT_ST : RO ;bitpos:[18] ;default: 1'b0 ; */\r
-/*description: This is the status bit for at_cmd_det_int_raw when at_cmd_char_det_int_ena\r
- is set to 1.*/\r
-#define UART_AT_CMD_CHAR_DET_INT_ST (BIT(18))\r
-#define UART_AT_CMD_CHAR_DET_INT_ST_M (BIT(18))\r
-#define UART_AT_CMD_CHAR_DET_INT_ST_V 0x1\r
-#define UART_AT_CMD_CHAR_DET_INT_ST_S 18\r
-/* UART_RS485_CLASH_INT_ST : RO ;bitpos:[17] ;default: 1'b0 ; */\r
-/*description: This is the status bit for rs485_clash_int_raw when rs485_clash_int_ena\r
- is set to 1.*/\r
-#define UART_RS485_CLASH_INT_ST (BIT(17))\r
-#define UART_RS485_CLASH_INT_ST_M (BIT(17))\r
-#define UART_RS485_CLASH_INT_ST_V 0x1\r
-#define UART_RS485_CLASH_INT_ST_S 17\r
-/* UART_RS485_FRM_ERR_INT_ST : RO ;bitpos:[16] ;default: 1'b0 ; */\r
-/*description: This is the status bit for rs485_fm_err_int_raw when rs485_fm_err_int_ena\r
- is set to 1.*/\r
-#define UART_RS485_FRM_ERR_INT_ST (BIT(16))\r
-#define UART_RS485_FRM_ERR_INT_ST_M (BIT(16))\r
-#define UART_RS485_FRM_ERR_INT_ST_V 0x1\r
-#define UART_RS485_FRM_ERR_INT_ST_S 16\r
-/* UART_RS485_PARITY_ERR_INT_ST : RO ;bitpos:[15] ;default: 1'b0 ; */\r
-/*description: This is the status bit for rs485_parity_err_int_raw when rs485_parity_int_ena\r
- is set to 1.*/\r
-#define UART_RS485_PARITY_ERR_INT_ST (BIT(15))\r
-#define UART_RS485_PARITY_ERR_INT_ST_M (BIT(15))\r
-#define UART_RS485_PARITY_ERR_INT_ST_V 0x1\r
-#define UART_RS485_PARITY_ERR_INT_ST_S 15\r
-/* UART_TX_DONE_INT_ST : RO ;bitpos:[14] ;default: 1'b0 ; */\r
-/*description: This is the status bit for tx_done_int_raw when tx_done_int_ena is set to 1.*/\r
-#define UART_TX_DONE_INT_ST (BIT(14))\r
-#define UART_TX_DONE_INT_ST_M (BIT(14))\r
-#define UART_TX_DONE_INT_ST_V 0x1\r
-#define UART_TX_DONE_INT_ST_S 14\r
-/* UART_TX_BRK_IDLE_DONE_INT_ST : RO ;bitpos:[13] ;default: 1'b0 ; */\r
-/*description: This is the stauts bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena\r
- is set to 1.*/\r
-#define UART_TX_BRK_IDLE_DONE_INT_ST (BIT(13))\r
-#define UART_TX_BRK_IDLE_DONE_INT_ST_M (BIT(13))\r
-#define UART_TX_BRK_IDLE_DONE_INT_ST_V 0x1\r
-#define UART_TX_BRK_IDLE_DONE_INT_ST_S 13\r
-/* UART_TX_BRK_DONE_INT_ST : RO ;bitpos:[12] ;default: 1'b0 ; */\r
-/*description: This is the status bit for tx_brk_done_int_raw when tx_brk_done_int_ena\r
- is set to 1.*/\r
-#define UART_TX_BRK_DONE_INT_ST (BIT(12))\r
-#define UART_TX_BRK_DONE_INT_ST_M (BIT(12))\r
-#define UART_TX_BRK_DONE_INT_ST_V 0x1\r
-#define UART_TX_BRK_DONE_INT_ST_S 12\r
-/* UART_GLITCH_DET_INT_ST : RO ;bitpos:[11] ;default: 1'b0 ; */\r
-/*description: This is the status bit for glitch_det_int_raw when glitch_det_int_ena\r
- is set to 1.*/\r
-#define UART_GLITCH_DET_INT_ST (BIT(11))\r
-#define UART_GLITCH_DET_INT_ST_M (BIT(11))\r
-#define UART_GLITCH_DET_INT_ST_V 0x1\r
-#define UART_GLITCH_DET_INT_ST_S 11\r
-/* UART_SW_XOFF_INT_ST : RO ;bitpos:[10] ;default: 1'b0 ; */\r
-/*description: This is the status bit for sw_xoff_int_raw when sw_xoff_int_ena is set to 1.*/\r
-#define UART_SW_XOFF_INT_ST (BIT(10))\r
-#define UART_SW_XOFF_INT_ST_M (BIT(10))\r
-#define UART_SW_XOFF_INT_ST_V 0x1\r
-#define UART_SW_XOFF_INT_ST_S 10\r
-/* UART_SW_XON_INT_ST : RO ;bitpos:[9] ;default: 1'b0 ; */\r
-/*description: This is the status bit for sw_xon_int_raw when sw_xon_int_ena is set to 1.*/\r
-#define UART_SW_XON_INT_ST (BIT(9))\r
-#define UART_SW_XON_INT_ST_M (BIT(9))\r
-#define UART_SW_XON_INT_ST_V 0x1\r
-#define UART_SW_XON_INT_ST_S 9\r
-/* UART_RXFIFO_TOUT_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */\r
-/*description: This is the status bit for rxfifo_tout_int_raw when rxfifo_tout_int_ena\r
- is set to 1.*/\r
-#define UART_RXFIFO_TOUT_INT_ST (BIT(8))\r
-#define UART_RXFIFO_TOUT_INT_ST_M (BIT(8))\r
-#define UART_RXFIFO_TOUT_INT_ST_V 0x1\r
-#define UART_RXFIFO_TOUT_INT_ST_S 8\r
-/* UART_BRK_DET_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */\r
-/*description: This is the status bit for brk_det_int_raw when brk_det_int_ena is set to 1.*/\r
-#define UART_BRK_DET_INT_ST (BIT(7))\r
-#define UART_BRK_DET_INT_ST_M (BIT(7))\r
-#define UART_BRK_DET_INT_ST_V 0x1\r
-#define UART_BRK_DET_INT_ST_S 7\r
-/* UART_CTS_CHG_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */\r
-/*description: This is the status bit for cts_chg_int_raw when cts_chg_int_ena is set to 1.*/\r
-#define UART_CTS_CHG_INT_ST (BIT(6))\r
-#define UART_CTS_CHG_INT_ST_M (BIT(6))\r
-#define UART_CTS_CHG_INT_ST_V 0x1\r
-#define UART_CTS_CHG_INT_ST_S 6\r
-/* UART_DSR_CHG_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */\r
-/*description: This is the status bit for dsr_chg_int_raw when dsr_chg_int_ena is set to 1.*/\r
-#define UART_DSR_CHG_INT_ST (BIT(5))\r
-#define UART_DSR_CHG_INT_ST_M (BIT(5))\r
-#define UART_DSR_CHG_INT_ST_V 0x1\r
-#define UART_DSR_CHG_INT_ST_S 5\r
-/* UART_RXFIFO_OVF_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */\r
-/*description: This is the status bit for rxfifo_ovf_int_raw when rxfifo_ovf_int_ena\r
- is set to 1.*/\r
-#define UART_RXFIFO_OVF_INT_ST (BIT(4))\r
-#define UART_RXFIFO_OVF_INT_ST_M (BIT(4))\r
-#define UART_RXFIFO_OVF_INT_ST_V 0x1\r
-#define UART_RXFIFO_OVF_INT_ST_S 4\r
-/* UART_FRM_ERR_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */\r
-/*description: This is the status bit for frm_err_int_raw when fm_err_int_ena is set to 1.*/\r
-#define UART_FRM_ERR_INT_ST (BIT(3))\r
-#define UART_FRM_ERR_INT_ST_M (BIT(3))\r
-#define UART_FRM_ERR_INT_ST_V 0x1\r
-#define UART_FRM_ERR_INT_ST_S 3\r
-/* UART_PARITY_ERR_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */\r
-/*description: This is the status bit for parity_err_int_raw when parity_err_int_ena\r
- is set to 1.*/\r
-#define UART_PARITY_ERR_INT_ST (BIT(2))\r
-#define UART_PARITY_ERR_INT_ST_M (BIT(2))\r
-#define UART_PARITY_ERR_INT_ST_V 0x1\r
-#define UART_PARITY_ERR_INT_ST_S 2\r
-/* UART_TXFIFO_EMPTY_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */\r
-/*description: This is the status bit for txfifo_empty_int_raw when txfifo_empty_int_ena\r
- is set to 1.*/\r
-#define UART_TXFIFO_EMPTY_INT_ST (BIT(1))\r
-#define UART_TXFIFO_EMPTY_INT_ST_M (BIT(1))\r
-#define UART_TXFIFO_EMPTY_INT_ST_V 0x1\r
-#define UART_TXFIFO_EMPTY_INT_ST_S 1\r
-/* UART_RXFIFO_FULL_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */\r
-/*description: This is the status bit for rxfifo_full_int_raw when rxfifo_full_int_ena\r
- is set to 1.*/\r
-#define UART_RXFIFO_FULL_INT_ST (BIT(0))\r
-#define UART_RXFIFO_FULL_INT_ST_M (BIT(0))\r
-#define UART_RXFIFO_FULL_INT_ST_V 0x1\r
-#define UART_RXFIFO_FULL_INT_ST_S 0\r
-\r
-#define UART_INT_ENA_REG(i) (REG_UART_BASE(i) + 0xC)\r
-/* UART_AT_CMD_CHAR_DET_INT_ENA : R/W ;bitpos:[18] ;default: 1'b0 ; */\r
-/*description: This is the enable bit for at_cmd_char_det_int_st register.*/\r
-#define UART_AT_CMD_CHAR_DET_INT_ENA (BIT(18))\r
-#define UART_AT_CMD_CHAR_DET_INT_ENA_M (BIT(18))\r
-#define UART_AT_CMD_CHAR_DET_INT_ENA_V 0x1\r
-#define UART_AT_CMD_CHAR_DET_INT_ENA_S 18\r
-/* UART_RS485_CLASH_INT_ENA : R/W ;bitpos:[17] ;default: 1'b0 ; */\r
-/*description: This is the enable bit for rs485_clash_int_st register.*/\r
-#define UART_RS485_CLASH_INT_ENA (BIT(17))\r
-#define UART_RS485_CLASH_INT_ENA_M (BIT(17))\r
-#define UART_RS485_CLASH_INT_ENA_V 0x1\r
-#define UART_RS485_CLASH_INT_ENA_S 17\r
-/* UART_RS485_FRM_ERR_INT_ENA : R/W ;bitpos:[16] ;default: 1'b0 ; */\r
-/*description: This is the enable bit for rs485_parity_err_int_st register.*/\r
-#define UART_RS485_FRM_ERR_INT_ENA (BIT(16))\r
-#define UART_RS485_FRM_ERR_INT_ENA_M (BIT(16))\r
-#define UART_RS485_FRM_ERR_INT_ENA_V 0x1\r
-#define UART_RS485_FRM_ERR_INT_ENA_S 16\r
-/* UART_RS485_PARITY_ERR_INT_ENA : R/W ;bitpos:[15] ;default: 1'b0 ; */\r
-/*description: This is the enable bit for rs485_parity_err_int_st register.*/\r
-#define UART_RS485_PARITY_ERR_INT_ENA (BIT(15))\r
-#define UART_RS485_PARITY_ERR_INT_ENA_M (BIT(15))\r
-#define UART_RS485_PARITY_ERR_INT_ENA_V 0x1\r
-#define UART_RS485_PARITY_ERR_INT_ENA_S 15\r
-/* UART_TX_DONE_INT_ENA : R/W ;bitpos:[14] ;default: 1'b0 ; */\r
-/*description: This is the enable bit for tx_done_int_st register.*/\r
-#define UART_TX_DONE_INT_ENA (BIT(14))\r
-#define UART_TX_DONE_INT_ENA_M (BIT(14))\r
-#define UART_TX_DONE_INT_ENA_V 0x1\r
-#define UART_TX_DONE_INT_ENA_S 14\r
-/* UART_TX_BRK_IDLE_DONE_INT_ENA : R/W ;bitpos:[13] ;default: 1'b0 ; */\r
-/*description: This is the enable bit for tx_brk_idle_done_int_st register.*/\r
-#define UART_TX_BRK_IDLE_DONE_INT_ENA (BIT(13))\r
-#define UART_TX_BRK_IDLE_DONE_INT_ENA_M (BIT(13))\r
-#define UART_TX_BRK_IDLE_DONE_INT_ENA_V 0x1\r
-#define UART_TX_BRK_IDLE_DONE_INT_ENA_S 13\r
-/* UART_TX_BRK_DONE_INT_ENA : R/W ;bitpos:[12] ;default: 1'b0 ; */\r
-/*description: This is the enable bit for tx_brk_done_int_st register.*/\r
-#define UART_TX_BRK_DONE_INT_ENA (BIT(12))\r
-#define UART_TX_BRK_DONE_INT_ENA_M (BIT(12))\r
-#define UART_TX_BRK_DONE_INT_ENA_V 0x1\r
-#define UART_TX_BRK_DONE_INT_ENA_S 12\r
-/* UART_GLITCH_DET_INT_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */\r
-/*description: This is the enable bit for glitch_det_int_st register.*/\r
-#define UART_GLITCH_DET_INT_ENA (BIT(11))\r
-#define UART_GLITCH_DET_INT_ENA_M (BIT(11))\r
-#define UART_GLITCH_DET_INT_ENA_V 0x1\r
-#define UART_GLITCH_DET_INT_ENA_S 11\r
-/* UART_SW_XOFF_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */\r
-/*description: This is the enable bit for sw_xoff_int_st register.*/\r
-#define UART_SW_XOFF_INT_ENA (BIT(10))\r
-#define UART_SW_XOFF_INT_ENA_M (BIT(10))\r
-#define UART_SW_XOFF_INT_ENA_V 0x1\r
-#define UART_SW_XOFF_INT_ENA_S 10\r
-/* UART_SW_XON_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */\r
-/*description: This is the enable bit for sw_xon_int_st register.*/\r
-#define UART_SW_XON_INT_ENA (BIT(9))\r
-#define UART_SW_XON_INT_ENA_M (BIT(9))\r
-#define UART_SW_XON_INT_ENA_V 0x1\r
-#define UART_SW_XON_INT_ENA_S 9\r
-/* UART_RXFIFO_TOUT_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */\r
-/*description: This is the enable bit for rxfifo_tout_int_st register.*/\r
-#define UART_RXFIFO_TOUT_INT_ENA (BIT(8))\r
-#define UART_RXFIFO_TOUT_INT_ENA_M (BIT(8))\r
-#define UART_RXFIFO_TOUT_INT_ENA_V 0x1\r
-#define UART_RXFIFO_TOUT_INT_ENA_S 8\r
-/* UART_BRK_DET_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */\r
-/*description: This is the enable bit for brk_det_int_st register.*/\r
-#define UART_BRK_DET_INT_ENA (BIT(7))\r
-#define UART_BRK_DET_INT_ENA_M (BIT(7))\r
-#define UART_BRK_DET_INT_ENA_V 0x1\r
-#define UART_BRK_DET_INT_ENA_S 7\r
-/* UART_CTS_CHG_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */\r
-/*description: This is the enable bit for cts_chg_int_st register.*/\r
-#define UART_CTS_CHG_INT_ENA (BIT(6))\r
-#define UART_CTS_CHG_INT_ENA_M (BIT(6))\r
-#define UART_CTS_CHG_INT_ENA_V 0x1\r
-#define UART_CTS_CHG_INT_ENA_S 6\r
-/* UART_DSR_CHG_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */\r
-/*description: This is the enable bit for dsr_chg_int_st register.*/\r
-#define UART_DSR_CHG_INT_ENA (BIT(5))\r
-#define UART_DSR_CHG_INT_ENA_M (BIT(5))\r
-#define UART_DSR_CHG_INT_ENA_V 0x1\r
-#define UART_DSR_CHG_INT_ENA_S 5\r
-/* UART_RXFIFO_OVF_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */\r
-/*description: This is the enable bit for rxfifo_ovf_int_st register.*/\r
-#define UART_RXFIFO_OVF_INT_ENA (BIT(4))\r
-#define UART_RXFIFO_OVF_INT_ENA_M (BIT(4))\r
-#define UART_RXFIFO_OVF_INT_ENA_V 0x1\r
-#define UART_RXFIFO_OVF_INT_ENA_S 4\r
-/* UART_FRM_ERR_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */\r
-/*description: This is the enable bit for frm_err_int_st register.*/\r
-#define UART_FRM_ERR_INT_ENA (BIT(3))\r
-#define UART_FRM_ERR_INT_ENA_M (BIT(3))\r
-#define UART_FRM_ERR_INT_ENA_V 0x1\r
-#define UART_FRM_ERR_INT_ENA_S 3\r
-/* UART_PARITY_ERR_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */\r
-/*description: This is the enable bit for parity_err_int_st register.*/\r
-#define UART_PARITY_ERR_INT_ENA (BIT(2))\r
-#define UART_PARITY_ERR_INT_ENA_M (BIT(2))\r
-#define UART_PARITY_ERR_INT_ENA_V 0x1\r
-#define UART_PARITY_ERR_INT_ENA_S 2\r
-/* UART_TXFIFO_EMPTY_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */\r
-/*description: This is the enable bit for rxfifo_full_int_st register.*/\r
-#define UART_TXFIFO_EMPTY_INT_ENA (BIT(1))\r
-#define UART_TXFIFO_EMPTY_INT_ENA_M (BIT(1))\r
-#define UART_TXFIFO_EMPTY_INT_ENA_V 0x1\r
-#define UART_TXFIFO_EMPTY_INT_ENA_S 1\r
-/* UART_RXFIFO_FULL_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */\r
-/*description: This is the enable bit for rxfifo_full_int_st register.*/\r
-#define UART_RXFIFO_FULL_INT_ENA (BIT(0))\r
-#define UART_RXFIFO_FULL_INT_ENA_M (BIT(0))\r
-#define UART_RXFIFO_FULL_INT_ENA_V 0x1\r
-#define UART_RXFIFO_FULL_INT_ENA_S 0\r
-\r
-#define UART_INT_CLR_REG(i) (REG_UART_BASE(i) + 0x10)\r
-/* UART_AT_CMD_CHAR_DET_INT_CLR : WO ;bitpos:[18] ;default: 1'b0 ; */\r
-/*description: Set this bit to clear the at_cmd_char_det_int_raw interrupt.*/\r
-#define UART_AT_CMD_CHAR_DET_INT_CLR (BIT(18))\r
-#define UART_AT_CMD_CHAR_DET_INT_CLR_M (BIT(18))\r
-#define UART_AT_CMD_CHAR_DET_INT_CLR_V 0x1\r
-#define UART_AT_CMD_CHAR_DET_INT_CLR_S 18\r
-/* UART_RS485_CLASH_INT_CLR : WO ;bitpos:[17] ;default: 1'b0 ; */\r
-/*description: Set this bit to clear the rs485_clash_int_raw interrupt.*/\r
-#define UART_RS485_CLASH_INT_CLR (BIT(17))\r
-#define UART_RS485_CLASH_INT_CLR_M (BIT(17))\r
-#define UART_RS485_CLASH_INT_CLR_V 0x1\r
-#define UART_RS485_CLASH_INT_CLR_S 17\r
-/* UART_RS485_FRM_ERR_INT_CLR : WO ;bitpos:[16] ;default: 1'b0 ; */\r
-/*description: Set this bit to clear the rs485_frm_err_int_raw interrupt.*/\r
-#define UART_RS485_FRM_ERR_INT_CLR (BIT(16))\r
-#define UART_RS485_FRM_ERR_INT_CLR_M (BIT(16))\r
-#define UART_RS485_FRM_ERR_INT_CLR_V 0x1\r
-#define UART_RS485_FRM_ERR_INT_CLR_S 16\r
-/* UART_RS485_PARITY_ERR_INT_CLR : WO ;bitpos:[15] ;default: 1'b0 ; */\r
-/*description: Set this bit to clear the rs485_parity_err_int_raw interrupt.*/\r
-#define UART_RS485_PARITY_ERR_INT_CLR (BIT(15))\r
-#define UART_RS485_PARITY_ERR_INT_CLR_M (BIT(15))\r
-#define UART_RS485_PARITY_ERR_INT_CLR_V 0x1\r
-#define UART_RS485_PARITY_ERR_INT_CLR_S 15\r
-/* UART_TX_DONE_INT_CLR : WO ;bitpos:[14] ;default: 1'b0 ; */\r
-/*description: Set this bit to clear the tx_done_int_raw interrupt.*/\r
-#define UART_TX_DONE_INT_CLR (BIT(14))\r
-#define UART_TX_DONE_INT_CLR_M (BIT(14))\r
-#define UART_TX_DONE_INT_CLR_V 0x1\r
-#define UART_TX_DONE_INT_CLR_S 14\r
-/* UART_TX_BRK_IDLE_DONE_INT_CLR : WO ;bitpos:[13] ;default: 1'b0 ; */\r
-/*description: Set this bit to clear the tx_brk_idle_done_int_raw interrupt.*/\r
-#define UART_TX_BRK_IDLE_DONE_INT_CLR (BIT(13))\r
-#define UART_TX_BRK_IDLE_DONE_INT_CLR_M (BIT(13))\r
-#define UART_TX_BRK_IDLE_DONE_INT_CLR_V 0x1\r
-#define UART_TX_BRK_IDLE_DONE_INT_CLR_S 13\r
-/* UART_TX_BRK_DONE_INT_CLR : WO ;bitpos:[12] ;default: 1'b0 ; */\r
-/*description: Set this bit to clear the tx_brk_done_int_raw interrupt..*/\r
-#define UART_TX_BRK_DONE_INT_CLR (BIT(12))\r
-#define UART_TX_BRK_DONE_INT_CLR_M (BIT(12))\r
-#define UART_TX_BRK_DONE_INT_CLR_V 0x1\r
-#define UART_TX_BRK_DONE_INT_CLR_S 12\r
-/* UART_GLITCH_DET_INT_CLR : WO ;bitpos:[11] ;default: 1'b0 ; */\r
-/*description: Set this bit to clear the glitch_det_int_raw interrupt.*/\r
-#define UART_GLITCH_DET_INT_CLR (BIT(11))\r
-#define UART_GLITCH_DET_INT_CLR_M (BIT(11))\r
-#define UART_GLITCH_DET_INT_CLR_V 0x1\r
-#define UART_GLITCH_DET_INT_CLR_S 11\r
-/* UART_SW_XOFF_INT_CLR : WO ;bitpos:[10] ;default: 1'b0 ; */\r
-/*description: Set this bit to clear the sw_xon_int_raw interrupt.*/\r
-#define UART_SW_XOFF_INT_CLR (BIT(10))\r
-#define UART_SW_XOFF_INT_CLR_M (BIT(10))\r
-#define UART_SW_XOFF_INT_CLR_V 0x1\r
-#define UART_SW_XOFF_INT_CLR_S 10\r
-/* UART_SW_XON_INT_CLR : WO ;bitpos:[9] ;default: 1'b0 ; */\r
-/*description: Set this bit to clear the sw_xon_int_raw interrupt.*/\r
-#define UART_SW_XON_INT_CLR (BIT(9))\r
-#define UART_SW_XON_INT_CLR_M (BIT(9))\r
-#define UART_SW_XON_INT_CLR_V 0x1\r
-#define UART_SW_XON_INT_CLR_S 9\r
-/* UART_RXFIFO_TOUT_INT_CLR : WO ;bitpos:[8] ;default: 1'b0 ; */\r
-/*description: Set this bit to clear the rxfifo_tout_int_raw interrupt.*/\r
-#define UART_RXFIFO_TOUT_INT_CLR (BIT(8))\r
-#define UART_RXFIFO_TOUT_INT_CLR_M (BIT(8))\r
-#define UART_RXFIFO_TOUT_INT_CLR_V 0x1\r
-#define UART_RXFIFO_TOUT_INT_CLR_S 8\r
-/* UART_BRK_DET_INT_CLR : WO ;bitpos:[7] ;default: 1'b0 ; */\r
-/*description: Set this bit to clear the brk_det_int_raw interrupt.*/\r
-#define UART_BRK_DET_INT_CLR (BIT(7))\r
-#define UART_BRK_DET_INT_CLR_M (BIT(7))\r
-#define UART_BRK_DET_INT_CLR_V 0x1\r
-#define UART_BRK_DET_INT_CLR_S 7\r
-/* UART_CTS_CHG_INT_CLR : WO ;bitpos:[6] ;default: 1'b0 ; */\r
-/*description: Set this bit to clear the cts_chg_int_raw interrupt.*/\r
-#define UART_CTS_CHG_INT_CLR (BIT(6))\r
-#define UART_CTS_CHG_INT_CLR_M (BIT(6))\r
-#define UART_CTS_CHG_INT_CLR_V 0x1\r
-#define UART_CTS_CHG_INT_CLR_S 6\r
-/* UART_DSR_CHG_INT_CLR : WO ;bitpos:[5] ;default: 1'b0 ; */\r
-/*description: Set this bit to clear the dsr_chg_int_raw interrupt.*/\r
-#define UART_DSR_CHG_INT_CLR (BIT(5))\r
-#define UART_DSR_CHG_INT_CLR_M (BIT(5))\r
-#define UART_DSR_CHG_INT_CLR_V 0x1\r
-#define UART_DSR_CHG_INT_CLR_S 5\r
-/* UART_RXFIFO_OVF_INT_CLR : WO ;bitpos:[4] ;default: 1'b0 ; */\r
-/*description: Set this bit to clear rxfifo_ovf_int_raw interrupt.*/\r
-#define UART_RXFIFO_OVF_INT_CLR (BIT(4))\r
-#define UART_RXFIFO_OVF_INT_CLR_M (BIT(4))\r
-#define UART_RXFIFO_OVF_INT_CLR_V 0x1\r
-#define UART_RXFIFO_OVF_INT_CLR_S 4\r
-/* UART_FRM_ERR_INT_CLR : WO ;bitpos:[3] ;default: 1'b0 ; */\r
-/*description: Set this bit to clear frm_err_int_raw interrupt.*/\r
-#define UART_FRM_ERR_INT_CLR (BIT(3))\r
-#define UART_FRM_ERR_INT_CLR_M (BIT(3))\r
-#define UART_FRM_ERR_INT_CLR_V 0x1\r
-#define UART_FRM_ERR_INT_CLR_S 3\r
-/* UART_PARITY_ERR_INT_CLR : WO ;bitpos:[2] ;default: 1'b0 ; */\r
-/*description: Set this bit to clear parity_err_int_raw interrupt.*/\r
-#define UART_PARITY_ERR_INT_CLR (BIT(2))\r
-#define UART_PARITY_ERR_INT_CLR_M (BIT(2))\r
-#define UART_PARITY_ERR_INT_CLR_V 0x1\r
-#define UART_PARITY_ERR_INT_CLR_S 2\r
-/* UART_TXFIFO_EMPTY_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */\r
-/*description: Set this bit to clear txfifo_empty_int_raw interrupt.*/\r
-#define UART_TXFIFO_EMPTY_INT_CLR (BIT(1))\r
-#define UART_TXFIFO_EMPTY_INT_CLR_M (BIT(1))\r
-#define UART_TXFIFO_EMPTY_INT_CLR_V 0x1\r
-#define UART_TXFIFO_EMPTY_INT_CLR_S 1\r
-/* UART_RXFIFO_FULL_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */\r
-/*description: Set this bit to clear the rxfifo_full_int_raw interrupt.*/\r
-#define UART_RXFIFO_FULL_INT_CLR (BIT(0))\r
-#define UART_RXFIFO_FULL_INT_CLR_M (BIT(0))\r
-#define UART_RXFIFO_FULL_INT_CLR_V 0x1\r
-#define UART_RXFIFO_FULL_INT_CLR_S 0\r
-\r
-#define UART_CLKDIV_REG(i) (REG_UART_BASE(i) + 0x14)\r
-/* UART_CLKDIV_FRAG : R/W ;bitpos:[23:20] ;default: 4'h0 ; */\r
-/*description: The register value is the decimal part of the frequency divider's factor.*/\r
-#define UART_CLKDIV_FRAG 0x0000000F\r
-#define UART_CLKDIV_FRAG_M ((UART_CLKDIV_FRAG_V)<<(UART_CLKDIV_FRAG_S))\r
-#define UART_CLKDIV_FRAG_V 0xF\r
-#define UART_CLKDIV_FRAG_S 20\r
-/* UART_CLKDIV : R/W ;bitpos:[19:0] ;default: 20'h2B6 ; */\r
-/*description: The register value is the integer part of the frequency divider's factor.*/\r
-#define UART_CLKDIV 0x000FFFFF\r
-#define UART_CLKDIV_M ((UART_CLKDIV_V)<<(UART_CLKDIV_S))\r
-#define UART_CLKDIV_V 0xFFFFF\r
-#define UART_CLKDIV_S 0\r
-\r
-#define UART_AUTOBAUD_REG(i) (REG_UART_BASE(i) + 0x18)\r
-/* UART_GLITCH_FILT : R/W ;bitpos:[15:8] ;default: 8'h10 ; */\r
-/*description: when input pulse width is lower then this value igore this pulse.this\r
- register is used in autobaud detect process.*/\r
-#define UART_GLITCH_FILT 0x000000FF\r
-#define UART_GLITCH_FILT_M ((UART_GLITCH_FILT_V)<<(UART_GLITCH_FILT_S))\r
-#define UART_GLITCH_FILT_V 0xFF\r
-#define UART_GLITCH_FILT_S 8\r
-/* UART_AUTOBAUD_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */\r
-/*description: This is the enable bit for detecting baudrate.*/\r
-#define UART_AUTOBAUD_EN (BIT(0))\r
-#define UART_AUTOBAUD_EN_M (BIT(0))\r
-#define UART_AUTOBAUD_EN_V 0x1\r
-#define UART_AUTOBAUD_EN_S 0\r
-\r
-#define UART_STATUS_REG(i) (REG_UART_BASE(i) + 0x1C)\r
-/* UART_TXD : RO ;bitpos:[31] ;default: 8'h0 ; */\r
-/*description: This register represent the level value of the internal uart rxd signal.*/\r
-#define UART_TXD (BIT(31))\r
-#define UART_TXD_M (BIT(31))\r
-#define UART_TXD_V 0x1\r
-#define UART_TXD_S 31\r
-/* UART_RTSN : RO ;bitpos:[30] ;default: 1'b0 ; */\r
-/*description: This register represent the level value of the internal uart cts signal.*/\r
-#define UART_RTSN (BIT(30))\r
-#define UART_RTSN_M (BIT(30))\r
-#define UART_RTSN_V 0x1\r
-#define UART_RTSN_S 30\r
-/* UART_DTRN : RO ;bitpos:[29] ;default: 1'b0 ; */\r
-/*description: The register represent the level value of the internal uart dsr signal.*/\r
-#define UART_DTRN (BIT(29))\r
-#define UART_DTRN_M (BIT(29))\r
-#define UART_DTRN_V 0x1\r
-#define UART_DTRN_S 29\r
-/* UART_ST_UTX_OUT : RO ;bitpos:[27:24] ;default: 4'b0 ; */\r
-/*description: This register stores the value of transmitter's finite state\r
- machine. 0:TX_IDLE 1:TX_STRT 2:TX_DAT0 3:TX_DAT1 4:TX_DAT2 5:TX_DAT3 6:TX_DAT4 7:TX_DAT5 8:TX_DAT6 9:TX_DAT7 10:TX_PRTY 11:TX_STP1 12:TX_STP2 13:TX_DL0 14:TX_DL1*/\r
-#define UART_ST_UTX_OUT 0x0000000F\r
-#define UART_ST_UTX_OUT_M ((UART_ST_UTX_OUT_V)<<(UART_ST_UTX_OUT_S))\r
-#define UART_ST_UTX_OUT_V 0xF\r
-#define UART_ST_UTX_OUT_S 24\r
-/* UART_TXFIFO_CNT : RO ;bitpos:[23:16] ;default: 8'b0 ; */\r
-/*description: (tx_mem_cnt txfifo_cnt) stores the byte num of valid datas in\r
- transmitter's fifo.tx_mem_cnt stores the 3 most significant bits txfifo_cnt stores the 8 least significant bits.*/\r
-#define UART_TXFIFO_CNT 0x000000FF\r
-#define UART_TXFIFO_CNT_M ((UART_TXFIFO_CNT_V)<<(UART_TXFIFO_CNT_S))\r
-#define UART_TXFIFO_CNT_V 0xFF\r
-#define UART_TXFIFO_CNT_S 16\r
-/* UART_RXD : RO ;bitpos:[15] ;default: 1'b0 ; */\r
-/*description: This register stores the level value of the internal uart rxd signal.*/\r
-#define UART_RXD (BIT(15))\r
-#define UART_RXD_M (BIT(15))\r
-#define UART_RXD_V 0x1\r
-#define UART_RXD_S 15\r
-/* UART_CTSN : RO ;bitpos:[14] ;default: 1'b0 ; */\r
-/*description: This register stores the level value of the internal uart cts signal.*/\r
-#define UART_CTSN (BIT(14))\r
-#define UART_CTSN_M (BIT(14))\r
-#define UART_CTSN_V 0x1\r
-#define UART_CTSN_S 14\r
-/* UART_DSRN : RO ;bitpos:[13] ;default: 1'b0 ; */\r
-/*description: This register stores the level value of the internal uart dsr signal.*/\r
-#define UART_DSRN (BIT(13))\r
-#define UART_DSRN_M (BIT(13))\r
-#define UART_DSRN_V 0x1\r
-#define UART_DSRN_S 13\r
-/* UART_ST_URX_OUT : RO ;bitpos:[11:8] ;default: 4'b0 ; */\r
-/*description: This register stores the value of receiver's finite state machine.\r
- 0:RX_IDLE 1:RX_STRT 2:RX_DAT0 3:RX_DAT1 4:RX_DAT2 5:RX_DAT3 6:RX_DAT4 7:RX_DAT5 8:RX_DAT6 9:RX_DAT7 10:RX_PRTY 11:RX_STP1 12:RX_STP2 13:RX_DL1*/\r
-#define UART_ST_URX_OUT 0x0000000F\r
-#define UART_ST_URX_OUT_M ((UART_ST_URX_OUT_V)<<(UART_ST_URX_OUT_S))\r
-#define UART_ST_URX_OUT_V 0xF\r
-#define UART_ST_URX_OUT_S 8\r
-/* UART_RXFIFO_CNT : RO ;bitpos:[7:0] ;default: 8'b0 ; */\r
-/*description: (rx_mem_cnt rxfifo_cnt) stores the byte num of valid datas in\r
- receiver's fifo. rx_mem_cnt register stores the 3 most significant bits rxfifo_cnt stores the 8 least significant bits.*/\r
-#define UART_RXFIFO_CNT 0x000000FF\r
-#define UART_RXFIFO_CNT_M ((UART_RXFIFO_CNT_V)<<(UART_RXFIFO_CNT_S))\r
-#define UART_RXFIFO_CNT_V 0xFF\r
-#define UART_RXFIFO_CNT_S 0\r
-\r
-#define UART_CONF0_REG(i) (REG_UART_BASE(i) + 0x20)\r
-/* UART_TICK_REF_ALWAYS_ON : R/W ;bitpos:[27] ;default: 1'b1 ; */\r
-/*description: This register is used to select the clock.1.apb clock 0:ref_tick*/\r
-#define UART_TICK_REF_ALWAYS_ON (BIT(27))\r
-#define UART_TICK_REF_ALWAYS_ON_M (BIT(27))\r
-#define UART_TICK_REF_ALWAYS_ON_V 0x1\r
-#define UART_TICK_REF_ALWAYS_ON_S 27\r
-/* UART_ERR_WR_MASK : R/W ;bitpos:[26] ;default: 1'b0 ; */\r
-/*description: 1.receiver stops storing data int fifo when data is wrong.\r
- 0.receiver stores the data even if the received data is wrong.*/\r
-#define UART_ERR_WR_MASK (BIT(26))\r
-#define UART_ERR_WR_MASK_M (BIT(26))\r
-#define UART_ERR_WR_MASK_V 0x1\r
-#define UART_ERR_WR_MASK_S 26\r
-/* UART_CLK_EN : R/W ;bitpos:[25] ;default: 1'h0 ; */\r
-/*description: 1.force clock on for registers.support clock only when write registers*/\r
-#define UART_CLK_EN (BIT(25))\r
-#define UART_CLK_EN_M (BIT(25))\r
-#define UART_CLK_EN_V 0x1\r
-#define UART_CLK_EN_S 25\r
-/* UART_DTR_INV : R/W ;bitpos:[24] ;default: 1'h0 ; */\r
-/*description: Set this bit to inverse the level value of uart dtr signal.*/\r
-#define UART_DTR_INV (BIT(24))\r
-#define UART_DTR_INV_M (BIT(24))\r
-#define UART_DTR_INV_V 0x1\r
-#define UART_DTR_INV_S 24\r
-/* UART_RTS_INV : R/W ;bitpos:[23] ;default: 1'h0 ; */\r
-/*description: Set this bit to inverse the level value of uart rts signal.*/\r
-#define UART_RTS_INV (BIT(23))\r
-#define UART_RTS_INV_M (BIT(23))\r
-#define UART_RTS_INV_V 0x1\r
-#define UART_RTS_INV_S 23\r
-/* UART_TXD_INV : R/W ;bitpos:[22] ;default: 1'h0 ; */\r
-/*description: Set this bit to inverse the level value of uart txd signal.*/\r
-#define UART_TXD_INV (BIT(22))\r
-#define UART_TXD_INV_M (BIT(22))\r
-#define UART_TXD_INV_V 0x1\r
-#define UART_TXD_INV_S 22\r
-/* UART_DSR_INV : R/W ;bitpos:[21] ;default: 1'h0 ; */\r
-/*description: Set this bit to inverse the level value of uart dsr signal.*/\r
-#define UART_DSR_INV (BIT(21))\r
-#define UART_DSR_INV_M (BIT(21))\r
-#define UART_DSR_INV_V 0x1\r
-#define UART_DSR_INV_S 21\r
-/* UART_CTS_INV : R/W ;bitpos:[20] ;default: 1'h0 ; */\r
-/*description: Set this bit to inverse the level value of uart cts signal.*/\r
-#define UART_CTS_INV (BIT(20))\r
-#define UART_CTS_INV_M (BIT(20))\r
-#define UART_CTS_INV_V 0x1\r
-#define UART_CTS_INV_S 20\r
-/* UART_RXD_INV : R/W ;bitpos:[19] ;default: 1'h0 ; */\r
-/*description: Set this bit to inverse the level value of uart rxd signal.*/\r
-#define UART_RXD_INV (BIT(19))\r
-#define UART_RXD_INV_M (BIT(19))\r
-#define UART_RXD_INV_V 0x1\r
-#define UART_RXD_INV_S 19\r
-/* UART_TXFIFO_RST : R/W ;bitpos:[18] ;default: 1'h0 ; */\r
-/*description: Set this bit to reset uart transmitter's fifo.*/\r
-#define UART_TXFIFO_RST (BIT(18))\r
-#define UART_TXFIFO_RST_M (BIT(18))\r
-#define UART_TXFIFO_RST_V 0x1\r
-#define UART_TXFIFO_RST_S 18\r
-/* UART_RXFIFO_RST : R/W ;bitpos:[17] ;default: 1'h0 ; */\r
-/*description: Set this bit to reset uart receiver's fifo.*/\r
-#define UART_RXFIFO_RST (BIT(17))\r
-#define UART_RXFIFO_RST_M (BIT(17))\r
-#define UART_RXFIFO_RST_V 0x1\r
-#define UART_RXFIFO_RST_S 17\r
-/* UART_IRDA_EN : R/W ;bitpos:[16] ;default: 1'h0 ; */\r
-/*description: Set this bit to enable irda protocol.*/\r
-#define UART_IRDA_EN (BIT(16))\r
-#define UART_IRDA_EN_M (BIT(16))\r
-#define UART_IRDA_EN_V 0x1\r
-#define UART_IRDA_EN_S 16\r
-/* UART_TX_FLOW_EN : R/W ;bitpos:[15] ;default: 1'b0 ; */\r
-/*description: Set this bit to enable transmitter's flow control function.*/\r
-#define UART_TX_FLOW_EN (BIT(15))\r
-#define UART_TX_FLOW_EN_M (BIT(15))\r
-#define UART_TX_FLOW_EN_V 0x1\r
-#define UART_TX_FLOW_EN_S 15\r
-/* UART_LOOPBACK : R/W ;bitpos:[14] ;default: 1'b0 ; */\r
-/*description: Set this bit to enable uart loopback test mode.*/\r
-#define UART_LOOPBACK (BIT(14))\r
-#define UART_LOOPBACK_M (BIT(14))\r
-#define UART_LOOPBACK_V 0x1\r
-#define UART_LOOPBACK_S 14\r
-/* UART_IRDA_RX_INV : R/W ;bitpos:[13] ;default: 1'b0 ; */\r
-/*description: Set this bit to inverse the level value of irda receiver's level.*/\r
-#define UART_IRDA_RX_INV (BIT(13))\r
-#define UART_IRDA_RX_INV_M (BIT(13))\r
-#define UART_IRDA_RX_INV_V 0x1\r
-#define UART_IRDA_RX_INV_S 13\r
-/* UART_IRDA_TX_INV : R/W ;bitpos:[12] ;default: 1'b0 ; */\r
-/*description: Set this bit to inverse the level value of irda transmitter's level.*/\r
-#define UART_IRDA_TX_INV (BIT(12))\r
-#define UART_IRDA_TX_INV_M (BIT(12))\r
-#define UART_IRDA_TX_INV_V 0x1\r
-#define UART_IRDA_TX_INV_S 12\r
-/* UART_IRDA_WCTL : R/W ;bitpos:[11] ;default: 1'b0 ; */\r
-/*description: 1.the irda transmitter's 11th bit is the same to the 10th bit.\r
- 0.set irda transmitter's 11th bit to 0.*/\r
-#define UART_IRDA_WCTL (BIT(11))\r
-#define UART_IRDA_WCTL_M (BIT(11))\r
-#define UART_IRDA_WCTL_V 0x1\r
-#define UART_IRDA_WCTL_S 11\r
-/* UART_IRDA_TX_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */\r
-/*description: This is the start enable bit for irda transmitter.*/\r
-#define UART_IRDA_TX_EN (BIT(10))\r
-#define UART_IRDA_TX_EN_M (BIT(10))\r
-#define UART_IRDA_TX_EN_V 0x1\r
-#define UART_IRDA_TX_EN_S 10\r
-/* UART_IRDA_DPLX : R/W ;bitpos:[9] ;default: 1'b0 ; */\r
-/*description: Set this bit to enable irda loopback mode.*/\r
-#define UART_IRDA_DPLX (BIT(9))\r
-#define UART_IRDA_DPLX_M (BIT(9))\r
-#define UART_IRDA_DPLX_V 0x1\r
-#define UART_IRDA_DPLX_S 9\r
-/* UART_TXD_BRK : R/W ;bitpos:[8] ;default: 1'b0 ; */\r
-/*description: Set this bit to enbale transmitter to send 0 when the process\r
- of sending data is done.*/\r
-#define UART_TXD_BRK (BIT(8))\r
-#define UART_TXD_BRK_M (BIT(8))\r
-#define UART_TXD_BRK_V 0x1\r
-#define UART_TXD_BRK_S 8\r
-/* UART_SW_DTR : R/W ;bitpos:[7] ;default: 1'b0 ; */\r
-/*description: This register is used to configure the software dtr signal which\r
- is used in software flow control..*/\r
-#define UART_SW_DTR (BIT(7))\r
-#define UART_SW_DTR_M (BIT(7))\r
-#define UART_SW_DTR_V 0x1\r
-#define UART_SW_DTR_S 7\r
-/* UART_SW_RTS : R/W ;bitpos:[6] ;default: 1'b0 ; */\r
-/*description: This register is used to configure the software rts signal which\r
- is used in software flow control.*/\r
-#define UART_SW_RTS (BIT(6))\r
-#define UART_SW_RTS_M (BIT(6))\r
-#define UART_SW_RTS_V 0x1\r
-#define UART_SW_RTS_S 6\r
-/* UART_STOP_BIT_NUM : R/W ;bitpos:[5:4] ;default: 2'd1 ; */\r
-/*description: This register is used to set the length of stop bit. 1:1bit 2:1.5bits 3:2bits*/\r
-#define UART_STOP_BIT_NUM 0x00000003\r
-#define UART_STOP_BIT_NUM_M ((UART_STOP_BIT_NUM_V)<<(UART_STOP_BIT_NUM_S))\r
-#define UART_STOP_BIT_NUM_V 0x3\r
-#define UART_STOP_BIT_NUM_S 4\r
-/* UART_BIT_NUM : R/W ;bitpos:[3:2] ;default: 2'd3 ; */\r
-/*description: This registe is used to set the length of data: 0:5bits 1:6bits 2:7bits 3:8bits*/\r
-#define UART_BIT_NUM 0x00000003\r
-#define UART_BIT_NUM_M ((UART_BIT_NUM_V)<<(UART_BIT_NUM_S))\r
-#define UART_BIT_NUM_V 0x3\r
-#define UART_BIT_NUM_S 2\r
-/* UART_PARITY_EN : R/W ;bitpos:[1] ;default: 1'b0 ; */\r
-/*description: Set this bit to enable uart parity check.*/\r
-#define UART_PARITY_EN (BIT(1))\r
-#define UART_PARITY_EN_M (BIT(1))\r
-#define UART_PARITY_EN_V 0x1\r
-#define UART_PARITY_EN_S 1\r
-/* UART_PARITY : R/W ;bitpos:[0] ;default: 1'b0 ; */\r
-/*description: This register is used to configure the parity check mode. 0:even 1:odd*/\r
-#define UART_PARITY (BIT(0))\r
-#define UART_PARITY_M (BIT(0))\r
-#define UART_PARITY_V 0x1\r
-#define UART_PARITY_S 0\r
-\r
-#define UART_CONF1_REG(i) (REG_UART_BASE(i) + 0x24)\r
-/* UART_RX_TOUT_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */\r
-/*description: This is the enble bit for uart receiver's timeout function.*/\r
-#define UART_RX_TOUT_EN (BIT(31))\r
-#define UART_RX_TOUT_EN_M (BIT(31))\r
-#define UART_RX_TOUT_EN_V 0x1\r
-#define UART_RX_TOUT_EN_S 31\r
-/* UART_RX_TOUT_THRHD : R/W ;bitpos:[30:24] ;default: 7'b0 ; */\r
-/*description: This register is used to configure the timeout value for uart\r
- receiver receiving a byte.*/\r
-#define UART_RX_TOUT_THRHD 0x0000007F\r
-#define UART_RX_TOUT_THRHD_M ((UART_RX_TOUT_THRHD_V)<<(UART_RX_TOUT_THRHD_S))\r
-#define UART_RX_TOUT_THRHD_V 0x7F\r
-#define UART_RX_TOUT_THRHD_S 24\r
-/* UART_RX_FLOW_EN : R/W ;bitpos:[23] ;default: 1'b0 ; */\r
-/*description: This is the flow enable bit for uart receiver. 1:choose software\r
- flow control with configuring sw_rts signal*/\r
-#define UART_RX_FLOW_EN (BIT(23))\r
-#define UART_RX_FLOW_EN_M (BIT(23))\r
-#define UART_RX_FLOW_EN_V 0x1\r
-#define UART_RX_FLOW_EN_S 23\r
-/* UART_RX_FLOW_THRHD : R/W ;bitpos:[22:16] ;default: 7'h0 ; */\r
-/*description: when receiver receives more data than its threshold value.\r
- receiver produce signal to tell the transmitter stop transferring data. the threshold value is (rx_flow_thrhd_h3 rx_flow_thrhd).*/\r
-#define UART_RX_FLOW_THRHD 0x0000007F\r
-#define UART_RX_FLOW_THRHD_M ((UART_RX_FLOW_THRHD_V)<<(UART_RX_FLOW_THRHD_S))\r
-#define UART_RX_FLOW_THRHD_V 0x7F\r
-#define UART_RX_FLOW_THRHD_S 16\r
-/* UART_TXFIFO_EMPTY_THRHD : R/W ;bitpos:[14:8] ;default: 7'h60 ; */\r
-/*description: when the data amount in transmitter fifo is less than its threshold\r
- value. it will produce txfifo_empty_int_raw interrupt. the threshold value is (tx_mem_empty_thrhd txfifo_empty_thrhd)*/\r
-#define UART_TXFIFO_EMPTY_THRHD 0x0000007F\r
-#define UART_TXFIFO_EMPTY_THRHD_M ((UART_TXFIFO_EMPTY_THRHD_V)<<(UART_TXFIFO_EMPTY_THRHD_S))\r
-#define UART_TXFIFO_EMPTY_THRHD_V 0x7F\r
-#define UART_TXFIFO_EMPTY_THRHD_S 8\r
-/* UART_RXFIFO_FULL_THRHD : R/W ;bitpos:[6:0] ;default: 7'h60 ; */\r
-/*description: When receiver receives more data than its threshold value.receiver\r
- will produce rxfifo_full_int_raw interrupt.the threshold value is (rx_flow_thrhd_h3 rxfifo_full_thrhd).*/\r
-#define UART_RXFIFO_FULL_THRHD 0x0000007F\r
-#define UART_RXFIFO_FULL_THRHD_M ((UART_RXFIFO_FULL_THRHD_V)<<(UART_RXFIFO_FULL_THRHD_S))\r
-#define UART_RXFIFO_FULL_THRHD_V 0x7F\r
-#define UART_RXFIFO_FULL_THRHD_S 0\r
-\r
-#define UART_LOWPULSE_REG(i) (REG_UART_BASE(i) + 0x28)\r
-/* UART_LOWPULSE_MIN_CNT : RO ;bitpos:[19:0] ;default: 20'hFFFFF ; */\r
-/*description: This register stores the value of the minimum duration time for\r
- the low level pulse. it is used in baudrate-detect process.*/\r
-#define UART_LOWPULSE_MIN_CNT 0x000FFFFF\r
-#define UART_LOWPULSE_MIN_CNT_M ((UART_LOWPULSE_MIN_CNT_V)<<(UART_LOWPULSE_MIN_CNT_S))\r
-#define UART_LOWPULSE_MIN_CNT_V 0xFFFFF\r
-#define UART_LOWPULSE_MIN_CNT_S 0\r
-\r
-#define UART_HIGHPULSE_REG(i) (REG_UART_BASE(i) + 0x2C)\r
-/* UART_HIGHPULSE_MIN_CNT : RO ;bitpos:[19:0] ;default: 20'hFFFFF ; */\r
-/*description: This register stores the value of the maxinum duration time\r
- for the high level pulse. it is used in baudrate-detect process.*/\r
-#define UART_HIGHPULSE_MIN_CNT 0x000FFFFF\r
-#define UART_HIGHPULSE_MIN_CNT_M ((UART_HIGHPULSE_MIN_CNT_V)<<(UART_HIGHPULSE_MIN_CNT_S))\r
-#define UART_HIGHPULSE_MIN_CNT_V 0xFFFFF\r
-#define UART_HIGHPULSE_MIN_CNT_S 0\r
-\r
-#define UART_RXD_CNT_REG(i) (REG_UART_BASE(i) + 0x30)\r
-/* UART_RXD_EDGE_CNT : RO ;bitpos:[9:0] ;default: 10'h0 ; */\r
-/*description: This register stores the count of rxd edge change. it is used\r
- in baudrate-detect process.*/\r
-#define UART_RXD_EDGE_CNT 0x000003FF\r
-#define UART_RXD_EDGE_CNT_M ((UART_RXD_EDGE_CNT_V)<<(UART_RXD_EDGE_CNT_S))\r
-#define UART_RXD_EDGE_CNT_V 0x3FF\r
-#define UART_RXD_EDGE_CNT_S 0\r
-\r
-#define UART_FLOW_CONF_REG(i) (REG_UART_BASE(i) + 0x34)\r
-/* UART_SEND_XOFF : R/W ;bitpos:[5] ;default: 1'b0 ; */\r
-/*description: Set this bit to send xoff char. it is cleared by hardware automatically.*/\r
-#define UART_SEND_XOFF (BIT(5))\r
-#define UART_SEND_XOFF_M (BIT(5))\r
-#define UART_SEND_XOFF_V 0x1\r
-#define UART_SEND_XOFF_S 5\r
-/* UART_SEND_XON : R/W ;bitpos:[4] ;default: 1'b0 ; */\r
-/*description: Set this bit to send xon char. it is cleared by hardware automatically.*/\r
-#define UART_SEND_XON (BIT(4))\r
-#define UART_SEND_XON_M (BIT(4))\r
-#define UART_SEND_XON_V 0x1\r
-#define UART_SEND_XON_S 4\r
-/* UART_FORCE_XOFF : R/W ;bitpos:[3] ;default: 1'b0 ; */\r
-/*description: Set this bit to set ctsn to enable the transmitter to go on sending data.*/\r
-#define UART_FORCE_XOFF (BIT(3))\r
-#define UART_FORCE_XOFF_M (BIT(3))\r
-#define UART_FORCE_XOFF_V 0x1\r
-#define UART_FORCE_XOFF_S 3\r
-/* UART_FORCE_XON : R/W ;bitpos:[2] ;default: 1'b0 ; */\r
-/*description: Set this bit to clear ctsn to stop the transmitter from sending data.*/\r
-#define UART_FORCE_XON (BIT(2))\r
-#define UART_FORCE_XON_M (BIT(2))\r
-#define UART_FORCE_XON_V 0x1\r
-#define UART_FORCE_XON_S 2\r
-/* UART_XONOFF_DEL : R/W ;bitpos:[1] ;default: 1'b0 ; */\r
-/*description: Set this bit to remove flow control char from the received data.*/\r
-#define UART_XONOFF_DEL (BIT(1))\r
-#define UART_XONOFF_DEL_M (BIT(1))\r
-#define UART_XONOFF_DEL_V 0x1\r
-#define UART_XONOFF_DEL_S 1\r
-/* UART_SW_FLOW_CON_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */\r
-/*description: Set this bit to enable software flow control. it is used with\r
- register sw_xon or sw_xoff .*/\r
-#define UART_SW_FLOW_CON_EN (BIT(0))\r
-#define UART_SW_FLOW_CON_EN_M (BIT(0))\r
-#define UART_SW_FLOW_CON_EN_V 0x1\r
-#define UART_SW_FLOW_CON_EN_S 0\r
-\r
-#define UART_SLEEP_CONF_REG(i) (REG_UART_BASE(i) + 0x38)\r
-/* UART_ACTIVE_THRESHOLD : R/W ;bitpos:[9:0] ;default: 10'hf0 ; */\r
-/*description: When the input rxd edge changes more than this register value.\r
- the uart is active from light sleeping mode.*/\r
-#define UART_ACTIVE_THRESHOLD 0x000003FF\r
-#define UART_ACTIVE_THRESHOLD_M ((UART_ACTIVE_THRESHOLD_V)<<(UART_ACTIVE_THRESHOLD_S))\r
-#define UART_ACTIVE_THRESHOLD_V 0x3FF\r
-#define UART_ACTIVE_THRESHOLD_S 0\r
-\r
-#define UART_SWFC_CONF_REG(i) (REG_UART_BASE(i) + 0x3C)\r
-/* UART_XOFF_CHAR : R/W ;bitpos:[31:24] ;default: 8'h13 ; */\r
-/*description: This register stores the xoff flow control char.*/\r
-#define UART_XOFF_CHAR 0x000000FF\r
-#define UART_XOFF_CHAR_M ((UART_XOFF_CHAR_V)<<(UART_XOFF_CHAR_S))\r
-#define UART_XOFF_CHAR_V 0xFF\r
-#define UART_XOFF_CHAR_S 24\r
-/* UART_XON_CHAR : R/W ;bitpos:[23:16] ;default: 8'h11 ; */\r
-/*description: This register stores the xon flow control char.*/\r
-#define UART_XON_CHAR 0x000000FF\r
-#define UART_XON_CHAR_M ((UART_XON_CHAR_V)<<(UART_XON_CHAR_S))\r
-#define UART_XON_CHAR_V 0xFF\r
-#define UART_XON_CHAR_S 16\r
-/* UART_XOFF_THRESHOLD : R/W ;bitpos:[15:8] ;default: 8'he0 ; */\r
-/*description: When the data amount in receiver's fifo is less than this register\r
- value. it will send a xon char with uart_sw_flow_con_en set to 1.*/\r
-#define UART_XOFF_THRESHOLD 0x000000FF\r
-#define UART_XOFF_THRESHOLD_M ((UART_XOFF_THRESHOLD_V)<<(UART_XOFF_THRESHOLD_S))\r
-#define UART_XOFF_THRESHOLD_V 0xFF\r
-#define UART_XOFF_THRESHOLD_S 8\r
-/* UART_XON_THRESHOLD : R/W ;bitpos:[7:0] ;default: 8'h0 ; */\r
-/*description: when the data amount in receiver's fifo is more than this register\r
- value. it will send a xoff char with uart_sw_flow_con_en set to 1.*/\r
-#define UART_XON_THRESHOLD 0x000000FF\r
-#define UART_XON_THRESHOLD_M ((UART_XON_THRESHOLD_V)<<(UART_XON_THRESHOLD_S))\r
-#define UART_XON_THRESHOLD_V 0xFF\r
-#define UART_XON_THRESHOLD_S 0\r
-\r
-#define UART_IDLE_CONF_REG(i) (REG_UART_BASE(i) + 0x40)\r
-/* UART_TX_BRK_NUM : R/W ;bitpos:[27:20] ;default: 8'ha ; */\r
-/*description: This register is used to configure the num of 0 send after the\r
- process of sending data is done. it is active when txd_brk is set to 1.*/\r
-#define UART_TX_BRK_NUM 0x000000FF\r
-#define UART_TX_BRK_NUM_M ((UART_TX_BRK_NUM_V)<<(UART_TX_BRK_NUM_S))\r
-#define UART_TX_BRK_NUM_V 0xFF\r
-#define UART_TX_BRK_NUM_S 20\r
-/* UART_TX_IDLE_NUM : R/W ;bitpos:[19:10] ;default: 10'h100 ; */\r
-/*description: This register is used to configure the duration time between transfers.*/\r
-#define UART_TX_IDLE_NUM 0x000003FF\r
-#define UART_TX_IDLE_NUM_M ((UART_TX_IDLE_NUM_V)<<(UART_TX_IDLE_NUM_S))\r
-#define UART_TX_IDLE_NUM_V 0x3FF\r
-#define UART_TX_IDLE_NUM_S 10\r
-/* UART_RX_IDLE_THRHD : R/W ;bitpos:[9:0] ;default: 10'h100 ; */\r
-/*description: when receiver takes more time than this register value to receive\r
- a byte data. it will produce frame end signal for uhci to stop receiving data.*/\r
-#define UART_RX_IDLE_THRHD 0x000003FF\r
-#define UART_RX_IDLE_THRHD_M ((UART_RX_IDLE_THRHD_V)<<(UART_RX_IDLE_THRHD_S))\r
-#define UART_RX_IDLE_THRHD_V 0x3FF\r
-#define UART_RX_IDLE_THRHD_S 0\r
-\r
-#define UART_RS485_CONF_REG(i) (REG_UART_BASE(i) + 0x44)\r
-/* UART_RS485_TX_DLY_NUM : R/W ;bitpos:[9:6] ;default: 4'b0 ; */\r
-/*description: This register is used to delay the transmitter's internal data signal.*/\r
-#define UART_RS485_TX_DLY_NUM 0x0000000F\r
-#define UART_RS485_TX_DLY_NUM_M ((UART_RS485_TX_DLY_NUM_V)<<(UART_RS485_TX_DLY_NUM_S))\r
-#define UART_RS485_TX_DLY_NUM_V 0xF\r
-#define UART_RS485_TX_DLY_NUM_S 6\r
-/* UART_RS485_RX_DLY_NUM : R/W ;bitpos:[5] ;default: 1'b0 ; */\r
-/*description: This register is used to delay the receiver's internal data signal.*/\r
-#define UART_RS485_RX_DLY_NUM (BIT(5))\r
-#define UART_RS485_RX_DLY_NUM_M (BIT(5))\r
-#define UART_RS485_RX_DLY_NUM_V 0x1\r
-#define UART_RS485_RX_DLY_NUM_S 5\r
-/* UART_RS485RXBY_TX_EN : R/W ;bitpos:[4] ;default: 1'b0 ; */\r
-/*description: 1: enable rs485's transmitter to send data when rs485's receiver\r
- is busy. 0:rs485's transmitter should not send data when its receiver is busy.*/\r
-#define UART_RS485RXBY_TX_EN (BIT(4))\r
-#define UART_RS485RXBY_TX_EN_M (BIT(4))\r
-#define UART_RS485RXBY_TX_EN_V 0x1\r
-#define UART_RS485RXBY_TX_EN_S 4\r
-/* UART_RS485TX_RX_EN : R/W ;bitpos:[3] ;default: 1'b0 ; */\r
-/*description: Set this bit to enable loopback transmitter's output data signal\r
- to receiver's input data signal.*/\r
-#define UART_RS485TX_RX_EN (BIT(3))\r
-#define UART_RS485TX_RX_EN_M (BIT(3))\r
-#define UART_RS485TX_RX_EN_V 0x1\r
-#define UART_RS485TX_RX_EN_S 3\r
-/* UART_DL1_EN : R/W ;bitpos:[2] ;default: 1'b0 ; */\r
-/*description: Set this bit to delay the stop bit by 1 bit.*/\r
-#define UART_DL1_EN (BIT(2))\r
-#define UART_DL1_EN_M (BIT(2))\r
-#define UART_DL1_EN_V 0x1\r
-#define UART_DL1_EN_S 2\r
-/* UART_DL0_EN : R/W ;bitpos:[1] ;default: 1'b0 ; */\r
-/*description: Set this bit to delay the stop bit by 1 bit.*/\r
-#define UART_DL0_EN (BIT(1))\r
-#define UART_DL0_EN_M (BIT(1))\r
-#define UART_DL0_EN_V 0x1\r
-#define UART_DL0_EN_S 1\r
-/* UART_RS485_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */\r
-/*description: Set this bit to choose rs485 mode.*/\r
-#define UART_RS485_EN (BIT(0))\r
-#define UART_RS485_EN_M (BIT(0))\r
-#define UART_RS485_EN_V 0x1\r
-#define UART_RS485_EN_S 0\r
-\r
-#define UART_AT_CMD_PRECNT_REG(i) (REG_UART_BASE(i) + 0x48)\r
-/* UART_PRE_IDLE_NUM : R/W ;bitpos:[23:0] ;default: 24'h186a00 ; */\r
-/*description: This register is used to configure the idle duration time before\r
- the first at_cmd is received by receiver. when the the duration is less than this register value it will not take the next data received as at_cmd char.*/\r
-#define UART_PRE_IDLE_NUM 0x00FFFFFF\r
-#define UART_PRE_IDLE_NUM_M ((UART_PRE_IDLE_NUM_V)<<(UART_PRE_IDLE_NUM_S))\r
-#define UART_PRE_IDLE_NUM_V 0xFFFFFF\r
-#define UART_PRE_IDLE_NUM_S 0\r
-\r
-#define UART_AT_CMD_POSTCNT_REG(i) (REG_UART_BASE(i) + 0x4c)\r
-/* UART_POST_IDLE_NUM : R/W ;bitpos:[23:0] ;default: 24'h186a00 ; */\r
-/*description: This register is used to configure the duration time between\r
- the last at_cmd and the next data. when the duration is less than this register value it will not take the previous data as at_cmd char.*/\r
-#define UART_POST_IDLE_NUM 0x00FFFFFF\r
-#define UART_POST_IDLE_NUM_M ((UART_POST_IDLE_NUM_V)<<(UART_POST_IDLE_NUM_S))\r
-#define UART_POST_IDLE_NUM_V 0xFFFFFF\r
-#define UART_POST_IDLE_NUM_S 0\r
-\r
-#define UART_AT_CMD_GAPTOUT_REG(i) (REG_UART_BASE(i) + 0x50)\r
-/* UART_RX_GAP_TOUT : R/W ;bitpos:[23:0] ;default: 24'h1e00 ; */\r
-/*description: This register is used to configure the duration time between\r
- the at_cmd chars. when the duration time is less than this register value it will not take the datas as continous at_cmd chars.*/\r
-#define UART_RX_GAP_TOUT 0x00FFFFFF\r
-#define UART_RX_GAP_TOUT_M ((UART_RX_GAP_TOUT_V)<<(UART_RX_GAP_TOUT_S))\r
-#define UART_RX_GAP_TOUT_V 0xFFFFFF\r
-#define UART_RX_GAP_TOUT_S 0\r
-\r
-#define UART_AT_CMD_CHAR_REG(i) (REG_UART_BASE(i) + 0x54)\r
-/* UART_CHAR_NUM : R/W ;bitpos:[15:8] ;default: 8'h3 ; */\r
-/*description: This register is used to configure the num of continous at_cmd\r
- chars received by receiver.*/\r
-#define UART_CHAR_NUM 0x000000FF\r
-#define UART_CHAR_NUM_M ((UART_CHAR_NUM_V)<<(UART_CHAR_NUM_S))\r
-#define UART_CHAR_NUM_V 0xFF\r
-#define UART_CHAR_NUM_S 8\r
-/* UART_AT_CMD_CHAR : R/W ;bitpos:[7:0] ;default: 8'h2b ; */\r
-/*description: This register is used to configure the content of at_cmd char.*/\r
-#define UART_AT_CMD_CHAR 0x000000FF\r
-#define UART_AT_CMD_CHAR_M ((UART_AT_CMD_CHAR_V)<<(UART_AT_CMD_CHAR_S))\r
-#define UART_AT_CMD_CHAR_V 0xFF\r
-#define UART_AT_CMD_CHAR_S 0\r
-\r
-#define UART_MEM_CONF_REG(i) (REG_UART_BASE(i) + 0x58)\r
-/* UART_TX_MEM_EMPTY_THRHD : R/W ;bitpos:[30:28] ;default: 3'h0 ; */\r
-/*description: refer to txfifo_empty_thrhd 's describtion.*/\r
-#define UART_TX_MEM_EMPTY_THRHD 0x00000007\r
-#define UART_TX_MEM_EMPTY_THRHD_M ((UART_TX_MEM_EMPTY_THRHD_V)<<(UART_TX_MEM_EMPTY_THRHD_S))\r
-#define UART_TX_MEM_EMPTY_THRHD_V 0x7\r
-#define UART_TX_MEM_EMPTY_THRHD_S 28\r
-/* UART_RX_MEM_FULL_THRHD : R/W ;bitpos:[27:25] ;default: 3'h0 ; */\r
-/*description: refer to the rxfifo_full_thrhd's describtion.*/\r
-#define UART_RX_MEM_FULL_THRHD 0x00000007\r
-#define UART_RX_MEM_FULL_THRHD_M ((UART_RX_MEM_FULL_THRHD_V)<<(UART_RX_MEM_FULL_THRHD_S))\r
-#define UART_RX_MEM_FULL_THRHD_V 0x7\r
-#define UART_RX_MEM_FULL_THRHD_S 25\r
-/* UART_XOFF_THRESHOLD_H2 : R/W ;bitpos:[24:23] ;default: 2'h0 ; */\r
-/*description: refer to the uart_xoff_threshold's describtion.*/\r
-#define UART_XOFF_THRESHOLD_H2 0x00000003\r
-#define UART_XOFF_THRESHOLD_H2_M ((UART_XOFF_THRESHOLD_H2_V)<<(UART_XOFF_THRESHOLD_H2_S))\r
-#define UART_XOFF_THRESHOLD_H2_V 0x3\r
-#define UART_XOFF_THRESHOLD_H2_S 23\r
-/* UART_XON_THRESHOLD_H2 : R/W ;bitpos:[22:21] ;default: 2'h0 ; */\r
-/*description: refer to the uart_xon_threshold's describtion.*/\r
-#define UART_XON_THRESHOLD_H2 0x00000003\r
-#define UART_XON_THRESHOLD_H2_M ((UART_XON_THRESHOLD_H2_V)<<(UART_XON_THRESHOLD_H2_S))\r
-#define UART_XON_THRESHOLD_H2_V 0x3\r
-#define UART_XON_THRESHOLD_H2_S 21\r
-/* UART_RX_TOUT_THRHD_H3 : R/W ;bitpos:[20:18] ;default: 3'h0 ; */\r
-/*description: refer to the rx_tout_thrhd's describtion.*/\r
-#define UART_RX_TOUT_THRHD_H3 0x00000007\r
-#define UART_RX_TOUT_THRHD_H3_M ((UART_RX_TOUT_THRHD_H3_V)<<(UART_RX_TOUT_THRHD_H3_S))\r
-#define UART_RX_TOUT_THRHD_H3_V 0x7\r
-#define UART_RX_TOUT_THRHD_H3_S 18\r
-/* UART_RX_FLOW_THRHD_H3 : R/W ;bitpos:[17:15] ;default: 3'h0 ; */\r
-/*description: refer to the rx_flow_thrhd's describtion.*/\r
-#define UART_RX_FLOW_THRHD_H3 0x00000007\r
-#define UART_RX_FLOW_THRHD_H3_M ((UART_RX_FLOW_THRHD_H3_V)<<(UART_RX_FLOW_THRHD_H3_S))\r
-#define UART_RX_FLOW_THRHD_H3_V 0x7\r
-#define UART_RX_FLOW_THRHD_H3_S 15\r
-/* UART_TX_SIZE : R/W ;bitpos:[10:7] ;default: 4'h1 ; */\r
-/*description: This register is used to configure the amount of mem allocated\r
- to transmitter's fifo.the default byte num is 128.*/\r
-#define UART_TX_SIZE 0x0000000F\r
-#define UART_TX_SIZE_M ((UART_TX_SIZE_V)<<(UART_TX_SIZE_S))\r
-#define UART_TX_SIZE_V 0xF\r
-#define UART_TX_SIZE_S 7\r
-/* UART_RX_SIZE : R/W ;bitpos:[6:3] ;default: 4'h1 ; */\r
-/*description: This register is used to configure the amount of mem allocated\r
- to receiver's fifo. the default byte num is 128.*/\r
-#define UART_RX_SIZE 0x0000000F\r
-#define UART_RX_SIZE_M ((UART_RX_SIZE_V)<<(UART_RX_SIZE_S))\r
-#define UART_RX_SIZE_V 0xF\r
-#define UART_RX_SIZE_S 3\r
-/* UART_MEM_PD : R/W ;bitpos:[0] ;default: 1'b0 ; */\r
-/*description: Set this bit to power down mem.when reg_mem_pd registers in\r
- the 3 uarts are all set to 1 mem will enter low power mode.*/\r
-#define UART_MEM_PD (BIT(0))\r
-#define UART_MEM_PD_M (BIT(0))\r
-#define UART_MEM_PD_V 0x1\r
-#define UART_MEM_PD_S 0\r
-\r
-#define UART_MEM_TX_STATUS_REG(i) (REG_UART_BASE(i) + 0x5c)\r
-/* UART_MEM_TX_STATUS : RO ;bitpos:[23:0] ;default: 24'h0 ; */\r
-/*description: */\r
-#define UART_MEM_TX_STATUS 0x00FFFFFF\r
-#define UART_MEM_TX_STATUS_M ((UART_MEM_TX_STATUS_V)<<(UART_MEM_TX_STATUS_S))\r
-#define UART_MEM_TX_STATUS_V 0xFFFFFF\r
-#define UART_MEM_TX_STATUS_S 0\r
-\r
-#define UART_MEM_RX_STATUS_REG(i) (REG_UART_BASE(i) + 0x60)\r
-/* UART_MEM_RX_STATUS : RO ;bitpos:[23:0] ;default: 24'h0 ; */\r
-/*description: */\r
-#define UART_MEM_RX_STATUS 0x00FFFFFF\r
-#define UART_MEM_RX_STATUS_M ((UART_MEM_RX_STATUS_V)<<(UART_MEM_RX_STATUS_S))\r
-#define UART_MEM_RX_STATUS_V 0xFFFFFF\r
-#define UART_MEM_RX_STATUS_S 0\r
-\r
-#define UART_MEM_CNT_STATUS_REG(i) (REG_UART_BASE(i) + 0x64)\r
-/* UART_TX_MEM_CNT : RO ;bitpos:[5:3] ;default: 3'b0 ; */\r
-/*description: refer to the txfifo_cnt's describtion.*/\r
-#define UART_TX_MEM_CNT 0x00000007\r
-#define UART_TX_MEM_CNT_M ((UART_TX_MEM_CNT_V)<<(UART_TX_MEM_CNT_S))\r
-#define UART_TX_MEM_CNT_V 0x7\r
-#define UART_TX_MEM_CNT_S 3\r
-/* UART_RX_MEM_CNT : RO ;bitpos:[2:0] ;default: 3'b0 ; */\r
-/*description: refer to the rxfifo_cnt's describtion.*/\r
-#define UART_RX_MEM_CNT 0x00000007\r
-#define UART_RX_MEM_CNT_M ((UART_RX_MEM_CNT_V)<<(UART_RX_MEM_CNT_S))\r
-#define UART_RX_MEM_CNT_V 0x7\r
-#define UART_RX_MEM_CNT_S 0\r
-\r
-#define UART_POSPULSE_REG(i) (REG_UART_BASE(i) + 0x68)\r
-/* UART_POSEDGE_MIN_CNT : RO ;bitpos:[19:0] ;default: 20'hFFFFF ; */\r
-/*description: This register stores the count of rxd posedge edge. it is used\r
- in boudrate-detect process.*/\r
-#define UART_POSEDGE_MIN_CNT 0x000FFFFF\r
-#define UART_POSEDGE_MIN_CNT_M ((UART_POSEDGE_MIN_CNT_V)<<(UART_POSEDGE_MIN_CNT_S))\r
-#define UART_POSEDGE_MIN_CNT_V 0xFFFFF\r
-#define UART_POSEDGE_MIN_CNT_S 0\r
-\r
-#define UART_NEGPULSE_REG(i) (REG_UART_BASE(i) + 0x6c)\r
-/* UART_NEGEDGE_MIN_CNT : RO ;bitpos:[19:0] ;default: 20'hFFFFF ; */\r
-/*description: This register stores the count of rxd negedge edge. it is used\r
- in boudrate-detect process.*/\r
-#define UART_NEGEDGE_MIN_CNT 0x000FFFFF\r
-#define UART_NEGEDGE_MIN_CNT_M ((UART_NEGEDGE_MIN_CNT_V)<<(UART_NEGEDGE_MIN_CNT_S))\r
-#define UART_NEGEDGE_MIN_CNT_V 0xFFFFF\r
-#define UART_NEGEDGE_MIN_CNT_S 0\r
-\r
-#define UART_DATE_REG(i) (REG_UART_BASE(i) + 0x78)\r
-/* UART_DATE : R/W ;bitpos:[31:0] ;default: 32'h15122500 ; */\r
-/*description: */\r
-#define UART_DATE 0xFFFFFFFF\r
-#define UART_DATE_M ((UART_DATE_V)<<(UART_DATE_S))\r
-#define UART_DATE_V 0xFFFFFFFF\r
-#define UART_DATE_S 0\r
-\r
-#define UART_ID_REG(i) (REG_UART_BASE(i) + 0x7C)\r
-/* UART_ID : R/W ;bitpos:[31:0] ;default: 32'h0500 ; */\r
-/*description: */\r
-#define UART_ID 0xFFFFFFFF\r
-#define UART_ID_M ((UART_ID_V)<<(UART_ID_S))\r
-#define UART_ID_V 0xFFFFFFFF\r
-#define UART_ID_S 0\r
-\r
-\r
-\r
-\r
-#endif /*__UART_REG_H__ */\r
-\r
-\r
+// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+#ifndef __UART_REG_H__
+#define __UART_REG_H__
+
+
+#include "soc.h"
+
+#define REG_UART_BASE( i ) (DR_REG_UART_BASE + (i) * 0x10000 + ( i > 1 ? 0xe000 : 0 ) )
+#define REG_UART_AHB_BASE(i) (0x60000000 + (i) * 0x10000 + ( i > 1 ? 0xe000 : 0 ) )
+#define UART_FIFO_AHB_REG(i) (REG_UART_AHB_BASE(i) + 0x0)
+#define UART_FIFO_REG(i) (REG_UART_BASE(i) + 0x0)
+
+/* UART_RXFIFO_RD_BYTE : RO ;bitpos:[7:0] ;default: 8'b0 ; */
+/*description: This register stores one byte data read by rx fifo.*/
+#define UART_RXFIFO_RD_BYTE 0x000000FF
+#define UART_RXFIFO_RD_BYTE_M ((UART_RXFIFO_RD_BYTE_V)<<(UART_RXFIFO_RD_BYTE_S))
+#define UART_RXFIFO_RD_BYTE_V 0xFF
+#define UART_RXFIFO_RD_BYTE_S 0
+
+#define UART_INT_RAW_REG(i) (REG_UART_BASE(i) + 0x4)
+/* UART_AT_CMD_CHAR_DET_INT_RAW : RO ;bitpos:[18] ;default: 1'b0 ; */
+/*description: This interrupt raw bit turns to high level when receiver detects
+ the configured at_cmd chars.*/
+#define UART_AT_CMD_CHAR_DET_INT_RAW (BIT(18))
+#define UART_AT_CMD_CHAR_DET_INT_RAW_M (BIT(18))
+#define UART_AT_CMD_CHAR_DET_INT_RAW_V 0x1
+#define UART_AT_CMD_CHAR_DET_INT_RAW_S 18
+/* UART_RS485_CLASH_INT_RAW : RO ;bitpos:[17] ;default: 1'b0 ; */
+/*description: This interrupt raw bit turns to high level when rs485 detects
+ the clash between transmitter and receiver.*/
+#define UART_RS485_CLASH_INT_RAW (BIT(17))
+#define UART_RS485_CLASH_INT_RAW_M (BIT(17))
+#define UART_RS485_CLASH_INT_RAW_V 0x1
+#define UART_RS485_CLASH_INT_RAW_S 17
+/* UART_RS485_FRM_ERR_INT_RAW : RO ;bitpos:[16] ;default: 1'b0 ; */
+/*description: This interrupt raw bit turns to high level when rs485 detects
+ the data frame error.*/
+#define UART_RS485_FRM_ERR_INT_RAW (BIT(16))
+#define UART_RS485_FRM_ERR_INT_RAW_M (BIT(16))
+#define UART_RS485_FRM_ERR_INT_RAW_V 0x1
+#define UART_RS485_FRM_ERR_INT_RAW_S 16
+/* UART_RS485_PARITY_ERR_INT_RAW : RO ;bitpos:[15] ;default: 1'b0 ; */
+/*description: This interrupt raw bit turns to high level when rs485 detects the parity error.*/
+#define UART_RS485_PARITY_ERR_INT_RAW (BIT(15))
+#define UART_RS485_PARITY_ERR_INT_RAW_M (BIT(15))
+#define UART_RS485_PARITY_ERR_INT_RAW_V 0x1
+#define UART_RS485_PARITY_ERR_INT_RAW_S 15
+/* UART_TX_DONE_INT_RAW : RO ;bitpos:[14] ;default: 1'b0 ; */
+/*description: This interrupt raw bit turns to high level when transmitter has
+ send all the data in fifo.*/
+#define UART_TX_DONE_INT_RAW (BIT(14))
+#define UART_TX_DONE_INT_RAW_M (BIT(14))
+#define UART_TX_DONE_INT_RAW_V 0x1
+#define UART_TX_DONE_INT_RAW_S 14
+/* UART_TX_BRK_IDLE_DONE_INT_RAW : RO ;bitpos:[13] ;default: 1'b0 ; */
+/*description: This interrupt raw bit turns to high level when transmitter has
+ kept the shortest duration after the last data has been send.*/
+#define UART_TX_BRK_IDLE_DONE_INT_RAW (BIT(13))
+#define UART_TX_BRK_IDLE_DONE_INT_RAW_M (BIT(13))
+#define UART_TX_BRK_IDLE_DONE_INT_RAW_V 0x1
+#define UART_TX_BRK_IDLE_DONE_INT_RAW_S 13
+/* UART_TX_BRK_DONE_INT_RAW : RO ;bitpos:[12] ;default: 1'b0 ; */
+/*description: This interrupt raw bit turns to high level when transmitter completes
+ sendding 0 after all the datas in transmitter's fifo are send.*/
+#define UART_TX_BRK_DONE_INT_RAW (BIT(12))
+#define UART_TX_BRK_DONE_INT_RAW_M (BIT(12))
+#define UART_TX_BRK_DONE_INT_RAW_V 0x1
+#define UART_TX_BRK_DONE_INT_RAW_S 12
+/* UART_GLITCH_DET_INT_RAW : RO ;bitpos:[11] ;default: 1'b0 ; */
+/*description: This interrupt raw bit turns to high level when receiver detects the start bit.*/
+#define UART_GLITCH_DET_INT_RAW (BIT(11))
+#define UART_GLITCH_DET_INT_RAW_M (BIT(11))
+#define UART_GLITCH_DET_INT_RAW_V 0x1
+#define UART_GLITCH_DET_INT_RAW_S 11
+/* UART_SW_XOFF_INT_RAW : RO ;bitpos:[10] ;default: 1'b0 ; */
+/*description: This interrupt raw bit turns to high level when receiver receives
+ xon char with uart_sw_flow_con_en is set to 1.*/
+#define UART_SW_XOFF_INT_RAW (BIT(10))
+#define UART_SW_XOFF_INT_RAW_M (BIT(10))
+#define UART_SW_XOFF_INT_RAW_V 0x1
+#define UART_SW_XOFF_INT_RAW_S 10
+/* UART_SW_XON_INT_RAW : RO ;bitpos:[9] ;default: 1'b0 ; */
+/*description: This interrupt raw bit turns to high level when receiver receives
+ xoff char with uart_sw_flow_con_en is set to 1.*/
+#define UART_SW_XON_INT_RAW (BIT(9))
+#define UART_SW_XON_INT_RAW_M (BIT(9))
+#define UART_SW_XON_INT_RAW_V 0x1
+#define UART_SW_XON_INT_RAW_S 9
+/* UART_RXFIFO_TOUT_INT_RAW : RO ;bitpos:[8] ;default: 1'b0 ; */
+/*description: This interrupt raw bit turns to high level when receiver takes
+ more time than rx_tout_thrhd to receive a byte.*/
+#define UART_RXFIFO_TOUT_INT_RAW (BIT(8))
+#define UART_RXFIFO_TOUT_INT_RAW_M (BIT(8))
+#define UART_RXFIFO_TOUT_INT_RAW_V 0x1
+#define UART_RXFIFO_TOUT_INT_RAW_S 8
+/* UART_BRK_DET_INT_RAW : RO ;bitpos:[7] ;default: 1'b0 ; */
+/*description: This interrupt raw bit turns to high level when receiver detects
+ the 0 after the stop bit.*/
+#define UART_BRK_DET_INT_RAW (BIT(7))
+#define UART_BRK_DET_INT_RAW_M (BIT(7))
+#define UART_BRK_DET_INT_RAW_V 0x1
+#define UART_BRK_DET_INT_RAW_S 7
+/* UART_CTS_CHG_INT_RAW : RO ;bitpos:[6] ;default: 1'b0 ; */
+/*description: This interrupt raw bit turns to high level when receiver detects
+ the edge change of ctsn signal.*/
+#define UART_CTS_CHG_INT_RAW (BIT(6))
+#define UART_CTS_CHG_INT_RAW_M (BIT(6))
+#define UART_CTS_CHG_INT_RAW_V 0x1
+#define UART_CTS_CHG_INT_RAW_S 6
+/* UART_DSR_CHG_INT_RAW : RO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: This interrupt raw bit turns to high level when receiver detects
+ the edge change of dsrn signal.*/
+#define UART_DSR_CHG_INT_RAW (BIT(5))
+#define UART_DSR_CHG_INT_RAW_M (BIT(5))
+#define UART_DSR_CHG_INT_RAW_V 0x1
+#define UART_DSR_CHG_INT_RAW_S 5
+/* UART_RXFIFO_OVF_INT_RAW : RO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: This interrupt raw bit turns to high level when receiver receives
+ more data than the fifo can store.*/
+#define UART_RXFIFO_OVF_INT_RAW (BIT(4))
+#define UART_RXFIFO_OVF_INT_RAW_M (BIT(4))
+#define UART_RXFIFO_OVF_INT_RAW_V 0x1
+#define UART_RXFIFO_OVF_INT_RAW_S 4
+/* UART_FRM_ERR_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: This interrupt raw bit turns to high level when receiver detects
+ data's frame error .*/
+#define UART_FRM_ERR_INT_RAW (BIT(3))
+#define UART_FRM_ERR_INT_RAW_M (BIT(3))
+#define UART_FRM_ERR_INT_RAW_V 0x1
+#define UART_FRM_ERR_INT_RAW_S 3
+/* UART_PARITY_ERR_INT_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */
+/*description: This interrupt raw bit turns to high level when receiver detects
+ the parity error of data.*/
+#define UART_PARITY_ERR_INT_RAW (BIT(2))
+#define UART_PARITY_ERR_INT_RAW_M (BIT(2))
+#define UART_PARITY_ERR_INT_RAW_V 0x1
+#define UART_PARITY_ERR_INT_RAW_S 2
+/* UART_TXFIFO_EMPTY_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: This interrupt raw bit turns to high level when the amount of
+ data in transmitter's fifo is less than ((tx_mem_cnttxfifo_cnt) .*/
+#define UART_TXFIFO_EMPTY_INT_RAW (BIT(1))
+#define UART_TXFIFO_EMPTY_INT_RAW_M (BIT(1))
+#define UART_TXFIFO_EMPTY_INT_RAW_V 0x1
+#define UART_TXFIFO_EMPTY_INT_RAW_S 1
+/* UART_RXFIFO_FULL_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: This interrupt raw bit turns to high level when receiver receives
+ more data than (rx_flow_thrhd_h3 rx_flow_thrhd).*/
+#define UART_RXFIFO_FULL_INT_RAW (BIT(0))
+#define UART_RXFIFO_FULL_INT_RAW_M (BIT(0))
+#define UART_RXFIFO_FULL_INT_RAW_V 0x1
+#define UART_RXFIFO_FULL_INT_RAW_S 0
+
+#define UART_INT_ST_REG(i) (REG_UART_BASE(i) + 0x8)
+/* UART_AT_CMD_CHAR_DET_INT_ST : RO ;bitpos:[18] ;default: 1'b0 ; */
+/*description: This is the status bit for at_cmd_det_int_raw when at_cmd_char_det_int_ena
+ is set to 1.*/
+#define UART_AT_CMD_CHAR_DET_INT_ST (BIT(18))
+#define UART_AT_CMD_CHAR_DET_INT_ST_M (BIT(18))
+#define UART_AT_CMD_CHAR_DET_INT_ST_V 0x1
+#define UART_AT_CMD_CHAR_DET_INT_ST_S 18
+/* UART_RS485_CLASH_INT_ST : RO ;bitpos:[17] ;default: 1'b0 ; */
+/*description: This is the status bit for rs485_clash_int_raw when rs485_clash_int_ena
+ is set to 1.*/
+#define UART_RS485_CLASH_INT_ST (BIT(17))
+#define UART_RS485_CLASH_INT_ST_M (BIT(17))
+#define UART_RS485_CLASH_INT_ST_V 0x1
+#define UART_RS485_CLASH_INT_ST_S 17
+/* UART_RS485_FRM_ERR_INT_ST : RO ;bitpos:[16] ;default: 1'b0 ; */
+/*description: This is the status bit for rs485_fm_err_int_raw when rs485_fm_err_int_ena
+ is set to 1.*/
+#define UART_RS485_FRM_ERR_INT_ST (BIT(16))
+#define UART_RS485_FRM_ERR_INT_ST_M (BIT(16))
+#define UART_RS485_FRM_ERR_INT_ST_V 0x1
+#define UART_RS485_FRM_ERR_INT_ST_S 16
+/* UART_RS485_PARITY_ERR_INT_ST : RO ;bitpos:[15] ;default: 1'b0 ; */
+/*description: This is the status bit for rs485_parity_err_int_raw when rs485_parity_int_ena
+ is set to 1.*/
+#define UART_RS485_PARITY_ERR_INT_ST (BIT(15))
+#define UART_RS485_PARITY_ERR_INT_ST_M (BIT(15))
+#define UART_RS485_PARITY_ERR_INT_ST_V 0x1
+#define UART_RS485_PARITY_ERR_INT_ST_S 15
+/* UART_TX_DONE_INT_ST : RO ;bitpos:[14] ;default: 1'b0 ; */
+/*description: This is the status bit for tx_done_int_raw when tx_done_int_ena is set to 1.*/
+#define UART_TX_DONE_INT_ST (BIT(14))
+#define UART_TX_DONE_INT_ST_M (BIT(14))
+#define UART_TX_DONE_INT_ST_V 0x1
+#define UART_TX_DONE_INT_ST_S 14
+/* UART_TX_BRK_IDLE_DONE_INT_ST : RO ;bitpos:[13] ;default: 1'b0 ; */
+/*description: This is the stauts bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena
+ is set to 1.*/
+#define UART_TX_BRK_IDLE_DONE_INT_ST (BIT(13))
+#define UART_TX_BRK_IDLE_DONE_INT_ST_M (BIT(13))
+#define UART_TX_BRK_IDLE_DONE_INT_ST_V 0x1
+#define UART_TX_BRK_IDLE_DONE_INT_ST_S 13
+/* UART_TX_BRK_DONE_INT_ST : RO ;bitpos:[12] ;default: 1'b0 ; */
+/*description: This is the status bit for tx_brk_done_int_raw when tx_brk_done_int_ena
+ is set to 1.*/
+#define UART_TX_BRK_DONE_INT_ST (BIT(12))
+#define UART_TX_BRK_DONE_INT_ST_M (BIT(12))
+#define UART_TX_BRK_DONE_INT_ST_V 0x1
+#define UART_TX_BRK_DONE_INT_ST_S 12
+/* UART_GLITCH_DET_INT_ST : RO ;bitpos:[11] ;default: 1'b0 ; */
+/*description: This is the status bit for glitch_det_int_raw when glitch_det_int_ena
+ is set to 1.*/
+#define UART_GLITCH_DET_INT_ST (BIT(11))
+#define UART_GLITCH_DET_INT_ST_M (BIT(11))
+#define UART_GLITCH_DET_INT_ST_V 0x1
+#define UART_GLITCH_DET_INT_ST_S 11
+/* UART_SW_XOFF_INT_ST : RO ;bitpos:[10] ;default: 1'b0 ; */
+/*description: This is the status bit for sw_xoff_int_raw when sw_xoff_int_ena is set to 1.*/
+#define UART_SW_XOFF_INT_ST (BIT(10))
+#define UART_SW_XOFF_INT_ST_M (BIT(10))
+#define UART_SW_XOFF_INT_ST_V 0x1
+#define UART_SW_XOFF_INT_ST_S 10
+/* UART_SW_XON_INT_ST : RO ;bitpos:[9] ;default: 1'b0 ; */
+/*description: This is the status bit for sw_xon_int_raw when sw_xon_int_ena is set to 1.*/
+#define UART_SW_XON_INT_ST (BIT(9))
+#define UART_SW_XON_INT_ST_M (BIT(9))
+#define UART_SW_XON_INT_ST_V 0x1
+#define UART_SW_XON_INT_ST_S 9
+/* UART_RXFIFO_TOUT_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */
+/*description: This is the status bit for rxfifo_tout_int_raw when rxfifo_tout_int_ena
+ is set to 1.*/
+#define UART_RXFIFO_TOUT_INT_ST (BIT(8))
+#define UART_RXFIFO_TOUT_INT_ST_M (BIT(8))
+#define UART_RXFIFO_TOUT_INT_ST_V 0x1
+#define UART_RXFIFO_TOUT_INT_ST_S 8
+/* UART_BRK_DET_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */
+/*description: This is the status bit for brk_det_int_raw when brk_det_int_ena is set to 1.*/
+#define UART_BRK_DET_INT_ST (BIT(7))
+#define UART_BRK_DET_INT_ST_M (BIT(7))
+#define UART_BRK_DET_INT_ST_V 0x1
+#define UART_BRK_DET_INT_ST_S 7
+/* UART_CTS_CHG_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */
+/*description: This is the status bit for cts_chg_int_raw when cts_chg_int_ena is set to 1.*/
+#define UART_CTS_CHG_INT_ST (BIT(6))
+#define UART_CTS_CHG_INT_ST_M (BIT(6))
+#define UART_CTS_CHG_INT_ST_V 0x1
+#define UART_CTS_CHG_INT_ST_S 6
+/* UART_DSR_CHG_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: This is the status bit for dsr_chg_int_raw when dsr_chg_int_ena is set to 1.*/
+#define UART_DSR_CHG_INT_ST (BIT(5))
+#define UART_DSR_CHG_INT_ST_M (BIT(5))
+#define UART_DSR_CHG_INT_ST_V 0x1
+#define UART_DSR_CHG_INT_ST_S 5
+/* UART_RXFIFO_OVF_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: This is the status bit for rxfifo_ovf_int_raw when rxfifo_ovf_int_ena
+ is set to 1.*/
+#define UART_RXFIFO_OVF_INT_ST (BIT(4))
+#define UART_RXFIFO_OVF_INT_ST_M (BIT(4))
+#define UART_RXFIFO_OVF_INT_ST_V 0x1
+#define UART_RXFIFO_OVF_INT_ST_S 4
+/* UART_FRM_ERR_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: This is the status bit for frm_err_int_raw when fm_err_int_ena is set to 1.*/
+#define UART_FRM_ERR_INT_ST (BIT(3))
+#define UART_FRM_ERR_INT_ST_M (BIT(3))
+#define UART_FRM_ERR_INT_ST_V 0x1
+#define UART_FRM_ERR_INT_ST_S 3
+/* UART_PARITY_ERR_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */
+/*description: This is the status bit for parity_err_int_raw when parity_err_int_ena
+ is set to 1.*/
+#define UART_PARITY_ERR_INT_ST (BIT(2))
+#define UART_PARITY_ERR_INT_ST_M (BIT(2))
+#define UART_PARITY_ERR_INT_ST_V 0x1
+#define UART_PARITY_ERR_INT_ST_S 2
+/* UART_TXFIFO_EMPTY_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: This is the status bit for txfifo_empty_int_raw when txfifo_empty_int_ena
+ is set to 1.*/
+#define UART_TXFIFO_EMPTY_INT_ST (BIT(1))
+#define UART_TXFIFO_EMPTY_INT_ST_M (BIT(1))
+#define UART_TXFIFO_EMPTY_INT_ST_V 0x1
+#define UART_TXFIFO_EMPTY_INT_ST_S 1
+/* UART_RXFIFO_FULL_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: This is the status bit for rxfifo_full_int_raw when rxfifo_full_int_ena
+ is set to 1.*/
+#define UART_RXFIFO_FULL_INT_ST (BIT(0))
+#define UART_RXFIFO_FULL_INT_ST_M (BIT(0))
+#define UART_RXFIFO_FULL_INT_ST_V 0x1
+#define UART_RXFIFO_FULL_INT_ST_S 0
+
+#define UART_INT_ENA_REG(i) (REG_UART_BASE(i) + 0xC)
+/* UART_AT_CMD_CHAR_DET_INT_ENA : R/W ;bitpos:[18] ;default: 1'b0 ; */
+/*description: This is the enable bit for at_cmd_char_det_int_st register.*/
+#define UART_AT_CMD_CHAR_DET_INT_ENA (BIT(18))
+#define UART_AT_CMD_CHAR_DET_INT_ENA_M (BIT(18))
+#define UART_AT_CMD_CHAR_DET_INT_ENA_V 0x1
+#define UART_AT_CMD_CHAR_DET_INT_ENA_S 18
+/* UART_RS485_CLASH_INT_ENA : R/W ;bitpos:[17] ;default: 1'b0 ; */
+/*description: This is the enable bit for rs485_clash_int_st register.*/
+#define UART_RS485_CLASH_INT_ENA (BIT(17))
+#define UART_RS485_CLASH_INT_ENA_M (BIT(17))
+#define UART_RS485_CLASH_INT_ENA_V 0x1
+#define UART_RS485_CLASH_INT_ENA_S 17
+/* UART_RS485_FRM_ERR_INT_ENA : R/W ;bitpos:[16] ;default: 1'b0 ; */
+/*description: This is the enable bit for rs485_parity_err_int_st register.*/
+#define UART_RS485_FRM_ERR_INT_ENA (BIT(16))
+#define UART_RS485_FRM_ERR_INT_ENA_M (BIT(16))
+#define UART_RS485_FRM_ERR_INT_ENA_V 0x1
+#define UART_RS485_FRM_ERR_INT_ENA_S 16
+/* UART_RS485_PARITY_ERR_INT_ENA : R/W ;bitpos:[15] ;default: 1'b0 ; */
+/*description: This is the enable bit for rs485_parity_err_int_st register.*/
+#define UART_RS485_PARITY_ERR_INT_ENA (BIT(15))
+#define UART_RS485_PARITY_ERR_INT_ENA_M (BIT(15))
+#define UART_RS485_PARITY_ERR_INT_ENA_V 0x1
+#define UART_RS485_PARITY_ERR_INT_ENA_S 15
+/* UART_TX_DONE_INT_ENA : R/W ;bitpos:[14] ;default: 1'b0 ; */
+/*description: This is the enable bit for tx_done_int_st register.*/
+#define UART_TX_DONE_INT_ENA (BIT(14))
+#define UART_TX_DONE_INT_ENA_M (BIT(14))
+#define UART_TX_DONE_INT_ENA_V 0x1
+#define UART_TX_DONE_INT_ENA_S 14
+/* UART_TX_BRK_IDLE_DONE_INT_ENA : R/W ;bitpos:[13] ;default: 1'b0 ; */
+/*description: This is the enable bit for tx_brk_idle_done_int_st register.*/
+#define UART_TX_BRK_IDLE_DONE_INT_ENA (BIT(13))
+#define UART_TX_BRK_IDLE_DONE_INT_ENA_M (BIT(13))
+#define UART_TX_BRK_IDLE_DONE_INT_ENA_V 0x1
+#define UART_TX_BRK_IDLE_DONE_INT_ENA_S 13
+/* UART_TX_BRK_DONE_INT_ENA : R/W ;bitpos:[12] ;default: 1'b0 ; */
+/*description: This is the enable bit for tx_brk_done_int_st register.*/
+#define UART_TX_BRK_DONE_INT_ENA (BIT(12))
+#define UART_TX_BRK_DONE_INT_ENA_M (BIT(12))
+#define UART_TX_BRK_DONE_INT_ENA_V 0x1
+#define UART_TX_BRK_DONE_INT_ENA_S 12
+/* UART_GLITCH_DET_INT_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */
+/*description: This is the enable bit for glitch_det_int_st register.*/
+#define UART_GLITCH_DET_INT_ENA (BIT(11))
+#define UART_GLITCH_DET_INT_ENA_M (BIT(11))
+#define UART_GLITCH_DET_INT_ENA_V 0x1
+#define UART_GLITCH_DET_INT_ENA_S 11
+/* UART_SW_XOFF_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */
+/*description: This is the enable bit for sw_xoff_int_st register.*/
+#define UART_SW_XOFF_INT_ENA (BIT(10))
+#define UART_SW_XOFF_INT_ENA_M (BIT(10))
+#define UART_SW_XOFF_INT_ENA_V 0x1
+#define UART_SW_XOFF_INT_ENA_S 10
+/* UART_SW_XON_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */
+/*description: This is the enable bit for sw_xon_int_st register.*/
+#define UART_SW_XON_INT_ENA (BIT(9))
+#define UART_SW_XON_INT_ENA_M (BIT(9))
+#define UART_SW_XON_INT_ENA_V 0x1
+#define UART_SW_XON_INT_ENA_S 9
+/* UART_RXFIFO_TOUT_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */
+/*description: This is the enable bit for rxfifo_tout_int_st register.*/
+#define UART_RXFIFO_TOUT_INT_ENA (BIT(8))
+#define UART_RXFIFO_TOUT_INT_ENA_M (BIT(8))
+#define UART_RXFIFO_TOUT_INT_ENA_V 0x1
+#define UART_RXFIFO_TOUT_INT_ENA_S 8
+/* UART_BRK_DET_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: This is the enable bit for brk_det_int_st register.*/
+#define UART_BRK_DET_INT_ENA (BIT(7))
+#define UART_BRK_DET_INT_ENA_M (BIT(7))
+#define UART_BRK_DET_INT_ENA_V 0x1
+#define UART_BRK_DET_INT_ENA_S 7
+/* UART_CTS_CHG_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: This is the enable bit for cts_chg_int_st register.*/
+#define UART_CTS_CHG_INT_ENA (BIT(6))
+#define UART_CTS_CHG_INT_ENA_M (BIT(6))
+#define UART_CTS_CHG_INT_ENA_V 0x1
+#define UART_CTS_CHG_INT_ENA_S 6
+/* UART_DSR_CHG_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: This is the enable bit for dsr_chg_int_st register.*/
+#define UART_DSR_CHG_INT_ENA (BIT(5))
+#define UART_DSR_CHG_INT_ENA_M (BIT(5))
+#define UART_DSR_CHG_INT_ENA_V 0x1
+#define UART_DSR_CHG_INT_ENA_S 5
+/* UART_RXFIFO_OVF_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: This is the enable bit for rxfifo_ovf_int_st register.*/
+#define UART_RXFIFO_OVF_INT_ENA (BIT(4))
+#define UART_RXFIFO_OVF_INT_ENA_M (BIT(4))
+#define UART_RXFIFO_OVF_INT_ENA_V 0x1
+#define UART_RXFIFO_OVF_INT_ENA_S 4
+/* UART_FRM_ERR_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: This is the enable bit for frm_err_int_st register.*/
+#define UART_FRM_ERR_INT_ENA (BIT(3))
+#define UART_FRM_ERR_INT_ENA_M (BIT(3))
+#define UART_FRM_ERR_INT_ENA_V 0x1
+#define UART_FRM_ERR_INT_ENA_S 3
+/* UART_PARITY_ERR_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: This is the enable bit for parity_err_int_st register.*/
+#define UART_PARITY_ERR_INT_ENA (BIT(2))
+#define UART_PARITY_ERR_INT_ENA_M (BIT(2))
+#define UART_PARITY_ERR_INT_ENA_V 0x1
+#define UART_PARITY_ERR_INT_ENA_S 2
+/* UART_TXFIFO_EMPTY_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: This is the enable bit for rxfifo_full_int_st register.*/
+#define UART_TXFIFO_EMPTY_INT_ENA (BIT(1))
+#define UART_TXFIFO_EMPTY_INT_ENA_M (BIT(1))
+#define UART_TXFIFO_EMPTY_INT_ENA_V 0x1
+#define UART_TXFIFO_EMPTY_INT_ENA_S 1
+/* UART_RXFIFO_FULL_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: This is the enable bit for rxfifo_full_int_st register.*/
+#define UART_RXFIFO_FULL_INT_ENA (BIT(0))
+#define UART_RXFIFO_FULL_INT_ENA_M (BIT(0))
+#define UART_RXFIFO_FULL_INT_ENA_V 0x1
+#define UART_RXFIFO_FULL_INT_ENA_S 0
+
+#define UART_INT_CLR_REG(i) (REG_UART_BASE(i) + 0x10)
+/* UART_AT_CMD_CHAR_DET_INT_CLR : WO ;bitpos:[18] ;default: 1'b0 ; */
+/*description: Set this bit to clear the at_cmd_char_det_int_raw interrupt.*/
+#define UART_AT_CMD_CHAR_DET_INT_CLR (BIT(18))
+#define UART_AT_CMD_CHAR_DET_INT_CLR_M (BIT(18))
+#define UART_AT_CMD_CHAR_DET_INT_CLR_V 0x1
+#define UART_AT_CMD_CHAR_DET_INT_CLR_S 18
+/* UART_RS485_CLASH_INT_CLR : WO ;bitpos:[17] ;default: 1'b0 ; */
+/*description: Set this bit to clear the rs485_clash_int_raw interrupt.*/
+#define UART_RS485_CLASH_INT_CLR (BIT(17))
+#define UART_RS485_CLASH_INT_CLR_M (BIT(17))
+#define UART_RS485_CLASH_INT_CLR_V 0x1
+#define UART_RS485_CLASH_INT_CLR_S 17
+/* UART_RS485_FRM_ERR_INT_CLR : WO ;bitpos:[16] ;default: 1'b0 ; */
+/*description: Set this bit to clear the rs485_frm_err_int_raw interrupt.*/
+#define UART_RS485_FRM_ERR_INT_CLR (BIT(16))
+#define UART_RS485_FRM_ERR_INT_CLR_M (BIT(16))
+#define UART_RS485_FRM_ERR_INT_CLR_V 0x1
+#define UART_RS485_FRM_ERR_INT_CLR_S 16
+/* UART_RS485_PARITY_ERR_INT_CLR : WO ;bitpos:[15] ;default: 1'b0 ; */
+/*description: Set this bit to clear the rs485_parity_err_int_raw interrupt.*/
+#define UART_RS485_PARITY_ERR_INT_CLR (BIT(15))
+#define UART_RS485_PARITY_ERR_INT_CLR_M (BIT(15))
+#define UART_RS485_PARITY_ERR_INT_CLR_V 0x1
+#define UART_RS485_PARITY_ERR_INT_CLR_S 15
+/* UART_TX_DONE_INT_CLR : WO ;bitpos:[14] ;default: 1'b0 ; */
+/*description: Set this bit to clear the tx_done_int_raw interrupt.*/
+#define UART_TX_DONE_INT_CLR (BIT(14))
+#define UART_TX_DONE_INT_CLR_M (BIT(14))
+#define UART_TX_DONE_INT_CLR_V 0x1
+#define UART_TX_DONE_INT_CLR_S 14
+/* UART_TX_BRK_IDLE_DONE_INT_CLR : WO ;bitpos:[13] ;default: 1'b0 ; */
+/*description: Set this bit to clear the tx_brk_idle_done_int_raw interrupt.*/
+#define UART_TX_BRK_IDLE_DONE_INT_CLR (BIT(13))
+#define UART_TX_BRK_IDLE_DONE_INT_CLR_M (BIT(13))
+#define UART_TX_BRK_IDLE_DONE_INT_CLR_V 0x1
+#define UART_TX_BRK_IDLE_DONE_INT_CLR_S 13
+/* UART_TX_BRK_DONE_INT_CLR : WO ;bitpos:[12] ;default: 1'b0 ; */
+/*description: Set this bit to clear the tx_brk_done_int_raw interrupt..*/
+#define UART_TX_BRK_DONE_INT_CLR (BIT(12))
+#define UART_TX_BRK_DONE_INT_CLR_M (BIT(12))
+#define UART_TX_BRK_DONE_INT_CLR_V 0x1
+#define UART_TX_BRK_DONE_INT_CLR_S 12
+/* UART_GLITCH_DET_INT_CLR : WO ;bitpos:[11] ;default: 1'b0 ; */
+/*description: Set this bit to clear the glitch_det_int_raw interrupt.*/
+#define UART_GLITCH_DET_INT_CLR (BIT(11))
+#define UART_GLITCH_DET_INT_CLR_M (BIT(11))
+#define UART_GLITCH_DET_INT_CLR_V 0x1
+#define UART_GLITCH_DET_INT_CLR_S 11
+/* UART_SW_XOFF_INT_CLR : WO ;bitpos:[10] ;default: 1'b0 ; */
+/*description: Set this bit to clear the sw_xon_int_raw interrupt.*/
+#define UART_SW_XOFF_INT_CLR (BIT(10))
+#define UART_SW_XOFF_INT_CLR_M (BIT(10))
+#define UART_SW_XOFF_INT_CLR_V 0x1
+#define UART_SW_XOFF_INT_CLR_S 10
+/* UART_SW_XON_INT_CLR : WO ;bitpos:[9] ;default: 1'b0 ; */
+/*description: Set this bit to clear the sw_xon_int_raw interrupt.*/
+#define UART_SW_XON_INT_CLR (BIT(9))
+#define UART_SW_XON_INT_CLR_M (BIT(9))
+#define UART_SW_XON_INT_CLR_V 0x1
+#define UART_SW_XON_INT_CLR_S 9
+/* UART_RXFIFO_TOUT_INT_CLR : WO ;bitpos:[8] ;default: 1'b0 ; */
+/*description: Set this bit to clear the rxfifo_tout_int_raw interrupt.*/
+#define UART_RXFIFO_TOUT_INT_CLR (BIT(8))
+#define UART_RXFIFO_TOUT_INT_CLR_M (BIT(8))
+#define UART_RXFIFO_TOUT_INT_CLR_V 0x1
+#define UART_RXFIFO_TOUT_INT_CLR_S 8
+/* UART_BRK_DET_INT_CLR : WO ;bitpos:[7] ;default: 1'b0 ; */
+/*description: Set this bit to clear the brk_det_int_raw interrupt.*/
+#define UART_BRK_DET_INT_CLR (BIT(7))
+#define UART_BRK_DET_INT_CLR_M (BIT(7))
+#define UART_BRK_DET_INT_CLR_V 0x1
+#define UART_BRK_DET_INT_CLR_S 7
+/* UART_CTS_CHG_INT_CLR : WO ;bitpos:[6] ;default: 1'b0 ; */
+/*description: Set this bit to clear the cts_chg_int_raw interrupt.*/
+#define UART_CTS_CHG_INT_CLR (BIT(6))
+#define UART_CTS_CHG_INT_CLR_M (BIT(6))
+#define UART_CTS_CHG_INT_CLR_V 0x1
+#define UART_CTS_CHG_INT_CLR_S 6
+/* UART_DSR_CHG_INT_CLR : WO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: Set this bit to clear the dsr_chg_int_raw interrupt.*/
+#define UART_DSR_CHG_INT_CLR (BIT(5))
+#define UART_DSR_CHG_INT_CLR_M (BIT(5))
+#define UART_DSR_CHG_INT_CLR_V 0x1
+#define UART_DSR_CHG_INT_CLR_S 5
+/* UART_RXFIFO_OVF_INT_CLR : WO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: Set this bit to clear rxfifo_ovf_int_raw interrupt.*/
+#define UART_RXFIFO_OVF_INT_CLR (BIT(4))
+#define UART_RXFIFO_OVF_INT_CLR_M (BIT(4))
+#define UART_RXFIFO_OVF_INT_CLR_V 0x1
+#define UART_RXFIFO_OVF_INT_CLR_S 4
+/* UART_FRM_ERR_INT_CLR : WO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: Set this bit to clear frm_err_int_raw interrupt.*/
+#define UART_FRM_ERR_INT_CLR (BIT(3))
+#define UART_FRM_ERR_INT_CLR_M (BIT(3))
+#define UART_FRM_ERR_INT_CLR_V 0x1
+#define UART_FRM_ERR_INT_CLR_S 3
+/* UART_PARITY_ERR_INT_CLR : WO ;bitpos:[2] ;default: 1'b0 ; */
+/*description: Set this bit to clear parity_err_int_raw interrupt.*/
+#define UART_PARITY_ERR_INT_CLR (BIT(2))
+#define UART_PARITY_ERR_INT_CLR_M (BIT(2))
+#define UART_PARITY_ERR_INT_CLR_V 0x1
+#define UART_PARITY_ERR_INT_CLR_S 2
+/* UART_TXFIFO_EMPTY_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: Set this bit to clear txfifo_empty_int_raw interrupt.*/
+#define UART_TXFIFO_EMPTY_INT_CLR (BIT(1))
+#define UART_TXFIFO_EMPTY_INT_CLR_M (BIT(1))
+#define UART_TXFIFO_EMPTY_INT_CLR_V 0x1
+#define UART_TXFIFO_EMPTY_INT_CLR_S 1
+/* UART_RXFIFO_FULL_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: Set this bit to clear the rxfifo_full_int_raw interrupt.*/
+#define UART_RXFIFO_FULL_INT_CLR (BIT(0))
+#define UART_RXFIFO_FULL_INT_CLR_M (BIT(0))
+#define UART_RXFIFO_FULL_INT_CLR_V 0x1
+#define UART_RXFIFO_FULL_INT_CLR_S 0
+
+#define UART_CLKDIV_REG(i) (REG_UART_BASE(i) + 0x14)
+/* UART_CLKDIV_FRAG : R/W ;bitpos:[23:20] ;default: 4'h0 ; */
+/*description: The register value is the decimal part of the frequency divider's factor.*/
+#define UART_CLKDIV_FRAG 0x0000000F
+#define UART_CLKDIV_FRAG_M ((UART_CLKDIV_FRAG_V)<<(UART_CLKDIV_FRAG_S))
+#define UART_CLKDIV_FRAG_V 0xF
+#define UART_CLKDIV_FRAG_S 20
+/* UART_CLKDIV : R/W ;bitpos:[19:0] ;default: 20'h2B6 ; */
+/*description: The register value is the integer part of the frequency divider's factor.*/
+#define UART_CLKDIV 0x000FFFFF
+#define UART_CLKDIV_M ((UART_CLKDIV_V)<<(UART_CLKDIV_S))
+#define UART_CLKDIV_V 0xFFFFF
+#define UART_CLKDIV_S 0
+
+#define UART_AUTOBAUD_REG(i) (REG_UART_BASE(i) + 0x18)
+/* UART_GLITCH_FILT : R/W ;bitpos:[15:8] ;default: 8'h10 ; */
+/*description: when input pulse width is lower then this value igore this pulse.this
+ register is used in autobaud detect process.*/
+#define UART_GLITCH_FILT 0x000000FF
+#define UART_GLITCH_FILT_M ((UART_GLITCH_FILT_V)<<(UART_GLITCH_FILT_S))
+#define UART_GLITCH_FILT_V 0xFF
+#define UART_GLITCH_FILT_S 8
+/* UART_AUTOBAUD_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: This is the enable bit for detecting baudrate.*/
+#define UART_AUTOBAUD_EN (BIT(0))
+#define UART_AUTOBAUD_EN_M (BIT(0))
+#define UART_AUTOBAUD_EN_V 0x1
+#define UART_AUTOBAUD_EN_S 0
+
+#define UART_STATUS_REG(i) (REG_UART_BASE(i) + 0x1C)
+/* UART_TXD : RO ;bitpos:[31] ;default: 8'h0 ; */
+/*description: This register represent the level value of the internal uart rxd signal.*/
+#define UART_TXD (BIT(31))
+#define UART_TXD_M (BIT(31))
+#define UART_TXD_V 0x1
+#define UART_TXD_S 31
+/* UART_RTSN : RO ;bitpos:[30] ;default: 1'b0 ; */
+/*description: This register represent the level value of the internal uart cts signal.*/
+#define UART_RTSN (BIT(30))
+#define UART_RTSN_M (BIT(30))
+#define UART_RTSN_V 0x1
+#define UART_RTSN_S 30
+/* UART_DTRN : RO ;bitpos:[29] ;default: 1'b0 ; */
+/*description: The register represent the level value of the internal uart dsr signal.*/
+#define UART_DTRN (BIT(29))
+#define UART_DTRN_M (BIT(29))
+#define UART_DTRN_V 0x1
+#define UART_DTRN_S 29
+/* UART_ST_UTX_OUT : RO ;bitpos:[27:24] ;default: 4'b0 ; */
+/*description: This register stores the value of transmitter's finite state
+ machine. 0:TX_IDLE 1:TX_STRT 2:TX_DAT0 3:TX_DAT1 4:TX_DAT2 5:TX_DAT3 6:TX_DAT4 7:TX_DAT5 8:TX_DAT6 9:TX_DAT7 10:TX_PRTY 11:TX_STP1 12:TX_STP2 13:TX_DL0 14:TX_DL1*/
+#define UART_ST_UTX_OUT 0x0000000F
+#define UART_ST_UTX_OUT_M ((UART_ST_UTX_OUT_V)<<(UART_ST_UTX_OUT_S))
+#define UART_ST_UTX_OUT_V 0xF
+#define UART_ST_UTX_OUT_S 24
+/* UART_TXFIFO_CNT : RO ;bitpos:[23:16] ;default: 8'b0 ; */
+/*description: (tx_mem_cnt txfifo_cnt) stores the byte num of valid datas in
+ transmitter's fifo.tx_mem_cnt stores the 3 most significant bits txfifo_cnt stores the 8 least significant bits.*/
+#define UART_TXFIFO_CNT 0x000000FF
+#define UART_TXFIFO_CNT_M ((UART_TXFIFO_CNT_V)<<(UART_TXFIFO_CNT_S))
+#define UART_TXFIFO_CNT_V 0xFF
+#define UART_TXFIFO_CNT_S 16
+/* UART_RXD : RO ;bitpos:[15] ;default: 1'b0 ; */
+/*description: This register stores the level value of the internal uart rxd signal.*/
+#define UART_RXD (BIT(15))
+#define UART_RXD_M (BIT(15))
+#define UART_RXD_V 0x1
+#define UART_RXD_S 15
+/* UART_CTSN : RO ;bitpos:[14] ;default: 1'b0 ; */
+/*description: This register stores the level value of the internal uart cts signal.*/
+#define UART_CTSN (BIT(14))
+#define UART_CTSN_M (BIT(14))
+#define UART_CTSN_V 0x1
+#define UART_CTSN_S 14
+/* UART_DSRN : RO ;bitpos:[13] ;default: 1'b0 ; */
+/*description: This register stores the level value of the internal uart dsr signal.*/
+#define UART_DSRN (BIT(13))
+#define UART_DSRN_M (BIT(13))
+#define UART_DSRN_V 0x1
+#define UART_DSRN_S 13
+/* UART_ST_URX_OUT : RO ;bitpos:[11:8] ;default: 4'b0 ; */
+/*description: This register stores the value of receiver's finite state machine.
+ 0:RX_IDLE 1:RX_STRT 2:RX_DAT0 3:RX_DAT1 4:RX_DAT2 5:RX_DAT3 6:RX_DAT4 7:RX_DAT5 8:RX_DAT6 9:RX_DAT7 10:RX_PRTY 11:RX_STP1 12:RX_STP2 13:RX_DL1*/
+#define UART_ST_URX_OUT 0x0000000F
+#define UART_ST_URX_OUT_M ((UART_ST_URX_OUT_V)<<(UART_ST_URX_OUT_S))
+#define UART_ST_URX_OUT_V 0xF
+#define UART_ST_URX_OUT_S 8
+/* UART_RXFIFO_CNT : RO ;bitpos:[7:0] ;default: 8'b0 ; */
+/*description: (rx_mem_cnt rxfifo_cnt) stores the byte num of valid datas in
+ receiver's fifo. rx_mem_cnt register stores the 3 most significant bits rxfifo_cnt stores the 8 least significant bits.*/
+#define UART_RXFIFO_CNT 0x000000FF
+#define UART_RXFIFO_CNT_M ((UART_RXFIFO_CNT_V)<<(UART_RXFIFO_CNT_S))
+#define UART_RXFIFO_CNT_V 0xFF
+#define UART_RXFIFO_CNT_S 0
+
+#define UART_CONF0_REG(i) (REG_UART_BASE(i) + 0x20)
+/* UART_TICK_REF_ALWAYS_ON : R/W ;bitpos:[27] ;default: 1'b1 ; */
+/*description: This register is used to select the clock.1.apb clock 0:ref_tick*/
+#define UART_TICK_REF_ALWAYS_ON (BIT(27))
+#define UART_TICK_REF_ALWAYS_ON_M (BIT(27))
+#define UART_TICK_REF_ALWAYS_ON_V 0x1
+#define UART_TICK_REF_ALWAYS_ON_S 27
+/* UART_ERR_WR_MASK : R/W ;bitpos:[26] ;default: 1'b0 ; */
+/*description: 1.receiver stops storing data int fifo when data is wrong.
+ 0.receiver stores the data even if the received data is wrong.*/
+#define UART_ERR_WR_MASK (BIT(26))
+#define UART_ERR_WR_MASK_M (BIT(26))
+#define UART_ERR_WR_MASK_V 0x1
+#define UART_ERR_WR_MASK_S 26
+/* UART_CLK_EN : R/W ;bitpos:[25] ;default: 1'h0 ; */
+/*description: 1.force clock on for registers.support clock only when write registers*/
+#define UART_CLK_EN (BIT(25))
+#define UART_CLK_EN_M (BIT(25))
+#define UART_CLK_EN_V 0x1
+#define UART_CLK_EN_S 25
+/* UART_DTR_INV : R/W ;bitpos:[24] ;default: 1'h0 ; */
+/*description: Set this bit to inverse the level value of uart dtr signal.*/
+#define UART_DTR_INV (BIT(24))
+#define UART_DTR_INV_M (BIT(24))
+#define UART_DTR_INV_V 0x1
+#define UART_DTR_INV_S 24
+/* UART_RTS_INV : R/W ;bitpos:[23] ;default: 1'h0 ; */
+/*description: Set this bit to inverse the level value of uart rts signal.*/
+#define UART_RTS_INV (BIT(23))
+#define UART_RTS_INV_M (BIT(23))
+#define UART_RTS_INV_V 0x1
+#define UART_RTS_INV_S 23
+/* UART_TXD_INV : R/W ;bitpos:[22] ;default: 1'h0 ; */
+/*description: Set this bit to inverse the level value of uart txd signal.*/
+#define UART_TXD_INV (BIT(22))
+#define UART_TXD_INV_M (BIT(22))
+#define UART_TXD_INV_V 0x1
+#define UART_TXD_INV_S 22
+/* UART_DSR_INV : R/W ;bitpos:[21] ;default: 1'h0 ; */
+/*description: Set this bit to inverse the level value of uart dsr signal.*/
+#define UART_DSR_INV (BIT(21))
+#define UART_DSR_INV_M (BIT(21))
+#define UART_DSR_INV_V 0x1
+#define UART_DSR_INV_S 21
+/* UART_CTS_INV : R/W ;bitpos:[20] ;default: 1'h0 ; */
+/*description: Set this bit to inverse the level value of uart cts signal.*/
+#define UART_CTS_INV (BIT(20))
+#define UART_CTS_INV_M (BIT(20))
+#define UART_CTS_INV_V 0x1
+#define UART_CTS_INV_S 20
+/* UART_RXD_INV : R/W ;bitpos:[19] ;default: 1'h0 ; */
+/*description: Set this bit to inverse the level value of uart rxd signal.*/
+#define UART_RXD_INV (BIT(19))
+#define UART_RXD_INV_M (BIT(19))
+#define UART_RXD_INV_V 0x1
+#define UART_RXD_INV_S 19
+/* UART_TXFIFO_RST : R/W ;bitpos:[18] ;default: 1'h0 ; */
+/*description: Set this bit to reset uart transmitter's fifo.*/
+#define UART_TXFIFO_RST (BIT(18))
+#define UART_TXFIFO_RST_M (BIT(18))
+#define UART_TXFIFO_RST_V 0x1
+#define UART_TXFIFO_RST_S 18
+/* UART_RXFIFO_RST : R/W ;bitpos:[17] ;default: 1'h0 ; */
+/*description: Set this bit to reset uart receiver's fifo.*/
+#define UART_RXFIFO_RST (BIT(17))
+#define UART_RXFIFO_RST_M (BIT(17))
+#define UART_RXFIFO_RST_V 0x1
+#define UART_RXFIFO_RST_S 17
+/* UART_IRDA_EN : R/W ;bitpos:[16] ;default: 1'h0 ; */
+/*description: Set this bit to enable irda protocol.*/
+#define UART_IRDA_EN (BIT(16))
+#define UART_IRDA_EN_M (BIT(16))
+#define UART_IRDA_EN_V 0x1
+#define UART_IRDA_EN_S 16
+/* UART_TX_FLOW_EN : R/W ;bitpos:[15] ;default: 1'b0 ; */
+/*description: Set this bit to enable transmitter's flow control function.*/
+#define UART_TX_FLOW_EN (BIT(15))
+#define UART_TX_FLOW_EN_M (BIT(15))
+#define UART_TX_FLOW_EN_V 0x1
+#define UART_TX_FLOW_EN_S 15
+/* UART_LOOPBACK : R/W ;bitpos:[14] ;default: 1'b0 ; */
+/*description: Set this bit to enable uart loopback test mode.*/
+#define UART_LOOPBACK (BIT(14))
+#define UART_LOOPBACK_M (BIT(14))
+#define UART_LOOPBACK_V 0x1
+#define UART_LOOPBACK_S 14
+/* UART_IRDA_RX_INV : R/W ;bitpos:[13] ;default: 1'b0 ; */
+/*description: Set this bit to inverse the level value of irda receiver's level.*/
+#define UART_IRDA_RX_INV (BIT(13))
+#define UART_IRDA_RX_INV_M (BIT(13))
+#define UART_IRDA_RX_INV_V 0x1
+#define UART_IRDA_RX_INV_S 13
+/* UART_IRDA_TX_INV : R/W ;bitpos:[12] ;default: 1'b0 ; */
+/*description: Set this bit to inverse the level value of irda transmitter's level.*/
+#define UART_IRDA_TX_INV (BIT(12))
+#define UART_IRDA_TX_INV_M (BIT(12))
+#define UART_IRDA_TX_INV_V 0x1
+#define UART_IRDA_TX_INV_S 12
+/* UART_IRDA_WCTL : R/W ;bitpos:[11] ;default: 1'b0 ; */
+/*description: 1.the irda transmitter's 11th bit is the same to the 10th bit.
+ 0.set irda transmitter's 11th bit to 0.*/
+#define UART_IRDA_WCTL (BIT(11))
+#define UART_IRDA_WCTL_M (BIT(11))
+#define UART_IRDA_WCTL_V 0x1
+#define UART_IRDA_WCTL_S 11
+/* UART_IRDA_TX_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */
+/*description: This is the start enable bit for irda transmitter.*/
+#define UART_IRDA_TX_EN (BIT(10))
+#define UART_IRDA_TX_EN_M (BIT(10))
+#define UART_IRDA_TX_EN_V 0x1
+#define UART_IRDA_TX_EN_S 10
+/* UART_IRDA_DPLX : R/W ;bitpos:[9] ;default: 1'b0 ; */
+/*description: Set this bit to enable irda loopback mode.*/
+#define UART_IRDA_DPLX (BIT(9))
+#define UART_IRDA_DPLX_M (BIT(9))
+#define UART_IRDA_DPLX_V 0x1
+#define UART_IRDA_DPLX_S 9
+/* UART_TXD_BRK : R/W ;bitpos:[8] ;default: 1'b0 ; */
+/*description: Set this bit to enbale transmitter to send 0 when the process
+ of sending data is done.*/
+#define UART_TXD_BRK (BIT(8))
+#define UART_TXD_BRK_M (BIT(8))
+#define UART_TXD_BRK_V 0x1
+#define UART_TXD_BRK_S 8
+/* UART_SW_DTR : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: This register is used to configure the software dtr signal which
+ is used in software flow control..*/
+#define UART_SW_DTR (BIT(7))
+#define UART_SW_DTR_M (BIT(7))
+#define UART_SW_DTR_V 0x1
+#define UART_SW_DTR_S 7
+/* UART_SW_RTS : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: This register is used to configure the software rts signal which
+ is used in software flow control.*/
+#define UART_SW_RTS (BIT(6))
+#define UART_SW_RTS_M (BIT(6))
+#define UART_SW_RTS_V 0x1
+#define UART_SW_RTS_S 6
+/* UART_STOP_BIT_NUM : R/W ;bitpos:[5:4] ;default: 2'd1 ; */
+/*description: This register is used to set the length of stop bit. 1:1bit 2:1.5bits 3:2bits*/
+#define UART_STOP_BIT_NUM 0x00000003
+#define UART_STOP_BIT_NUM_M ((UART_STOP_BIT_NUM_V)<<(UART_STOP_BIT_NUM_S))
+#define UART_STOP_BIT_NUM_V 0x3
+#define UART_STOP_BIT_NUM_S 4
+/* UART_BIT_NUM : R/W ;bitpos:[3:2] ;default: 2'd3 ; */
+/*description: This registe is used to set the length of data: 0:5bits 1:6bits 2:7bits 3:8bits*/
+#define UART_BIT_NUM 0x00000003
+#define UART_BIT_NUM_M ((UART_BIT_NUM_V)<<(UART_BIT_NUM_S))
+#define UART_BIT_NUM_V 0x3
+#define UART_BIT_NUM_S 2
+/* UART_PARITY_EN : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: Set this bit to enable uart parity check.*/
+#define UART_PARITY_EN (BIT(1))
+#define UART_PARITY_EN_M (BIT(1))
+#define UART_PARITY_EN_V 0x1
+#define UART_PARITY_EN_S 1
+/* UART_PARITY : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: This register is used to configure the parity check mode. 0:even 1:odd*/
+#define UART_PARITY (BIT(0))
+#define UART_PARITY_M (BIT(0))
+#define UART_PARITY_V 0x1
+#define UART_PARITY_S 0
+
+#define UART_CONF1_REG(i) (REG_UART_BASE(i) + 0x24)
+/* UART_RX_TOUT_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */
+/*description: This is the enble bit for uart receiver's timeout function.*/
+#define UART_RX_TOUT_EN (BIT(31))
+#define UART_RX_TOUT_EN_M (BIT(31))
+#define UART_RX_TOUT_EN_V 0x1
+#define UART_RX_TOUT_EN_S 31
+/* UART_RX_TOUT_THRHD : R/W ;bitpos:[30:24] ;default: 7'b0 ; */
+/*description: This register is used to configure the timeout value for uart
+ receiver receiving a byte.*/
+#define UART_RX_TOUT_THRHD 0x0000007F
+#define UART_RX_TOUT_THRHD_M ((UART_RX_TOUT_THRHD_V)<<(UART_RX_TOUT_THRHD_S))
+#define UART_RX_TOUT_THRHD_V 0x7F
+#define UART_RX_TOUT_THRHD_S 24
+/* UART_RX_FLOW_EN : R/W ;bitpos:[23] ;default: 1'b0 ; */
+/*description: This is the flow enable bit for uart receiver. 1:choose software
+ flow control with configuring sw_rts signal*/
+#define UART_RX_FLOW_EN (BIT(23))
+#define UART_RX_FLOW_EN_M (BIT(23))
+#define UART_RX_FLOW_EN_V 0x1
+#define UART_RX_FLOW_EN_S 23
+/* UART_RX_FLOW_THRHD : R/W ;bitpos:[22:16] ;default: 7'h0 ; */
+/*description: when receiver receives more data than its threshold value.
+ receiver produce signal to tell the transmitter stop transferring data. the threshold value is (rx_flow_thrhd_h3 rx_flow_thrhd).*/
+#define UART_RX_FLOW_THRHD 0x0000007F
+#define UART_RX_FLOW_THRHD_M ((UART_RX_FLOW_THRHD_V)<<(UART_RX_FLOW_THRHD_S))
+#define UART_RX_FLOW_THRHD_V 0x7F
+#define UART_RX_FLOW_THRHD_S 16
+/* UART_TXFIFO_EMPTY_THRHD : R/W ;bitpos:[14:8] ;default: 7'h60 ; */
+/*description: when the data amount in transmitter fifo is less than its threshold
+ value. it will produce txfifo_empty_int_raw interrupt. the threshold value is (tx_mem_empty_thrhd txfifo_empty_thrhd)*/
+#define UART_TXFIFO_EMPTY_THRHD 0x0000007F
+#define UART_TXFIFO_EMPTY_THRHD_M ((UART_TXFIFO_EMPTY_THRHD_V)<<(UART_TXFIFO_EMPTY_THRHD_S))
+#define UART_TXFIFO_EMPTY_THRHD_V 0x7F
+#define UART_TXFIFO_EMPTY_THRHD_S 8
+/* UART_RXFIFO_FULL_THRHD : R/W ;bitpos:[6:0] ;default: 7'h60 ; */
+/*description: When receiver receives more data than its threshold value.receiver
+ will produce rxfifo_full_int_raw interrupt.the threshold value is (rx_flow_thrhd_h3 rxfifo_full_thrhd).*/
+#define UART_RXFIFO_FULL_THRHD 0x0000007F
+#define UART_RXFIFO_FULL_THRHD_M ((UART_RXFIFO_FULL_THRHD_V)<<(UART_RXFIFO_FULL_THRHD_S))
+#define UART_RXFIFO_FULL_THRHD_V 0x7F
+#define UART_RXFIFO_FULL_THRHD_S 0
+
+#define UART_LOWPULSE_REG(i) (REG_UART_BASE(i) + 0x28)
+/* UART_LOWPULSE_MIN_CNT : RO ;bitpos:[19:0] ;default: 20'hFFFFF ; */
+/*description: This register stores the value of the minimum duration time for
+ the low level pulse. it is used in baudrate-detect process.*/
+#define UART_LOWPULSE_MIN_CNT 0x000FFFFF
+#define UART_LOWPULSE_MIN_CNT_M ((UART_LOWPULSE_MIN_CNT_V)<<(UART_LOWPULSE_MIN_CNT_S))
+#define UART_LOWPULSE_MIN_CNT_V 0xFFFFF
+#define UART_LOWPULSE_MIN_CNT_S 0
+
+#define UART_HIGHPULSE_REG(i) (REG_UART_BASE(i) + 0x2C)
+/* UART_HIGHPULSE_MIN_CNT : RO ;bitpos:[19:0] ;default: 20'hFFFFF ; */
+/*description: This register stores the value of the maxinum duration time
+ for the high level pulse. it is used in baudrate-detect process.*/
+#define UART_HIGHPULSE_MIN_CNT 0x000FFFFF
+#define UART_HIGHPULSE_MIN_CNT_M ((UART_HIGHPULSE_MIN_CNT_V)<<(UART_HIGHPULSE_MIN_CNT_S))
+#define UART_HIGHPULSE_MIN_CNT_V 0xFFFFF
+#define UART_HIGHPULSE_MIN_CNT_S 0
+
+#define UART_RXD_CNT_REG(i) (REG_UART_BASE(i) + 0x30)
+/* UART_RXD_EDGE_CNT : RO ;bitpos:[9:0] ;default: 10'h0 ; */
+/*description: This register stores the count of rxd edge change. it is used
+ in baudrate-detect process.*/
+#define UART_RXD_EDGE_CNT 0x000003FF
+#define UART_RXD_EDGE_CNT_M ((UART_RXD_EDGE_CNT_V)<<(UART_RXD_EDGE_CNT_S))
+#define UART_RXD_EDGE_CNT_V 0x3FF
+#define UART_RXD_EDGE_CNT_S 0
+
+#define UART_FLOW_CONF_REG(i) (REG_UART_BASE(i) + 0x34)
+/* UART_SEND_XOFF : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: Set this bit to send xoff char. it is cleared by hardware automatically.*/
+#define UART_SEND_XOFF (BIT(5))
+#define UART_SEND_XOFF_M (BIT(5))
+#define UART_SEND_XOFF_V 0x1
+#define UART_SEND_XOFF_S 5
+/* UART_SEND_XON : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: Set this bit to send xon char. it is cleared by hardware automatically.*/
+#define UART_SEND_XON (BIT(4))
+#define UART_SEND_XON_M (BIT(4))
+#define UART_SEND_XON_V 0x1
+#define UART_SEND_XON_S 4
+/* UART_FORCE_XOFF : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: Set this bit to set ctsn to enable the transmitter to go on sending data.*/
+#define UART_FORCE_XOFF (BIT(3))
+#define UART_FORCE_XOFF_M (BIT(3))
+#define UART_FORCE_XOFF_V 0x1
+#define UART_FORCE_XOFF_S 3
+/* UART_FORCE_XON : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: Set this bit to clear ctsn to stop the transmitter from sending data.*/
+#define UART_FORCE_XON (BIT(2))
+#define UART_FORCE_XON_M (BIT(2))
+#define UART_FORCE_XON_V 0x1
+#define UART_FORCE_XON_S 2
+/* UART_XONOFF_DEL : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: Set this bit to remove flow control char from the received data.*/
+#define UART_XONOFF_DEL (BIT(1))
+#define UART_XONOFF_DEL_M (BIT(1))
+#define UART_XONOFF_DEL_V 0x1
+#define UART_XONOFF_DEL_S 1
+/* UART_SW_FLOW_CON_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: Set this bit to enable software flow control. it is used with
+ register sw_xon or sw_xoff .*/
+#define UART_SW_FLOW_CON_EN (BIT(0))
+#define UART_SW_FLOW_CON_EN_M (BIT(0))
+#define UART_SW_FLOW_CON_EN_V 0x1
+#define UART_SW_FLOW_CON_EN_S 0
+
+#define UART_SLEEP_CONF_REG(i) (REG_UART_BASE(i) + 0x38)
+/* UART_ACTIVE_THRESHOLD : R/W ;bitpos:[9:0] ;default: 10'hf0 ; */
+/*description: When the input rxd edge changes more than this register value.
+ the uart is active from light sleeping mode.*/
+#define UART_ACTIVE_THRESHOLD 0x000003FF
+#define UART_ACTIVE_THRESHOLD_M ((UART_ACTIVE_THRESHOLD_V)<<(UART_ACTIVE_THRESHOLD_S))
+#define UART_ACTIVE_THRESHOLD_V 0x3FF
+#define UART_ACTIVE_THRESHOLD_S 0
+
+#define UART_SWFC_CONF_REG(i) (REG_UART_BASE(i) + 0x3C)
+/* UART_XOFF_CHAR : R/W ;bitpos:[31:24] ;default: 8'h13 ; */
+/*description: This register stores the xoff flow control char.*/
+#define UART_XOFF_CHAR 0x000000FF
+#define UART_XOFF_CHAR_M ((UART_XOFF_CHAR_V)<<(UART_XOFF_CHAR_S))
+#define UART_XOFF_CHAR_V 0xFF
+#define UART_XOFF_CHAR_S 24
+/* UART_XON_CHAR : R/W ;bitpos:[23:16] ;default: 8'h11 ; */
+/*description: This register stores the xon flow control char.*/
+#define UART_XON_CHAR 0x000000FF
+#define UART_XON_CHAR_M ((UART_XON_CHAR_V)<<(UART_XON_CHAR_S))
+#define UART_XON_CHAR_V 0xFF
+#define UART_XON_CHAR_S 16
+/* UART_XOFF_THRESHOLD : R/W ;bitpos:[15:8] ;default: 8'he0 ; */
+/*description: When the data amount in receiver's fifo is less than this register
+ value. it will send a xon char with uart_sw_flow_con_en set to 1.*/
+#define UART_XOFF_THRESHOLD 0x000000FF
+#define UART_XOFF_THRESHOLD_M ((UART_XOFF_THRESHOLD_V)<<(UART_XOFF_THRESHOLD_S))
+#define UART_XOFF_THRESHOLD_V 0xFF
+#define UART_XOFF_THRESHOLD_S 8
+/* UART_XON_THRESHOLD : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
+/*description: when the data amount in receiver's fifo is more than this register
+ value. it will send a xoff char with uart_sw_flow_con_en set to 1.*/
+#define UART_XON_THRESHOLD 0x000000FF
+#define UART_XON_THRESHOLD_M ((UART_XON_THRESHOLD_V)<<(UART_XON_THRESHOLD_S))
+#define UART_XON_THRESHOLD_V 0xFF
+#define UART_XON_THRESHOLD_S 0
+
+#define UART_IDLE_CONF_REG(i) (REG_UART_BASE(i) + 0x40)
+/* UART_TX_BRK_NUM : R/W ;bitpos:[27:20] ;default: 8'ha ; */
+/*description: This register is used to configure the num of 0 send after the
+ process of sending data is done. it is active when txd_brk is set to 1.*/
+#define UART_TX_BRK_NUM 0x000000FF
+#define UART_TX_BRK_NUM_M ((UART_TX_BRK_NUM_V)<<(UART_TX_BRK_NUM_S))
+#define UART_TX_BRK_NUM_V 0xFF
+#define UART_TX_BRK_NUM_S 20
+/* UART_TX_IDLE_NUM : R/W ;bitpos:[19:10] ;default: 10'h100 ; */
+/*description: This register is used to configure the duration time between transfers.*/
+#define UART_TX_IDLE_NUM 0x000003FF
+#define UART_TX_IDLE_NUM_M ((UART_TX_IDLE_NUM_V)<<(UART_TX_IDLE_NUM_S))
+#define UART_TX_IDLE_NUM_V 0x3FF
+#define UART_TX_IDLE_NUM_S 10
+/* UART_RX_IDLE_THRHD : R/W ;bitpos:[9:0] ;default: 10'h100 ; */
+/*description: when receiver takes more time than this register value to receive
+ a byte data. it will produce frame end signal for uhci to stop receiving data.*/
+#define UART_RX_IDLE_THRHD 0x000003FF
+#define UART_RX_IDLE_THRHD_M ((UART_RX_IDLE_THRHD_V)<<(UART_RX_IDLE_THRHD_S))
+#define UART_RX_IDLE_THRHD_V 0x3FF
+#define UART_RX_IDLE_THRHD_S 0
+
+#define UART_RS485_CONF_REG(i) (REG_UART_BASE(i) + 0x44)
+/* UART_RS485_TX_DLY_NUM : R/W ;bitpos:[9:6] ;default: 4'b0 ; */
+/*description: This register is used to delay the transmitter's internal data signal.*/
+#define UART_RS485_TX_DLY_NUM 0x0000000F
+#define UART_RS485_TX_DLY_NUM_M ((UART_RS485_TX_DLY_NUM_V)<<(UART_RS485_TX_DLY_NUM_S))
+#define UART_RS485_TX_DLY_NUM_V 0xF
+#define UART_RS485_TX_DLY_NUM_S 6
+/* UART_RS485_RX_DLY_NUM : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: This register is used to delay the receiver's internal data signal.*/
+#define UART_RS485_RX_DLY_NUM (BIT(5))
+#define UART_RS485_RX_DLY_NUM_M (BIT(5))
+#define UART_RS485_RX_DLY_NUM_V 0x1
+#define UART_RS485_RX_DLY_NUM_S 5
+/* UART_RS485RXBY_TX_EN : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: 1: enable rs485's transmitter to send data when rs485's receiver
+ is busy. 0:rs485's transmitter should not send data when its receiver is busy.*/
+#define UART_RS485RXBY_TX_EN (BIT(4))
+#define UART_RS485RXBY_TX_EN_M (BIT(4))
+#define UART_RS485RXBY_TX_EN_V 0x1
+#define UART_RS485RXBY_TX_EN_S 4
+/* UART_RS485TX_RX_EN : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: Set this bit to enable loopback transmitter's output data signal
+ to receiver's input data signal.*/
+#define UART_RS485TX_RX_EN (BIT(3))
+#define UART_RS485TX_RX_EN_M (BIT(3))
+#define UART_RS485TX_RX_EN_V 0x1
+#define UART_RS485TX_RX_EN_S 3
+/* UART_DL1_EN : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: Set this bit to delay the stop bit by 1 bit.*/
+#define UART_DL1_EN (BIT(2))
+#define UART_DL1_EN_M (BIT(2))
+#define UART_DL1_EN_V 0x1
+#define UART_DL1_EN_S 2
+/* UART_DL0_EN : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: Set this bit to delay the stop bit by 1 bit.*/
+#define UART_DL0_EN (BIT(1))
+#define UART_DL0_EN_M (BIT(1))
+#define UART_DL0_EN_V 0x1
+#define UART_DL0_EN_S 1
+/* UART_RS485_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: Set this bit to choose rs485 mode.*/
+#define UART_RS485_EN (BIT(0))
+#define UART_RS485_EN_M (BIT(0))
+#define UART_RS485_EN_V 0x1
+#define UART_RS485_EN_S 0
+
+#define UART_AT_CMD_PRECNT_REG(i) (REG_UART_BASE(i) + 0x48)
+/* UART_PRE_IDLE_NUM : R/W ;bitpos:[23:0] ;default: 24'h186a00 ; */
+/*description: This register is used to configure the idle duration time before
+ the first at_cmd is received by receiver. when the the duration is less than this register value it will not take the next data received as at_cmd char.*/
+#define UART_PRE_IDLE_NUM 0x00FFFFFF
+#define UART_PRE_IDLE_NUM_M ((UART_PRE_IDLE_NUM_V)<<(UART_PRE_IDLE_NUM_S))
+#define UART_PRE_IDLE_NUM_V 0xFFFFFF
+#define UART_PRE_IDLE_NUM_S 0
+
+#define UART_AT_CMD_POSTCNT_REG(i) (REG_UART_BASE(i) + 0x4c)
+/* UART_POST_IDLE_NUM : R/W ;bitpos:[23:0] ;default: 24'h186a00 ; */
+/*description: This register is used to configure the duration time between
+ the last at_cmd and the next data. when the duration is less than this register value it will not take the previous data as at_cmd char.*/
+#define UART_POST_IDLE_NUM 0x00FFFFFF
+#define UART_POST_IDLE_NUM_M ((UART_POST_IDLE_NUM_V)<<(UART_POST_IDLE_NUM_S))
+#define UART_POST_IDLE_NUM_V 0xFFFFFF
+#define UART_POST_IDLE_NUM_S 0
+
+#define UART_AT_CMD_GAPTOUT_REG(i) (REG_UART_BASE(i) + 0x50)
+/* UART_RX_GAP_TOUT : R/W ;bitpos:[23:0] ;default: 24'h1e00 ; */
+/*description: This register is used to configure the duration time between
+ the at_cmd chars. when the duration time is less than this register value it will not take the datas as continous at_cmd chars.*/
+#define UART_RX_GAP_TOUT 0x00FFFFFF
+#define UART_RX_GAP_TOUT_M ((UART_RX_GAP_TOUT_V)<<(UART_RX_GAP_TOUT_S))
+#define UART_RX_GAP_TOUT_V 0xFFFFFF
+#define UART_RX_GAP_TOUT_S 0
+
+#define UART_AT_CMD_CHAR_REG(i) (REG_UART_BASE(i) + 0x54)
+/* UART_CHAR_NUM : R/W ;bitpos:[15:8] ;default: 8'h3 ; */
+/*description: This register is used to configure the num of continous at_cmd
+ chars received by receiver.*/
+#define UART_CHAR_NUM 0x000000FF
+#define UART_CHAR_NUM_M ((UART_CHAR_NUM_V)<<(UART_CHAR_NUM_S))
+#define UART_CHAR_NUM_V 0xFF
+#define UART_CHAR_NUM_S 8
+/* UART_AT_CMD_CHAR : R/W ;bitpos:[7:0] ;default: 8'h2b ; */
+/*description: This register is used to configure the content of at_cmd char.*/
+#define UART_AT_CMD_CHAR 0x000000FF
+#define UART_AT_CMD_CHAR_M ((UART_AT_CMD_CHAR_V)<<(UART_AT_CMD_CHAR_S))
+#define UART_AT_CMD_CHAR_V 0xFF
+#define UART_AT_CMD_CHAR_S 0
+
+#define UART_MEM_CONF_REG(i) (REG_UART_BASE(i) + 0x58)
+/* UART_TX_MEM_EMPTY_THRHD : R/W ;bitpos:[30:28] ;default: 3'h0 ; */
+/*description: refer to txfifo_empty_thrhd 's describtion.*/
+#define UART_TX_MEM_EMPTY_THRHD 0x00000007
+#define UART_TX_MEM_EMPTY_THRHD_M ((UART_TX_MEM_EMPTY_THRHD_V)<<(UART_TX_MEM_EMPTY_THRHD_S))
+#define UART_TX_MEM_EMPTY_THRHD_V 0x7
+#define UART_TX_MEM_EMPTY_THRHD_S 28
+/* UART_RX_MEM_FULL_THRHD : R/W ;bitpos:[27:25] ;default: 3'h0 ; */
+/*description: refer to the rxfifo_full_thrhd's describtion.*/
+#define UART_RX_MEM_FULL_THRHD 0x00000007
+#define UART_RX_MEM_FULL_THRHD_M ((UART_RX_MEM_FULL_THRHD_V)<<(UART_RX_MEM_FULL_THRHD_S))
+#define UART_RX_MEM_FULL_THRHD_V 0x7
+#define UART_RX_MEM_FULL_THRHD_S 25
+/* UART_XOFF_THRESHOLD_H2 : R/W ;bitpos:[24:23] ;default: 2'h0 ; */
+/*description: refer to the uart_xoff_threshold's describtion.*/
+#define UART_XOFF_THRESHOLD_H2 0x00000003
+#define UART_XOFF_THRESHOLD_H2_M ((UART_XOFF_THRESHOLD_H2_V)<<(UART_XOFF_THRESHOLD_H2_S))
+#define UART_XOFF_THRESHOLD_H2_V 0x3
+#define UART_XOFF_THRESHOLD_H2_S 23
+/* UART_XON_THRESHOLD_H2 : R/W ;bitpos:[22:21] ;default: 2'h0 ; */
+/*description: refer to the uart_xon_threshold's describtion.*/
+#define UART_XON_THRESHOLD_H2 0x00000003
+#define UART_XON_THRESHOLD_H2_M ((UART_XON_THRESHOLD_H2_V)<<(UART_XON_THRESHOLD_H2_S))
+#define UART_XON_THRESHOLD_H2_V 0x3
+#define UART_XON_THRESHOLD_H2_S 21
+/* UART_RX_TOUT_THRHD_H3 : R/W ;bitpos:[20:18] ;default: 3'h0 ; */
+/*description: refer to the rx_tout_thrhd's describtion.*/
+#define UART_RX_TOUT_THRHD_H3 0x00000007
+#define UART_RX_TOUT_THRHD_H3_M ((UART_RX_TOUT_THRHD_H3_V)<<(UART_RX_TOUT_THRHD_H3_S))
+#define UART_RX_TOUT_THRHD_H3_V 0x7
+#define UART_RX_TOUT_THRHD_H3_S 18
+/* UART_RX_FLOW_THRHD_H3 : R/W ;bitpos:[17:15] ;default: 3'h0 ; */
+/*description: refer to the rx_flow_thrhd's describtion.*/
+#define UART_RX_FLOW_THRHD_H3 0x00000007
+#define UART_RX_FLOW_THRHD_H3_M ((UART_RX_FLOW_THRHD_H3_V)<<(UART_RX_FLOW_THRHD_H3_S))
+#define UART_RX_FLOW_THRHD_H3_V 0x7
+#define UART_RX_FLOW_THRHD_H3_S 15
+/* UART_TX_SIZE : R/W ;bitpos:[10:7] ;default: 4'h1 ; */
+/*description: This register is used to configure the amount of mem allocated
+ to transmitter's fifo.the default byte num is 128.*/
+#define UART_TX_SIZE 0x0000000F
+#define UART_TX_SIZE_M ((UART_TX_SIZE_V)<<(UART_TX_SIZE_S))
+#define UART_TX_SIZE_V 0xF
+#define UART_TX_SIZE_S 7
+/* UART_RX_SIZE : R/W ;bitpos:[6:3] ;default: 4'h1 ; */
+/*description: This register is used to configure the amount of mem allocated
+ to receiver's fifo. the default byte num is 128.*/
+#define UART_RX_SIZE 0x0000000F
+#define UART_RX_SIZE_M ((UART_RX_SIZE_V)<<(UART_RX_SIZE_S))
+#define UART_RX_SIZE_V 0xF
+#define UART_RX_SIZE_S 3
+/* UART_MEM_PD : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: Set this bit to power down mem.when reg_mem_pd registers in
+ the 3 uarts are all set to 1 mem will enter low power mode.*/
+#define UART_MEM_PD (BIT(0))
+#define UART_MEM_PD_M (BIT(0))
+#define UART_MEM_PD_V 0x1
+#define UART_MEM_PD_S 0
+
+#define UART_MEM_TX_STATUS_REG(i) (REG_UART_BASE(i) + 0x5c)
+/* UART_MEM_TX_STATUS : RO ;bitpos:[23:0] ;default: 24'h0 ; */
+/*description: */
+#define UART_MEM_TX_STATUS 0x00FFFFFF
+#define UART_MEM_TX_STATUS_M ((UART_MEM_TX_STATUS_V)<<(UART_MEM_TX_STATUS_S))
+#define UART_MEM_TX_STATUS_V 0xFFFFFF
+#define UART_MEM_TX_STATUS_S 0
+
+#define UART_MEM_RX_STATUS_REG(i) (REG_UART_BASE(i) + 0x60)
+/* UART_MEM_RX_STATUS : RO ;bitpos:[23:0] ;default: 24'h0 ; */
+/*description: */
+#define UART_MEM_RX_STATUS 0x00FFFFFF
+#define UART_MEM_RX_STATUS_M ((UART_MEM_RX_STATUS_V)<<(UART_MEM_RX_STATUS_S))
+#define UART_MEM_RX_STATUS_V 0xFFFFFF
+#define UART_MEM_RX_STATUS_S 0
+
+#define UART_MEM_CNT_STATUS_REG(i) (REG_UART_BASE(i) + 0x64)
+/* UART_TX_MEM_CNT : RO ;bitpos:[5:3] ;default: 3'b0 ; */
+/*description: refer to the txfifo_cnt's describtion.*/
+#define UART_TX_MEM_CNT 0x00000007
+#define UART_TX_MEM_CNT_M ((UART_TX_MEM_CNT_V)<<(UART_TX_MEM_CNT_S))
+#define UART_TX_MEM_CNT_V 0x7
+#define UART_TX_MEM_CNT_S 3
+/* UART_RX_MEM_CNT : RO ;bitpos:[2:0] ;default: 3'b0 ; */
+/*description: refer to the rxfifo_cnt's describtion.*/
+#define UART_RX_MEM_CNT 0x00000007
+#define UART_RX_MEM_CNT_M ((UART_RX_MEM_CNT_V)<<(UART_RX_MEM_CNT_S))
+#define UART_RX_MEM_CNT_V 0x7
+#define UART_RX_MEM_CNT_S 0
+
+#define UART_POSPULSE_REG(i) (REG_UART_BASE(i) + 0x68)
+/* UART_POSEDGE_MIN_CNT : RO ;bitpos:[19:0] ;default: 20'hFFFFF ; */
+/*description: This register stores the count of rxd posedge edge. it is used
+ in boudrate-detect process.*/
+#define UART_POSEDGE_MIN_CNT 0x000FFFFF
+#define UART_POSEDGE_MIN_CNT_M ((UART_POSEDGE_MIN_CNT_V)<<(UART_POSEDGE_MIN_CNT_S))
+#define UART_POSEDGE_MIN_CNT_V 0xFFFFF
+#define UART_POSEDGE_MIN_CNT_S 0
+
+#define UART_NEGPULSE_REG(i) (REG_UART_BASE(i) + 0x6c)
+/* UART_NEGEDGE_MIN_CNT : RO ;bitpos:[19:0] ;default: 20'hFFFFF ; */
+/*description: This register stores the count of rxd negedge edge. it is used
+ in boudrate-detect process.*/
+#define UART_NEGEDGE_MIN_CNT 0x000FFFFF
+#define UART_NEGEDGE_MIN_CNT_M ((UART_NEGEDGE_MIN_CNT_V)<<(UART_NEGEDGE_MIN_CNT_S))
+#define UART_NEGEDGE_MIN_CNT_V 0xFFFFF
+#define UART_NEGEDGE_MIN_CNT_S 0
+
+#define UART_DATE_REG(i) (REG_UART_BASE(i) + 0x78)
+/* UART_DATE : R/W ;bitpos:[31:0] ;default: 32'h15122500 ; */
+/*description: */
+#define UART_DATE 0xFFFFFFFF
+#define UART_DATE_M ((UART_DATE_V)<<(UART_DATE_S))
+#define UART_DATE_V 0xFFFFFFFF
+#define UART_DATE_S 0
+
+#define UART_ID_REG(i) (REG_UART_BASE(i) + 0x7C)
+/* UART_ID : R/W ;bitpos:[31:0] ;default: 32'h0500 ; */
+/*description: */
+#define UART_ID 0xFFFFFFFF
+#define UART_ID_M ((UART_ID_V)<<(UART_ID_S))
+#define UART_ID_V 0xFFFFFFFF
+#define UART_ID_S 0
+
+
+
+
+#endif /*__UART_REG_H__ */
+
+
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