[MSP430] Minor fixes/improvements for assembler/disassembler

* Teach AsmParser to recognize @rn in distination operand as 0(rn).
* Do not allow Disassembler decoding instructions that have size more
  than a number of input bytes.
* Fix UB in MSP430MCCodeEmitter.

Patch by Kristina Bessonova!

Differential Revision: https://reviews.llvm.org/D56547

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@350903 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/MSP430/AsmParser/MSP430AsmParser.cpp b/lib/Target/MSP430/AsmParser/MSP430AsmParser.cpp
index 3cc6da2c21aaf8d6912853ff3c46ad152c4f9f27..1ad70ac72c737597ffe9c7c22d8ae24baca09ecb 100644 (file)
--- a/lib/Target/MSP430/AsmParser/MSP430AsmParser.cpp
+++ b/lib/Target/MSP430/AsmParser/MSP430AsmParser.cpp
@@ -497,7 +497,11 @@ bool MSP430AsmParser::ParseOperand(OperandVector &Operands) {
         getLexer().Lex(); // Eat '+'
         return false;
       }
-      Operands.push_back(MSP430Operand::CreateIndReg(RegNo, StartLoc, EndLoc));
+      if (Operands.size() > 1) // Emulate @rd in destination position as 0(rd)
+        Operands.push_back(MSP430Operand::CreateMem(RegNo,
+            MCConstantExpr::create(0, getContext()), StartLoc, EndLoc));
+      else
+        Operands.push_back(MSP430Operand::CreateIndReg(RegNo, StartLoc, EndLoc));
       return false;
     }
     case AsmToken::Hash:

diff --git a/lib/Target/MSP430/Disassembler/MSP430Disassembler.cpp b/lib/Target/MSP430/Disassembler/MSP430Disassembler.cpp
index 2a66b4ed7f2d150fa2df1e1b081715fe1b17f0c8..e5da130f9bbb3e511d7c2334f313baaf812191b9 100644 (file)
--- a/lib/Target/MSP430/Disassembler/MSP430Disassembler.cpp
+++ b/lib/Target/MSP430/Disassembler/MSP430Disassembler.cpp
@@ -249,6 +249,10 @@ DecodeStatus MSP430Disassembler::getInstructionI(MCInst &MI, uint64_t &Size,
   case amSymbolic:
   case amImmediate:
   case amAbsolute:
+    if (Bytes.size() < (Words + 1) * 2) {
+      Size = 2;
+      return DecodeStatus::Fail;
+    }
     Insn |= (uint64_t)support::endian::read16le(Bytes.data() + 2) << 16;
     ++Words;
     break;
@@ -259,6 +263,10 @@ DecodeStatus MSP430Disassembler::getInstructionI(MCInst &MI, uint64_t &Size,
   case amIndexed:
   case amSymbolic:
   case amAbsolute:
+    if (Bytes.size() < (Words + 1) * 2) {
+      Size = 2;
+      return DecodeStatus::Fail;
+    }
     Insn |= (uint64_t)support::endian::read16le(Bytes.data() + Words * 2)
         << (Words * 16);
     ++Words;
@@ -296,6 +304,10 @@ DecodeStatus MSP430Disassembler::getInstructionII(MCInst &MI, uint64_t &Size,
   case amSymbolic:
   case amImmediate:
   case amAbsolute:
+    if (Bytes.size() < (Words + 1) * 2) {
+      Size = 2;
+      return DecodeStatus::Fail;
+    }
     Insn |= (uint64_t)support::endian::read16le(Bytes.data() + 2) << 16;
     ++Words;
     break;

diff --git a/lib/Target/MSP430/MCTargetDesc/MSP430MCCodeEmitter.cpp b/lib/Target/MSP430/MCTargetDesc/MSP430MCCodeEmitter.cpp
index adf2384f6e99515bdae8300b11b4516172e79bc1..06f9f307cb1a3343a91c2b27eb157274fbef3b2b 100644 (file)
--- a/lib/Target/MSP430/MCTargetDesc/MSP430MCCodeEmitter.cpp
+++ b/lib/Target/MSP430/MCTargetDesc/MSP430MCCodeEmitter.cpp
@@ -128,7 +128,7 @@ unsigned MSP430MCCodeEmitter::getMemOpValue(const MCInst &MI, unsigned Op,
   const MCOperand &MO2 = MI.getOperand(Op + 1);
   if (MO2.isImm()) {
     Offset += 2;
-    return (MO2.getImm() << 4) | Reg;
+    return ((unsigned)MO2.getImm() << 4) | Reg;
   }
 
   assert(MO2.isExpr() && "Expr operand expected");

diff --git a/test/MC/Disassembler/MSP430/unknown.txt b/test/MC/Disassembler/MSP430/unknown.txt
new file mode 100644 (file)
index 0000000..d7e680b
--- /dev/null
+++ b/test/MC/Disassembler/MSP430/unknown.txt
@@ -0,0 +1,13 @@
+# RUN: not llvm-mc -disassemble -triple=msp430 %s 2>&1 | FileCheck %s
+
+# This should not decode as 'and.b @r15+, (0)r1' [0xf1,0xff,0x00,0x00]
+[0xf1 0xff]
+# CHECK: warning: invalid instruction encoding
+
+# This should not decode as 'add 6(r7), 6(r5)' [0x95 0x57 0x06 0x00 0x06 0x00]
+[0x95 0x57 0x06 0x00]
+# CHECK: warning: invalid instruction encoding
+
+# This should not decode as 'call 6(r7)' [0x97 0x12 0x06 0x00]
+[0x97 0x12]
+# CHECK: warning: invalid instruction encoding

diff --git a/test/MC/MSP430/addrmode.s b/test/MC/MSP430/addrmode.s
index 7e389b6a50f60738c7a5ddf5accad82725cf6ba6..c787e683aeab8d2ce80b47c0abe50222a6b721b3 100644 (file)
--- a/test/MC/MSP430/addrmode.s
+++ b/test/MC/MSP430/addrmode.s
@@ -21,11 +21,13 @@ foo:
   mov #42, 12(r15)
   mov #42, &disp
   mov disp, disp+2
+  mov r7, @r15
 
 ; CHECK: mov #42, r15          ; encoding: [0x3f,0x40,0x2a,0x00]
 ; CHECK: mov #42, 12(r15)      ; encoding: [0xbf,0x40,0x2a,0x00,0x0c,0x00]
 ; CHECK: mov #42, &disp        ; encoding: [0xb2,0x40,0x2a,0x00,A,A]
 ; CHECK: mov disp, disp+2      ; encoding: [0x90,0x40,A,A,B,B]
+; CHECK: mov r7, 0(r15)        ; encoding: [0x8f,0x47,0x00,0x00]
 
   add r7, r8
   add 6(r7), r8

diff --git a/test/MC/MSP430/invalid.s b/test/MC/MSP430/invalid.s
index 2815b520dd5556f0921d2d3e2f3532d83bb96c51..ce686bd83f1edb01b67ff56e835de1e5c72e9616 100644 (file)
--- a/test/MC/MSP430/invalid.s
+++ b/test/MC/MSP430/invalid.s
@@ -4,7 +4,6 @@ foo:
   mov    r7        ; CHECK: :[[@LINE]]:3: error: too few operands for instruction
 
   ;; invalid destination addressing modes
-  mov    r7, @r15  ; CHECK: :[[@LINE]]:14: error: invalid operand for instruction
   mov    r7, @r15+ ; CHECK: :[[@LINE]]:14: error: invalid operand for instruction
   mov    r7, #0    ; CHECK: :[[@LINE]]:14: error: invalid operand for instruction
   mov    r7, #123  ; CHECK: :[[@LINE]]:14: error: invalid operand for instruction