-#menu "Driver configurations"
+menu "Driver configurations"
menu "ADC configuration"
endmenu # ADC Configuration
-#endmenu # Driver configurations
+menu "SPI master configuration"
+config SPI_MASTER_IN_IRAM
+ bool "Place transmitting functions of SPI master into IRAM"
+ default n
+ select SPI_MASTER_ISR_IN_IRAM
+ help
+ Normally only the ISR of SPI master is placed in the IRAM, so that it
+ can work without the flash when interrupt is triggered.
+ For other functions, there's some possibility that the flash cache
+ miss when running inside and out of SPI functions, which may increase
+ the interval of SPI transactions.
+ Enable this to put ``queue_trans``, ``get_trans_result`` and
+ ``transmit`` functions into the IRAM to avoid possible cache miss.
+
+ During unit test, this is enabled to measure the ideal case of api.
+
+config SPI_MASTER_ISR_IN_IRAM
+ bool "Place SPI master ISR function into IRAM"
+ default y
+ help
+ Place the SPI master ISR in to IRAM to avoid possibly cache miss, or
+ being disabled during flash writing access.
+
+endmenu # SPI Master Configuration
+
+endmenu # Driver configurations
#define NO_CS 3 //Number of CS pins per SPI host
+#ifdef CONFIG_SPI_MASTER_ISR_IN_IRAM
+#define SPI_MASTER_ISR_ATTR IRAM_ATTR
+#else
+#define SPI_MASTER_ISR_ATTR
+#endif
+
+#ifdef CONFIG_SPI_MASTER_IN_IRAM
+#define SPI_MASTER_ATTR IRAM_ATTR
+#else
+#define SPI_MASTER_ATTR
+#endif
+
/// struct to hold private transaction data (like tx and rx buffer for DMA).
typedef struct {
}
}
- err = esp_intr_alloc(spicommon_irqsource_for_host(host), ESP_INTR_FLAG_INTRDISABLED, spi_intr, (void*)spihost[host], &spihost[host]->intr);
+ int flags = ESP_INTR_FLAG_INTRDISABLED;
+#ifdef CONFIG_SPI_MASTER_ISR_IN_IRAM
+ flags |= ESP_INTR_FLAG_IRAM;
+#endif
+ err = esp_intr_alloc(spicommon_irqsource_for_host(host), flags, spi_intr, (void*)spihost[host], &spihost[host]->intr);
if (err != ESP_OK) {
ret = err;
goto cleanup;
//This is run in interrupt context and apart from initialization and destruction, this is the only code
//touching the host (=spihost[x]) variable. The rest of the data arrives in queues. That is why there are
//no muxes in this code.
-static void IRAM_ATTR spi_intr(void *arg)
+static void SPI_MASTER_ISR_ATTR spi_intr(void *arg)
{
int i;
BaseType_t r;
}
-esp_err_t spi_device_queue_trans(spi_device_handle_t handle, spi_transaction_t *trans_desc, TickType_t ticks_to_wait)
+esp_err_t SPI_MASTER_ATTR spi_device_queue_trans(spi_device_handle_t handle, spi_transaction_t *trans_desc, TickType_t ticks_to_wait)
{
esp_err_t ret = ESP_OK;
BaseType_t r;
return ret;
}
-esp_err_t spi_device_get_trans_result(spi_device_handle_t handle, spi_transaction_t **trans_desc, TickType_t ticks_to_wait)
+esp_err_t SPI_MASTER_ATTR spi_device_get_trans_result(spi_device_handle_t handle, spi_transaction_t **trans_desc, TickType_t ticks_to_wait)
{
BaseType_t r;
spi_trans_priv trans_buf;
}
//Porcelain to do one blocking transmission.
-esp_err_t spi_device_transmit(spi_device_handle_t handle, spi_transaction_t *trans_desc)
+esp_err_t SPI_MASTER_ATTR spi_device_transmit(spi_device_handle_t handle, spi_transaction_t *trans_desc)
{
esp_err_t ret;
spi_transaction_t *ret_trans;