if (MI->isBundle()) {
const MachineBasicBlock* MBB = MI->getParent();
MachineBasicBlock::const_instr_iterator MII = MI->getIterator();
- unsigned IgnoreCount = 0;
for (++MII; MII != MBB->instr_end() && MII->isInsideBundle(); ++MII)
- if (MII->getOpcode() == TargetOpcode::DBG_VALUE ||
- MII->getOpcode() == TargetOpcode::IMPLICIT_DEF)
- ++IgnoreCount;
- else
+ if (!MII->isDebugValue() && !MII->isImplicitDef())
HexagonLowerToMC(MCII, &*MII, MCB, *this);
}
else
bool HexagonSplitDoubleRegs::isProfitable(const USet &Part, LoopRegMap &IRM)
const {
- unsigned FixedNum = 0, SplitNum = 0, LoopPhiNum = 0;
+ unsigned FixedNum = 0, LoopPhiNum = 0;
int32_t TotalP = 0;
for (unsigned DR : Part) {
LoopPhiNum++;
}
// Splittable instruction.
- SplitNum++;
int32_t P = profit(UseI);
if (P == std::numeric_limits<int>::min())
return false;
HexagonMCErrInfo errInfo;
if (HexagonMCInstrInfo::isBundle(MCB)) {
bool hasConditional = false;
- unsigned Branches = 0, Returns = 0, NewIndirectBranches = 0,
- NewValueBranches = 0, Conditional = HEXAGON_PRESHUFFLE_PACKET_SIZE,
+ unsigned Branches = 0,
+ Conditional = HEXAGON_PRESHUFFLE_PACKET_SIZE,
Unconditional = HEXAGON_PRESHUFFLE_PACKET_SIZE;
for (unsigned i = HexagonMCInstrInfo::bundleInstructionsOffset;
if (HexagonMCInstrInfo::getDesc(MCII, MCI).isBranch() ||
HexagonMCInstrInfo::getDesc(MCII, MCI).isCall()) {
++Branches;
- if (HexagonMCInstrInfo::getDesc(MCII, MCI).isIndirectBranch() &&
- HexagonMCInstrInfo::isPredicatedNew(MCII, MCI))
- ++NewIndirectBranches;
- if (HexagonMCInstrInfo::isNewValue(MCII, MCI))
- ++NewValueBranches;
-
if (HexagonMCInstrInfo::isPredicated(MCII, MCI) ||
HexagonMCInstrInfo::isPredicatedNew(MCII, MCI)) {
hasConditional = true;
Unconditional = i; // Record the position of the unconditional branch.
}
}
- if (HexagonMCInstrInfo::getDesc(MCII, MCI).isReturn() &&
- HexagonMCInstrInfo::getDesc(MCII, MCI).mayLoad())
- ++Returns;
}
if (Branches) // FIXME: should "Defs.count(Hexagon::PC)" be here too?