[NFC][InstCombine] Redundant masking before left-shift: tests with assume

If the legality check is `(shiftNbits-maskNbits) s>= 0`,
then we can simplify it to `shiftNbits u>= maskNbits`,
which is easier to check for.

However, currently switching the `dropRedundantMaskingOfLeftShiftInput()`
to `SimplifyICmpInst()` does not catch these cases and regresses
currently-handled cases, so i'll leave it as is for now.

https://rise4fun.com/Alive/25P

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@366564 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/test/Transforms/InstCombine/redundant-left-shift-input-masking-variant-c.ll b/test/Transforms/InstCombine/redundant-left-shift-input-masking-variant-c.ll
index 54bd16f082bc3bc40a147bc9e7b3079430d28d1b..79a540d3452c388b84852e3680aa300b02105623 100644 (file)
--- a/test/Transforms/InstCombine/redundant-left-shift-input-masking-variant-c.ll
+++ b/test/Transforms/InstCombine/redundant-left-shift-input-masking-variant-c.ll
@@ -237,10 +237,36 @@ define i32 @t10_nuw_nsw(i32 %x, i32 %nbits) {
   ret i32 %t2
 }
 
+; Special test
+
+declare void @llvm.assume(i1 %cond)
+
+; We can't simplify (%shiftnbits-%masknbits) but we have an assumption.
+define i32 @t11_assume_uge(i32 %x, i32 %masknbits, i32 %shiftnbits) {
+; CHECK-LABEL: @t11_assume_uge(
+; CHECK-NEXT:    [[CMP:%.*]] = icmp uge i32 [[SHIFTNBITS:%.*]], [[MASKNBITS:%.*]]
+; CHECK-NEXT:    call void @llvm.assume(i1 [[CMP]])
+; CHECK-NEXT:    [[T0:%.*]] = lshr i32 -1, [[MASKNBITS]]
+; CHECK-NEXT:    [[T1:%.*]] = and i32 [[T0]], [[X:%.*]]
+; CHECK-NEXT:    call void @use32(i32 [[T0]])
+; CHECK-NEXT:    call void @use32(i32 [[T1]])
+; CHECK-NEXT:    [[T2:%.*]] = shl i32 [[T1]], [[SHIFTNBITS]]
+; CHECK-NEXT:    ret i32 [[T2]]
+;
+  %cmp = icmp uge i32 %shiftnbits, %masknbits
+  call void @llvm.assume(i1 %cmp)
+  %t0 = lshr i32 -1, %masknbits
+  %t1 = and i32 %t0, %x
+  call void @use32(i32 %t0)
+  call void @use32(i32 %t1)
+  %t2 = shl i32 %t1, %shiftnbits
+  ret i32 %t2
+}
+
 ; Negative tests
 
-define i32 @n11_not_minus_one(i32 %x, i32 %nbits) {
-; CHECK-LABEL: @n11_not_minus_one(
+define i32 @n12_not_minus_one(i32 %x, i32 %nbits) {
+; CHECK-LABEL: @n12_not_minus_one(
 ; CHECK-NEXT:    [[T0:%.*]] = lshr i32 -2, [[NBITS:%.*]]
 ; CHECK-NEXT:    [[T1:%.*]] = and i32 [[T0]], [[X:%.*]]
 ; CHECK-NEXT:    call void @use32(i32 [[T0]])
@@ -256,8 +282,8 @@ define i32 @n11_not_minus_one(i32 %x, i32 %nbits) {
   ret i32 %t2
 }
 
-define i32 @n12_shamt_is_smaller(i32 %x, i32 %nbits) {
-; CHECK-LABEL: @n12_shamt_is_smaller(
+define i32 @n13_shamt_is_smaller(i32 %x, i32 %nbits) {
+; CHECK-LABEL: @n13_shamt_is_smaller(
 ; CHECK-NEXT:    [[T0:%.*]] = lshr i32 -1, [[NBITS:%.*]]
 ; CHECK-NEXT:    [[T1:%.*]] = and i32 [[T0]], [[X:%.*]]
 ; CHECK-NEXT:    [[T2:%.*]] = add i32 [[NBITS]], -1

diff --git a/test/Transforms/InstCombine/redundant-left-shift-input-masking-variant-d.ll b/test/Transforms/InstCombine/redundant-left-shift-input-masking-variant-d.ll
index 1f0446cb0ecde06db3f411317b5626a743a2c994..e01ac41055f6404bc23dc39f1d340caada40f622 100644 (file)
--- a/test/Transforms/InstCombine/redundant-left-shift-input-masking-variant-d.ll
+++ b/test/Transforms/InstCombine/redundant-left-shift-input-masking-variant-d.ll
@@ -288,10 +288,40 @@ define i32 @t10_nuw_nsw(i32 %x, i32 %nbits) {
   ret i32 %t3
 }
 
+; Special test
+
+declare void @llvm.assume(i1 %cond)
+
+; We can't simplify (%shiftnbits-%masknbits) but we have an assumption.
+define i32 @t11_assume_uge(i32 %x, i32 %masknbits, i32 %shiftnbits) {
+; CHECK-LABEL: @t11_assume_uge(
+; CHECK-NEXT:    [[CMP:%.*]] = icmp uge i32 [[SHIFTNBITS:%.*]], [[MASKNBITS:%.*]]
+; CHECK-NEXT:    call void @llvm.assume(i1 [[CMP]])
+; CHECK-NEXT:    [[T0:%.*]] = shl i32 -1, [[MASKNBITS]]
+; CHECK-NEXT:    [[T1:%.*]] = lshr i32 [[T0]], [[MASKNBITS]]
+; CHECK-NEXT:    [[T2:%.*]] = and i32 [[T1]], [[X:%.*]]
+; CHECK-NEXT:    call void @use32(i32 [[T0]])
+; CHECK-NEXT:    call void @use32(i32 [[T1]])
+; CHECK-NEXT:    call void @use32(i32 [[T2]])
+; CHECK-NEXT:    [[T4:%.*]] = shl i32 [[T2]], [[SHIFTNBITS]]
+; CHECK-NEXT:    ret i32 [[T4]]
+;
+  %cmp = icmp uge i32 %shiftnbits, %masknbits
+  call void @llvm.assume(i1 %cmp)
+  %t0 = shl i32 -1, %masknbits
+  %t1 = lshr i32 %t0, %masknbits
+  %t2 = and i32 %t1, %x
+  call void @use32(i32 %t0)
+  call void @use32(i32 %t1)
+  call void @use32(i32 %t2)
+  %t4 = shl i32 %t2, %shiftnbits
+  ret i32 %t4
+}
+
 ; Negative tests
 
-define i32 @n11_different_shamts0(i32 %x, i32 %nbits0, i32 %nbits1) {
-; CHECK-LABEL: @n11_different_shamts0(
+define i32 @n12_different_shamts0(i32 %x, i32 %nbits0, i32 %nbits1) {
+; CHECK-LABEL: @n12_different_shamts0(
 ; CHECK-NEXT:    [[T0:%.*]] = shl i32 [[X:%.*]], [[NBITS0:%.*]]
 ; CHECK-NEXT:    [[T1:%.*]] = lshr i32 [[T0]], [[NBITS1:%.*]]
 ; CHECK-NEXT:    [[T2:%.*]] = and i32 [[T1]], [[X]]
@@ -311,8 +341,8 @@ define i32 @n11_different_shamts0(i32 %x, i32 %nbits0, i32 %nbits1) {
   ret i32 %t3
 }
 
-define i32 @n12_different_shamts1(i32 %x, i32 %nbits0, i32 %nbits1) {
-; CHECK-LABEL: @n12_different_shamts1(
+define i32 @n13_different_shamts1(i32 %x, i32 %nbits0, i32 %nbits1) {
+; CHECK-LABEL: @n13_different_shamts1(
 ; CHECK-NEXT:    [[T0:%.*]] = shl i32 [[X:%.*]], [[NBITS0:%.*]]
 ; CHECK-NEXT:    [[T1:%.*]] = lshr i32 [[T0]], [[NBITS1:%.*]]
 ; CHECK-NEXT:    [[T2:%.*]] = and i32 [[T1]], [[X]]
@@ -332,8 +362,8 @@ define i32 @n12_different_shamts1(i32 %x, i32 %nbits0, i32 %nbits1) {
   ret i32 %t3
 }
 
-define i32 @n13_shamt_is_smaller(i32 %x, i32 %nbits) {
-; CHECK-LABEL: @n13_shamt_is_smaller(
+define i32 @n14_shamt_is_smaller(i32 %x, i32 %nbits) {
+; CHECK-LABEL: @n14_shamt_is_smaller(
 ; CHECK-NEXT:    [[T0:%.*]] = shl i32 -1, [[NBITS:%.*]]
 ; CHECK-NEXT:    [[T1:%.*]] = lshr i32 [[T0]], [[NBITS]]
 ; CHECK-NEXT:    [[T2:%.*]] = and i32 [[T1]], [[X:%.*]]

diff --git a/test/Transforms/InstCombine/redundant-left-shift-input-masking-variant-e.ll b/test/Transforms/InstCombine/redundant-left-shift-input-masking-variant-e.ll
index 0a76225588e88582deb42c60063434278f670463..104340b08d5e9b3f3eb1a8cd478cddb82ec6986c 100644 (file)
--- a/test/Transforms/InstCombine/redundant-left-shift-input-masking-variant-e.ll
+++ b/test/Transforms/InstCombine/redundant-left-shift-input-masking-variant-e.ll
@@ -173,10 +173,36 @@ define i32 @t7_nuw_nsw(i32 %x, i32 %nbits) {
   ret i32 %t2
 }
 
+; Special test
+
+declare void @llvm.assume(i1 %cond)
+
+; We can't simplify (%shiftnbits-%masknbits) but we have an assumption.
+define i32 @t8_assume_uge(i32 %x, i32 %masknbits, i32 %shiftnbits) {
+; CHECK-LABEL: @t8_assume_uge(
+; CHECK-NEXT:    [[CMP:%.*]] = icmp uge i32 [[SHIFTNBITS:%.*]], [[MASKNBITS:%.*]]
+; CHECK-NEXT:    call void @llvm.assume(i1 [[CMP]])
+; CHECK-NEXT:    [[T0:%.*]] = shl i32 [[X:%.*]], [[MASKNBITS]]
+; CHECK-NEXT:    [[T1:%.*]] = lshr i32 [[T0]], [[MASKNBITS]]
+; CHECK-NEXT:    call void @use32(i32 [[T0]])
+; CHECK-NEXT:    call void @use32(i32 [[T1]])
+; CHECK-NEXT:    [[T2:%.*]] = shl i32 [[T1]], [[SHIFTNBITS]]
+; CHECK-NEXT:    ret i32 [[T2]]
+;
+  %cmp = icmp uge i32 %shiftnbits, %masknbits
+  call void @llvm.assume(i1 %cmp)
+  %t0 = shl i32 %x, %masknbits
+  %t1 = lshr i32 %t0, %masknbits
+  call void @use32(i32 %t0)
+  call void @use32(i32 %t1)
+  %t2 = shl i32 %t1, %shiftnbits
+  ret i32 %t2
+}
+
 ; Negative tests
 
-define i32 @n8_different_shamts0(i32 %x, i32 %nbits0, i32 %nbits1) {
-; CHECK-LABEL: @n8_different_shamts0(
+define i32 @n9_different_shamts0(i32 %x, i32 %nbits0, i32 %nbits1) {
+; CHECK-LABEL: @n9_different_shamts0(
 ; CHECK-NEXT:    [[T0:%.*]] = shl i32 [[X:%.*]], [[NBITS0:%.*]]
 ; CHECK-NEXT:    [[T1:%.*]] = lshr i32 [[T0]], [[NBITS1:%.*]]
 ; CHECK-NEXT:    call void @use32(i32 [[T0]])
@@ -192,8 +218,8 @@ define i32 @n8_different_shamts0(i32 %x, i32 %nbits0, i32 %nbits1) {
   ret i32 %t2
 }
 
-define i32 @n9_different_shamts1(i32 %x, i32 %nbits0, i32 %nbits1) {
-; CHECK-LABEL: @n9_different_shamts1(
+define i32 @n10_different_shamts1(i32 %x, i32 %nbits0, i32 %nbits1) {
+; CHECK-LABEL: @n10_different_shamts1(
 ; CHECK-NEXT:    [[T0:%.*]] = shl i32 [[X:%.*]], [[NBITS0:%.*]]
 ; CHECK-NEXT:    [[T1:%.*]] = lshr i32 [[T0]], [[NBITS1:%.*]]
 ; CHECK-NEXT:    call void @use32(i32 [[T0]])
@@ -209,8 +235,8 @@ define i32 @n9_different_shamts1(i32 %x, i32 %nbits0, i32 %nbits1) {
   ret i32 %t2
 }
 
-define i32 @n10_shamt_is_smaller(i32 %x, i32 %nbits) {
-; CHECK-LABEL: @n10_shamt_is_smaller(
+define i32 @n11_shamt_is_smaller(i32 %x, i32 %nbits) {
+; CHECK-LABEL: @n11_shamt_is_smaller(
 ; CHECK-NEXT:    [[T0:%.*]] = shl i32 [[X:%.*]], [[NBITS:%.*]]
 ; CHECK-NEXT:    [[T1:%.*]] = lshr i32 [[T0]], [[NBITS]]
 ; CHECK-NEXT:    [[T2:%.*]] = add i32 [[NBITS]], -1

diff --git a/test/Transforms/InstCombine/redundant-left-shift-input-masking-variant-f.ll b/test/Transforms/InstCombine/redundant-left-shift-input-masking-variant-f.ll
index 0e1e56869f07dfd12e4fa09377677eb536d71501..331d85edb7316bbdeb36b3811d2ac7a9f72ecef5 100644 (file)
--- a/test/Transforms/InstCombine/redundant-left-shift-input-masking-variant-f.ll
+++ b/test/Transforms/InstCombine/redundant-left-shift-input-masking-variant-f.ll
@@ -173,10 +173,36 @@ define i32 @t7_nuw_nsw(i32 %x, i32 %nbits) {
   ret i32 %t2
 }
 
+; Special test
+
+declare void @llvm.assume(i1 %cond)
+
+; We can't simplify (%shiftnbits-%masknbits) but we have an assumption.
+define i32 @t8_assume_uge(i32 %x, i32 %masknbits, i32 %shiftnbits) {
+; CHECK-LABEL: @t8_assume_uge(
+; CHECK-NEXT:    [[CMP:%.*]] = icmp uge i32 [[SHIFTNBITS:%.*]], [[MASKNBITS:%.*]]
+; CHECK-NEXT:    call void @llvm.assume(i1 [[CMP]])
+; CHECK-NEXT:    [[T0:%.*]] = shl i32 [[X:%.*]], [[MASKNBITS]]
+; CHECK-NEXT:    [[T1:%.*]] = ashr i32 [[T0]], [[MASKNBITS]]
+; CHECK-NEXT:    call void @use32(i32 [[T0]])
+; CHECK-NEXT:    call void @use32(i32 [[T1]])
+; CHECK-NEXT:    [[T2:%.*]] = shl i32 [[T1]], [[SHIFTNBITS]]
+; CHECK-NEXT:    ret i32 [[T2]]
+;
+  %cmp = icmp uge i32 %shiftnbits, %masknbits
+  call void @llvm.assume(i1 %cmp)
+  %t0 = shl i32 %x, %masknbits
+  %t1 = ashr i32 %t0, %masknbits
+  call void @use32(i32 %t0)
+  call void @use32(i32 %t1)
+  %t2 = shl i32 %t1, %shiftnbits
+  ret i32 %t2
+}
+
 ; Negative tests
 
-define i32 @n8_different_shamts0(i32 %x, i32 %nbits0, i32 %nbits1) {
-; CHECK-LABEL: @n8_different_shamts0(
+define i32 @n9_different_shamts0(i32 %x, i32 %nbits0, i32 %nbits1) {
+; CHECK-LABEL: @n9_different_shamts0(
 ; CHECK-NEXT:    [[T0:%.*]] = shl i32 [[X:%.*]], [[NBITS0:%.*]]
 ; CHECK-NEXT:    [[T1:%.*]] = ashr i32 [[T0]], [[NBITS1:%.*]]
 ; CHECK-NEXT:    call void @use32(i32 [[T0]])
@@ -192,8 +218,8 @@ define i32 @n8_different_shamts0(i32 %x, i32 %nbits0, i32 %nbits1) {
   ret i32 %t2
 }
 
-define i32 @n9_different_shamts1(i32 %x, i32 %nbits0, i32 %nbits1) {
-; CHECK-LABEL: @n9_different_shamts1(
+define i32 @n10_different_shamts1(i32 %x, i32 %nbits0, i32 %nbits1) {
+; CHECK-LABEL: @n10_different_shamts1(
 ; CHECK-NEXT:    [[T0:%.*]] = shl i32 [[X:%.*]], [[NBITS0:%.*]]
 ; CHECK-NEXT:    [[T1:%.*]] = ashr i32 [[T0]], [[NBITS1:%.*]]
 ; CHECK-NEXT:    call void @use32(i32 [[T0]])
@@ -209,8 +235,8 @@ define i32 @n9_different_shamts1(i32 %x, i32 %nbits0, i32 %nbits1) {
   ret i32 %t2
 }
 
-define i32 @n10_shamt_is_smaller(i32 %x, i32 %nbits) {
-; CHECK-LABEL: @n10_shamt_is_smaller(
+define i32 @n11_shamt_is_smaller(i32 %x, i32 %nbits) {
+; CHECK-LABEL: @n11_shamt_is_smaller(
 ; CHECK-NEXT:    [[T0:%.*]] = shl i32 [[X:%.*]], [[NBITS:%.*]]
 ; CHECK-NEXT:    [[T1:%.*]] = ashr i32 [[T0]], [[NBITS]]
 ; CHECK-NEXT:    [[T2:%.*]] = add i32 [[NBITS]], -1