switch (Op.getOpcode()) {
default: llvm_unreachable("Unknown instruction!");
case ISD::ADDCARRY:
+ if (Carry.getOpcode() != ISD::UADDO && Carry.getOpcode() != ISD::ADDCARRY)
+ return SDValue();
+
BaseOp = SystemZISD::ADDCARRY;
CCValid = SystemZ::CCMASK_LOGICAL;
CCMask = SystemZ::CCMASK_LOGICAL_CARRY;
break;
case ISD::SUBCARRY:
+ if (Carry.getOpcode() != ISD::USUBO && Carry.getOpcode() != ISD::SUBCARRY)
+ return SDValue();
+
BaseOp = SystemZISD::SUBCARRY;
CCValid = SystemZ::CCMASK_LOGICAL;
CCMask = SystemZ::CCMASK_LOGICAL_BORROW;
--- /dev/null
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
+
+define i8 @test(i8 %x) {
+; CHECK-LABEL: test:
+; CHECK: # %bb.0:
+; CHECK-NEXT: slgfi %r0, 1
+; CHECK-NEXT: ipm %r0
+; CHECK-NEXT: afi %r0, -536870912
+; CHECK-NEXT: srl %r0, 31
+; CHECK-NEXT: ar %r2, %r0
+; CHECK-NEXT: br %r14
+ %usubo = tail call { i64, i1 } @llvm.usub.with.overflow.i64(i64 undef, i64 1)
+ %ov = extractvalue { i64, i1 } %usubo, 1
+ %ovext = zext i1 %ov to i8
+ %ret = add i8 %x, %ovext
+ ret i8 %ret
+}
+
+; Function Attrs: nounwind readnone speculatable
+declare { i64, i1 } @llvm.usub.with.overflow.i64(i64, i64) #0
+
+attributes #0 = { nounwind readnone speculatable }