Move write key and stage action select constants into headers

diff --git a/components/esp32/include/soc/rtc_cntl_reg.h b/components/esp32/include/soc/rtc_cntl_reg.h
index 24e0f1403c9626cd42e3cba4b2c4c1cd1ad28f15..bb4e2afced7199f553671cf89ea9cde13bfdf4fb 100644 (file)
--- a/components/esp32/include/soc/rtc_cntl_reg.h
+++ b/components/esp32/include/soc/rtc_cntl_reg.h
@@ -14,7 +14,8 @@
 #ifndef _SOC_RTC_CNTL_REG_H_
 #define _SOC_RTC_CNTL_REG_H_
 
-#define WDT_WRITE_KEY 0x50D83AA1
+/* The value that needs to be written to RTC_CNTL_WDT_WKEY to write-enable the wdt registers */
+#define RTC_CNTL_WDT_WKEY_VALUE 0x50D83AA1
 
 
 #include "soc.h"

diff --git a/components/esp32/include/soc/timer_group_reg.h b/components/esp32/include/soc/timer_group_reg.h
index 0d67cab517d09cc435f5031e14991bb1b54a649f..2db2a7e3f1b51b689d1f1cc2944b087187deb110 100644 (file)
--- a/components/esp32/include/soc/timer_group_reg.h
+++ b/components/esp32/include/soc/timer_group_reg.h
@@ -15,7 +15,15 @@
 #define __TIMG_REG_H__
 #include "soc.h"
 
-#define WDT_WRITE_KEY 0x50D83AA1
+/* The value that needs to be written to TIMG_WDT_WKEY to write-enable the wdt registers */
+#define TIMG_WDT_WKEY_VALUE 0x50D83AA1
+
+/* Possible values for TIMG_WDT_STGx */
+#define TIMG_WDT_STG_SEL_OFF 0
+#define TIMG_WDT_STG_SEL_INT 1
+#define TIMG_WDT_STG_SEL_RESET_CPU 2
+#define TIMG_WDT_STG_SEL_RESET_SYSTEM 3
+
 
 #define REG_TIMG_BASE(i)       (DR_REG_TIMERGROUP0_BASE + i*0x1000)
 #define TIMG_T0CONFIG_REG(i)          (REG_TIMG_BASE(i) + 0x0000)

diff --git a/components/esp32/int_wdt.c b/components/esp32/int_wdt.c
index 5f123ee368cd96a9e2cf6b1e33c70491a7379493..93a4d9fe62b0713b5094a83e4d09f7b550b821cf 100644 (file)
--- a/components/esp32/int_wdt.c
+++ b/components/esp32/int_wdt.c
@@ -36,13 +36,13 @@
 
 
 void esp_int_wdt_init() {
-    TIMERG1.wdt_wprotect=WDT_WRITE_KEY;
-    TIMERG1.wdt_config0.sys_reset_length=7;             //3.2uS
-    TIMERG1.wdt_config0.cpu_reset_length=7;             //3.2uS
+    TIMERG1.wdt_wprotect=TIMG_WDT_WKEY_VALUE;
+    TIMERG1.wdt_config0.sys_reset_length=7;                 //3.2uS
+    TIMERG1.wdt_config0.cpu_reset_length=7;                 //3.2uS
     TIMERG1.wdt_config0.level_int_en=1;
-    TIMERG1.wdt_config0.stg0=1;                         //1st stage timeout: interrupt
-    TIMERG1.wdt_config0.stg1=3;                         //2nd stage timeout: reset system
-    TIMERG1.wdt_config1.clk_prescale=80*500;            //Prescaler: wdt counts in ticks of 0.5mS
+    TIMERG1.wdt_config0.stg0=TIMG_WDT_STG_SEL_INT;          //1st stage timeout: interrupt
+    TIMERG1.wdt_config0.stg1=TIMG_WDT_STG_SEL_RESET_SYSTEM; //2nd stage timeout: reset system
+    TIMERG1.wdt_config1.clk_prescale=80*500;                //Prescaler: wdt counts in ticks of 0.5mS
     //The timer configs initially are set to 5 seconds, to make sure the CPU can start up. The tick hook sets
     //it to their actual value.
     TIMERG1.wdt_config2=10000;
@@ -72,7 +72,7 @@ void vApplicationTickHook(void) {
     } else {
         //Only feed wdt if app cpu also ticked.
         if (int_wdt_app_cpu_ticked) {
-            TIMERG1.wdt_wprotect=WDT_WRITE_KEY;
+            TIMERG1.wdt_wprotect=TIMG_WDT_WKEY_VALUE;
             TIMERG1.wdt_config2=CONFIG_INT_WDT_TIMEOUT_MS*2;        //Set timeout before interrupt
             TIMERG1.wdt_config3=CONFIG_INT_WDT_TIMEOUT_MS*4;        //Set timeout before reset
             TIMERG1.wdt_feed=1;
@@ -84,7 +84,7 @@ void vApplicationTickHook(void) {
 #else
 void vApplicationTickHook(void) {
     if (xPortGetCoreID()!=0) return;
-    TIMERG1.wdt_wprotect=WDT_WRITE_KEY;
+    TIMERG1.wdt_wprotect=TIMG_WDT_WKEY_VALUE;
     TIMERG1.wdt_config2=CONFIG_INT_WDT_TIMEOUT_MS*2;        //Set timeout before interrupt
     TIMERG1.wdt_config3=CONFIG_INT_WDT_TIMEOUT_MS*4;        //Set timeout before reset
     TIMERG1.wdt_feed=1;

diff --git a/components/esp32/panic.c b/components/esp32/panic.c
index 758d581d0915235803ec6298d88e5999c969605e..274364008b2ea904b81baf088adff25ea4838496 100644 (file)
--- a/components/esp32/panic.c
+++ b/components/esp32/panic.c
@@ -203,17 +203,17 @@ all watchdogs except the timer group 0 watchdog, and it reconfigures that to res
 one second.
 */
 static void reconfigureAllWdts() {
-       TIMERG0.wdt_wprotect=WDT_WRITE_KEY;
+       TIMERG0.wdt_wprotect=TIMG_WDT_WKEY_VALUE;
        TIMERG0.wdt_feed=1;
        TIMERG0.wdt_config0.sys_reset_length=7;                         //3.2uS
        TIMERG0.wdt_config0.cpu_reset_length=7;                         //3.2uS
-       TIMERG0.wdt_config0.stg0=3;                                                     //1st stage timeout: reset system
+       TIMERG0.wdt_config0.stg0=TIMG_WDT_STG_SEL_RESET_SYSTEM; //1st stage timeout: reset system
        TIMERG0.wdt_config1.clk_prescale=80*500;                        //Prescaler: wdt counts in ticks of 0.5mS
        TIMERG0.wdt_config2=2000;                                                       //1 second before reset
        TIMERG0.wdt_config0.en=1;
        TIMERG0.wdt_wprotect=0;
        //Disable wdt 1
-       TIMERG1.wdt_wprotect=WDT_WRITE_KEY;
+       TIMERG1.wdt_wprotect=TIMG_WDT_WKEY_VALUE;
        TIMERG1.wdt_config0.en=0;
        TIMERG1.wdt_wprotect=0;
 }
@@ -222,10 +222,10 @@ static void reconfigureAllWdts() {
 This disables all the watchdogs for when we call the gdbstub.
 */
 static void disableAllWdts() {
-       TIMERG0.wdt_wprotect=WDT_WRITE_KEY;
+       TIMERG0.wdt_wprotect=TIMG_WDT_WKEY_VALUE;
        TIMERG0.wdt_config0.en=0;
        TIMERG0.wdt_wprotect=0;
-       TIMERG1.wdt_wprotect=WDT_WRITE_KEY;
+       TIMERG1.wdt_wprotect=TIMG_WDT_WKEY_VALUE;
        TIMERG1.wdt_config0.en=0;
        TIMERG0.wdt_wprotect=0;
 }

diff --git a/components/esp32/task_wdt.c b/components/esp32/task_wdt.c
index 24d3977b184c383b35a0e609657a658db250ce7d..bec1cadaa7cb00ea1940a4eb04c497c4267193ce 100644 (file)
--- a/components/esp32/task_wdt.c
+++ b/components/esp32/task_wdt.c
@@ -49,7 +49,7 @@ static void IRAM_ATTR task_wdt_isr(void *arg) {
     wdt_task_t *wdttask;
     const char *cpu;
     //Feed the watchdog so we do not reset
-    TIMERG0.wdt_wprotect=WDT_WRITE_KEY;
+    TIMERG0.wdt_wprotect=TIMG_WDT_WKEY_VALUE;
     TIMERG0.wdt_feed=1;
     TIMERG0.wdt_wprotect=0;
     //Ack interrupt
@@ -107,7 +107,7 @@ void esp_task_wdt_feed() {
     }
     if (do_feed_wdt) {
         //All tasks have checked in; time to feed the hw watchdog.
-        TIMERG0.wdt_wprotect=WDT_WRITE_KEY;
+        TIMERG0.wdt_wprotect=TIMG_WDT_WKEY_VALUE;
         TIMERG0.wdt_feed=1;
         TIMERG0.wdt_wprotect=0;
         //Reset fed_watchdog status
@@ -141,13 +141,13 @@ void esp_task_wdt_delete() {
 }
 
 void esp_task_wdt_init() {
-    TIMERG0.wdt_wprotect=WDT_WRITE_KEY;
-    TIMERG0.wdt_config0.sys_reset_length=7;             //3.2uS
-    TIMERG0.wdt_config0.cpu_reset_length=7;             //3.2uS
+    TIMERG0.wdt_wprotect=TIMG_WDT_WKEY_VALUE;
+    TIMERG0.wdt_config0.sys_reset_length=7;                 //3.2uS
+    TIMERG0.wdt_config0.cpu_reset_length=7;                 //3.2uS
     TIMERG0.wdt_config0.level_int_en=1;
-    TIMERG0.wdt_config0.stg0=1;                         //1st stage timeout: interrupt
-    TIMERG0.wdt_config0.stg1=3;                         //2nd stage timeout: reset system
-    TIMERG0.wdt_config1.clk_prescale=80*500;            //Prescaler: wdt counts in ticks of 0.5mS
+    TIMERG0.wdt_config0.stg0=TIMG_WDT_STG_SEL_INT;          //1st stage timeout: interrupt
+    TIMERG0.wdt_config0.stg1=TIMG_WDT_STG_SEL_RESET_SYSTEM; //2nd stage timeout: reset system
+    TIMERG0.wdt_config1.clk_prescale=80*500;                //Prescaler: wdt counts in ticks of 0.5mS
     TIMERG0.wdt_config2=CONFIG_TASK_WDT_TIMEOUT_S*2000;     //Set timeout before interrupt
     TIMERG0.wdt_config3=CONFIG_TASK_WDT_TIMEOUT_S*4000;     //Set timeout before reset
     TIMERG0.wdt_config0.en=1;