[AMDGPU][MC][GFX10] Enabled null for 64-bit dst operands

See https://bugs.llvm.org/show_bug.cgi?id=43524

Reviewers: arsenm, rampitec

Differential Revision: https://reviews.llvm.org/D68785

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@374557 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp b/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
index 9ef8b309ee22239e5eba386f4c0213c251c2e79a..75e0fb8520f5d6baeb40761cd6bbc4808f63545f 100644 (file)
--- a/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
+++ b/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
@@ -290,6 +290,10 @@ public:
     return isOff() || isVReg32();
   }
 
+  bool isNull() const {
+    return isRegKind() && getReg() == AMDGPU::SGPR_NULL;
+  }
+
   bool isSDWAOperand(MVT type) const;
   bool isSDWAFP16Operand() const;
   bool isSDWAFP32Operand() const;
@@ -6976,6 +6980,14 @@ unsigned AMDGPUAsmParser::validateTargetOperandClass(MCParsedAsmOperand &Op,
     return Operand.isInterpAttr() ? Match_Success : Match_InvalidOperand;
   case MCK_AttrChan:
     return Operand.isAttrChan() ? Match_Success : Match_InvalidOperand;
+  case MCK_SReg_64:
+  case MCK_SReg_64_XEXEC:
+    // Null is defined as a 32-bit register but
+    // it should also be enabled with 64-bit operands.
+    // The following code enables it for SReg_64 operands
+    // used as source and destination. Remaining source
+    // operands are handled in isInlinableImm.
+    return Operand.isNull() ? Match_Success : Match_InvalidOperand;
   default:
     return Match_InvalidOperand;
   }

diff --git a/test/MC/AMDGPU/sop1.s b/test/MC/AMDGPU/sop1.s
index e4aacd6a75b72381ff9bd16f41636c9120b5333b..97920ac70517fe5d0b36c209741722ebefd4ab81 100644 (file)
--- a/test/MC/AMDGPU/sop1.s
+++ b/test/MC/AMDGPU/sop1.s
@@ -1,6 +1,7 @@
 // RUN: not llvm-mc -arch=amdgcn -show-encoding %s | FileCheck --check-prefix=GCN --check-prefix=SICI %s
 // RUN: not llvm-mc -arch=amdgcn -mcpu=fiji -show-encoding %s 2>&1 | FileCheck --check-prefix=GCN --check-prefix=VI --check-prefix=GFX89 %s
 // RUN: not llvm-mc -arch=amdgcn -mcpu=gfx900 -show-encoding %s 2>&1 | FileCheck --check-prefix=GCN --check-prefix=GFX89 --check-prefix=GFX9 %s
+// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1010 -show-encoding %s 2>&1 | FileCheck --check-prefix=GCN --check-prefix=GFX10 %s
 
 // RUN: not llvm-mc -arch=amdgcn -show-encoding %s 2>&1 | FileCheck --check-prefix=NOSICI --check-prefix=NOSICIVI %s
 // RUN: not llvm-mc -arch=amdgcn -mcpu=fiji -show-encoding %s 2>&1 | FileCheck --check-prefix=NOVI --check-prefix=NOSICIVI --check-prefix=NOGFX89 %s
@@ -34,6 +35,10 @@ s_mov_b64 s[2:3], s[4:5]
 // SICI: s_mov_b64 s[2:3], s[4:5] ; encoding: [0x04,0x04,0x82,0xbe]
 // GFX89: s_mov_b64 s[2:3], s[4:5] ; encoding: [0x04,0x01,0x82,0xbe]
 
+s_mov_b64 null, s[4:5]
+// GFX10: s_mov_b64 null, s[4:5] ; encoding: [0x04,0x04,0xfd,0xbe]
+// NOSICIVI: error: not a valid operand.
+
 s_mov_b64 s[2:3], 0xffffffffffffffff
 // SICI: s_mov_b64 s[2:3], -1 ; encoding: [0xc1,0x04,0x82,0xbe]
 // GFX89: s_mov_b64 s[2:3], -1 ; encoding: [0xc1,0x01,0x82,0xbe]

diff --git a/test/MC/AMDGPU/sop2.s b/test/MC/AMDGPU/sop2.s
index 84e157cb5b6c3fd8f6225a1fdaa5a8c3af45b99d..c1fe19a787d01fadb1df3b0aae26686ddc576073 100644 (file)
--- a/test/MC/AMDGPU/sop2.s
+++ b/test/MC/AMDGPU/sop2.s
@@ -3,6 +3,7 @@
 // RUN: not llvm-mc -arch=amdgcn -mcpu=bonaire -show-encoding %s | FileCheck --check-prefix=GCN --check-prefix=SICI %s
 // RUN: not llvm-mc -arch=amdgcn -mcpu=fiji -show-encoding %s | FileCheck --check-prefix=GCN --check-prefix=GFX89 %s
 // RUN: not llvm-mc -arch=amdgcn -mcpu=gfx900 -show-encoding %s | FileCheck --check-prefix=GCN --check-prefix=GFX89 --check-prefix=GFX9 %s
+// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1010 -show-encoding %s | FileCheck --check-prefix=GCN --check-prefix=GFX10 %s
 
 // RUN: not llvm-mc -arch=amdgcn -show-encoding %s 2>&1 | FileCheck --check-prefix=NOSICIVI %s
 // RUN: not llvm-mc -arch=amdgcn -mcpu=tahiti -show-encoding %s 2>&1 | FileCheck --check-prefix=NOSICIVI %s
@@ -60,6 +61,10 @@ s_and_b32 s2, 0xFFFF0000, -65536
 // SICI: s_and_b32 s2, 0xffff0000, 0xffff0000 ; encoding: [0xff,0xff,0x02,0x87,0x00,0x00,0xff,0xff]
 // GFX89: s_and_b32 s2, 0xffff0000, 0xffff0000 ; encoding: [0xff,0xff,0x02,0x86,0x00,0x00,0xff,0xff]
 
+s_and_b64 null, s[4:5], s[6:7]
+// GFX10: s_and_b64 null, s[4:5], s[6:7] ; encoding: [0x04,0x06,0xfd,0x87]
+// NOSICIVI: error: not a valid operand.
+
 s_and_b64 s[2:3], s[4:5], s[6:7]
 // SICI: s_and_b64 s[2:3], s[4:5], s[6:7] ; encoding: [0x04,0x06,0x82,0x87]
 // GFX89: s_and_b64 s[2:3], s[4:5], s[6:7] ; encoding: [0x04,0x06,0x82,0x86]

diff --git a/test/MC/AMDGPU/sopk.s b/test/MC/AMDGPU/sopk.s
index 2c924571222ba6871414ebe4cacaaaa0696ab8a5..ebadd76cee2f378037fc6df88402d45234804409 100644 (file)
--- a/test/MC/AMDGPU/sopk.s
+++ b/test/MC/AMDGPU/sopk.s
@@ -1,12 +1,13 @@
 // RUN: not llvm-mc -arch=amdgcn -show-encoding %s | FileCheck --check-prefix=GCN --check-prefix=SICI %s
 // RUN: not llvm-mc -arch=amdgcn -mcpu=tahiti -show-encoding %s | FileCheck --check-prefix=GCN --check-prefix=SICI %s
 // RUN: not llvm-mc -arch=amdgcn -mcpu=fiji -show-encoding %s | FileCheck --check-prefix=GCN --check-prefix=VI9 --check-prefix=VI %s
-// RUN: llvm-mc -arch=amdgcn -mcpu=gfx900 -show-encoding %s | FileCheck --check-prefix=GCN --check-prefix=VI9 --check-prefix=GFX9 %s
+// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx900 -show-encoding %s | FileCheck --check-prefix=GCN --check-prefix=VI9 --check-prefix=GFX9 %s
 // RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1010 -show-encoding %s | FileCheck --check-prefix=GCN --check-prefix=GFX10 %s
 
 // RUN: not llvm-mc -arch=amdgcn %s 2>&1 | FileCheck -check-prefix=NOSICIVI %s
 // RUN: not llvm-mc -arch=amdgcn -mcpu=tahiti %s 2>&1 | FileCheck -check-prefix=NOSICIVI -check-prefix=NOSI %s
 // RUN: not llvm-mc -arch=amdgcn -mcpu=fiji %s 2>&1 | FileCheck -check-prefix=NOSICIVI -check-prefix=NOVI %s
+// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx900 %s 2>&1 | FileCheck --check-prefix=NOGFX9 %s
 
 //===----------------------------------------------------------------------===//
 // Instructions
@@ -319,6 +320,11 @@ s_endpgm_ordered_ps_done
 // GFX9:     s_endpgm_ordered_ps_done ; encoding: [0x00,0x00,0x9e,0xbf]
 // NOSICIVI: error: instruction not supported on this GPU
 
+s_call_b64 null, 12609
+// GFX10: s_call_b64 null, 12609 ; encoding: [0x41,0x31,0x7d,0xbb]
+// NOSICIVI: error: not a valid operand.
+// NOGFX9: error: not a valid operand.
+
 s_call_b64 s[12:13], 12609
 // GFX9:     s_call_b64 s[12:13], 12609 ; encoding: [0x41,0x31,0x8c,0xba]
 // NOSICIVI: error: instruction not supported on this GPU

diff --git a/test/MC/Disassembler/AMDGPU/gfx10_dasm_all.txt b/test/MC/Disassembler/AMDGPU/gfx10_dasm_all.txt
index d0af32996082b94ecfe5b539ef8f02b95adb6648..1ad843512822906ab6e1b69af388f0c36787d187 100644 (file)
--- a/test/MC/Disassembler/AMDGPU/gfx10_dasm_all.txt
+++ b/test/MC/Disassembler/AMDGPU/gfx10_dasm_all.txt
@@ -8978,6 +8978,9 @@
 # GFX10: s_and_b32 vcc_lo, s1, s2        ; encoding: [0x01,0x02,0x6a,0x87]
 0x01,0x02,0x6a,0x87
 
+# GFX10: s_and_b64 null, s[4:5], s[6:7] ; encoding: [0x04,0x06,0xfd,0x87]
+0x04,0x06,0xfd,0x87
+
 # GFX10: s_and_b64 exec, s[2:3], s[4:5]  ; encoding: [0x02,0x04,0xfe,0x87]
 0x02,0x04,0xfe,0x87
 
@@ -11693,6 +11696,9 @@
 # GFX10: s_buffer_store_dwordx4 s[96:99], s[8:11], s0 ; encoding: [0x04,0x18,0x68,0xf4,0x00,0x00,0x00,0x00]
 0x04,0x18,0x68,0xf4,0x00,0x00,0x00,0x00
 
+# GFX10: s_call_b64 null, 12609        ; encoding: [0x41,0x31,0x7d,0xbb]
+0x41,0x31,0x7d,0xbb
+
 # GFX10: s_call_b64 exec, 4660         ; encoding: [0x34,0x12,0x7e,0xbb]
 0x34,0x12,0x7e,0xbb
 
@@ -15665,6 +15671,9 @@
 # GFX10: s_mov_b32 vcc_lo, s1            ; encoding: [0x01,0x03,0xea,0xbe]
 0x01,0x03,0xea,0xbe
 
+# GFX10: s_mov_b64 null, s[4:5]          ; encoding: [0x04,0x04,0xfd,0xbe]
+0x04,0x04,0xfd,0xbe
+
 # GFX10: s_mov_b64 exec, s[2:3]          ; encoding: [0x02,0x04,0xfe,0xbe]
 0x02,0x04,0xfe,0xbe