]> granicus.if.org Git - llvm/commitdiff
[X86] Add CLWB schedule test
authorSimon Pilgrim <llvm-dev@redking.me.uk>
Wed, 13 Dec 2017 22:09:09 +0000 (22:09 +0000)
committerSimon Pilgrim <llvm-dev@redking.me.uk>
Wed, 13 Dec 2017 22:09:09 +0000 (22:09 +0000)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320644 91177308-0d34-0410-b5e6-96231b3b80d8

test/CodeGen/X86/clwb-schedule.ll [new file with mode: 0644]

diff --git a/test/CodeGen/X86/clwb-schedule.ll b/test/CodeGen/X86/clwb-schedule.ll
new file mode 100644 (file)
index 0000000..24931ad
--- /dev/null
@@ -0,0 +1,18 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -print-schedule -mcpu=x86-64 -mattr=+clwb | FileCheck %s --check-prefix=GENERIC
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -print-schedule -mcpu=skx | FileCheck %s --check-prefix=SKX
+
+define void @clwb(i8* %a0) nounwind {
+; GENERIC-LABEL: clwb:
+; GENERIC:       # %bb.0:
+; GENERIC-NEXT:    clwb (%rdi) # sched: [4:0.50]
+; GENERIC-NEXT:    retq # sched: [1:1.00]
+;
+; SKX-LABEL: clwb:
+; SKX:       # %bb.0:
+; SKX-NEXT:    clwb (%rdi) # sched: [5:0.50]
+; SKX-NEXT:    retq # sched: [7:1.00]
+  tail call void @llvm.x86.clwb(i8* %a0)
+  ret void
+}
+declare void @llvm.x86.clwb(i8*) nounwind