Revert "[GlobalISel] Introduce a generic floating point floor opcode, G_FFLOOR"

This reverts commit b05ecba6d687fcb3078509220c67458bf1d77a2e.

Apparently adding floor breaks AMDGPU somehow, so I have to back this out
while I look into it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@353065 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/include/llvm/Support/TargetOpcodes.def b/include/llvm/Support/TargetOpcodes.def
index 5f4e9c67a0934d48e17bcb001d4766b950f3ef3f..23d008a0147282bd7123d2f19de3cc60805cfc5a 100644 (file)
--- a/include/llvm/Support/TargetOpcodes.def
+++ b/include/llvm/Support/TargetOpcodes.def
@@ -529,9 +529,6 @@ HANDLE_TARGET_OPCODE(G_FSIN)
 /// Floating point square root.
 HANDLE_TARGET_OPCODE(G_FSQRT)
 
-/// Floating point floor.
-HANDLE_TARGET_OPCODE(G_FFLOOR)
-
 /// Generic AddressSpaceCast.
 HANDLE_TARGET_OPCODE(G_ADDRSPACE_CAST)
 

diff --git a/include/llvm/Target/GenericOpcodes.td b/include/llvm/Target/GenericOpcodes.td
index 41d1ed9937aedf08ff4bce0f96133f9afc09f4fd..b61ed92650101774718bc9a8eea5bcad7703235b 100644 (file)
--- a/include/llvm/Target/GenericOpcodes.td
+++ b/include/llvm/Target/GenericOpcodes.td
@@ -579,13 +579,6 @@ def G_FSQRT : GenericInstruction {
   let hasSideEffects = 0;
 }
 
-// Floating point floor of a value.
-def G_FFLOOR : GenericInstruction {
-  let OutOperandList = (outs type0:$dst);
-  let InOperandList = (ins type0:$src1);
-  let hasSideEffects = 0;
-}
-
 //------------------------------------------------------------------------------
 // Opcodes for LLVM Intrinsics
 //------------------------------------------------------------------------------

diff --git a/include/llvm/Target/GlobalISel/SelectionDAGCompat.td b/include/llvm/Target/GlobalISel/SelectionDAGCompat.td
index 6b0434a0758cd44bacbc96d6dcdc2f310e47a0cc..cbda4ab86a504fed662f6f835aca0c7ef8ab5a75 100644 (file)
--- a/include/llvm/Target/GlobalISel/SelectionDAGCompat.td
+++ b/include/llvm/Target/GlobalISel/SelectionDAGCompat.td
@@ -93,7 +93,6 @@ def : GINodeEquiv<G_FCOS, fcos>;
 def : GINodeEquiv<G_FSIN, fsin>;
 def : GINodeEquiv<G_FABS, fabs>;
 def : GINodeEquiv<G_FSQRT, fsqrt>;
-def : GINodeEquiv<G_FFLOOR, ffloor>;
 
 // Broadly speaking G_LOAD is equivalent to ISD::LOAD but there are some
 // complications that tablegen must take care of. For example, Predicates such

diff --git a/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir b/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
index ab144eedfacc26d1626b76f304db70a7430d3f57..09574f0b85d4db66b0222e5b81102708820925ce 100644 (file)
--- a/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
+++ b/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
@@ -340,10 +340,7 @@
 # DEBUG: .. the first uncovered type index: 1, OK
 #
 # DEBUG-NEXT: G_FSQRT (opcode {{[0-9]+}}): 1 type index
-# DEBUG: .. type index coverage check SKIPPED: user-defined predicate detected
-#
-# DEBUG-NEXT: G_FFLOOR (opcode {{[0-9]+}}): 1 type index
-# DEBUG: .. type index coverage check SKIPPED: no rules defined
+# DEBUG: .. the first uncovered type index: 1, OK
 
 # CHECK-NOT: ill-defined