chore(spi): fix the terms of native to iomux

diff --git a/components/driver/include/driver/spi_common.h b/components/driver/include/driver/spi_common.h
index 9f014d2792b74ec1bd661ea16645ad364ddb4ede..d81a9430b74c387dfdf328db23e80fca32d8de28 100644 (file)
--- a/components/driver/include/driver/spi_common.h
+++ b/components/driver/include/driver/spi_common.h
@@ -100,11 +100,9 @@ bool spicommon_dma_chan_claim(int dma_chan);
  */
 bool spicommon_dma_chan_free(int dma_chan);
 
-
-
 #define SPICOMMON_BUSFLAG_SLAVE         0          ///< Initialize I/O in slave mode
 #define SPICOMMON_BUSFLAG_MASTER        (1<<0)     ///< Initialize I/O in master mode
-#define SPICOMMON_BUSFLAG_NATIVE_PINS   (1<<1)     ///< Check using native pins. Or indicates the pins are configured through the IO mux rather than GPIO matrix.
+#define SPICOMMON_BUSFLAG_NATIVE_PINS   (1<<1)     ///< Check using iomux pins. Or indicates the pins are configured through the IO mux rather than GPIO matrix.
 #define SPICOMMON_BUSFLAG_SCLK          (1<<2)     ///< Check existing of SCLK pin. Or indicates CLK line initialized.
 #define SPICOMMON_BUSFLAG_MISO          (1<<3)     ///< Check existing of MISO pin. Or indicates MISO line initialized.
 #define SPICOMMON_BUSFLAG_MOSI          (1<<4)     ///< Check existing of MOSI pin. Or indicates CLK line initialized.
@@ -125,7 +123,7 @@ bool spicommon_dma_chan_free(int dma_chan);
  * @param flags Combination of SPICOMMON_BUSFLAG_* flags, set to ensure the pins set are capable with some functions:
  *              - ``SPICOMMON_BUSFLAG_MASTER``: Initialize I/O in master mode
  *              - ``SPICOMMON_BUSFLAG_SLAVE``: Initialize I/O in slave mode
- *              - ``SPICOMMON_BUSFLAG_NATIVE_PINS``: Pins set should match the native pins of the controller.
+ *              - ``SPICOMMON_BUSFLAG_NATIVE_PINS``: Pins set should match the iomux pins of the controller.
  *              - ``SPICOMMON_BUSFLAG_SCLK``, ``SPICOMMON_BUSFLAG_MISO``, ``SPICOMMON_BUSFLAG_MOSI``: 
  *                  Make sure SCLK/MISO/MOSI is/are set to a valid GPIO. Also check output capability according to the mode.
  *              - ``SPICOMMON_BUSFLAG_DUAL``: Make sure both MISO and MOSI are output capable so that DIO mode is capable.
@@ -133,7 +131,7 @@ bool spicommon_dma_chan_free(int dma_chan);
  *              - ``SPICOMMON_BUSFLAG_QUAD``: Combination of ``SPICOMMON_BUSFLAG_DUAL`` and ``SPICOMMON_BUSFLAG_WPHD``.
  * @param[out] flags_o A SPICOMMON_BUSFLAG_* flag combination of bus abilities will be written to this address.
  *              Leave to NULL if not needed.
- *              - ``SPICOMMON_BUSFLAG_NATIVE_PINS``: The bus is connected to native pins.
+ *              - ``SPICOMMON_BUSFLAG_NATIVE_PINS``: The bus is connected to iomux pins.
  *              - ``SPICOMMON_BUSFLAG_SCLK``, ``SPICOMMON_BUSFLAG_MISO``, ``SPICOMMON_BUSFLAG_MOSI``: The bus has
  *                  CLK/MISO/MOSI connected.
  *              - ``SPICOMMON_BUSFLAG_DUAL``: The bus is capable with DIO mode.

diff --git a/components/driver/include/driver/spi_master.h b/components/driver/include/driver/spi_master.h
index a882336941d1b6f0f82b318372ce181933af9833..4e64c404edde9d3dc850e67a6b5bc9b2d5e0eab7 100644 (file)
--- a/components/driver/include/driver/spi_master.h
+++ b/components/driver/include/driver/spi_master.h
@@ -48,7 +48,7 @@ extern "C"
 #define SPI_DEVICE_POSITIVE_CS             (1<<3)  ///< Make CS positive during a transaction instead of negative
 #define SPI_DEVICE_HALFDUPLEX              (1<<4)  ///< Transmit data before receiving it, instead of simultaneously
 #define SPI_DEVICE_CLK_AS_CS               (1<<5)  ///< Output clock on CS line if CS is active
-/** There are timing issue when reading at high frequency (the frequency is related to whether native pins are used, valid time after slave sees the clock).
+/** There are timing issue when reading at high frequency (the frequency is related to whether iomux pins are used, valid time after slave sees the clock).
   *     - In half-duplex mode, the driver automatically inserts dummy bits before reading phase to fix the timing issue. Set this flag to disable this feature.
   *     - In full-duplex mode, however, the hardware cannot use dummy bits, so there is no way to prevent data being read from getting corrupted.
   *       Set this flag to confirm that you're going to work with output only, or read without dummy bits at your own risk.
@@ -274,7 +274,7 @@ int spi_cal_clock(int fapb, int hz, int duty_cycle, uint32_t* reg_o);
 /**
   * @brief Calculate the timing settings of specified frequency and settings.
   *
-  * @param gpio_is_used True if using GPIO matrix, or False if native pins are used.
+  * @param gpio_is_used True if using GPIO matrix, or False if iomux pins are used.
   * @param input_delay_ns Input delay from SCLK launch edge to MISO data valid.
   * @param eff_clk Effective clock frequency (in Hz) from spi_cal_clock.
   * @param dummy_o Address of dummy bits used output. Set to NULL if not needed.

diff --git a/components/driver/spi_common.c b/components/driver/spi_common.c
index 52f239af3bb1c097d03866c2ff7770c685f5e980..a605f144ccf0525099aef6e43aadb6743ad63617 100644 (file)
--- a/components/driver/spi_common.c
+++ b/components/driver/spi_common.c
@@ -65,12 +65,12 @@ typedef struct {
     const uint8_t spihd_in;
     const uint8_t spics_out[3];     // /CS GPIO output mux signals
     const uint8_t spics_in;
-    const uint8_t spiclk_native;    //IO pins of IO_MUX muxed signals
-    const uint8_t spid_native;
-    const uint8_t spiq_native;
-    const uint8_t spiwp_native;
-    const uint8_t spihd_native;
-    const uint8_t spics0_native;
+    const uint8_t spiclk_iomux_pin;    //IO pins of IO_MUX muxed signals
+    const uint8_t spid_iomux_pin;
+    const uint8_t spiq_iomux_pin;
+    const uint8_t spiwp_iomux_pin;
+    const uint8_t spihd_iomux_pin;
+    const uint8_t spics0_iomux_pin;
     const uint8_t irq;              //irq source for interrupt mux
     const uint8_t irq_dma;          //dma irq source for interrupt mux
     const periph_module_t module;   //peripheral module, for enabling clock etc
@@ -94,12 +94,12 @@ static const spi_signal_conn_t io_signal[3] = {
         .spihd_in = SPIHD_IN_IDX,
         .spics_out = {SPICS0_OUT_IDX, SPICS1_OUT_IDX, SPICS2_OUT_IDX},
         .spics_in = SPICS0_IN_IDX,
-        .spiclk_native = 6,
-        .spid_native = 8,
-        .spiq_native = 7,
-        .spiwp_native = 10,
-        .spihd_native = 9,
-        .spics0_native = 11,
+        .spiclk_iomux_pin = 6,
+        .spid_iomux_pin = 8,
+        .spiq_iomux_pin = 7,
+        .spiwp_iomux_pin = 10,
+        .spihd_iomux_pin = 9,
+        .spics0_iomux_pin = 11,
         .irq = ETS_SPI1_INTR_SOURCE,
         .irq_dma = ETS_SPI1_DMA_INTR_SOURCE,
         .module = PERIPH_SPI_MODULE,
@@ -117,12 +117,12 @@ static const spi_signal_conn_t io_signal[3] = {
         .spihd_in = HSPIHD_IN_IDX,
         .spics_out = {HSPICS0_OUT_IDX, HSPICS1_OUT_IDX, HSPICS2_OUT_IDX},
         .spics_in = HSPICS0_IN_IDX,
-        .spiclk_native = 14,
-        .spid_native = 13,
-        .spiq_native = 12,
-        .spiwp_native = 2,
-        .spihd_native = 4,
-        .spics0_native = 15,
+        .spiclk_iomux_pin = 14,
+        .spid_iomux_pin = 13,
+        .spiq_iomux_pin = 12,
+        .spiwp_iomux_pin = 2,
+        .spihd_iomux_pin = 4,
+        .spics0_iomux_pin = 15,
         .irq = ETS_SPI2_INTR_SOURCE,
         .irq_dma = ETS_SPI2_DMA_INTR_SOURCE,
         .module = PERIPH_HSPI_MODULE,
@@ -140,12 +140,12 @@ static const spi_signal_conn_t io_signal[3] = {
         .spihd_in = VSPIHD_IN_IDX,
         .spics_out = {VSPICS0_OUT_IDX, VSPICS1_OUT_IDX, VSPICS2_OUT_IDX},
         .spics_in = VSPICS0_IN_IDX,
-        .spiclk_native = 18,
-        .spid_native = 23,
-        .spiq_native = 19,
-        .spiwp_native = 22,
-        .spihd_native = 21,
-        .spics0_native = 5,
+        .spiclk_iomux_pin = 18,
+        .spid_iomux_pin = 23,
+        .spiq_iomux_pin = 19,
+        .spiwp_iomux_pin = 22,
+        .spihd_iomux_pin = 21,
+        .spics0_iomux_pin = 5,
         .irq = ETS_SPI3_INTR_SOURCE,
         .irq_dma = ETS_SPI3_DMA_INTR_SOURCE,
         .module = PERIPH_VSPI_MODULE,
@@ -228,7 +228,7 @@ it should be able to be initialized.
 */
 esp_err_t spicommon_bus_initialize_io(spi_host_device_t host, const spi_bus_config_t *bus_config, int dma_chan, uint32_t flags, uint32_t* flags_o)
 {
-    bool native = true;
+    bool use_iomux = true;
     uint32_t temp_flag=0;
     bool quad_pins_exist = true;
     //the MISO should be output capable in slave mode, or in DIO/QIO mode.
@@ -236,24 +236,24 @@ esp_err_t spicommon_bus_initialize_io(spi_host_device_t host, const spi_bus_conf
     //the MOSI should be output capble in master mode, or in DIO/QIO mode.
     bool mosi_output = (flags&SPICOMMON_BUSFLAG_MASTER)!=0 || flags&SPICOMMON_BUSFLAG_DUAL;
 
-    //check pins existence and if the selected pins correspond to the native pins of the peripheral
+    //check pins existence and if the selected pins correspond to the iomux pins of the peripheral
     if (bus_config->sclk_io_num>=0) {
         temp_flag |= SPICOMMON_BUSFLAG_SCLK;
         SPI_CHECK(GPIO_IS_VALID_OUTPUT_GPIO(bus_config->sclk_io_num), "sclk not valid", ESP_ERR_INVALID_ARG);
-        if (bus_config->sclk_io_num != io_signal[host].spiclk_native) native = false;
+        if (bus_config->sclk_io_num != io_signal[host].spiclk_iomux_pin) use_iomux = false;
     } else {
         SPI_CHECK((flags&SPICOMMON_BUSFLAG_SCLK)==0, "sclk pin required.", ESP_ERR_INVALID_ARG);
     }
     if (bus_config->quadwp_io_num>=0) {
         SPI_CHECK(GPIO_IS_VALID_OUTPUT_GPIO(bus_config->quadwp_io_num), "spiwp not valid", ESP_ERR_INVALID_ARG);
-        if (bus_config->quadwp_io_num != io_signal[host].spiwp_native) native = false;
+        if (bus_config->quadwp_io_num != io_signal[host].spiwp_iomux_pin) use_iomux = false;
     } else {
         quad_pins_exist = false;
         SPI_CHECK((flags&SPICOMMON_BUSFLAG_WPHD)==0, "spiwp pin required.", ESP_ERR_INVALID_ARG);
     }
     if (bus_config->quadhd_io_num>=0) {
         SPI_CHECK(GPIO_IS_VALID_OUTPUT_GPIO(bus_config->quadhd_io_num), "spihd not valid", ESP_ERR_INVALID_ARG);
-        if (bus_config->quadhd_io_num != io_signal[host].spihd_native) native = false;
+        if (bus_config->quadhd_io_num != io_signal[host].spihd_iomux_pin) use_iomux = false;
     } else {
         quad_pins_exist = false;
         SPI_CHECK((flags&SPICOMMON_BUSFLAG_WPHD)==0, "spihd pin required.", ESP_ERR_INVALID_ARG);
@@ -265,7 +265,7 @@ esp_err_t spicommon_bus_initialize_io(spi_host_device_t host, const spi_bus_conf
         } else {
             SPI_CHECK(GPIO_IS_VALID_GPIO(bus_config->mosi_io_num), "mosi not valid", ESP_ERR_INVALID_ARG);
         }
-        if (bus_config->mosi_io_num != io_signal[host].spid_native) native = false;
+        if (bus_config->mosi_io_num != io_signal[host].spid_iomux_pin) use_iomux = false;
     } else {
         SPI_CHECK((flags&SPICOMMON_BUSFLAG_MOSI)==0, "mosi pin required.", ESP_ERR_INVALID_ARG);
     }
@@ -276,7 +276,7 @@ esp_err_t spicommon_bus_initialize_io(spi_host_device_t host, const spi_bus_conf
         } else {
             SPI_CHECK(GPIO_IS_VALID_GPIO(bus_config->miso_io_num), "miso not valid", ESP_ERR_INVALID_ARG);
         }
-        if (bus_config->miso_io_num != io_signal[host].spiq_native) native = false;
+        if (bus_config->miso_io_num != io_signal[host].spiq_iomux_pin) use_iomux = false;
     } else {
         SPI_CHECK((flags&SPICOMMON_BUSFLAG_MISO)==0, "miso pin required.", ESP_ERR_INVALID_ARG);
     }
@@ -287,13 +287,13 @@ esp_err_t spicommon_bus_initialize_io(spi_host_device_t host, const spi_bus_conf
     }
     //set flags for QUAD mode according to the existence of wp and hd
     if (quad_pins_exist) temp_flag |= SPICOMMON_BUSFLAG_WPHD;
-    //check native pins if required.
-    SPI_CHECK((flags&SPICOMMON_BUSFLAG_NATIVE_PINS)==0 || native, "not using native pins", ESP_ERR_INVALID_ARG);
+    //check iomux pins if required.
+    SPI_CHECK((flags&SPICOMMON_BUSFLAG_NATIVE_PINS)==0 || use_iomux, "not using iomux pins", ESP_ERR_INVALID_ARG);
 
-    if (native) {
-        //All SPI native pin selections resolve to 1, so we put that here instead of trying to figure
+    if (use_iomux) {
+        //All SPI iomux pin selections resolve to 1, so we put that here instead of trying to figure
         //out which FUNC_GPIOx_xSPIxx to grab; they all are defined to 1 anyway.
-        ESP_LOGD(SPI_TAG, "SPI%d use native pins.", host );
+        ESP_LOGD(SPI_TAG, "SPI%d use iomux pins.", host );
         if (bus_config->mosi_io_num >= 0) {
             gpio_iomux_in(bus_config->mosi_io_num, io_signal[host].spid_in);
             gpio_iomux_out(bus_config->mosi_io_num, FUNC_SPI, false);
@@ -378,11 +378,11 @@ static void reset_func_to_gpio(int func)
 
 esp_err_t spicommon_bus_free_io(spi_host_device_t host)
 {
-    if (REG_GET_FIELD(GPIO_PIN_MUX_REG[io_signal[host].spid_native], MCU_SEL) == 1) PIN_FUNC_SELECT(GPIO_PIN_MUX_REG[io_signal[host].spid_native], PIN_FUNC_GPIO);
-    if (REG_GET_FIELD(GPIO_PIN_MUX_REG[io_signal[host].spiq_native], MCU_SEL) == 1) PIN_FUNC_SELECT(GPIO_PIN_MUX_REG[io_signal[host].spiq_native], PIN_FUNC_GPIO);
-    if (REG_GET_FIELD(GPIO_PIN_MUX_REG[io_signal[host].spiclk_native], MCU_SEL) == 1) PIN_FUNC_SELECT(GPIO_PIN_MUX_REG[io_signal[host].spiclk_native], PIN_FUNC_GPIO);
-    if (REG_GET_FIELD(GPIO_PIN_MUX_REG[io_signal[host].spiwp_native], MCU_SEL) == 1) PIN_FUNC_SELECT(GPIO_PIN_MUX_REG[io_signal[host].spiwp_native], PIN_FUNC_GPIO);
-    if (REG_GET_FIELD(GPIO_PIN_MUX_REG[io_signal[host].spihd_native], MCU_SEL) == 1) PIN_FUNC_SELECT(GPIO_PIN_MUX_REG[io_signal[host].spihd_native], PIN_FUNC_GPIO);
+    if (REG_GET_FIELD(GPIO_PIN_MUX_REG[io_signal[host].spid_iomux_pin], MCU_SEL) == 1) PIN_FUNC_SELECT(GPIO_PIN_MUX_REG[io_signal[host].spid_iomux_pin], PIN_FUNC_GPIO);
+    if (REG_GET_FIELD(GPIO_PIN_MUX_REG[io_signal[host].spiq_iomux_pin], MCU_SEL) == 1) PIN_FUNC_SELECT(GPIO_PIN_MUX_REG[io_signal[host].spiq_iomux_pin], PIN_FUNC_GPIO);
+    if (REG_GET_FIELD(GPIO_PIN_MUX_REG[io_signal[host].spiclk_iomux_pin], MCU_SEL) == 1) PIN_FUNC_SELECT(GPIO_PIN_MUX_REG[io_signal[host].spiclk_iomux_pin], PIN_FUNC_GPIO);
+    if (REG_GET_FIELD(GPIO_PIN_MUX_REG[io_signal[host].spiwp_iomux_pin], MCU_SEL) == 1) PIN_FUNC_SELECT(GPIO_PIN_MUX_REG[io_signal[host].spiwp_iomux_pin], PIN_FUNC_GPIO);
+    if (REG_GET_FIELD(GPIO_PIN_MUX_REG[io_signal[host].spihd_iomux_pin], MCU_SEL) == 1) PIN_FUNC_SELECT(GPIO_PIN_MUX_REG[io_signal[host].spihd_iomux_pin], PIN_FUNC_GPIO);
     reset_func_to_gpio(io_signal[host].spid_out);
     reset_func_to_gpio(io_signal[host].spiq_out);
     reset_func_to_gpio(io_signal[host].spiclk_out);
@@ -393,7 +393,7 @@ esp_err_t spicommon_bus_free_io(spi_host_device_t host)
 
 void spicommon_cs_initialize(spi_host_device_t host, int cs_io_num, int cs_num, int force_gpio_matrix)
 {
-    if (!force_gpio_matrix && cs_io_num == io_signal[host].spics0_native && cs_num == 0) {
+    if (!force_gpio_matrix && cs_io_num == io_signal[host].spics0_iomux_pin && cs_num == 0) {
         //The cs0s for all SPI peripherals map to pin mux source 1, so we use that instead of a define.
         gpio_iomux_in(cs_io_num, io_signal[host].spics_in);
         gpio_iomux_out(cs_io_num, FUNC_SPI, false);
@@ -407,8 +407,8 @@ void spicommon_cs_initialize(spi_host_device_t host, int cs_io_num, int cs_num,
 
 void spicommon_cs_free(spi_host_device_t host, int cs_io_num)
 {
-    if (cs_io_num == 0 && REG_GET_FIELD(GPIO_PIN_MUX_REG[io_signal[host].spics0_native], MCU_SEL) == 1) {
-        PIN_FUNC_SELECT(GPIO_PIN_MUX_REG[io_signal[host].spics0_native], PIN_FUNC_GPIO);
+    if (cs_io_num == 0 && REG_GET_FIELD(GPIO_PIN_MUX_REG[io_signal[host].spics0_iomux_pin], MCU_SEL) == 1) {
+        PIN_FUNC_SELECT(GPIO_PIN_MUX_REG[io_signal[host].spics0_iomux_pin], PIN_FUNC_GPIO);
     }
     reset_func_to_gpio(io_signal[host].spics_out[cs_io_num]);
 }

diff --git a/components/driver/spi_master.c b/components/driver/spi_master.c
index e070ba9c6603061816a626f7d736b319145df8e1..02cb88455f12c1a82920ed4e3ad0e4204acb2c1c 100644 (file)
--- a/components/driver/spi_master.c
+++ b/components/driver/spi_master.c
@@ -324,7 +324,7 @@ esp_err_t spi_bus_add_device(spi_host_device_t host, const spi_device_interface_
     eff_clk = spi_cal_clock(apbclk, dev_config->clock_speed_hz, duty_cycle, (uint32_t*)&clk_reg);
     int freq_limit = spi_get_freq_limit(!(spihost[host]->flags&SPICOMMON_BUSFLAG_NATIVE_PINS), dev_config->input_delay_ns);
     //GPIO matrix can only change data at 80Mhz rate, which only allows 40MHz SPI clock.
-    SPI_CHECK(eff_clk <= 40*1000*1000 || spihost[host]->flags&SPICOMMON_BUSFLAG_NATIVE_PINS, "80MHz only supported on native pins", ESP_ERR_INVALID_ARG);
+    SPI_CHECK(eff_clk <= 40*1000*1000 || spihost[host]->flags&SPICOMMON_BUSFLAG_NATIVE_PINS, "80MHz only supported on iomux pins", ESP_ERR_INVALID_ARG);
     //Speed >=40MHz over GPIO matrix needs a dummy cycle, but these don't work for full-duplex connections.
     spi_get_timing(!(spihost[host]->flags&SPICOMMON_BUSFLAG_NATIVE_PINS), dev_config->input_delay_ns, eff_clk, &dummy_required, &miso_delay);
     SPI_CHECK( dev_config->flags & SPI_DEVICE_HALFDUPLEX || dummy_required == 0 ||

diff --git a/components/driver/test/test_spi_master.c b/components/driver/test/test_spi_master.c
index 8dcb6210e0e69aa856f1a96e28354ec0ba75a081..64b3544baa80a6cba554de508a06ed7d4594141e 100644 (file)
--- a/components/driver/test/test_spi_master.c
+++ b/components/driver/test/test_spi_master.c
@@ -294,30 +294,24 @@ TEST_CASE("SPI Master test, interaction of multiple devs", "[spi][ignore]") {
     destroy_spi_bus(handle1);
 }
 
-#define NATIVE_SCLK 14
-#define NATIVE_MISO 12
-#define NATIVE_MOSI 13
-#define NATIVE_WP   2
-#define NATIVE_HD   4
-
 TEST_CASE("spi bus setting with different pin configs", "[spi]")
 {
     spi_bus_config_t cfg;
     uint32_t flags_o;
     uint32_t flags_expected;
 
-    ESP_LOGI(TAG, "test 6 native output pins...");
+    ESP_LOGI(TAG, "test 6 iomux output pins...");
     flags_expected = SPICOMMON_BUSFLAG_SCLK | SPICOMMON_BUSFLAG_MOSI | SPICOMMON_BUSFLAG_MISO | SPICOMMON_BUSFLAG_NATIVE_PINS | SPICOMMON_BUSFLAG_QUAD;
-    cfg = (spi_bus_config_t){.mosi_io_num = NATIVE_MOSI, .miso_io_num = NATIVE_MISO, .sclk_io_num = NATIVE_SCLK, .quadhd_io_num = NATIVE_HD, .quadwp_io_num = NATIVE_WP,
+    cfg = (spi_bus_config_t){.mosi_io_num = HSPI_IOMUX_PIN_NUM_MOSI, .miso_io_num = HSPI_IOMUX_PIN_NUM_MISO, .sclk_io_num = HSPI_IOMUX_PIN_NUM_CLK, .quadhd_io_num = HSPI_IOMUX_PIN_NUM_HD, .quadwp_io_num = HSPI_IOMUX_PIN_NUM_WP,
         .max_transfer_sz = 8, .flags = flags_expected};
     TEST_ESP_OK(spicommon_bus_initialize_io(HSPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_MASTER, &flags_o));
     TEST_ASSERT_EQUAL_HEX32( flags_expected, flags_o );
     TEST_ESP_OK(spicommon_bus_initialize_io(HSPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_SLAVE, &flags_o));
     TEST_ASSERT_EQUAL_HEX32( flags_expected, flags_o );
 
-    ESP_LOGI(TAG, "test 4 native output pins...");
+    ESP_LOGI(TAG, "test 4 iomux output pins...");
     flags_expected = SPICOMMON_BUSFLAG_SCLK | SPICOMMON_BUSFLAG_MOSI | SPICOMMON_BUSFLAG_MISO | SPICOMMON_BUSFLAG_NATIVE_PINS | SPICOMMON_BUSFLAG_DUAL;
-    cfg = (spi_bus_config_t){.mosi_io_num = NATIVE_MOSI, .miso_io_num = NATIVE_MISO, .sclk_io_num = NATIVE_SCLK, .quadhd_io_num = -1, .quadwp_io_num = -1,
+    cfg = (spi_bus_config_t){.mosi_io_num = HSPI_IOMUX_PIN_NUM_MOSI, .miso_io_num = HSPI_IOMUX_PIN_NUM_MISO, .sclk_io_num = HSPI_IOMUX_PIN_NUM_CLK, .quadhd_io_num = -1, .quadwp_io_num = -1,
         .max_transfer_sz = 8, .flags = flags_expected};
     TEST_ESP_OK(spicommon_bus_initialize_io(HSPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_MASTER, &flags_o));
     TEST_ASSERT_EQUAL_HEX32( flags_expected, flags_o );
@@ -327,7 +321,7 @@ TEST_CASE("spi bus setting with different pin configs", "[spi]")
     ESP_LOGI(TAG, "test 6 output pins...");
     flags_expected = SPICOMMON_BUSFLAG_SCLK | SPICOMMON_BUSFLAG_MOSI | SPICOMMON_BUSFLAG_MISO | SPICOMMON_BUSFLAG_QUAD;
     //swap MOSI and MISO
-    cfg = (spi_bus_config_t){.mosi_io_num = NATIVE_MISO, .miso_io_num = NATIVE_MOSI, .sclk_io_num = NATIVE_SCLK, .quadhd_io_num = NATIVE_HD, .quadwp_io_num = NATIVE_WP,
+    cfg = (spi_bus_config_t){.mosi_io_num = HSPI_IOMUX_PIN_NUM_MISO, .miso_io_num = HSPI_IOMUX_PIN_NUM_MOSI, .sclk_io_num = HSPI_IOMUX_PIN_NUM_CLK, .quadhd_io_num = HSPI_IOMUX_PIN_NUM_HD, .quadwp_io_num = HSPI_IOMUX_PIN_NUM_WP,
         .max_transfer_sz = 8, .flags = flags_expected};
     TEST_ESP_OK(spicommon_bus_initialize_io(HSPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_MASTER, &flags_o));
     TEST_ASSERT_EQUAL_HEX32( flags_expected, flags_o );
@@ -337,7 +331,7 @@ TEST_CASE("spi bus setting with different pin configs", "[spi]")
     ESP_LOGI(TAG, "test 4 output pins...");
     flags_expected = SPICOMMON_BUSFLAG_SCLK | SPICOMMON_BUSFLAG_MOSI | SPICOMMON_BUSFLAG_MISO |  SPICOMMON_BUSFLAG_DUAL;
     //swap MOSI and MISO
-    cfg = (spi_bus_config_t){.mosi_io_num = NATIVE_MISO, .miso_io_num = NATIVE_MOSI, .sclk_io_num = NATIVE_SCLK, .quadhd_io_num = -1, .quadwp_io_num = -1,
+    cfg = (spi_bus_config_t){.mosi_io_num = HSPI_IOMUX_PIN_NUM_MISO, .miso_io_num = HSPI_IOMUX_PIN_NUM_MOSI, .sclk_io_num = HSPI_IOMUX_PIN_NUM_CLK, .quadhd_io_num = -1, .quadwp_io_num = -1,
         .max_transfer_sz = 8, .flags = flags_expected};
     TEST_ESP_OK(spicommon_bus_initialize_io(HSPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_MASTER, &flags_o));
     TEST_ASSERT_EQUAL_HEX32( flags_expected, flags_o );
@@ -346,14 +340,14 @@ TEST_CASE("spi bus setting with different pin configs", "[spi]")
 
     ESP_LOGI(TAG, "test master 5 output pins and MOSI on input-only pin...");
     flags_expected = SPICOMMON_BUSFLAG_SCLK | SPICOMMON_BUSFLAG_MOSI | SPICOMMON_BUSFLAG_MISO | SPICOMMON_BUSFLAG_WPHD;
-    cfg = (spi_bus_config_t){.mosi_io_num = NATIVE_MOSI, .miso_io_num = 34, .sclk_io_num = NATIVE_SCLK, .quadhd_io_num = NATIVE_HD, .quadwp_io_num = NATIVE_WP,
+    cfg = (spi_bus_config_t){.mosi_io_num = HSPI_IOMUX_PIN_NUM_MOSI, .miso_io_num = 34, .sclk_io_num = HSPI_IOMUX_PIN_NUM_CLK, .quadhd_io_num = HSPI_IOMUX_PIN_NUM_HD, .quadwp_io_num = HSPI_IOMUX_PIN_NUM_WP,
         .max_transfer_sz = 8, .flags = flags_expected};
     TEST_ESP_OK(spicommon_bus_initialize_io(HSPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_MASTER, &flags_o));
     TEST_ASSERT_EQUAL_HEX32( flags_expected, flags_o );
 
     ESP_LOGI(TAG, "test slave 5 output pins and MISO on input-only pin...");
     flags_expected = SPICOMMON_BUSFLAG_SCLK | SPICOMMON_BUSFLAG_MOSI | SPICOMMON_BUSFLAG_MISO | SPICOMMON_BUSFLAG_WPHD;
-    cfg = (spi_bus_config_t){.mosi_io_num = 34, .miso_io_num = NATIVE_MISO, .sclk_io_num = NATIVE_SCLK, .quadhd_io_num = NATIVE_HD, .quadwp_io_num = NATIVE_WP,
+    cfg = (spi_bus_config_t){.mosi_io_num = 34, .miso_io_num = HSPI_IOMUX_PIN_NUM_MISO, .sclk_io_num = HSPI_IOMUX_PIN_NUM_CLK, .quadhd_io_num = HSPI_IOMUX_PIN_NUM_HD, .quadwp_io_num = HSPI_IOMUX_PIN_NUM_WP,
         .max_transfer_sz = 8, .flags = flags_expected};
     TEST_ESP_OK(spicommon_bus_initialize_io(HSPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_SLAVE, &flags_o));
     TEST_ASSERT_EQUAL_HEX32( flags_expected, flags_o );
@@ -361,14 +355,14 @@ TEST_CASE("spi bus setting with different pin configs", "[spi]")
     ESP_LOGI(TAG, "test master 3 output pins and MOSI on input-only pin...");
     flags_expected = SPICOMMON_BUSFLAG_SCLK | SPICOMMON_BUSFLAG_MOSI | SPICOMMON_BUSFLAG_MISO;
 
-    cfg = (spi_bus_config_t){.mosi_io_num = NATIVE_MOSI, .miso_io_num = 34, .sclk_io_num = NATIVE_SCLK, .quadhd_io_num = -1, .quadwp_io_num = -1,
+    cfg = (spi_bus_config_t){.mosi_io_num = HSPI_IOMUX_PIN_NUM_MOSI, .miso_io_num = 34, .sclk_io_num = HSPI_IOMUX_PIN_NUM_CLK, .quadhd_io_num = -1, .quadwp_io_num = -1,
         .max_transfer_sz = 8, .flags = flags_expected};
     TEST_ESP_OK(spicommon_bus_initialize_io(HSPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_MASTER, &flags_o));
     TEST_ASSERT_EQUAL_HEX32( flags_expected, flags_o );
 
     ESP_LOGI(TAG, "test slave 3 output pins and MISO on input-only pin...");
     flags_expected = SPICOMMON_BUSFLAG_SCLK | SPICOMMON_BUSFLAG_MOSI | SPICOMMON_BUSFLAG_MISO;
-    cfg = (spi_bus_config_t){.mosi_io_num = 34, .miso_io_num = NATIVE_MISO, .sclk_io_num = NATIVE_SCLK, .quadhd_io_num = -1, .quadwp_io_num = -1,
+    cfg = (spi_bus_config_t){.mosi_io_num = 34, .miso_io_num = HSPI_IOMUX_PIN_NUM_MISO, .sclk_io_num = HSPI_IOMUX_PIN_NUM_CLK, .quadhd_io_num = -1, .quadwp_io_num = -1,
         .max_transfer_sz = 8, .flags = flags_expected};
     TEST_ESP_OK(spicommon_bus_initialize_io(HSPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_SLAVE, &flags_o));
     TEST_ASSERT_EQUAL_HEX32( flags_expected, flags_o );
@@ -376,7 +370,7 @@ TEST_CASE("spi bus setting with different pin configs", "[spi]")
     ESP_LOGI(TAG, "check native flag for 6 output pins...");
     flags_expected = SPICOMMON_BUSFLAG_NATIVE_PINS;
     //swap MOSI and MISO
-    cfg = (spi_bus_config_t){.mosi_io_num = NATIVE_MISO, .miso_io_num = NATIVE_MOSI, .sclk_io_num = NATIVE_SCLK, .quadhd_io_num = NATIVE_HD, .quadwp_io_num = NATIVE_WP,
+    cfg = (spi_bus_config_t){.mosi_io_num = HSPI_IOMUX_PIN_NUM_MISO, .miso_io_num = HSPI_IOMUX_PIN_NUM_MOSI, .sclk_io_num = HSPI_IOMUX_PIN_NUM_CLK, .quadhd_io_num = HSPI_IOMUX_PIN_NUM_HD, .quadwp_io_num = HSPI_IOMUX_PIN_NUM_WP,
         .max_transfer_sz = 8, .flags = flags_expected};
     TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(HSPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_MASTER, &flags_o));
     TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(HSPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_SLAVE, &flags_o));
@@ -384,61 +378,61 @@ TEST_CASE("spi bus setting with different pin configs", "[spi]")
     ESP_LOGI(TAG, "check native flag for 4 output pins...");
     flags_expected = SPICOMMON_BUSFLAG_NATIVE_PINS;
     //swap MOSI and MISO
-    cfg = (spi_bus_config_t){.mosi_io_num = NATIVE_MISO, .miso_io_num = NATIVE_MOSI, .sclk_io_num = NATIVE_SCLK, .quadhd_io_num = -1, .quadwp_io_num = -1,
+    cfg = (spi_bus_config_t){.mosi_io_num = HSPI_IOMUX_PIN_NUM_MISO, .miso_io_num = HSPI_IOMUX_PIN_NUM_MOSI, .sclk_io_num = HSPI_IOMUX_PIN_NUM_CLK, .quadhd_io_num = -1, .quadwp_io_num = -1,
         .max_transfer_sz = 8, .flags = flags_expected};
     TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(HSPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_MASTER, &flags_o));
     TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(HSPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_SLAVE, &flags_o));
 
     ESP_LOGI(TAG, "check dual flag for master 5 output pins and MISO/MOSI on input-only pin...");
     flags_expected = SPICOMMON_BUSFLAG_DUAL;
-    cfg = (spi_bus_config_t){.mosi_io_num = NATIVE_MOSI, .miso_io_num = 34, .sclk_io_num = NATIVE_SCLK, .quadhd_io_num = NATIVE_HD, .quadwp_io_num = NATIVE_WP,
+    cfg = (spi_bus_config_t){.mosi_io_num = HSPI_IOMUX_PIN_NUM_MOSI, .miso_io_num = 34, .sclk_io_num = HSPI_IOMUX_PIN_NUM_CLK, .quadhd_io_num = HSPI_IOMUX_PIN_NUM_HD, .quadwp_io_num = HSPI_IOMUX_PIN_NUM_WP,
         .max_transfer_sz = 8, .flags = flags_expected};
     TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(HSPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_MASTER, &flags_o));
     TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(HSPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_SLAVE, &flags_o));
-    cfg = (spi_bus_config_t){.mosi_io_num = 34, .miso_io_num = NATIVE_MISO, .sclk_io_num = NATIVE_SCLK, .quadhd_io_num = NATIVE_HD, .quadwp_io_num = NATIVE_WP,
+    cfg = (spi_bus_config_t){.mosi_io_num = 34, .miso_io_num = HSPI_IOMUX_PIN_NUM_MISO, .sclk_io_num = HSPI_IOMUX_PIN_NUM_CLK, .quadhd_io_num = HSPI_IOMUX_PIN_NUM_HD, .quadwp_io_num = HSPI_IOMUX_PIN_NUM_WP,
         .max_transfer_sz = 8, .flags = flags_expected};
     TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(HSPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_MASTER, &flags_o));
     TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(HSPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_SLAVE, &flags_o));
 
     ESP_LOGI(TAG, "check dual flag for master 3 output pins and MISO/MOSI on input-only pin...");
     flags_expected = SPICOMMON_BUSFLAG_DUAL;
-    cfg = (spi_bus_config_t){.mosi_io_num = NATIVE_MOSI, .miso_io_num = 34, .sclk_io_num = NATIVE_SCLK, .quadhd_io_num = -1, .quadwp_io_num = -1,
+    cfg = (spi_bus_config_t){.mosi_io_num = HSPI_IOMUX_PIN_NUM_MOSI, .miso_io_num = 34, .sclk_io_num = HSPI_IOMUX_PIN_NUM_CLK, .quadhd_io_num = -1, .quadwp_io_num = -1,
         .max_transfer_sz = 8, .flags = flags_expected};
     TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(HSPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_MASTER, &flags_o));
     TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(HSPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_SLAVE, &flags_o));
-    cfg = (spi_bus_config_t){.mosi_io_num = 34, .miso_io_num = NATIVE_MISO, .sclk_io_num = NATIVE_SCLK, .quadhd_io_num = -1, .quadwp_io_num = -1,
+    cfg = (spi_bus_config_t){.mosi_io_num = 34, .miso_io_num = HSPI_IOMUX_PIN_NUM_MISO, .sclk_io_num = HSPI_IOMUX_PIN_NUM_CLK, .quadhd_io_num = -1, .quadwp_io_num = -1,
         .max_transfer_sz = 8, .flags = flags_expected};
     TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(HSPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_MASTER, &flags_o));
     TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(HSPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_SLAVE, &flags_o));
 
     ESP_LOGI(TAG, "check sclk flag...");
     flags_expected = SPICOMMON_BUSFLAG_SCLK;
-    cfg = (spi_bus_config_t){.mosi_io_num = NATIVE_MOSI, .miso_io_num = NATIVE_MISO, .sclk_io_num = -1, .quadhd_io_num = NATIVE_HD, .quadwp_io_num = NATIVE_WP,
+    cfg = (spi_bus_config_t){.mosi_io_num = HSPI_IOMUX_PIN_NUM_MOSI, .miso_io_num = HSPI_IOMUX_PIN_NUM_MISO, .sclk_io_num = -1, .quadhd_io_num = HSPI_IOMUX_PIN_NUM_HD, .quadwp_io_num = HSPI_IOMUX_PIN_NUM_WP,
         .max_transfer_sz = 8, .flags = flags_expected};
     TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(HSPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_MASTER, &flags_o));
     TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(HSPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_SLAVE, &flags_o));
 
     ESP_LOGI(TAG, "check mosi flag...");
     flags_expected = SPICOMMON_BUSFLAG_MOSI;
-    cfg = (spi_bus_config_t){.mosi_io_num = -1, .miso_io_num = NATIVE_MISO, .sclk_io_num = NATIVE_SCLK, .quadhd_io_num = NATIVE_HD, .quadwp_io_num = NATIVE_WP,
+    cfg = (spi_bus_config_t){.mosi_io_num = -1, .miso_io_num = HSPI_IOMUX_PIN_NUM_MISO, .sclk_io_num = HSPI_IOMUX_PIN_NUM_CLK, .quadhd_io_num = HSPI_IOMUX_PIN_NUM_HD, .quadwp_io_num = HSPI_IOMUX_PIN_NUM_WP,
         .max_transfer_sz = 8, .flags = flags_expected};
     TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(HSPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_MASTER, &flags_o));
     TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(HSPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_SLAVE, &flags_o));
 
     ESP_LOGI(TAG, "check miso flag...");
     flags_expected = SPICOMMON_BUSFLAG_MISO;
-    cfg = (spi_bus_config_t){.mosi_io_num = NATIVE_MOSI, .miso_io_num = -1, .sclk_io_num = NATIVE_SCLK, .quadhd_io_num = NATIVE_HD, .quadwp_io_num = NATIVE_WP,
+    cfg = (spi_bus_config_t){.mosi_io_num = HSPI_IOMUX_PIN_NUM_MOSI, .miso_io_num = -1, .sclk_io_num = HSPI_IOMUX_PIN_NUM_CLK, .quadhd_io_num = HSPI_IOMUX_PIN_NUM_HD, .quadwp_io_num = HSPI_IOMUX_PIN_NUM_WP,
         .max_transfer_sz = 8, .flags = flags_expected};
     TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(HSPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_MASTER, &flags_o));
     TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(HSPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_SLAVE, &flags_o));
 
     ESP_LOGI(TAG, "check quad flag...");
     flags_expected = SPICOMMON_BUSFLAG_QUAD;
-    cfg = (spi_bus_config_t){.mosi_io_num = NATIVE_MOSI, .miso_io_num = NATIVE_MISO, .sclk_io_num = NATIVE_SCLK, .quadhd_io_num = -1, .quadwp_io_num = NATIVE_WP,
+    cfg = (spi_bus_config_t){.mosi_io_num = HSPI_IOMUX_PIN_NUM_MOSI, .miso_io_num = HSPI_IOMUX_PIN_NUM_MISO, .sclk_io_num = HSPI_IOMUX_PIN_NUM_CLK, .quadhd_io_num = -1, .quadwp_io_num = HSPI_IOMUX_PIN_NUM_WP,
         .max_transfer_sz = 8, .flags = flags_expected};
     TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(HSPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_MASTER, &flags_o));
     TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(HSPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_SLAVE, &flags_o));
-    cfg = (spi_bus_config_t){.mosi_io_num = NATIVE_MOSI, .miso_io_num = NATIVE_MISO, .sclk_io_num = NATIVE_SCLK, .quadhd_io_num = NATIVE_HD, .quadwp_io_num = -1,
+    cfg = (spi_bus_config_t){.mosi_io_num = HSPI_IOMUX_PIN_NUM_MOSI, .miso_io_num = HSPI_IOMUX_PIN_NUM_MISO, .sclk_io_num = HSPI_IOMUX_PIN_NUM_CLK, .quadhd_io_num = HSPI_IOMUX_PIN_NUM_HD, .quadwp_io_num = -1,
         .max_transfer_sz = 8, .flags = flags_expected};
     TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(HSPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_MASTER, &flags_o));
     TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(HSPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_SLAVE, &flags_o));
@@ -510,15 +504,15 @@ DRAM_ATTR  static uint32_t data_dram[320]={0};
 static const uint32_t data_drom[320] = {0};
 
 #if 1 //HSPI
-#define PIN_NUM_MISO HSPI_NATIVE_PIN_NUM_MISO
-#define PIN_NUM_MOSI HSPI_NATIVE_PIN_NUM_MOSI
-#define PIN_NUM_CLK  HSPI_NATIVE_PIN_NUM_CLK
-#define PIN_NUM_CS   HSPI_NATIVE_PIN_NUM_CS
+#define PIN_NUM_MISO HSPI_IOMUX_PIN_NUM_MISO
+#define PIN_NUM_MOSI HSPI_IOMUX_PIN_NUM_MOSI
+#define PIN_NUM_CLK  HSPI_IOMUX_PIN_NUM_CLK
+#define PIN_NUM_CS   HSPI_IOMUX_PIN_NUM_CS
 #elif 1 //VSPI
-#define PIN_NUM_MISO VSPI_NATIVE_PIN_NUM_MISO
-#define PIN_NUM_MOSI VSPI_NATIVE_PIN_NUM_MOSI
-#define PIN_NUM_CLK  VSPI_NATIVE_PIN_NUM_CLK
-#define PIN_NUM_CS   VSPI_NATIVE_PIN_NUM_CS
+#define PIN_NUM_MISO VSPI_IOMUX_PIN_NUM_MISO
+#define PIN_NUM_MOSI VSPI_IOMUX_PIN_NUM_MOSI
+#define PIN_NUM_CLK  VSPI_IOMUX_PIN_NUM_CLK
+#define PIN_NUM_CS   VSPI_IOMUX_PIN_NUM_CS
 #endif
 
 #define PIN_NUM_DC   21
@@ -1038,8 +1032,8 @@ typedef struct {
      */
     int freq_limit;
     spi_dup_t dup;
-    bool master_native;
-    bool slave_native;
+    bool master_iomux;
+    bool slave_iomux;
     int slave_tv_ns;
 } test_timing_config_t;
 
@@ -1058,67 +1052,67 @@ typedef struct {
 
 
 static test_timing_config_t timing_master_conf_t[] = {/**/
-    { .cfg_name = "FULL_DUP, MASTER NATIVE",
+    { .cfg_name = "FULL_DUP, MASTER IOMUX",
       .freq_limit = SPI_MASTER_FREQ_13M,
       .dup = FULL_DUPLEX,
-      .master_native = true,
-      .slave_native = false,
+      .master_iomux = true,
+      .slave_iomux = false,
       .slave_tv_ns = TV_INT_CONNECT_GPIO,
     },
-    { .cfg_name = "FULL_DUP, SLAVE NATIVE",
+    { .cfg_name = "FULL_DUP, SLAVE IOMUX",
       .freq_limit = SPI_MASTER_FREQ_13M,
       .dup = FULL_DUPLEX,
-      .master_native = false,
-      .slave_native = true,
+      .master_iomux = false,
+      .slave_iomux = true,
       .slave_tv_ns = TV_INT_CONNECT,
     },
     { .cfg_name = "FULL_DUP, BOTH GPIO",
       .freq_limit = SPI_MASTER_FREQ_10M,
       .dup = FULL_DUPLEX,
-      .master_native = false,
-      .slave_native = false,
+      .master_iomux = false,
+      .slave_iomux = false,
       .slave_tv_ns = TV_INT_CONNECT_GPIO,
     },
-    { .cfg_name = "HALF_DUP, MASTER NATIVE",
+    { .cfg_name = "HALF_DUP, MASTER IOMUX",
       .freq_limit = ESP_SPI_SLAVE_MAX_FREQ_SYNC,
       .dup = HALF_DUPLEX_MISO,
-      .master_native = true,
-      .slave_native = false,
+      .master_iomux = true,
+      .slave_iomux = false,
       .slave_tv_ns = TV_INT_CONNECT_GPIO,
     },
-    { .cfg_name = "HALF_DUP, SLAVE NATIVE",
+    { .cfg_name = "HALF_DUP, SLAVE IOMUX",
       .freq_limit = ESP_SPI_SLAVE_MAX_FREQ_SYNC,
       .dup = HALF_DUPLEX_MISO,
-      .master_native = false,
-      .slave_native = true,
+      .master_iomux = false,
+      .slave_iomux = true,
       .slave_tv_ns = TV_INT_CONNECT,
     },
     { .cfg_name = "HALF_DUP, BOTH GPIO",
       .freq_limit = ESP_SPI_SLAVE_MAX_FREQ_SYNC,
       .dup = HALF_DUPLEX_MISO,
-      .master_native = false,
-      .slave_native = false,
+      .master_iomux = false,
+      .slave_iomux = false,
       .slave_tv_ns = TV_INT_CONNECT_GPIO,
     },
-    { .cfg_name = "MOSI_DUP, MASTER NATIVE",
+    { .cfg_name = "MOSI_DUP, MASTER IOMUX",
       .freq_limit = ESP_SPI_SLAVE_MAX_FREQ_SYNC,
       .dup = HALF_DUPLEX_MOSI,
-      .master_native = true,
-      .slave_native = false,
+      .master_iomux = true,
+      .slave_iomux = false,
       .slave_tv_ns = TV_INT_CONNECT_GPIO,
     },
-    { .cfg_name = "MOSI_DUP, SLAVE NATIVE",
+    { .cfg_name = "MOSI_DUP, SLAVE IOMUX",
       .freq_limit = ESP_SPI_SLAVE_MAX_FREQ_SYNC,
       .dup = HALF_DUPLEX_MOSI,
-      .master_native = false,
-      .slave_native = true,
+      .master_iomux = false,
+      .slave_iomux = true,
       .slave_tv_ns = TV_INT_CONNECT,
     },
     { .cfg_name = "MOSI_DUP, BOTH GPIO",
       .freq_limit = ESP_SPI_SLAVE_MAX_FREQ_SYNC,
       .dup = HALF_DUPLEX_MOSI,
-      .master_native = false,
-      .slave_native = false,
+      .master_iomux = false,
+      .slave_iomux = false,
       .slave_tv_ns = TV_INT_CONNECT_GPIO,
     },
 };
@@ -1171,39 +1165,39 @@ TEST_CASE("test timing_master","[spi][timeout=120]")
             slvcfg.mode = slave_mode;
 
             //pin config & initialize
-            //we can't have two sets of native pins on the same pins
-            assert(!conf->master_native || !conf->slave_native);
-            if (conf->slave_native) {
-                //only in this case, use VSPI native pins
-                buscfg.miso_io_num = VSPI_NATIVE_PIN_NUM_MISO;
-                buscfg.mosi_io_num = VSPI_NATIVE_PIN_NUM_MOSI;
-                buscfg.sclk_io_num = VSPI_NATIVE_PIN_NUM_CLK;
-                devcfg.spics_io_num = VSPI_NATIVE_PIN_NUM_CS;
-                slvcfg.spics_io_num = VSPI_NATIVE_PIN_NUM_CS;
+            //we can't have two sets of iomux pins on the same pins
+            assert(!conf->master_iomux || !conf->slave_iomux);
+            if (conf->slave_iomux) {
+                //only in this case, use VSPI iomux pins
+                buscfg.miso_io_num = VSPI_IOMUX_PIN_NUM_MISO;
+                buscfg.mosi_io_num = VSPI_IOMUX_PIN_NUM_MOSI;
+                buscfg.sclk_io_num = VSPI_IOMUX_PIN_NUM_CLK;
+                devcfg.spics_io_num = VSPI_IOMUX_PIN_NUM_CS;
+                slvcfg.spics_io_num = VSPI_IOMUX_PIN_NUM_CS;
             } else {
-                buscfg.miso_io_num = HSPI_NATIVE_PIN_NUM_MISO;
-                buscfg.mosi_io_num = HSPI_NATIVE_PIN_NUM_MOSI;
-                buscfg.sclk_io_num = HSPI_NATIVE_PIN_NUM_CLK;
-                devcfg.spics_io_num = HSPI_NATIVE_PIN_NUM_CS;
-                slvcfg.spics_io_num = HSPI_NATIVE_PIN_NUM_CS;
+                buscfg.miso_io_num = HSPI_IOMUX_PIN_NUM_MISO;
+                buscfg.mosi_io_num = HSPI_IOMUX_PIN_NUM_MOSI;
+                buscfg.sclk_io_num = HSPI_IOMUX_PIN_NUM_CLK;
+                devcfg.spics_io_num = HSPI_IOMUX_PIN_NUM_CS;
+                slvcfg.spics_io_num = HSPI_IOMUX_PIN_NUM_CS;
             }
             slave_pull_up(&buscfg, slvcfg.spics_io_num);
 
-            //this does nothing, but avoid the driver from using native pins if required
-            buscfg.quadhd_io_num = (!conf->master_native && !conf->slave_native? VSPI_NATIVE_PIN_NUM_MISO: -1);
+            //this does nothing, but avoid the driver from using iomux pins if required
+            buscfg.quadhd_io_num = (!conf->master_iomux && !conf->slave_iomux? VSPI_IOMUX_PIN_NUM_MISO: -1);
             TEST_ESP_OK(spi_bus_initialize(HSPI_HOST, &buscfg, 0));
             TEST_ESP_OK(spi_bus_add_device(HSPI_HOST, &devcfg, &spi));
-            //slave automatically use native pins if pins are on VSPI_* pins
+            //slave automatically use iomux pins if pins are on VSPI_* pins
             buscfg.quadhd_io_num = -1;
             TEST_ESP_OK( spi_slave_initialize(VSPI_HOST, &buscfg, &slvcfg, 0) );
 
             //initialize master and slave on the same pins break some of the output configs, fix them
-            if (conf->master_native) {
+            if (conf->master_iomux) {
                 gpio_output_sel(buscfg.mosi_io_num, FUNC_SPI, HSPID_OUT_IDX);
                 gpio_output_sel(buscfg.miso_io_num, FUNC_GPIO, VSPIQ_OUT_IDX);
                 gpio_output_sel(devcfg.spics_io_num, FUNC_SPI, HSPICS0_OUT_IDX);
                 gpio_output_sel(buscfg.sclk_io_num, FUNC_SPI, HSPICLK_OUT_IDX);
-            } else if (conf->slave_native) {
+            } else if (conf->slave_iomux) {
                 gpio_output_sel(buscfg.mosi_io_num, FUNC_GPIO, HSPID_OUT_IDX);
                 gpio_output_sel(buscfg.miso_io_num, FUNC_SPI, VSPIQ_OUT_IDX);
                 gpio_output_sel(devcfg.spics_io_num, FUNC_GPIO, HSPICS0_OUT_IDX);

diff --git a/components/soc/esp32/include/driver/spi_pins.h b/components/soc/esp32/include/driver/spi_pins.h
index 0073dbacd69826c3703b085a790f1b7e2770bb5a..b94c48d7fbf834d4c1e93df60ea1e08abebd7cac 100644 (file)
--- a/components/soc/esp32/include/driver/spi_pins.h
+++ b/components/soc/esp32/include/driver/spi_pins.h
@@ -15,14 +15,18 @@
 #ifndef _DRIVER_SPI_PINS_H_\r
 #define _DRIVER_SPI_PINS_H_\r
 \r
-#define HSPI_NATIVE_PIN_NUM_MISO 12\r
-#define HSPI_NATIVE_PIN_NUM_MOSI 13\r
-#define HSPI_NATIVE_PIN_NUM_CLK  14\r
-#define HSPI_NATIVE_PIN_NUM_CS   15\r
+#define HSPI_IOMUX_PIN_NUM_MISO 12\r
+#define HSPI_IOMUX_PIN_NUM_MOSI 13\r
+#define HSPI_IOMUX_PIN_NUM_CLK  14\r
+#define HSPI_IOMUX_PIN_NUM_CS   15\r
+#define HSPI_IOMUX_PIN_NUM_WP   2\r
+#define HSPI_IOMUX_PIN_NUM_HD   4\r
 \r
-#define VSPI_NATIVE_PIN_NUM_MISO 19\r
-#define VSPI_NATIVE_PIN_NUM_MOSI 23\r
-#define VSPI_NATIVE_PIN_NUM_CLK  18\r
-#define VSPI_NATIVE_PIN_NUM_CS   5\r
+#define VSPI_IOMUX_PIN_NUM_MISO 19\r
+#define VSPI_IOMUX_PIN_NUM_MOSI 23\r
+#define VSPI_IOMUX_PIN_NUM_CLK  18\r
+#define VSPI_IOMUX_PIN_NUM_CS   5\r
+#define VSPI_IOMUX_PIN_NUM_WP   22\r
+#define VSPI_IOMUX_PIN_NUM_HD   21\r
 \r
 #endif
\ No newline at end of file