Fix SIMD VR/PR instruction encoding for the following instructions:

 - PEXTRW
 - MOVMSKPD
 - MOVMSKPS
 - PMOVMSKB
Reported by: Vivek Mohan <vivekm@phreaker.net>

Also, while we're here, fix all CVT* SIMD instructions; they were variously
incorrect (mostly with regards to accepted operands).

New testcase, simd-2, tests all the above (output verified with GNU objdump).

svn path=/trunk/yasm/; revision=1093

diff --git a/modules/arch/x86/tests/Makefile.inc b/modules/arch/x86/tests/Makefile.inc
index 073cafeeaa211d8295ac106c1daebfe884edf724..8a423108b588d8ce5f50464ab0ba98606e429976 100644 (file)
--- a/modules/arch/x86/tests/Makefile.inc
+++ b/modules/arch/x86/tests/Makefile.inc
@@ -110,6 +110,9 @@ EXTRA_DIST += modules/arch/x86/tests/shift.hex
 EXTRA_DIST += modules/arch/x86/tests/simd-1.asm
 EXTRA_DIST += modules/arch/x86/tests/simd-1.errwarn
 EXTRA_DIST += modules/arch/x86/tests/simd-1.hex
+EXTRA_DIST += modules/arch/x86/tests/simd-2.asm
+EXTRA_DIST += modules/arch/x86/tests/simd-2.errwarn
+EXTRA_DIST += modules/arch/x86/tests/simd-2.hex
 EXTRA_DIST += modules/arch/x86/tests/stos.asm
 EXTRA_DIST += modules/arch/x86/tests/stos.errwarn
 EXTRA_DIST += modules/arch/x86/tests/stos.hex

diff --git a/modules/arch/x86/tests/simd-2.asm b/modules/arch/x86/tests/simd-2.asm
new file mode 100644 (file)
index 0000000..a3a351a
--- /dev/null
+++ b/modules/arch/x86/tests/simd-2.asm
@@ -0,0 +1,104 @@
+[bits 32]\r
+pextrw ebx, mm5, 0             ; 0F C5 DD 00\r
+pextrw ecx, xmm0, 1            ; 66 0F C5 C8 01\r
+\r
+pinsrw mm3, esi, 5             ; 0F C4 DE 05\r
+pinsrw mm3, [0], 4             ; 0F C4 1D 00 00 00 00 04\r
+\r
+pinsrw xmm1, eax, 3            ; 66 0F C4 C8 03\r
+pinsrw xmm1, [0], 2            ; 66 0F C4 0D 00 00 00 00 02\r
+\r
+movmskpd edx, xmm7             ; 66 0F 50 D7\r
+movmskps eax, xmm1             ; 0F 50 C1\r
+\r
+pmovmskb edi, mm0              ; 0F D7 F8\r
+pmovmskb esi, xmm1             ; 66 0F D7 F1\r
+\r
+cvtdq2pd xmm5, xmm4            ; F3 0F E6 EC\r
+cvtdq2pd xmm3, [0]             ; F3 0F E6 1D 00 00 00 00\r
+cvtdq2pd xmm2, qword [0]       ; F3 0F E6 15 00 00 00 00\r
+\r
+cvtdq2ps xmm1, xmm2            ; 0F 5B CA\r
+cvtdq2ps xmm4, [0]             ; 0F 5B 25 00 00 00 00\r
+cvtdq2ps xmm5, dqword [0]      ; 0F 5B 2D 00 00 00 00\r
+\r
+cvtpd2dq xmm0, xmm1            ; F2 0F E6 C1\r
+cvtpd2dq xmm2, [0]             ; F2 0F E6 15 00 00 00 00\r
+cvtpd2dq xmm3, dqword [0]      ; F2 0F E6 1D 00 00 00 00\r
+\r
+cvtpd2pi mm4, xmm5             ; 66 0F 2D E5\r
+cvtpd2pi mm6, [0]              ; 66 0F 2D 35 00 00 00 00\r
+cvtpd2pi mm7, dqword [0]       ; 66 0F 2D 3D 00 00 00 00\r
+\r
+cvtpd2ps xmm1, xmm2            ; 66 0F 5A CA\r
+cvtpd2ps xmm3, [0]             ; 66 0F 5A 1D 00 00 00 00\r
+cvtpd2ps xmm4, dqword [0]      ; 66 0F 5A 25 00 00 00 00\r
+\r
+cvtpi2pd xmm5, mm6             ; 66 0F 2A EE\r
+cvtpi2pd xmm7, [0]             ; 66 0F 2A 3D 00 00 00 00\r
+cvtpi2pd xmm0, qword [0]       ; 66 0F 2A 05 00 00 00 00\r
+\r
+cvtpi2ps xmm2, mm3             ; 0F 2A D3\r
+cvtpi2ps xmm4, [0]             ; 0F 2A 25 00 00 00 00\r
+cvtpi2ps xmm5, qword [0]       ; 0F 2A 2D 00 00 00 00\r
+\r
+cvtps2dq xmm6, xmm7            ; 66 0F 5B F7\r
+cvtps2dq xmm0, [0]             ; 66 0F 5B 05 00 00 00 00\r
+cvtps2dq xmm1, dqword [0]      ; 66 0F 5B 0D 00 00 00 00\r
+\r
+cvtps2pd xmm2, xmm3            ; 0F 5A D3\r
+cvtps2pd xmm4, [0]             ; 0F 5A 25 00 00 00 00\r
+cvtps2pd xmm5, qword [0]       ; 0F 5A 2D 00 00 00 00\r
+\r
+cvtps2pi mm6, xmm7             ; 0F 2D F7\r
+cvtps2pi mm0, [0]              ; 0F 2D 05 00 00 00 00\r
+cvtps2pi mm1, qword [0]                ; 0F 2D 0D 00 00 00 00\r
+\r
+cvtsd2si edx, xmm0             ; F2 0F 2D D0\r
+cvtsd2si eax, [0]              ; F2 0F 2D 05 00 00 00 00\r
+cvtsd2si ebx, qword [0]                ; F2 0F 2D 1D 00 00 00 00\r
+\r
+cvtsd2ss xmm1, xmm2            ; F2 0F 5A CA\r
+cvtsd2ss xmm3, [0]             ; F2 0F 5A 1D 00 00 00 00\r
+cvtsd2ss xmm4, qword [0]       ; F2 0F 5A 25 00 00 00 00\r
+\r
+cvtsi2sd xmm5, eax             ; F2 0F 2A E8\r
+cvtsi2sd xmm6, [0]             ; F2 0F 2A 35 00 00 00 00\r
+cvtsi2sd xmm7, dword [0]       ; F2 0F 2A 3D 00 00 00 00\r
+\r
+cvtsi2ss xmm0, edx             ; F3 0F 2A C2\r
+cvtsi2ss xmm1, [0]             ; F3 0F 2A 0D 00 00 00 00\r
+cvtsi2ss xmm2, dword [0]       ; F3 0F 2A 15 00 00 00 00\r
+\r
+cvtss2sd xmm3, xmm4            ; F3 0F 5A DC\r
+cvtss2sd xmm5, [0]             ; F3 0F 5A 2D 00 00 00 00\r
+cvtss2sd xmm6, dword [0]       ; F3 0F 5A 35 00 00 00 00\r
+\r
+cvtss2si ebx, xmm7             ; F3 0F 2D DF\r
+cvtss2si ecx, [0]              ; F3 0F 2D 0D 00 00 00 00\r
+cvtss2si eax, dword [0]                ; F3 0F 2D 05 00 00 00 00\r
+\r
+cvttpd2pi mm0, xmm1            ; 66 0F 2C C1\r
+cvttpd2pi mm2, [0]             ; 66 0F 2C 15 00 00 00 00\r
+cvttpd2pi mm3, dqword [0]      ; 66 0F 2C 1D 00 00 00 00\r
+\r
+cvttpd2dq xmm4, xmm5           ; 66 0F E6 E5\r
+cvttpd2dq xmm6, [0]            ; 66 0F E6 35 00 00 00 00\r
+cvttpd2dq xmm7, dqword [0]     ; 66 0F E6 3D 00 00 00 00\r
+\r
+cvttps2dq xmm0, xmm1           ; F3 0F 5B C1\r
+cvttps2dq xmm2, [0]            ; F3 0F 5B 15 00 00 00 00\r
+cvttps2dq xmm3, dqword [0]     ; F3 0F 5B 1D 00 00 00 00\r
+\r
+cvttps2pi mm4, xmm5            ; 0F 2C E5\r
+cvttps2pi mm6, [0]             ; 0F 2C 35 00 00 00 00\r
+cvttps2pi mm7, qword [0]       ; 0F 2C 3D 00 00 00 00\r
+\r
+cvttsd2si ecx, xmm0            ; F2 0F 2C C8\r
+cvttsd2si ebx, [0]             ; F2 0F 2C 1D 00 00 00 00\r
+cvttsd2si edi, qword [0]       ; F2 0F 2C 3D 00 00 00 00\r
+\r
+cvttss2si esi, xmm3            ; F3 0F 2C F3\r
+cvttss2si ebp, [0]             ; F3 0F 2C 2D 00 00 00 00\r
+cvttss2si eax, dword [0]       ; F3 0F 2C 05 00 00 00 00\r
+\r

diff --git a/modules/arch/x86/tests/simd-2.errwarn b/modules/arch/x86/tests/simd-2.errwarn
new file mode 100644 (file)
index 0000000..e69de29

diff --git a/modules/arch/x86/tests/simd-2.hex b/modules/arch/x86/tests/simd-2.hex
new file mode 100644 (file)
index 0000000..a34ddc1
--- /dev/null
+++ b/modules/arch/x86/tests/simd-2.hex
@@ -0,0 +1,474 @@
+0f 
+c5 
+dd 
+00 
+66 
+0f 
+c5 
+c8 
+01 
+0f 
+c4 
+de 
+05 
+0f 
+c4 
+1d 
+00 
+00 
+00 
+00 
+04 
+66 
+0f 
+c4 
+c8 
+03 
+66 
+0f 
+c4 
+0d 
+00 
+00 
+00 
+00 
+02 
+66 
+0f 
+50 
+d7 
+0f 
+50 
+c1 
+0f 
+d7 
+f8 
+66 
+0f 
+d7 
+f1 
+f3 
+0f 
+e6 
+ec 
+f3 
+0f 
+e6 
+1d 
+00 
+00 
+00 
+00 
+f3 
+0f 
+e6 
+15 
+00 
+00 
+00 
+00 
+0f 
+5b 
+ca 
+0f 
+5b 
+25 
+00 
+00 
+00 
+00 
+0f 
+5b 
+2d 
+00 
+00 
+00 
+00 
+f2 
+0f 
+e6 
+c1 
+f2 
+0f 
+e6 
+15 
+00 
+00 
+00 
+00 
+f2 
+0f 
+e6 
+1d 
+00 
+00 
+00 
+00 
+66 
+0f 
+2d 
+e5 
+66 
+0f 
+2d 
+35 
+00 
+00 
+00 
+00 
+66 
+0f 
+2d 
+3d 
+00 
+00 
+00 
+00 
+66 
+0f 
+5a 
+ca 
+66 
+0f 
+5a 
+1d 
+00 
+00 
+00 
+00 
+66 
+0f 
+5a 
+25 
+00 
+00 
+00 
+00 
+66 
+0f 
+2a 
+ee 
+66 
+0f 
+2a 
+3d 
+00 
+00 
+00 
+00 
+66 
+0f 
+2a 
+05 
+00 
+00 
+00 
+00 
+0f 
+2a 
+d3 
+0f 
+2a 
+25 
+00 
+00 
+00 
+00 
+0f 
+2a 
+2d 
+00 
+00 
+00 
+00 
+66 
+0f 
+5b 
+f7 
+66 
+0f 
+5b 
+05 
+00 
+00 
+00 
+00 
+66 
+0f 
+5b 
+0d 
+00 
+00 
+00 
+00 
+0f 
+5a 
+d3 
+0f 
+5a 
+25 
+00 
+00 
+00 
+00 
+0f 
+5a 
+2d 
+00 
+00 
+00 
+00 
+0f 
+2d 
+f7 
+0f 
+2d 
+05 
+00 
+00 
+00 
+00 
+0f 
+2d 
+0d 
+00 
+00 
+00 
+00 
+f2 
+0f 
+2d 
+d0 
+f2 
+0f 
+2d 
+05 
+00 
+00 
+00 
+00 
+f2 
+0f 
+2d 
+1d 
+00 
+00 
+00 
+00 
+f2 
+0f 
+5a 
+ca 
+f2 
+0f 
+5a 
+1d 
+00 
+00 
+00 
+00 
+f2 
+0f 
+5a 
+25 
+00 
+00 
+00 
+00 
+f2 
+0f 
+2a 
+e8 
+f2 
+0f 
+2a 
+35 
+00 
+00 
+00 
+00 
+f2 
+0f 
+2a 
+3d 
+00 
+00 
+00 
+00 
+f3 
+0f 
+2a 
+c2 
+f3 
+0f 
+2a 
+0d 
+00 
+00 
+00 
+00 
+f3 
+0f 
+2a 
+15 
+00 
+00 
+00 
+00 
+f3 
+0f 
+5a 
+dc 
+f3 
+0f 
+5a 
+2d 
+00 
+00 
+00 
+00 
+f3 
+0f 
+5a 
+35 
+00 
+00 
+00 
+00 
+f3 
+0f 
+2d 
+df 
+f3 
+0f 
+2d 
+0d 
+00 
+00 
+00 
+00 
+f3 
+0f 
+2d 
+05 
+00 
+00 
+00 
+00 
+66 
+0f 
+2c 
+c1 
+66 
+0f 
+2c 
+15 
+00 
+00 
+00 
+00 
+66 
+0f 
+2c 
+1d 
+00 
+00 
+00 
+00 
+66 
+0f 
+e6 
+e5 
+66 
+0f 
+e6 
+35 
+00 
+00 
+00 
+00 
+66 
+0f 
+e6 
+3d 
+00 
+00 
+00 
+00 
+f3 
+0f 
+5b 
+c1 
+f3 
+0f 
+5b 
+15 
+00 
+00 
+00 
+00 
+f3 
+0f 
+5b 
+1d 
+00 
+00 
+00 
+00 
+0f 
+2c 
+e5 
+0f 
+2c 
+35 
+00 
+00 
+00 
+00 
+0f 
+2c 
+3d 
+00 
+00 
+00 
+00 
+f2 
+0f 
+2c 
+c8 
+f2 
+0f 
+2c 
+1d 
+00 
+00 
+00 
+00 
+f2 
+0f 
+2c 
+3d 
+00 
+00 
+00 
+00 
+f3 
+0f 
+2c 
+f3 
+f3 
+0f 
+2c 
+2d 
+00 
+00 
+00 
+00 
+f3 
+0f 
+2c 
+05 
+00 
+00 
+00 
+00 

diff --git a/modules/arch/x86/x86id.re b/modules/arch/x86/x86id.re
index 7dd6e43c6c626c96f12aab349d9d4697f429e3c9..50d67631bdb43d712c429e04e22dbd162d2fab26 100644 (file)
--- a/modules/arch/x86/x86id.re
+++ b/modules/arch/x86/x86id.re
@@ -1291,6 +1291,74 @@ static const x86_insn_info sseps_insn[] = {
       {OPT_SIMDReg|OPS_128|OPA_Spare, OPT_SIMDRM|OPS_128|OPS_Relaxed|OPA_EA, 0}
     }
 };
+static const x86_insn_info cvt_xmm_xmm64_ss_insn[] = {
+    { CPU_SSE, MOD_Op0Add|MOD_Op2Add, 0, 0, 3, {0x00, 0x0F, 0x00}, 0, 2,
+      {OPT_SIMDReg|OPS_128|OPA_Spare, OPT_SIMDReg|OPS_128|OPA_EA, 0}
+    },
+    { CPU_SSE, MOD_Op0Add|MOD_Op2Add, 0, 0, 3, {0x00, 0x0F, 0x00}, 0, 2,
+      {OPT_SIMDReg|OPS_128|OPA_Spare, OPT_Mem|OPS_64|OPS_Relaxed|OPA_EA, 0}
+    }
+};
+static const x86_insn_info cvt_xmm_xmm64_ps_insn[] = {
+    { CPU_SSE, MOD_Op1Add, 0, 0, 2, {0x0F, 0x00, 0x00}, 0, 2,
+      {OPT_SIMDReg|OPS_128|OPA_Spare, OPT_SIMDReg|OPS_128|OPA_EA, 0}
+    },
+    { CPU_SSE, MOD_Op1Add, 0, 0, 2, {0x0F, 0x00, 0x00}, 0, 2,
+      {OPT_SIMDReg|OPS_128|OPA_Spare, OPT_Mem|OPS_64|OPS_Relaxed|OPA_EA, 0}
+    }
+};
+static const x86_insn_info cvt_xmm_xmm32_insn[] = {
+    { CPU_SSE, MOD_Op0Add|MOD_Op2Add, 0, 0, 3, {0x00, 0x0F, 0x00}, 0, 2,
+      {OPT_SIMDReg|OPS_128|OPA_Spare, OPT_SIMDReg|OPS_128|OPA_EA, 0}
+    },
+    { CPU_SSE, MOD_Op0Add|MOD_Op2Add, 0, 0, 3, {0x00, 0x0F, 0x00}, 0, 2,
+      {OPT_SIMDReg|OPS_128|OPA_Spare, OPT_Mem|OPS_32|OPS_Relaxed|OPA_EA, 0}
+    }
+};
+static const x86_insn_info cvt_r32_xmm64_insn[] = {
+    { CPU_SSE, MOD_Op0Add|MOD_Op2Add, 0, 0, 3, {0x00, 0x0F, 0x00}, 0, 2,
+      {OPT_Reg|OPS_32|OPA_Spare, OPT_SIMDReg|OPS_128|OPA_EA, 0}
+    },
+    { CPU_SSE, MOD_Op0Add|MOD_Op2Add, 0, 0, 3, {0x00, 0x0F, 0x00}, 0, 2,
+      {OPT_Reg|OPS_32|OPA_Spare, OPT_Mem|OPS_64|OPS_Relaxed|OPA_EA, 0}
+    }
+};
+static const x86_insn_info cvt_r32_xmm32_insn[] = {
+    { CPU_SSE, MOD_Op0Add|MOD_Op2Add, 0, 0, 3, {0x00, 0x0F, 0x00}, 0, 2,
+      {OPT_Reg|OPS_32|OPA_Spare, OPT_SIMDReg|OPS_128|OPA_EA, 0}
+    },
+    { CPU_SSE, MOD_Op0Add|MOD_Op2Add, 0, 0, 3, {0x00, 0x0F, 0x00}, 0, 2,
+      {OPT_Reg|OPS_32|OPA_Spare, OPT_Mem|OPS_32|OPS_Relaxed|OPA_EA, 0}
+    }
+};
+static const x86_insn_info cvt_mm_xmm64_insn[] = {
+    { CPU_SSE, MOD_Op1Add, 0, 0, 2, {0x0F, 0x00, 0x00}, 0, 2,
+      {OPT_SIMDReg|OPS_64|OPA_Spare, OPT_SIMDReg|OPS_128|OPA_EA, 0}
+    },
+    { CPU_SSE, MOD_Op1Add, 0, 0, 2, {0x0F, 0x00, 0x00}, 0, 2,
+      {OPT_SIMDReg|OPS_64|OPA_Spare, OPT_Mem|OPS_64|OPS_Relaxed|OPA_EA, 0}
+    }
+};
+static const x86_insn_info cvt_mm_xmm_insn[] = {
+    { CPU_SSE, MOD_Op0Add|MOD_Op2Add, 0, 0, 3, {0x00, 0x0F, 0x00}, 0, 2,
+      {OPT_SIMDReg|OPS_64|OPA_Spare, OPT_SIMDRM|OPS_128|OPS_Relaxed|OPA_EA, 0}
+    }
+};
+static const x86_insn_info cvt_xmm_mm_ss_insn[] = {
+    { CPU_SSE, MOD_Op0Add|MOD_Op2Add, 0, 0, 3, {0x00, 0x0F, 0x00}, 0, 2,
+      {OPT_SIMDReg|OPS_128|OPA_Spare, OPT_SIMDRM|OPS_64|OPS_Relaxed|OPA_EA, 0}
+    }
+};
+static const x86_insn_info cvt_xmm_mm_ps_insn[] = {
+    { CPU_SSE, MOD_Op1Add, 0, 0, 2, {0x0F, 0x00, 0x00}, 0, 2,
+      {OPT_SIMDReg|OPS_128|OPA_Spare, OPT_SIMDRM|OPS_64|OPS_Relaxed|OPA_EA, 0}
+    }
+};
+static const x86_insn_info cvt_xmm_rm32_insn[] = {
+    { CPU_SSE, MOD_Op0Add|MOD_Op2Add, 0, 0, 3, {0x00, 0x0F, 0x00}, 0, 2,
+      {OPT_SIMDReg|OPS_128|OPA_Spare, OPT_RM|OPS_32|OPS_Relaxed|OPA_EA, 0}
+    }
+};
 static const x86_insn_info ssess_insn[] = {
     { CPU_SSE, MOD_Op0Add|MOD_Op2Add, 0, 0, 3, {0x00, 0x0F, 0x00}, 0, 2,
       {OPT_SIMDReg|OPS_128|OPA_Spare, OPT_SIMDRM|OPS_128|OPS_Relaxed|OPA_EA, 0}
@@ -1344,7 +1412,7 @@ static const x86_insn_info movhlps_insn[] = {
 };
 static const x86_insn_info movmskps_insn[] = {
     { CPU_SSE, 0, 0, 0, 2, {0x0F, 0x50, 0}, 0, 2,
-      {OPT_Reg|OPS_32|OPA_EA, OPT_SIMDReg|OPS_128|OPA_Spare, 0} }
+      {OPT_Reg|OPS_32|OPA_Spare, OPT_SIMDReg|OPS_128|OPA_EA, 0} }
 };
 static const x86_insn_info movntps_insn[] = {
     { CPU_SSE, 0, 0, 0, 2, {0x0F, 0x2B, 0}, 0, 2,
@@ -1364,10 +1432,10 @@ static const x86_insn_info movss_insn[] = {
 };
 static const x86_insn_info pextrw_insn[] = {
     { CPU_P3|CPU_MMX, 0, 0, 0, 2, {0x0F, 0xC5, 0}, 0, 3,
-      {OPT_Reg|OPS_32|OPA_EA, OPT_SIMDReg|OPS_64|OPA_Spare,
+      {OPT_Reg|OPS_32|OPA_Spare, OPT_SIMDReg|OPS_64|OPA_EA,
        OPT_Imm|OPS_8|OPS_Relaxed|OPA_Imm} },
     { CPU_SSE2, 0, 0, 0, 3, {0x66, 0x0F, 0xC5}, 0, 3,
-      {OPT_Reg|OPS_32|OPA_EA, OPT_SIMDReg|OPS_128|OPA_Spare,
+      {OPT_Reg|OPS_32|OPA_Spare, OPT_SIMDReg|OPS_128|OPA_EA,
        OPT_Imm|OPS_8|OPS_Relaxed|OPA_Imm} }
 };
 static const x86_insn_info pinsrw_insn[] = {
@@ -1375,20 +1443,20 @@ static const x86_insn_info pinsrw_insn[] = {
       {OPT_SIMDReg|OPS_64|OPA_Spare, OPT_Reg|OPS_32|OPA_EA,
        OPT_Imm|OPS_8|OPS_Relaxed|OPA_Imm} },
     { CPU_P3|CPU_MMX, 0, 0, 0, 2, {0x0F, 0xC4, 0}, 0, 3,
-      {OPT_SIMDReg|OPS_64|OPA_Spare, OPT_RM|OPS_16|OPS_Relaxed|OPA_EA,
+      {OPT_SIMDReg|OPS_64|OPA_Spare, OPT_Mem|OPS_16|OPS_Relaxed|OPA_EA,
        OPT_Imm|OPS_8|OPS_Relaxed|OPA_Imm} },
     { CPU_SSE2, 0, 0, 0, 3, {0x66, 0x0F, 0xC4}, 0, 3,
       {OPT_SIMDReg|OPS_128|OPA_Spare, OPT_Reg|OPS_32|OPA_EA,
        OPT_Imm|OPS_8|OPS_Relaxed|OPA_Imm} },
     { CPU_SSE2, 0, 0, 0, 3, {0x66, 0x0F, 0xC4}, 0, 3,
-      {OPT_SIMDReg|OPS_64|OPA_Spare, OPT_RM|OPS_16|OPS_Relaxed|OPA_EA,
+      {OPT_SIMDReg|OPS_128|OPA_Spare, OPT_Mem|OPS_16|OPS_Relaxed|OPA_EA,
        OPT_Imm|OPS_8|OPS_Relaxed|OPA_Imm} }
 };
 static const x86_insn_info pmovmskb_insn[] = {
     { CPU_P3|CPU_MMX, 0, 0, 0, 2, {0x0F, 0xD7, 0}, 0, 2,
-      {OPT_Reg|OPS_32|OPA_EA, OPT_SIMDReg|OPS_64|OPA_Spare, 0} },
+      {OPT_Reg|OPS_32|OPA_Spare, OPT_SIMDReg|OPS_64|OPA_EA, 0} },
     { CPU_SSE2, 0, 0, 0, 3, {0x66, 0x0F, 0xD7}, 0, 2,
-      {OPT_Reg|OPS_32|OPA_EA, OPT_SIMDReg|OPS_128|OPA_Spare, 0} }
+      {OPT_Reg|OPS_32|OPA_Spare, OPT_SIMDReg|OPS_128|OPA_EA, 0} }
 };
 static const x86_insn_info pshufw_insn[] = {
     { CPU_P3|CPU_MMX, 0, 0, 0, 2, {0x0F, 0x70, 0}, 0, 3,
@@ -1419,7 +1487,7 @@ static const x86_insn_info movhlpd_insn[] = {
 };
 static const x86_insn_info movmskpd_insn[] = {
     { CPU_SSE2, 0, 0, 0, 3, {0x66, 0x0F, 0x50}, 0, 2,
-      {OPT_Reg|OPS_32|OPA_EA, OPT_SIMDReg|OPS_128|OPA_Spare, 0} }
+      {OPT_Reg|OPS_32|OPA_Spare, OPT_SIMDReg|OPS_128|OPA_EA, 0} }
 };
 static const x86_insn_info movntpddq_insn[] = {
     { CPU_SSE2, MOD_Op2Add, 0, 0, 3, {0x66, 0x0F, 0x00}, 0, 2,
@@ -3399,12 +3467,12 @@ yasm_x86__parse_check_id(yasm_arch *arch, unsigned long data[4],
        C M P P S { RET_INSN(ssepsimm, 0xC2, CPU_SSE); }
        C M P S S { RET_INSN(ssessimm, 0xF3C2, CPU_SSE); }
        C O M I S S { RET_INSN(sseps, 0x2F, CPU_SSE); }
-       C V T P I "2" P S { RET_INSN(sseps, 0x2A, CPU_SSE); }
-       C V T P S "2" P I { RET_INSN(sseps, 0x2D, CPU_SSE); }
-       C V T S I "2" S S { RET_INSN(ssess, 0xF32A, CPU_SSE); }
-       C V T S S "2" S I { RET_INSN(ssess, 0xF32D, CPU_SSE); }
-       C V T T P S "2" P I { RET_INSN(sseps, 0x2C, CPU_SSE); }
-       C V T T S S "2" S I { RET_INSN(ssess, 0xF32C, CPU_SSE); }
+       C V T P I "2" P S { RET_INSN(cvt_xmm_mm_ps, 0x2A, CPU_SSE); }
+       C V T P S "2" P I { RET_INSN(cvt_mm_xmm64, 0x2D, CPU_SSE); }
+       C V T S I "2" S S { RET_INSN(cvt_xmm_rm32, 0xF32A, CPU_SSE); }
+       C V T S S "2" S I { RET_INSN(cvt_r32_xmm32, 0xF32D, CPU_SSE); }
+       C V T T P S "2" P I { RET_INSN(cvt_mm_xmm64, 0x2C, CPU_SSE); }
+       C V T T S S "2" S I { RET_INSN(cvt_r32_xmm32, 0xF32C, CPU_SSE); }
        D I V P S { RET_INSN(sseps, 0x5E, CPU_SSE); }
        D I V S S { RET_INSN(ssess, 0xF35E, CPU_SSE); }
        L D M X C S R { RET_INSN(ldstmxcsr, 0x02, CPU_SSE); }
@@ -3481,8 +3549,8 @@ yasm_x86__parse_check_id(yasm_arch *arch, unsigned long data[4],
        C M P P D { RET_INSN(ssessimm, 0x66C2, CPU_SSE2); }
        /* C M P S D is in string instructions above */
        C O M I S D { RET_INSN(ssess, 0x662F, CPU_SSE2); }
-       C V T P I "2" P D { RET_INSN(ssess, 0x662A, CPU_SSE2); }
-       C V T S I "2" S D { RET_INSN(ssess, 0xF22A, CPU_SSE2); }
+       C V T P I "2" P D { RET_INSN(cvt_xmm_mm_ss, 0x662A, CPU_SSE2); }
+       C V T S I "2" S D { RET_INSN(cvt_xmm_rm32, 0xF22A, CPU_SSE2); }
        D I V P D { RET_INSN(ssess, 0x665E, CPU_SSE2); }
        D I V S D { RET_INSN(ssess, 0xF25E, CPU_SSE2); }
        M A X P D { RET_INSN(ssess, 0x665F, CPU_SSE2); }
@@ -3509,18 +3577,18 @@ yasm_x86__parse_check_id(yasm_arch *arch, unsigned long data[4],
        U N P C K H P D { RET_INSN(ssess, 0x6615, CPU_SSE2); }
        U N P C K L P D { RET_INSN(ssess, 0x6614, CPU_SSE2); }
        X O R P D { RET_INSN(ssess, 0x6657, CPU_SSE2); }
-       C V T D Q "2" P D { RET_INSN(ssess, 0xF3E6, CPU_SSE2); }
+       C V T D Q "2" P D { RET_INSN(cvt_xmm_xmm64_ss, 0xF3E6, CPU_SSE2); }
        C V T P D "2" D Q { RET_INSN(ssess, 0xF2E6, CPU_SSE2); }
        C V T D Q "2" P S { RET_INSN(sseps, 0x5B, CPU_SSE2); }
-       C V T P D "2" P I { RET_INSN(ssess, 0x662D, CPU_SSE2); }
+       C V T P D "2" P I { RET_INSN(cvt_mm_xmm, 0x662D, CPU_SSE2); }
        C V T P D "2" P S { RET_INSN(ssess, 0x665A, CPU_SSE2); }
-       C V T P S "2" P D { RET_INSN(sseps, 0x5A, CPU_SSE2); }
+       C V T P S "2" P D { RET_INSN(cvt_xmm_xmm64_ps, 0x5A, CPU_SSE2); }
        C V T P S "2" D Q { RET_INSN(ssess, 0x665B, CPU_SSE2); }
-       C V T S D "2" S I { RET_INSN(ssess, 0xF22D, CPU_SSE2); }
-       C V T S D "2" S S { RET_INSN(ssess, 0xF25A, CPU_SSE2); }
-       C V T S S "2" S D { RET_INSN(ssess, 0xF35A, CPU_SSE2); }
-       C V T T P D "2" P I { RET_INSN(ssess, 0x662C, CPU_SSE2); }
-       C V T T S D "2" S I { RET_INSN(ssess, 0xF22C, CPU_SSE2); }
+       C V T S D "2" S I { RET_INSN(cvt_r32_xmm64, 0xF22D, CPU_SSE2); }
+       C V T S D "2" S S { RET_INSN(cvt_xmm_xmm64_ss, 0xF25A, CPU_SSE2); }
+       C V T S S "2" S D { RET_INSN(cvt_xmm_xmm32, 0xF35A, CPU_SSE2); }
+       C V T T P D "2" P I { RET_INSN(cvt_mm_xmm, 0x662C, CPU_SSE2); }
+       C V T T S D "2" S I { RET_INSN(cvt_r32_xmm64, 0xF22C, CPU_SSE2); }
        C V T T P D "2" D Q { RET_INSN(ssess, 0x66E6, CPU_SSE2); }
        C V T T P S "2" D Q { RET_INSN(ssess, 0xF35B, CPU_SSE2); }
        M A S K M O V D Q U { RET_INSN(maskmovdqu, 0, CPU_SSE2); }