AMDGPU/GlobalISel: Correct regbank for 1-bit and/or/xor

Bool values should use the scc/vcc regbank since r350611.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360877 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp b/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
index 24e0a03667d324142ff27c7906fc14107d8123fe..d9f095b7548ca122df4048b61e83c7f29f994484 100644 (file)
--- a/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
+++ b/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
@@ -770,7 +770,7 @@ AMDGPURegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
     unsigned Size = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
     if (Size == 1) {
       OpdsMapping[0] = OpdsMapping[1] =
-        OpdsMapping[2] = AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, Size);
+        OpdsMapping[2] = AMDGPU::getValueMapping(AMDGPU::VCCRegBankID, Size);
       break;
     }
 

diff --git a/test/CodeGen/AMDGPU/GlobalISel/regbankselect-and.mir b/test/CodeGen/AMDGPU/GlobalISel/regbankselect-and.mir
index c35327ff38513b84d6c87679f4f93e98485b742e..9e3d023349282a05af79790ff8929b345ac95e96 100644 (file)
--- a/test/CodeGen/AMDGPU/GlobalISel/regbankselect-and.mir
+++ b/test/CodeGen/AMDGPU/GlobalISel/regbankselect-and.mir
@@ -80,9 +80,9 @@ body: |
     ; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
     ; CHECK: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[C]]
     ; CHECK: [[ICMP1:%[0-9]+]]:scc(s1) = G_ICMP intpred(ne), [[COPY1]](s32), [[C]]
-    ; CHECK: [[COPY2:%[0-9]+]]:sgpr(s1) = COPY [[ICMP]](s1)
-    ; CHECK: [[COPY3:%[0-9]+]]:sgpr(s1) = COPY [[ICMP1]](s1)
-    ; CHECK: [[AND:%[0-9]+]]:sgpr(s1) = G_AND [[COPY2]], [[COPY3]]
+    ; CHECK: [[COPY2:%[0-9]+]]:vcc(s1) = COPY [[ICMP]](s1)
+    ; CHECK: [[COPY3:%[0-9]+]]:vcc(s1) = COPY [[ICMP1]](s1)
+    ; CHECK: [[AND:%[0-9]+]]:vcc(s1) = G_AND [[COPY2]], [[COPY3]]
     ; CHECK: S_NOP 0, implicit [[AND]](s1)
       %0:_(s32) = COPY $sgpr0
       %1:_(s32) = COPY $sgpr1
@@ -106,9 +106,7 @@ body: |
     ; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
     ; CHECK: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[C]]
     ; CHECK: [[ICMP1:%[0-9]+]]:vcc(s1) = G_ICMP intpred(ne), [[COPY1]](s32), [[C]]
-    ; CHECK: [[COPY2:%[0-9]+]]:sgpr(s1) = COPY [[ICMP]](s1)
-    ; CHECK: [[COPY3:%[0-9]+]]:sgpr(s1) = COPY [[ICMP1]](s1)
-    ; CHECK: [[AND:%[0-9]+]]:sgpr(s1) = G_AND [[COPY2]], [[COPY3]]
+    ; CHECK: [[AND:%[0-9]+]]:vcc(s1) = G_AND [[ICMP]], [[ICMP1]]
     ; CHECK: S_NOP 0, implicit [[AND]](s1)
       %0:_(s32) = COPY $vgpr0
       %1:_(s32) = COPY $vgpr1
@@ -132,9 +130,8 @@ body: |
     ; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
     ; CHECK: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[C]]
     ; CHECK: [[ICMP1:%[0-9]+]]:vcc(s1) = G_ICMP intpred(ne), [[COPY1]](s32), [[C]]
-    ; CHECK: [[COPY2:%[0-9]+]]:sgpr(s1) = COPY [[ICMP]](s1)
-    ; CHECK: [[COPY3:%[0-9]+]]:sgpr(s1) = COPY [[ICMP1]](s1)
-    ; CHECK: [[AND:%[0-9]+]]:sgpr(s1) = G_AND [[COPY2]], [[COPY3]]
+    ; CHECK: [[COPY2:%[0-9]+]]:vcc(s1) = COPY [[ICMP]](s1)
+    ; CHECK: [[AND:%[0-9]+]]:vcc(s1) = G_AND [[COPY2]], [[ICMP1]]
     ; CHECK: S_NOP 0, implicit [[AND]](s1)
       %0:_(s32) = COPY $sgpr0
       %1:_(s32) = COPY $vgpr0
@@ -156,7 +153,9 @@ body:             |
     ; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
     ; CHECK: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY]](s32)
     ; CHECK: [[TRUNC1:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY1]](s32)
-    ; CHECK: [[AND:%[0-9]+]]:sgpr(s1) = G_AND [[TRUNC]], [[TRUNC1]]
+    ; CHECK: [[COPY2:%[0-9]+]]:vcc(s1) = COPY [[TRUNC]](s1)
+    ; CHECK: [[COPY3:%[0-9]+]]:vcc(s1) = COPY [[TRUNC1]](s1)
+    ; CHECK: [[AND:%[0-9]+]]:vcc(s1) = G_AND [[COPY2]], [[COPY3]]
     ; CHECK: S_NOP 0, implicit [[AND]](s1)
     %0:_(s32) = COPY $sgpr0
     %1:_(s32) = COPY $sgpr1
@@ -178,8 +177,9 @@ body:             |
     ; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
     ; CHECK: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY]](s32)
     ; CHECK: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]]
-    ; CHECK: [[COPY2:%[0-9]+]]:sgpr(s1) = COPY [[ICMP]](s1)
-    ; CHECK: [[AND:%[0-9]+]]:sgpr(s1) = G_AND [[TRUNC]], [[COPY2]]
+    ; CHECK: [[COPY2:%[0-9]+]]:vcc(s1) = COPY [[TRUNC]](s1)
+    ; CHECK: [[COPY3:%[0-9]+]]:vcc(s1) = COPY [[ICMP]](s1)
+    ; CHECK: [[AND:%[0-9]+]]:vcc(s1) = G_AND [[COPY2]], [[COPY3]]
     ; CHECK: S_NOP 0, implicit [[AND]](s1)
     %0:_(s32) = COPY $sgpr0
     %1:_(s32) = COPY $sgpr1
@@ -200,8 +200,8 @@ body:             |
     ; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
     ; CHECK: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY]](s32)
     ; CHECK: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]]
-    ; CHECK: [[COPY2:%[0-9]+]]:sgpr(s1) = COPY [[ICMP]](s1)
-    ; CHECK: [[AND:%[0-9]+]]:sgpr(s1) = G_AND [[TRUNC]], [[COPY2]]
+    ; CHECK: [[COPY2:%[0-9]+]]:vcc(s1) = COPY [[TRUNC]](s1)
+    ; CHECK: [[AND:%[0-9]+]]:vcc(s1) = G_AND [[COPY2]], [[ICMP]]
     ; CHECK: S_NOP 0, implicit [[AND]](s1)
     %0:_(s32) = COPY $sgpr0
     %1:_(s32) = COPY $vgpr0

diff --git a/test/CodeGen/AMDGPU/GlobalISel/regbankselect-or.mir b/test/CodeGen/AMDGPU/GlobalISel/regbankselect-or.mir
index 0939b08c82766d11f25fac49599a6671dc1a7ee2..34c7f55886fd626efd62aecc7e89e8069f23987f 100644 (file)
--- a/test/CodeGen/AMDGPU/GlobalISel/regbankselect-or.mir
+++ b/test/CodeGen/AMDGPU/GlobalISel/regbankselect-or.mir
@@ -80,9 +80,9 @@ body: |
     ; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
     ; CHECK: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[C]]
     ; CHECK: [[ICMP1:%[0-9]+]]:scc(s1) = G_ICMP intpred(ne), [[COPY1]](s32), [[C]]
-    ; CHECK: [[COPY2:%[0-9]+]]:sgpr(s1) = COPY [[ICMP]](s1)
-    ; CHECK: [[COPY3:%[0-9]+]]:sgpr(s1) = COPY [[ICMP1]](s1)
-    ; CHECK: [[OR:%[0-9]+]]:sgpr(s1) = G_OR [[COPY2]], [[COPY3]]
+    ; CHECK: [[COPY2:%[0-9]+]]:vcc(s1) = COPY [[ICMP]](s1)
+    ; CHECK: [[COPY3:%[0-9]+]]:vcc(s1) = COPY [[ICMP1]](s1)
+    ; CHECK: [[OR:%[0-9]+]]:vcc(s1) = G_OR [[COPY2]], [[COPY3]]
     ; CHECK: S_NOP 0, implicit [[OR]](s1)
       %0:_(s32) = COPY $sgpr0
       %1:_(s32) = COPY $sgpr1
@@ -106,9 +106,7 @@ body: |
     ; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
     ; CHECK: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[C]]
     ; CHECK: [[ICMP1:%[0-9]+]]:vcc(s1) = G_ICMP intpred(ne), [[COPY1]](s32), [[C]]
-    ; CHECK: [[COPY2:%[0-9]+]]:sgpr(s1) = COPY [[ICMP]](s1)
-    ; CHECK: [[COPY3:%[0-9]+]]:sgpr(s1) = COPY [[ICMP1]](s1)
-    ; CHECK: [[OR:%[0-9]+]]:sgpr(s1) = G_OR [[COPY2]], [[COPY3]]
+    ; CHECK: [[OR:%[0-9]+]]:vcc(s1) = G_OR [[ICMP]], [[ICMP1]]
     ; CHECK: S_NOP 0, implicit [[OR]](s1)
       %0:_(s32) = COPY $vgpr0
       %1:_(s32) = COPY $vgpr1
@@ -132,9 +130,8 @@ body: |
     ; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
     ; CHECK: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[C]]
     ; CHECK: [[ICMP1:%[0-9]+]]:vcc(s1) = G_ICMP intpred(ne), [[COPY1]](s32), [[C]]
-    ; CHECK: [[COPY2:%[0-9]+]]:sgpr(s1) = COPY [[ICMP]](s1)
-    ; CHECK: [[COPY3:%[0-9]+]]:sgpr(s1) = COPY [[ICMP1]](s1)
-    ; CHECK: [[OR:%[0-9]+]]:sgpr(s1) = G_OR [[COPY2]], [[COPY3]]
+    ; CHECK: [[COPY2:%[0-9]+]]:vcc(s1) = COPY [[ICMP]](s1)
+    ; CHECK: [[OR:%[0-9]+]]:vcc(s1) = G_OR [[COPY2]], [[ICMP1]]
     ; CHECK: S_NOP 0, implicit [[OR]](s1)
       %0:_(s32) = COPY $sgpr0
       %1:_(s32) = COPY $vgpr0
@@ -156,7 +153,9 @@ body:             |
     ; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
     ; CHECK: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY]](s32)
     ; CHECK: [[TRUNC1:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY1]](s32)
-    ; CHECK: [[OR:%[0-9]+]]:sgpr(s1) = G_OR [[TRUNC]], [[TRUNC1]]
+    ; CHECK: [[COPY2:%[0-9]+]]:vcc(s1) = COPY [[TRUNC]](s1)
+    ; CHECK: [[COPY3:%[0-9]+]]:vcc(s1) = COPY [[TRUNC1]](s1)
+    ; CHECK: [[OR:%[0-9]+]]:vcc(s1) = G_OR [[COPY2]], [[COPY3]]
     ; CHECK: S_NOP 0, implicit [[OR]](s1)
     %0:_(s32) = COPY $sgpr0
     %1:_(s32) = COPY $sgpr1
@@ -178,8 +177,9 @@ body:             |
     ; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
     ; CHECK: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY]](s32)
     ; CHECK: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]]
-    ; CHECK: [[COPY2:%[0-9]+]]:sgpr(s1) = COPY [[ICMP]](s1)
-    ; CHECK: [[OR:%[0-9]+]]:sgpr(s1) = G_OR [[TRUNC]], [[COPY2]]
+    ; CHECK: [[COPY2:%[0-9]+]]:vcc(s1) = COPY [[TRUNC]](s1)
+    ; CHECK: [[COPY3:%[0-9]+]]:vcc(s1) = COPY [[ICMP]](s1)
+    ; CHECK: [[OR:%[0-9]+]]:vcc(s1) = G_OR [[COPY2]], [[COPY3]]
     ; CHECK: S_NOP 0, implicit [[OR]](s1)
     %0:_(s32) = COPY $sgpr0
     %1:_(s32) = COPY $sgpr1
@@ -200,8 +200,8 @@ body:             |
     ; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
     ; CHECK: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY]](s32)
     ; CHECK: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]]
-    ; CHECK: [[COPY2:%[0-9]+]]:sgpr(s1) = COPY [[ICMP]](s1)
-    ; CHECK: [[OR:%[0-9]+]]:sgpr(s1) = G_OR [[TRUNC]], [[COPY2]]
+    ; CHECK: [[COPY2:%[0-9]+]]:vcc(s1) = COPY [[TRUNC]](s1)
+    ; CHECK: [[OR:%[0-9]+]]:vcc(s1) = G_OR [[COPY2]], [[ICMP]]
     ; CHECK: S_NOP 0, implicit [[OR]](s1)
     %0:_(s32) = COPY $sgpr0
     %1:_(s32) = COPY $vgpr0

diff --git a/test/CodeGen/AMDGPU/GlobalISel/regbankselect-xor.mir b/test/CodeGen/AMDGPU/GlobalISel/regbankselect-xor.mir
index 33fe4d4ca273695731eb7578559f7b6cdd6ee475..f6544d0031220321ab670e354e17fcbdded9a1c6 100644 (file)
--- a/test/CodeGen/AMDGPU/GlobalISel/regbankselect-xor.mir
+++ b/test/CodeGen/AMDGPU/GlobalISel/regbankselect-xor.mir
@@ -80,9 +80,9 @@ body: |
     ; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
     ; CHECK: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[C]]
     ; CHECK: [[ICMP1:%[0-9]+]]:scc(s1) = G_ICMP intpred(ne), [[COPY1]](s32), [[C]]
-    ; CHECK: [[COPY2:%[0-9]+]]:sgpr(s1) = COPY [[ICMP]](s1)
-    ; CHECK: [[COPY3:%[0-9]+]]:sgpr(s1) = COPY [[ICMP1]](s1)
-    ; CHECK: [[XOR:%[0-9]+]]:sgpr(s1) = G_XOR [[COPY2]], [[COPY3]]
+    ; CHECK: [[COPY2:%[0-9]+]]:vcc(s1) = COPY [[ICMP]](s1)
+    ; CHECK: [[COPY3:%[0-9]+]]:vcc(s1) = COPY [[ICMP1]](s1)
+    ; CHECK: [[XOR:%[0-9]+]]:vcc(s1) = G_XOR [[COPY2]], [[COPY3]]
     ; CHECK: S_NOP 0, implicit [[XOR]](s1)
       %0:_(s32) = COPY $sgpr0
       %1:_(s32) = COPY $sgpr1
@@ -106,9 +106,7 @@ body: |
     ; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
     ; CHECK: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[C]]
     ; CHECK: [[ICMP1:%[0-9]+]]:vcc(s1) = G_ICMP intpred(ne), [[COPY1]](s32), [[C]]
-    ; CHECK: [[COPY2:%[0-9]+]]:sgpr(s1) = COPY [[ICMP]](s1)
-    ; CHECK: [[COPY3:%[0-9]+]]:sgpr(s1) = COPY [[ICMP1]](s1)
-    ; CHECK: [[XOR:%[0-9]+]]:sgpr(s1) = G_XOR [[COPY2]], [[COPY3]]
+    ; CHECK: [[XOR:%[0-9]+]]:vcc(s1) = G_XOR [[ICMP]], [[ICMP1]]
     ; CHECK: S_NOP 0, implicit [[XOR]](s1)
       %0:_(s32) = COPY $vgpr0
       %1:_(s32) = COPY $vgpr1
@@ -132,9 +130,8 @@ body: |
     ; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
     ; CHECK: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[C]]
     ; CHECK: [[ICMP1:%[0-9]+]]:vcc(s1) = G_ICMP intpred(ne), [[COPY1]](s32), [[C]]
-    ; CHECK: [[COPY2:%[0-9]+]]:sgpr(s1) = COPY [[ICMP]](s1)
-    ; CHECK: [[COPY3:%[0-9]+]]:sgpr(s1) = COPY [[ICMP1]](s1)
-    ; CHECK: [[XOR:%[0-9]+]]:sgpr(s1) = G_XOR [[COPY2]], [[COPY3]]
+    ; CHECK: [[COPY2:%[0-9]+]]:vcc(s1) = COPY [[ICMP]](s1)
+    ; CHECK: [[XOR:%[0-9]+]]:vcc(s1) = G_XOR [[COPY2]], [[ICMP1]]
     ; CHECK: S_NOP 0, implicit [[XOR]](s1)
       %0:_(s32) = COPY $sgpr0
       %1:_(s32) = COPY $vgpr0
@@ -156,7 +153,9 @@ body:             |
     ; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
     ; CHECK: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY]](s32)
     ; CHECK: [[TRUNC1:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY1]](s32)
-    ; CHECK: [[XOR:%[0-9]+]]:sgpr(s1) = G_XOR [[TRUNC]], [[TRUNC1]]
+    ; CHECK: [[COPY2:%[0-9]+]]:vcc(s1) = COPY [[TRUNC]](s1)
+    ; CHECK: [[COPY3:%[0-9]+]]:vcc(s1) = COPY [[TRUNC1]](s1)
+    ; CHECK: [[XOR:%[0-9]+]]:vcc(s1) = G_XOR [[COPY2]], [[COPY3]]
     ; CHECK: S_NOP 0, implicit [[XOR]](s1)
     %0:_(s32) = COPY $sgpr0
     %1:_(s32) = COPY $sgpr1
@@ -178,8 +177,9 @@ body:             |
     ; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
     ; CHECK: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY]](s32)
     ; CHECK: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]]
-    ; CHECK: [[COPY2:%[0-9]+]]:sgpr(s1) = COPY [[ICMP]](s1)
-    ; CHECK: [[XOR:%[0-9]+]]:sgpr(s1) = G_XOR [[TRUNC]], [[COPY2]]
+    ; CHECK: [[COPY2:%[0-9]+]]:vcc(s1) = COPY [[TRUNC]](s1)
+    ; CHECK: [[COPY3:%[0-9]+]]:vcc(s1) = COPY [[ICMP]](s1)
+    ; CHECK: [[XOR:%[0-9]+]]:vcc(s1) = G_XOR [[COPY2]], [[COPY3]]
     ; CHECK: S_NOP 0, implicit [[XOR]](s1)
     %0:_(s32) = COPY $sgpr0
     %1:_(s32) = COPY $sgpr1
@@ -200,8 +200,8 @@ body:             |
     ; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
     ; CHECK: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY]](s32)
     ; CHECK: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]]
-    ; CHECK: [[COPY2:%[0-9]+]]:sgpr(s1) = COPY [[ICMP]](s1)
-    ; CHECK: [[XOR:%[0-9]+]]:sgpr(s1) = G_XOR [[TRUNC]], [[COPY2]]
+    ; CHECK: [[COPY2:%[0-9]+]]:vcc(s1) = COPY [[TRUNC]](s1)
+    ; CHECK: [[XOR:%[0-9]+]]:vcc(s1) = G_XOR [[COPY2]], [[ICMP]]
     ; CHECK: S_NOP 0, implicit [[XOR]](s1)
     %0:_(s32) = COPY $sgpr0
     %1:_(s32) = COPY $vgpr0