[Power9] Add new instructions for floating point status and control registers.

Added the following P9 instructions: mffsce, mffscdrn, mffscdrni, mffscrn,
  mffscrni, mffsl

Differential Revision: https://reviews.llvm.org/D37167

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311903 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/PowerPC/PPCInstrFormats.td b/lib/Target/PowerPC/PPCInstrFormats.td
index ef7d2012a23327d52ce4e1c53eca567e681c6425..152096789c3d42abe8d5ad4f9448dfd1fd2cfb0c 100644 (file)
--- a/lib/Target/PowerPC/PPCInstrFormats.td
+++ b/lib/Target/PowerPC/PPCInstrFormats.td
@@ -725,6 +725,68 @@ class XForm_43<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
   let Inst{31}    = RC;
 }
 
+class X_FRT5_XO2_XO3_XO10<bits<6> opcode, bits<2> xo1, bits<3> xo2, bits<10> xo,
+                         dag OOL, dag IOL, string asmstr, InstrItinClass itin,
+                         list<dag> pattern>
+  : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
+  let Pattern = pattern;
+
+  let Inst{6-10}  = RST;
+  let Inst{11-12} = xo1;
+  let Inst{13-15} = xo2;
+  let Inst{16-20} = 0;
+  let Inst{21-30} = xo;
+  let Inst{31}    = 0;
+}
+
+class X_FRT5_XO2_XO3_FRB5_XO10<bits<6> opcode, bits<2> xo1, bits<3> xo2,
+                              bits<10> xo, dag OOL, dag IOL, string asmstr,
+                              InstrItinClass itin, list<dag> pattern>
+  : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
+  let Pattern = pattern;
+  bits<5> FRB;
+
+  let Inst{6-10}  = RST;
+  let Inst{11-12} = xo1;
+  let Inst{13-15} = xo2;
+  let Inst{16-20} = FRB;
+  let Inst{21-30} = xo;
+  let Inst{31}    = 0;
+}
+
+class X_FRT5_XO2_XO3_DRM3_XO10<bits<6> opcode, bits<2> xo1, bits<3> xo2,
+                              bits<10> xo, dag OOL, dag IOL, string asmstr,
+                              InstrItinClass itin, list<dag> pattern>
+  : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
+  let Pattern = pattern;
+  bits<3> DRM;
+
+  let Inst{6-10}  = RST;
+  let Inst{11-12} = xo1;
+  let Inst{13-15} = xo2;
+  let Inst{16-17} = 0;
+  let Inst{18-20} = DRM;
+  let Inst{21-30} = xo;
+  let Inst{31}    = 0;
+}
+
+class X_FRT5_XO2_XO3_RM2_X10<bits<6> opcode, bits<2> xo1, bits<3> xo2,
+                            bits<10> xo, dag OOL, dag IOL, string asmstr,
+                            InstrItinClass itin, list<dag> pattern>
+  : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
+  let Pattern = pattern;
+  bits<2> RM;
+
+  let Inst{6-10}  = RST;
+  let Inst{11-12} = xo1;
+  let Inst{13-15} = xo2;
+  let Inst{16-18} = 0;
+  let Inst{19-20} = RM;
+  let Inst{21-30} = xo;
+  let Inst{31}    = 0;
+}
+
+
 class XForm_0<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
               InstrItinClass itin, list<dag> pattern>
   : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {

diff --git a/lib/Target/PowerPC/PPCInstrInfo.td b/lib/Target/PowerPC/PPCInstrInfo.td
index dd7fc2659102afbc704146c132fe9db02b66b895..5a79349f6f258cb476e3a3db488cedd78cc2b674 100644 (file)
--- a/lib/Target/PowerPC/PPCInstrInfo.td
+++ b/lib/Target/PowerPC/PPCInstrInfo.td
@@ -2571,6 +2571,35 @@ let Uses = [RM] in {
   let Defs = [CR1] in
   def MFFSo : XForm_42<63, 583, (outs f8rc:$rT), (ins),
                       "mffs. $rT", IIC_IntMFFS, []>, isDOT;
+
+  def MFFSCE : X_FRT5_XO2_XO3_XO10<63, 0, 1, 583, (outs f8rc:$rT), (ins),
+                                  "mffsce $rT", IIC_IntMFFS, []>,
+               PPC970_DGroup_Single, PPC970_Unit_FPU;
+
+  def MFFSCDRN : X_FRT5_XO2_XO3_FRB5_XO10<63, 2, 4, 583, (outs f8rc:$rT),
+                                         (ins f8rc:$FRB), "mffscdrn $rT, $FRB",
+                                         IIC_IntMFFS, []>,
+                 PPC970_DGroup_Single, PPC970_Unit_FPU;
+
+  def MFFSCDRNI : X_FRT5_XO2_XO3_DRM3_XO10<63, 2, 5, 583, (outs f8rc:$rT),
+                                          (ins u3imm:$DRM),
+                                          "mffscdrni $rT, $DRM",
+                                          IIC_IntMFFS, []>,
+                  PPC970_DGroup_Single, PPC970_Unit_FPU;
+
+  def MFFSCRN : X_FRT5_XO2_XO3_FRB5_XO10<63, 2, 6, 583, (outs f8rc:$rT),
+                                        (ins f8rc:$FRB), "mffscrn $rT, $FRB",
+                                        IIC_IntMFFS, []>,
+                PPC970_DGroup_Single, PPC970_Unit_FPU;
+
+  def MFFSCRNI : X_FRT5_XO2_XO3_RM2_X10<63, 2, 7, 583, (outs f8rc:$rT),
+                                       (ins u2imm:$RM), "mffscrni $rT, $RM",
+                                       IIC_IntMFFS, []>,
+                 PPC970_DGroup_Single, PPC970_Unit_FPU;
+
+  def MFFSL  : X_FRT5_XO2_XO3_XO10<63, 3, 0, 583, (outs f8rc:$rT), (ins),
+                                  "mffsl $rT", IIC_IntMFFS, []>,
+               PPC970_DGroup_Single, PPC970_Unit_FPU;
 }
 
 let Predicates = [IsISA3_0] in {

diff --git a/test/MC/Disassembler/PowerPC/ppc64-encoding-fp.txt b/test/MC/Disassembler/PowerPC/ppc64-encoding-fp.txt
index 8c8ce65567a4add4ebf18c44c30220e9e56221e4..ea59a49ca0b1ac050fc6be583bbca556ab765f89 100644 (file)
--- a/test/MC/Disassembler/PowerPC/ppc64-encoding-fp.txt
+++ b/test/MC/Disassembler/PowerPC/ppc64-encoding-fp.txt
@@ -342,6 +342,24 @@
 # CHECK: mffs. 7
 0xfc 0xe0 0x04 0x8f
 
+# CHECK: mffsce 2
+0xfc 0x41 0x04 0x8e
+
+# CHECK: mffscdrn 2, 3
+0xfc 0x54 0x1c 0x8e
+
+# CHECK: mffscdrni 2, 3
+0xfc 0x55 0x1c 0x8e
+
+# CHECK: mffscrn 2, 3
+0xfc 0x56 0x1c 0x8e
+
+# CHECK: mffscrni 2, 3
+0xfc 0x57 0x1c 0x8e
+
+# CHECK: mffsl 2
+0xfc 0x58 0x04 0x8e
+
 # CHECK: mcrfs 4, 5
 0xfe 0x14 0x00 0x80
 

diff --git a/test/MC/PowerPC/ppc64-encoding-fp.s b/test/MC/PowerPC/ppc64-encoding-fp.s
index 0e74840ca167c78e35d8e2faa37ad8a4d7d29153..8dcf0ded16d181210f2f987825cf87c3a547acec 100644 (file)
--- a/test/MC/PowerPC/ppc64-encoding-fp.s
+++ b/test/MC/PowerPC/ppc64-encoding-fp.s
@@ -382,6 +382,24 @@
 # CHECK-BE: mffs. 7                         # encoding: [0xfc,0xe0,0x04,0x8f]
 # CHECK-LE: mffs. 7                         # encoding: [0x8f,0x04,0xe0,0xfc]
             mffs. 7
+# CHECK-BE: mffsce 2                        # encoding: [0xfc,0x41,0x04,0x8e]
+# CHECK-LE: mffsce 2                        # encoding: [0x8e,0x04,0x41,0xfc]
+            mffsce 2
+# CHECK-BE: mffscdrn 2, 3                   # encoding: [0xfc,0x54,0x1c,0x8e]
+# CHECK-LE: mffscdrn 2, 3                   # encoding: [0x8e,0x1c,0x54,0xfc]
+            mffscdrn 2, 3
+# CHECK-BE: mffscdrni 2, 3                  # encoding: [0xfc,0x55,0x1c,0x8e]
+# CHECK-LE: mffscdrni 2, 3                  # encoding: [0x8e,0x1c,0x55,0xfc]
+            mffscdrni 2, 3
+# CHECK-BE: mffscrn 2, 3                    # encoding: [0xfc,0x56,0x1c,0x8e]
+# CHECK-LE: mffscrn 2, 3                    # encoding: [0x8e,0x1c,0x56,0xfc]
+            mffscrn 2, 3
+# CHECK-BE: mffscrni 2, 3                   # encoding: [0xfc,0x57,0x1c,0x8e]
+# CHECK-LE: mffscrni 2, 3                   # encoding: [0x8e,0x1c,0x57,0xfc]
+            mffscrni 2, 3
+# CHECK-BE: mffsl 2                         # encoding: [0xfc,0x58,0x04,0x8e]
+# CHECK-LE: mffsl 2                         # encoding: [0x8e,0x04,0x58,0xfc]
+            mffsl 2
 # CHECK-BE: mcrfs 4, 5                      # encoding: [0xfe,0x14,0x00,0x80]
 # CHECK-LE: mcrfs 4, 5                      # encoding: [0x80,0x00,0x14,0xfe]
             mcrfs 4, 5