[TableGen] Fix a bug that MCSchedClassDesc is interfered between different SchedModel

Assume that, ModelA has scheduling resource for InstA and ModelB has scheduling resource for InstB. This is what the llvm::MCSchedClassDesc looks like:

llvm::MCSchedClassDesc ModelASchedClasses[] = {
...
InstA, 0, ...
InstB, -1,...
};

llvm::MCSchedClassDesc ModelBSchedClasses[] = {
...
InstA, -1,...
InstB, 0,...
};
The -1 means invalid num of macro ops, while it is valid if it is >=0. This is what we look like now:

llvm::MCSchedClassDesc ModelASchedClasses[] = {
...
InstA, 0, ...
InstB, 0,...
};

llvm::MCSchedClassDesc ModelBSchedClasses[] = {
...
InstA, 0,...
InstB, 0,...
};
And compiler hit the assertion here because the SCDesc is valid now for both InstA and InstB.

Differential Revision: https://reviews.llvm.org/D67950

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@374524 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/test/CodeGen/ARM/ParallelDSP/unroll-n-jam-smlad.ll b/test/CodeGen/ARM/ParallelDSP/unroll-n-jam-smlad.ll
index c72d4584537982a84a4dfbb7b1052282ccf47d91..16d0216df7e3b4dac286ae0edefbf28eebc25a51 100644 (file)
--- a/test/CodeGen/ARM/ParallelDSP/unroll-n-jam-smlad.ll
+++ b/test/CodeGen/ARM/ParallelDSP/unroll-n-jam-smlad.ll
@@ -45,7 +45,6 @@ entry:
 ; CHECK-REG-PRESSURE: ldr{{.*}}, [sp
 ; CHECK-REG-PRESSURE: ldr{{.*}}, [sp
 ; CHECK-REG-PRESSURE: ldr{{.*}}, [sp
-; CHECK-REG-PRESSURE: ldr{{.*}}, [sp
 ; CHECK-REG-PRESSURE: bne .LBB0_1
 
 for.body:

diff --git a/test/TableGen/InvalidMCSchedClassDesc.td b/test/TableGen/InvalidMCSchedClassDesc.td
new file mode 100644 (file)
index 0000000..f1b4ed0
--- /dev/null
+++ b/test/TableGen/InvalidMCSchedClassDesc.td
@@ -0,0 +1,47 @@
+// RUN: llvm-tblgen -gen-subtarget -I %p/../../include %s 2>&1 | FileCheck %s
+// Check if it is valid MCSchedClassDesc if didn't have the resources. 
+
+include "llvm/Target/Target.td"
+
+def MyTarget : Target;
+
+let OutOperandList = (outs), InOperandList = (ins) in {
+  def Inst_A : Instruction; 
+  def Inst_B : Instruction; 
+}
+
+let CompleteModel = 0 in {
+  def SchedModel_A: SchedMachineModel;
+  def SchedModel_B: SchedMachineModel;
+  def SchedModel_C: SchedMachineModel;
+}
+
+// Inst_B didn't have the resoures, and it is invalid.
+// CHECK: SchedModel_ASchedClasses[] = {
+// CHECK: {DBGFIELD("Inst_A")             1
+// CHECK-NEXT: {DBGFIELD("Inst_B")             16383 
+let SchedModel = SchedModel_A in {
+  def Write_A : SchedWriteRes<[]>;
+  def : InstRW<[Write_A], (instrs Inst_A)>;
+}
+
+// Inst_A didn't have the resoures, and it is invalid.
+// CHECK: SchedModel_BSchedClasses[] = {
+// CHECK: {DBGFIELD("Inst_A")             16383 
+// CHECK-NEXT: {DBGFIELD("Inst_B")             1 
+let SchedModel = SchedModel_B in {
+  def Write_B: SchedWriteRes<[]>; 
+  def : InstRW<[Write_B], (instrs Inst_B)>;
+}
+
+// CHECK: SchedModel_CSchedClasses[] = {
+// CHECK: {DBGFIELD("Inst_A")             1
+// CHECK-NEXT: {DBGFIELD("Inst_B")             1
+let SchedModel = SchedModel_C in {
+  def Write_C: SchedWriteRes<[]>; 
+  def : InstRW<[Write_C], (instrs Inst_A, Inst_B)>;
+}
+
+def ProcessorA: ProcessorModel<"ProcessorA", SchedModel_A, []>;
+def ProcessorB: ProcessorModel<"ProcessorB", SchedModel_B, []>;
+def ProcessorC: ProcessorModel<"ProcessorC", SchedModel_C, []>;

diff --git a/utils/TableGen/SubtargetEmitter.cpp b/utils/TableGen/SubtargetEmitter.cpp
index f970572365022c984e0cb662bdec644cfe078286..9b094adb7d5ced321bfcc2c3b8fecb8dac987c64 100644 (file)
--- a/utils/TableGen/SubtargetEmitter.cpp
+++ b/utils/TableGen/SubtargetEmitter.cpp
@@ -1057,6 +1057,7 @@ void SubtargetEmitter::GenSchedClassTables(const CodeGenProcModel &ProcModel,
         LLVM_DEBUG(dbgs() << ProcModel.ModelName
                           << " does not have resources for class " << SC.Name
                           << '\n');
+        SCDesc.NumMicroOps = MCSchedClassDesc::InvalidNumMicroOps;
       }
     }
     // Sum resources across all operand writes.