efuse: set timing configuration before writing

diff --git a/components/efuse/src/esp_efuse_utility.c b/components/efuse/src/esp_efuse_utility.c
index 03ea2608401fc537a018548a2004af3c2879ff63..a4a4d6d87e97b060b43120d465d41756ffe42f92 100644 (file)
--- a/components/efuse/src/esp_efuse_utility.c
+++ b/components/efuse/src/esp_efuse_utility.c
@@ -15,6 +15,7 @@
 #include "esp_efuse_utility.h"
 
 #include "soc/efuse_periph.h"
+#include "esp32/clk.h"
 #include "esp_log.h"
 #include "assert.h"
 #include "sdkconfig.h"
@@ -209,6 +210,25 @@ void esp_efuse_utility_burn_efuses(void)
         }
     }
 #else
+    // Update Efuse timing configuration
+    uint32_t apb_freq_mhz = esp_clk_apb_freq() / 1000000;
+    uint32_t clk_sel0, clk_sel1, dac_clk_div;
+    if (apb_freq_mhz <= 26) {
+        clk_sel0 = 250;
+        clk_sel1 = 255;
+        dac_clk_div = 52;
+    } else if (apb_freq_mhz <= 40) {
+        clk_sel0 = 160;
+        clk_sel1 = 255;
+        dac_clk_div = 80;
+    } else {
+        clk_sel0 = 80;
+        clk_sel1 = 128;
+        dac_clk_div = 100;
+    }
+    REG_SET_FIELD(EFUSE_DAC_CONF_REG, EFUSE_DAC_CLK_DIV, dac_clk_div);
+    REG_SET_FIELD(EFUSE_CLK_REG, EFUSE_CLK_SEL0, clk_sel0);
+    REG_SET_FIELD(EFUSE_CLK_REG, EFUSE_CLK_SEL1, clk_sel1);
     // Permanently update values written to the efuse write registers
     REG_WRITE(EFUSE_CONF_REG, EFUSE_CONF_WRITE);
     REG_WRITE(EFUSE_CMD_REG,  EFUSE_CMD_PGM);