[AArch64][GlobalISel] Lower G_SHUFFLE_VECTOR with 1 elt src and 1 elt mask.

Again, it's weird that these are allowed. Since lowering support was added in
r368709 we started crashing on compiling the neon intrinsics test in the test
suite. This fixes the lowering to fold the 1 elt src/mask case into copies.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@369135 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/CodeGen/GlobalISel/LegalizerHelper.cpp b/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
index ad1a41b09dd4ac5a90abf6b59908e70f3deb7816..c5f23859783685c8985d0592107eca0722510b9d 100644 (file)
--- a/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
+++ b/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
@@ -3823,7 +3823,6 @@ LegalizerHelper::lowerShuffleVector(MachineInstr &MI) {
   Register Src1Reg = MI.getOperand(2).getReg();
   LLT Src0Ty = MRI.getType(Src0Reg);
   LLT DstTy = MRI.getType(DstReg);
-  LLT EltTy = DstTy.getElementType();
   LLT IdxTy = LLT::scalar(32);
 
   const Constant *ShufMask = MI.getOperand(3).getShuffleMask();
@@ -3831,8 +3830,25 @@ LegalizerHelper::lowerShuffleVector(MachineInstr &MI) {
   SmallVector<int, 32> Mask;
   ShuffleVectorInst::getShuffleMask(ShufMask, Mask);
 
+  if (DstTy.isScalar()) {
+    if (Src0Ty.isVector())
+      return UnableToLegalize;
+
+    // This is just a SELECT.
+    assert(Mask.size() == 1 && "Expected a single mask element");
+    Register Val;
+    if (Mask[0] < 0 || Mask[0] > 1)
+      Val = MIRBuilder.buildUndef(DstTy).getReg(0);
+    else
+      Val = Mask[0] == 0 ? Src0Reg : Src1Reg;
+    MIRBuilder.buildCopy(DstReg, Val);
+    MI.eraseFromParent();
+    return Legalized;
+  }
+
   Register Undef;
   SmallVector<Register, 32> BuildVec;
+  LLT EltTy = DstTy.getElementType();
 
   for (int Idx : Mask) {
     if (Idx < 0) {

diff --git a/test/CodeGen/AArch64/GlobalISel/legalize-shuffle-vector.mir b/test/CodeGen/AArch64/GlobalISel/legalize-shuffle-vector.mir
index 73872091affd703ad041d2ee09d5c0461657fa5d..9d95c35f05a9b27605a1fb2d5b672b5c9a004e39 100644 (file)
--- a/test/CodeGen/AArch64/GlobalISel/legalize-shuffle-vector.mir
+++ b/test/CodeGen/AArch64/GlobalISel/legalize-shuffle-vector.mir
@@ -44,3 +44,29 @@ body:             |
     RET_ReallyLR implicit $q0
 
 ...
+---
+name:            shuffle_1elt_mask
+alignment:       2
+tracksRegLiveness: true
+body:             |
+  bb.1:
+    liveins: $d0, $d1
+
+    ; CHECK-LABEL: name: shuffle_1elt_mask
+    ; CHECK: liveins: $d0, $d1
+    ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $d0
+    ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $d1
+    ; CHECK: [[COPY2:%[0-9]+]]:_(s64) = COPY [[COPY]](s64)
+    ; CHECK: [[COPY3:%[0-9]+]]:_(s64) = COPY [[COPY1]](s64)
+    ; CHECK: $d0 = COPY [[COPY2]](s64)
+    ; CHECK: $d1 = COPY [[COPY3]](s64)
+    ; CHECK: RET_ReallyLR implicit $d0, implicit $d1
+    %0:_(s64) = COPY $d0
+    %1:_(s64) = COPY $d1
+    %3:_(s64) = G_SHUFFLE_VECTOR %0:_(s64), %1:_, shufflemask(0)
+    %4:_(s64) = G_SHUFFLE_VECTOR %0:_(s64), %1:_, shufflemask(1)
+    $d0 = COPY %3(s64)
+    $d1 = COPY %4(s64)
+    RET_ReallyLR implicit $d0, implicit $d1
+
+...