efuse/add cpu freq rating

This commit adds support for CPU max freqeuency rating
bits in CPU. Bootloader will now print an error if attempting
to 160MHz rated ESP32 at 240MHz.

EFUSE_CHIP_VER_RESERVE has been replaced by the
frequency rating bits. Dependancies on EFUSE_CHIP_VER_RESERVE
have been changed to use EFUSE_CHIP_VER_PKG

diff --git a/components/bootloader/subproject/main/bootloader_start.c b/components/bootloader/subproject/main/bootloader_start.c
index 56839e2f86c012d6e3717d6ee726e798ee8af32a..e7c8ab56bf127c68fdf30e439c6cf7168749a96c 100644 (file)
--- a/components/bootloader/subproject/main/bootloader_start.c
+++ b/components/bootloader/subproject/main/bootloader_start.c
@@ -447,6 +447,14 @@ void bootloader_main()
 {
     vddsdio_configure();
     flash_gpio_configure();
+#if (CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ == 240)
+    //Check if ESP32 is rated for a CPU frequency of 160MHz only
+    if (REG_GET_BIT(EFUSE_BLK0_RDATA3_REG, EFUSE_RD_CHIP_CPU_FREQ_RATED) &&
+        REG_GET_BIT(EFUSE_BLK0_RDATA3_REG, EFUSE_RD_CHIP_CPU_FREQ_LOW)) {
+        ESP_LOGE(TAG, "Chip CPU frequency rated for 160MHz. Modify CPU frequency in menuconfig");
+        return;
+    }
+#endif
     bootloader_clock_configure();
     uart_console_configure();
     wdt_reset_check();

diff --git a/components/bootloader/subproject/main/flash_qio_mode.c b/components/bootloader/subproject/main/flash_qio_mode.c
index 79b145c9761b5aa4bcd2fb29fa940a0b389860bc..001b76f41d5dd437c58379c4258c7736e3f6eba6 100644 (file)
--- a/components/bootloader/subproject/main/flash_qio_mode.c
+++ b/components/bootloader/subproject/main/flash_qio_mode.c
@@ -174,13 +174,15 @@ static esp_err_t enable_qio_mode(read_status_fn_t read_status_fn,
         // spiconfig specifies a custom efuse pin configuration. This config defines all pins -except- WP,
         // which is compiled into the bootloader instead.
         //
-        // Most commonly an overriden pin mapping means ESP32-D2WD. Warn if chip is ESP32-D2WD
-        // but someone has changed the WP pin assignment from that chip's WP pin.
-        uint32_t chip_ver = REG_GET_FIELD(EFUSE_BLK0_RDATA3_REG, EFUSE_RD_CHIP_VER_RESERVE);
-        uint32_t pkg_ver = chip_ver & 0x7;
-        const int PKG_VER_ESP32_D2WD = 2; // TODO: use chip detection API once available
-        if (pkg_ver == PKG_VER_ESP32_D2WD && CONFIG_BOOTLOADER_SPI_WP_PIN != ESP32_D2WD_WP_GPIO) {
-            ESP_LOGW(TAG, "Chip is ESP32-D2WD but flash WP pin is different value to internal flash");
+        // Most commonly an overriden pin mapping means ESP32-D2WD or ESP32-PICOD4.
+        //Warn if chip is ESP32-D2WD/ESP32-PICOD4 but someone has changed the WP pin
+        //assignment from that chip's WP pin.
+        uint32_t pkg_ver = REG_GET_FIELD(EFUSE_BLK0_RDATA3_REG, EFUSE_RD_CHIP_VER_PKG);
+        if (CONFIG_BOOTLOADER_SPI_WP_PIN != ESP32_D2WD_WP_GPIO  &&
+            (pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32D2WDQ5 ||
+             pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32PICOD2 ||
+             pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32PICOD4)) {
+            ESP_LOGW(TAG, "Chip is ESP32-D2WD/ESP32-PICOD4 but flash WP pin is different value to internal flash");
         }
     }
 

diff --git a/components/soc/esp32/include/soc/efuse_reg.h b/components/soc/esp32/include/soc/efuse_reg.h
index f95eb50ab28eea39729a981aef5d8b9f1973872c..0be58c4651433dc3b68ae3280f63ee1d4136a5e1 100644 (file)
--- a/components/soc/esp32/include/soc/efuse_reg.h
+++ b/components/soc/esp32/include/soc/efuse_reg.h
@@ -91,15 +91,21 @@
 #define EFUSE_RD_BLK3_PART_RESERVE_M  ((EFUSE_RD_BLK3_PART_RESERVE_V)<<(EFUSE_RD_BLK3_PART_RESERVE_S))
 #define EFUSE_RD_BLK3_PART_RESERVE_V  0x1
 #define EFUSE_RD_BLK3_PART_RESERVE_S  14
-/* EFUSE_RD_CHIP_VER_RESERVE : R/W ;bitpos:[13:12] ;default: 2'b0 ; */
-/*description: */
-#define EFUSE_RD_CHIP_VER_RESERVE  0x00000003
-#define EFUSE_RD_CHIP_VER_RESERVE_M  ((EFUSE_RD_CHIP_VER_RESERVE_V)<<(EFUSE_RD_CHIP_VER_RESERVE_S))
-#define EFUSE_RD_CHIP_VER_RESERVE_V  0x3
-#define EFUSE_RD_CHIP_VER_RESERVE_S  12
-/* EFUSE_RD_CHIP_VER : R/W ;bitpos:[11:9] ;default: 3'b0 ; */
+/* EFUSE_RD_CHIP_CPU_FREQ_RATED : R/W ;bitpos:[13] ;default: 1'b0 ; */
+/*description: If set, the ESP32's maximum CPU frequency has been rated*/
+#define EFUSE_RD_CHIP_CPU_FREQ_RATED  (BIT(13))
+#define EFUSE_RD_CHIP_CPU_FREQ_RATED_M  ((EFUSE_RD_CHIP_CPU_FREQ_RATED_V)<<(EFUSE_RD_CHIP_CPU_FREQ_RATED_S))
+#define EFUSE_RD_CHIP_CPU_FREQ_RATED_V  0x1
+#define EFUSE_RD_CHIP_CPU_FREQ_RATED_S  13
+/* EFUSE_RD_CHIP_CPU_FREQ_LOW : R/W ;bitpos:[12] ;default: 1'b0 ; */
+/*description: If set alongside EFUSE_RD_CHIP_CPU_FREQ_RATED, the ESP32's max CPU frequency is rated for 160MHz. 240MHz otherwise*/
+#define EFUSE_RD_CHIP_CPU_FREQ_LOW  (BIT(12))
+#define EFUSE_RD_CHIP_CPU_FREQ_LOW_M  ((EFUSE_RD_CHIP_CPU_FREQ_LOW_V)<<(EFUSE_RD_CHIP_CPU_FREQ_LOW_S))
+#define EFUSE_RD_CHIP_CPU_FREQ_LOW_V  0x1
+#define EFUSE_RD_CHIP_CPU_FREQ_LOW_S  12
+/* EFUSE_RD_CHIP_VER_PKG : R/W ;bitpos:[11:9] ;default: 3'b0 ; */
 /*description: chip package */
-#define EFUSE_RD_CHIP_VER  0x00000007
+#define EFUSE_RD_CHIP_VER_PKG  0x00000007
 #define EFUSE_RD_CHIP_VER_PKG_M  ((EFUSE_RD_CHIP_VER_PKG_V)<<(EFUSE_RD_CHIP_VER_PKG_S))
 #define EFUSE_RD_CHIP_VER_PKG_V  0x7
 #define EFUSE_RD_CHIP_VER_PKG_S  9
@@ -341,18 +347,29 @@
 #define EFUSE_BLK3_PART_RESERVE_M  ((EFUSE_BLK3_PART_RESERVE_V)<<(EFUSE_BLK3_PART_RESERVE_S))
 #define EFUSE_BLK3_PART_RESERVE_V  0x1
 #define EFUSE_BLK3_PART_RESERVE_S  14
-/* EFUSE_CHIP_VER_RESERVE : R/W ;bitpos:[13:12] ;default: 2'b0 ; */
-/*description: */
-#define EFUSE_CHIP_VER_RESERVE  0x00000003
-#define EFUSE_CHIP_VER_RESERVE_M  ((EFUSE_CHIP_VER_RESERVE_V)<<(EFUSE_CHIP_VER_RESERVE_S))
-#define EFUSE_CHIP_VER_RESERVE_V  0x3
-#define EFUSE_CHIP_VER_RESERVE_S  12
-/* EFUSE_CHIP_VER : R/W ;bitpos:[11:9] ;default: 3'b0 ; */
+/* EFUSE_CHIP_CPU_FREQ_RATED : R/W ;bitpos:[13] ;default: 1'b0 ; */
+/*description: If set, the ESP32's maximum CPU frequency has been rated*/
+#define EFUSE_CHIP_CPU_FREQ_RATED  (BIT(13))
+#define EFUSE_CHIP_CPU_FREQ_RATED_M  ((EFUSE_CHIP_CPU_FREQ_RATED_V)<<(EFUSE_CHIP_CPU_FREQ_RATED_S))
+#define EFUSE_CHIP_CPU_FREQ_RATED_V  0x1
+#define EFUSE_CHIP_CPU_FREQ_RATED_S  13
+/* EFUSE_CHIP_CPU_FREQ_LOW : R/W ;bitpos:[12] ;default: 1'b0 ; */
+/*description: If set alongside EFUSE_CHIP_CPU_FREQ_RATED, the ESP32's max CPU frequency is rated for 160MHz. 240MHz otherwise*/
+#define EFUSE_CHIP_CPU_FREQ_LOW  (BIT(12))
+#define EFUSE_CHIP_CPU_FREQ_LOW_M  ((EFUSE_CHIP_CPU_FREQ_LOW_V)<<(EFUSE_CHIP_CPU_FREQ_LOW_S))
+#define EFUSE_CHIP_CPU_FREQ_LOW_V  0x1
+#define EFUSE_CHIP_CPU_FREQ_LOW_S  12
+/* EFUSE_CHIP_VER_PKG : R/W ;bitpos:[11:9] ;default: 3'b0 ; */
 /*description: */
 #define EFUSE_CHIP_VER_PKG  0x00000007
 #define EFUSE_CHIP_VER_PKG_M  ((EFUSE_CHIP_VER_PKG_V)<<(EFUSE_CHIP_VER_PKG_S))
 #define EFUSE_CHIP_VER_PKG_V  0x7
 #define EFUSE_CHIP_VER_PKG_S  9
+#define EFUSE_CHIP_VER_PKG_ESP32D0WDQ6  0
+#define EFUSE_CHIP_VER_PKG_ESP32D0WDQ5  1
+#define EFUSE_CHIP_VER_PKG_ESP32D2WDQ5  2
+#define EFUSE_CHIP_VER_PKG_ESP32PICOD2  4
+#define EFUSE_CHIP_VER_PKG_ESP32PICOD4  5
 /* EFUSE_SPI_PAD_CONFIG_HD : R/W ;bitpos:[8:4] ;default: 5'b0 ; */
 /*description: program for SPI_pad_config_hd*/
 #define EFUSE_SPI_PAD_CONFIG_HD  0x0000001F