ARM: Add ACLE memory barrier intrinsic mapping

git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@213261 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Headers/arm_acle.h b/lib/Headers/arm_acle.h
index c51a5dcbef2dfa2d545f40622be0d519d10e0ff0..a0fd6894ab9692f442abbb4bdd12d1d41bbdb0ff 100644 (file)
--- a/lib/Headers/arm_acle.h
+++ b/lib/Headers/arm_acle.h
@@ -33,8 +33,15 @@
 #if defined(__cplusplus)
 extern "C" {
 #endif
- 
+
 /* 8 SYNCHRONIZATION, BARRIER AND HINT INTRINSICS */
+/* 8.3 Memory barriers */
+#if !defined(_MSC_VER)
+#define __dmb(i) __builtin_arm_dmb(i)
+#define __dsb(i) __builtin_arm_dsb(i)
+#define __isb(i) __builtin_arm_isb(i)
+#endif
+
 /* 8.4 Hints */
 
 #if !defined(_MSC_VER)

diff --git a/test/CodeGen/arm_acle.c b/test/CodeGen/arm_acle.c
index 41ebe1504c5d45cba7d2e95beaa967da8d037e21..e4d795a1542945585ad15db3777668570ea9b88a 100644 (file)
--- a/test/CodeGen/arm_acle.c
+++ b/test/CodeGen/arm_acle.c
@@ -3,8 +3,30 @@
 
 #include <arm_acle.h>
 
-/* Hints */
+/* 8 SYNCHRONIZATION, BARRIER AND HINT INTRINSICS */
+/* 8.3 Memory Barriers */
+// ARM-LABEL: test_dmb
+// AArch32: call void @llvm.arm.dmb(i32 1)
+// AArch64: call void @llvm.aarch64.dmb(i32 1)
+void test_dmb(void) {
+  __dmb(1);
+}
+
+// ARM-LABEL: test_dsb
+// AArch32: call void @llvm.arm.dsb(i32 2)
+// AArch64: call void @llvm.aarch64.dsb(i32 2)
+void test_dsb(void) {
+  __dsb(2);
+}
+
+// ARM-LABEL: test_isb
+// AArch32: call void @llvm.arm.isb(i32 3)
+// AArch64: call void @llvm.aarch64.isb(i32 3)
+void test_isb(void) {
+  __isb(3);
+}
 
+/* 8.4 Hints */
 // ARM-LABEL: test_yield
 // AArch32: call void @llvm.arm.hint(i32 1)
 // AArch64: call void @llvm.aarch64.hint(i32 1)