IRgen/ABI/ARM: Trust the backend to pass vectors correctly for the given ABI.

 - Therefore, we can lower out the NEON wrapper structs and pass the vectors
   directly. This makes a huge difference in the cleanliness of the IR after
   optimization.
 - I will trust, but verify, via future ABITest testing (for APCS-GNU, at
   least).

git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@114618 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/CodeGen/TargetInfo.cpp b/lib/CodeGen/TargetInfo.cpp
index 34a6d37726b5f5065f543037523ae1e216e58a08..f1da3c3903593356c5fa9bbe984626fc13a25d86 100644 (file)
--- a/lib/CodeGen/TargetInfo.cpp
+++ b/lib/CodeGen/TargetInfo.cpp
@@ -2272,6 +2272,17 @@ ABIArgInfo ARMABIInfo::classifyArgumentType(QualType Ty) const {
   if (isRecordWithNonTrivialDestructorOrCopyConstructor(Ty))
     return ABIArgInfo::getIndirect(0, /*ByVal=*/false);
 
+  // NEON vectors are implemented as (theoretically) opaque structures wrapping
+  // the underlying vector type. We trust the backend to pass the underlying
+  // vectors appropriately, so we can unwrap the structs which generally will
+  // lead to much cleaner IR.
+  if (const Type *SeltTy = isSingleElementStruct(Ty, getContext())) {
+    if (SeltTy->isVectorType())
+      return ABIArgInfo::getDirect(CGT.ConvertType(QualType(SeltTy, 0)));
+  }
+
+  // Otherwise, pass by coercing to a structure of the appropriate size.
+  //
   // FIXME: This is kind of nasty... but there isn't much choice because the ARM
   // backend doesn't support byval.
   // FIXME: This doesn't handle alignment > 64 bits.

diff --git a/test/CodeGen/arm-vector-arguments.c b/test/CodeGen/arm-vector-arguments.c
new file mode 100644 (file)
index 0000000..0d1bdd1
--- /dev/null
+++ b/test/CodeGen/arm-vector-arguments.c
@@ -0,0 +1,13 @@
+// RUN: %clang_cc1 -triple thumbv7-apple-darwin9 \
+// RUN:   -target-abi apcs-gnu \
+// RUN:   -target-cpu cortex-a8 \
+// RUN:   -mfloat-abi soft \
+// RUN:   -target-feature +soft-float-abi \
+// RUN:   -emit-llvm -w -o - %s | FileCheck %s
+
+#include <arm_neon.h>
+
+// CHECK: define void @f0(%struct.__simd128_int8_t* sret %agg.result, <16 x i8> %{{.*}}, <16 x i8> %{{.*}})
+int8x16_t f0(int8x16_t a0, int8x16_t a1) {
+  return vzipq_s8(a0, a1).val[0];
+}