[Hexagon] Add patterns to select A2_combine_ll and its variants

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318876 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/Hexagon/HexagonPatterns.td b/lib/Target/Hexagon/HexagonPatterns.td
index 05865c43f2d0e13c5ce747775a304583690ee02a..00ce6916fbdf705f8f8e17785e1166e31248fdd0 100644 (file)
--- a/lib/Target/Hexagon/HexagonPatterns.td
+++ b/lib/Target/Hexagon/HexagonPatterns.td
@@ -1130,6 +1130,16 @@ def: Pat<(or (or (shl (or (shl (i32 (extloadi8 (add I32:$b, 3))),
              (zextloadi8 I32:$b)),
          (A2_swiz (L2_loadri_io IntRegs:$b, 0))>;
 
+let AddedComplexity = 200 in {
+  def: Pat<(or (shl I32:$Rt, (i32 16)), (and I32:$Rs, (i32 65535))),
+           (A2_combine_ll I32:$Rt, I32:$Rs)>;
+  def: Pat<(or (shl I32:$Rt, (i32 16)), (srl I32:$Rs, (i32 16))),
+           (A2_combine_lh I32:$Rt, I32:$Rs)>;
+  def: Pat<(or (and I32:$Rt, (i32 268431360)), (and I32:$Rs, (i32 65535))),
+           (A2_combine_hl I32:$Rt, I32:$Rs)>;
+  def: Pat<(or (and I32:$Rt, (i32 268431360)), (srl I32:$Rs, (i32 16))),
+           (A2_combine_hh I32:$Rt, I32:$Rs)>;
+}
 
 def SDTHexagonVShift
   : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>, SDTCisVec<0>, SDTCisVT<2, i32>]>;

diff --git a/test/CodeGen/Hexagon/isel-combine-half.ll b/test/CodeGen/Hexagon/isel-combine-half.ll
new file mode 100644 (file)
index 0000000..c5cb5a9
--- /dev/null
+++ b/test/CodeGen/Hexagon/isel-combine-half.ll
@@ -0,0 +1,43 @@
+; RUN: llc -march=hexagon < %s | FileCheck %s
+
+; CHECK-LABEL: A2_combine_ll:
+; CHECK: combine(r1.l,r0.l)
+define i32 @A2_combine_ll(i32 %a0, i32 %a1) #0 {
+b2:
+  %v3 = and i32 %a0, 65535
+  %v4 = shl i32 %a1, 16
+  %v5 = or i32 %v3, %v4
+  ret i32 %v5
+}
+
+; CHECK-LABEL: A2_combine_lh:
+; CHECK: combine(r1.l,r0.h)
+define i32 @A2_combine_lh(i32 %a0, i32 %a1) #0 {
+b2:
+  %v3 = lshr i32 %a0, 16
+  %v4 = shl i32 %a1, 16
+  %v5 = or i32 %v4, %v3
+  ret i32 %v5
+}
+
+; CHECK-LABEL: A2_combine_hl:
+; CHECK: combine(r1.h,r0.l)
+define i32 @A2_combine_hl(i32 %a0, i32 %a1) #0 {
+b2:
+  %v3 = and i32 %a0, 65535
+  %v4 = and i32 %a1, 268431360
+  %v5 = or i32 %v3, %v4
+  ret i32 %v5
+}
+
+; CHECK-LABEL: A2_combine_hh:
+; CHECK: combine(r1.h,r0.h)
+define i32 @A2_combine_hh(i32 %a0, i32 %a1) #0 {
+b2:
+  %v3 = lshr i32 %a0, 16
+  %v4 = and i32 %a1, 268431360
+  %v5 = or i32 %v3, %v4
+  ret i32 %v5
+}
+
+attributes #0 = { noinline nounwind optnone readnone }

diff --git a/test/CodeGen/Hexagon/isel-prefer.ll b/test/CodeGen/Hexagon/isel-prefer.ll
index 7094544f54b74d07c3774bc47f1a6eef4b30f472..4cef0039cebcb8bcdf0c1e20221fd2f66c89400c 100644 (file)
--- a/test/CodeGen/Hexagon/isel-prefer.ll
+++ b/test/CodeGen/Hexagon/isel-prefer.ll
@@ -64,4 +64,4 @@ b1:
   ret i64 %v4
 }
 
-attributes #0 = { nounwind readnone }
+attributes #0 = { optnone noinline nounwind readnone }