ARM: TLS calling convention doesn't preserve r9 or r12 on Darwin.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300726 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/ARM/ARMCallingConv.td b/lib/Target/ARM/ARMCallingConv.td
index 7a7b7fede7c832fbe1c00ea17ce07378526d6fb9..bc7afdb7f1c9f9e0c11c50b2bb076c85a456694c 100644 (file)
--- a/lib/Target/ARM/ARMCallingConv.td
+++ b/lib/Target/ARM/ARMCallingConv.td
@@ -273,9 +273,9 @@ def CSR_iOS_SwiftError : CalleeSavedRegs<(sub CSR_iOS, R8)>;
 def CSR_iOS_ThisReturn : CalleeSavedRegs<(add LR, R7, R6, R5, R4,
                                          (sub CSR_AAPCS_ThisReturn, R9))>;
 
-def CSR_iOS_TLSCall : CalleeSavedRegs<(add LR, SP,
-                                           (sequence "R%u", 12, 1),
-                                           (sequence "D%u", 31, 0))>;
+def CSR_iOS_TLSCall
+    : CalleeSavedRegs<(add LR, SP, (sub(sequence "R%u", 12, 1), R9, R12),
+                      (sequence "D%u", 31, 0))>;
 
 // C++ TLS access function saves all registers except SP. Try to match
 // the order of CSRs in CSR_iOS.

diff --git a/test/CodeGen/ARM/darwin-tls-preserved.ll b/test/CodeGen/ARM/darwin-tls-preserved.ll
new file mode 100644 (file)
index 0000000..4969fab
--- /dev/null
+++ b/test/CodeGen/ARM/darwin-tls-preserved.ll
@@ -0,0 +1,24 @@
+; RUN: llc -mtriple=thumbv7k-apple-watchos2.0 -arm-atomic-cfg-tidy=0 -o - %s | FileCheck %s
+
+@tls_var = thread_local global i32 0
+
+; r9 and r12 can be live across the asm, but those get clobbered by the TLS
+; access (in a different BB to order it).
+define i32 @test_regs_preserved(i32* %ptr1, i32* %ptr2, i1 %tst1) {
+; CHECK-LABEL: test_regs_preserved:
+; CHECK: str {{.*}}, [sp
+; CHECK: mov {{.*}}, r12
+entry:
+  call void asm sideeffect "", "~{r0},~{r1},~{r2},~{r3},~{r4},~{r5},~{r6},~{r7},~{r8},~{r10},~{r11},~{r13},~{lr}"()
+  br i1 %tst1, label %get_tls, label %done
+
+get_tls:
+  %val = load i32, i32* @tls_var
+  br label %done
+
+done:
+  %res = phi i32 [%val, %get_tls], [0, %entry]
+  store i32 42, i32* %ptr1
+  store i32 42, i32* %ptr2
+  ret i32 %res
+}