#!/usr/bin/env perl
-#******************************************************************************
-#* Copyright(c) 2012, Intel Corp.
-#* Developers and authors:
-#* Shay Gueron (1, 2), and Vlad Krasnov (1)
-#* (1) Intel Corporation, Israel Development Center, Haifa, Israel
-#* (2) University of Haifa, Israel
-#******************************************************************************
-#* LICENSE:
-#* This submission to OpenSSL is to be made available under the OpenSSL
-#* license, and only to the OpenSSL project, in order to allow integration
-#* into the publicly distributed code.
-#* The use of this code, or portions of this code, or concepts embedded in
-#* this code, or modification of this code and/or algorithm(s) in it, or the
-#* use of this code for any other purpose than stated above, requires special
-#* licensing.
-#******************************************************************************
-#* DISCLAIMER:
-#* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS AND THE COPYRIGHT OWNERS
-#* ``AS IS''. ANY EXPRESSED OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
-#* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-#* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE CONTRIBUTORS OR THE COPYRIGHT
-#* OWNERS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
-#* OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-#* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-#* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-#* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-#* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-#* POSSIBILITY OF SUCH DAMAGE.
-#******************************************************************************
-#* Reference:
-#* [1] S. Gueron, V. Krasnov: "Software Implementation of Modular
-#* Exponentiation, Using Advanced Vector Instructions Architectures",
-#* F. Ozbudak and F. Rodriguez-Henriquez (Eds.): WAIFI 2012, LNCS 7369,
-#* pp. 119?135, 2012. Springer-Verlag Berlin Heidelberg 2012
-#* [2] S. Gueron: "Efficient Software Implementations of Modular
-#* Exponentiation", Journal of Cryptographic Engineering 2:31-43 (2012).
-#* [3] S. Gueron, V. Krasnov: "Speeding up Big-numbers Squaring",IEEE
-#* Proceedings of 9th International Conference on Information Technology:
-#* New Generations (ITNG 2012), pp.821-823 (2012)
-#* [4] S. Gueron, V. Krasnov: "[PATCH] Efficient and side channel analysis
-#* resistant 1024-bit modular exponentiation, for optimizing RSA2048
-#* on AVX2 capable x86_64 platforms",
-#* http://rt.openssl.org/Ticket/Display.html?id=2850&user=guest&pass=guest
-#******************************************************************************
-
-# +10% improvement by <appro@openssl.org>
+##############################################################################
+# #
+# Copyright (c) 2012, Intel Corporation #
+# #
+# All rights reserved. #
+# #
+# Redistribution and use in source and binary forms, with or without #
+# modification, are permitted provided that the following conditions are #
+# met: #
+# #
+# * Redistributions of source code must retain the above copyright #
+# notice, this list of conditions and the following disclaimer. #
+# #
+# * Redistributions in binary form must reproduce the above copyright #
+# notice, this list of conditions and the following disclaimer in the #
+# documentation and/or other materials provided with the #
+# distribution. #
+# #
+# * Neither the name of the Intel Corporation nor the names of its #
+# contributors may be used to endorse or promote products derived from #
+# this software without specific prior written permission. #
+# #
+# #
+# THIS SOFTWARE IS PROVIDED BY INTEL CORPORATION ""AS IS"" AND ANY #
+# EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE #
+# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR #
+# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL INTEL CORPORATION OR #
+# CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
+# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, #
+# PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR #
+# PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF #
+# LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
+# NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS #
+# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. #
+# #
+##############################################################################
+# Developers and authors: #
+# Shay Gueron (1, 2), and Vlad Krasnov (1) #
+# (1) Intel Corporation, Israel Development Center, Haifa, Israel #
+# (2) University of Haifa, Israel #
+##############################################################################
+# Reference: #
+# [1] S. Gueron, V. Krasnov: "Software Implementation of Modular #
+# Exponentiation, Using Advanced Vector Instructions Architectures", #
+# F. Ozbudak and F. Rodriguez-Henriquez (Eds.): WAIFI 2012, LNCS 7369, #
+# pp. 119?135, 2012. Springer-Verlag Berlin Heidelberg 2012 #
+# [2] S. Gueron: "Efficient Software Implementations of Modular #
+# Exponentiation", Journal of Cryptographic Engineering 2:31-43 (2012). #
+# [3] S. Gueron, V. Krasnov: "Speeding up Big-numbers Squaring",IEEE #
+# Proceedings of 9th International Conference on Information Technology: #
+# New Generations (ITNG 2012), pp.821-823 (2012) #
+# [4] S. Gueron, V. Krasnov: "[PATCH] Efficient and side channel analysis #
+# resistant 1024-bit modular exponentiation, for optimizing RSA2048 #
+# on AVX2 capable x86_64 platforms", #
+# http://rt.openssl.org/Ticket/Display.html?id=2850&user=guest&pass=guest#
+##############################################################################
+#
+# +13% improvement over original submission by <appro@openssl.org>
#
# rsa2048 sign/sec OpenSSL 1.0.1 scalar(*) this
-# 2.3GHz Haswell 621 732/+18% 1112/+79%
+# 2.3GHz Haswell 621 765/+23% 1113/+79%
#
# (*) if system doesn't support AVX2, for reference purposes;
push %r13
push %r14
push %r15
+ vzeroupper
___
$code.=<<___ if ($win64);
lea -0xa8(%rsp),%rsp
- movaps %xmm6,-0xd8(%rax)
- movaps %xmm7,-0xc8(%rax)
- movaps %xmm8,-0xb8(%rax)
- movaps %xmm9,-0xa8(%rax)
- movaps %xmm10,-0x98(%rax)
- movaps %xmm11,-0x88(%rax)
- movaps %xmm12,-0x78(%rax)
- movaps %xmm13,-0x68(%rax)
- movaps %xmm14,-0x58(%rax)
- movaps %xmm15,-0x48(%rax)
+ vmovaps %xmm6,-0xd8(%rax)
+ vmovaps %xmm7,-0xc8(%rax)
+ vmovaps %xmm8,-0xb8(%rax)
+ vmovaps %xmm9,-0xa8(%rax)
+ vmovaps %xmm10,-0x98(%rax)
+ vmovaps %xmm11,-0x88(%rax)
+ vmovaps %xmm12,-0x78(%rax)
+ vmovaps %xmm13,-0x68(%rax)
+ vmovaps %xmm14,-0x58(%rax)
+ vmovaps %xmm15,-0x48(%rax)
.Lsqr_1024_body:
___
$code.=<<___;
mov %rax,%rbp
- vzeroall
mov %rdx, $np # reassigned argument
sub \$$FrameSize, %rsp
mov $np, $tmp
and \$4095, $tmp # see if $np crosses page
add \$32*10, $tmp
shr \$12, $tmp
+ vpxor $ACC9,$ACC9,$ACC9
jz .Lsqr_1024_no_n_copy
# unaligned 256-bit load that crosses page boundary can
vmovdqu $ACC6, 32*6-128($np)
vmovdqu $ACC7, 32*7-128($np)
vmovdqu $ACC8, 32*8-128($np)
- vmovdqu $ACC9, 32*9-128($np) # $ACC9 is zero after vzeroall
+ vmovdqu $ACC9, 32*9-128($np) # $ACC9 is zero
.Lsqr_1024_no_n_copy:
and \$-1024, %rsp
push %r15
___
$code.=<<___ if ($win64);
+ vzeroupper
lea -0xa8(%rsp),%rsp
- movaps %xmm6,-0xd8(%rax)
- movaps %xmm7,-0xc8(%rax)
- movaps %xmm8,-0xb8(%rax)
- movaps %xmm9,-0xa8(%rax)
- movaps %xmm10,-0x98(%rax)
- movaps %xmm11,-0x88(%rax)
- movaps %xmm12,-0x78(%rax)
- movaps %xmm13,-0x68(%rax)
- movaps %xmm14,-0x58(%rax)
- movaps %xmm15,-0x48(%rax)
+ vmovaps %xmm6,-0xd8(%rax)
+ vmovaps %xmm7,-0xc8(%rax)
+ vmovaps %xmm8,-0xb8(%rax)
+ vmovaps %xmm9,-0xa8(%rax)
+ vmovaps %xmm10,-0x98(%rax)
+ vmovaps %xmm11,-0x88(%rax)
+ vmovaps %xmm12,-0x78(%rax)
+ vmovaps %xmm13,-0x68(%rax)
+ vmovaps %xmm14,-0x58(%rax)
+ vmovaps %xmm15,-0x48(%rax)
.Lmul_1024_body:
___
$code.=<<___;
# cross page boundary, swap it with $bp [meaning that caller
# is advised to lay down $ap and $bp next to each other, so
# that only one can cross page boundary].
+ .byte 0x67,0x67
mov $ap, $tmp
and \$4095, $tmp
add \$32*10, $tmp
and \$4095, $tmp # see if $np crosses page
add \$32*10, $tmp
+ .byte 0x67,0x67
shr \$12, $tmp
jz .Lmul_1024_no_n_copy
vpbroadcastq ($bp), $Bi
vmovdqu $ACC0, (%rsp) # clear top of stack
xor $r0, $r0
+ .byte 0x67
xor $r1, $r1
xor $r2, $r2
xor $r3, $r3
___
$code.=<<___ if ($win64);
lea -0x88(%rsp),%rax
+ vzeroupper
.LSEH_begin_rsaz_1024_gather5:
# I can't trust assembler to use specific encoding:-(
.byte 0x48,0x8d,0x60,0xe0 #lea -0x20(%rax),%rsp
- .byte 0x0f,0x29,0x70,0xe0 #movaps %xmm6,-0x20(%rax)
- .byte 0x0f,0x29,0x78,0xf0 #movaps %xmm7,-0x10(%rax)
- .byte 0x44,0x0f,0x29,0x00 #movaps %xmm8,0(%rax)
- .byte 0x44,0x0f,0x29,0x48,0x10 #movaps %xmm9,0x10(%rax)
- .byte 0x44,0x0f,0x29,0x50,0x20 #movaps %xmm10,0x20(%rax)
- .byte 0x44,0x0f,0x29,0x58,0x30 #movaps %xmm11,0x30(%rax)
- .byte 0x44,0x0f,0x29,0x60,0x40 #movaps %xmm12,0x40(%rax)
- .byte 0x44,0x0f,0x29,0x68,0x50 #movaps %xmm13,0x50(%rax)
- .byte 0x44,0x0f,0x29,0x70,0x60 #movaps %xmm14,0x60(%rax)
- .byte 0x44,0x0f,0x29,0x78,0x70 #movaps %xmm15,0x70(%rax)
+ .byte 0xc5,0xf8,0x29,0x70,0xe0 #vmovaps %xmm6,-0x20(%rax)
+ .byte 0xc5,0xf8,0x29,0x78,0xf0 #vmovaps %xmm7,-0x10(%rax)
+ .byte 0xc5,0x78,0x29,0x40,0x00 #vmovaps %xmm8,0(%rax)
+ .byte 0xc5,0x78,0x29,0x48,0x10 #vmovaps %xmm9,0x10(%rax)
+ .byte 0xc5,0x78,0x29,0x50,0x20 #vmovaps %xmm10,0x20(%rax)
+ .byte 0xc5,0x78,0x29,0x58,0x30 #vmovaps %xmm11,0x30(%rax)
+ .byte 0xc5,0x78,0x29,0x60,0x40 #vmovaps %xmm12,0x40(%rax)
+ .byte 0xc5,0x78,0x29,0x68,0x50 #vmovaps %xmm13,0x50(%rax)
+ .byte 0xc5,0x78,0x29,0x70,0x60 #vmovaps %xmm14,0x60(%rax)
+ .byte 0xc5,0x78,0x29,0x78,0x70 #vmovaps %xmm15,0x70(%rax)
___
$code.=<<___;
- vzeroupper
lea .Lgather_table(%rip),%r11
mov $power,%eax
and \$3,$power
vpbroadcastb 2(%r11,%rax), %xmm14
vpbroadcastb 1(%r11,%rax), %xmm15
- lea ($inp,$power),$inp
+ lea 64($inp,$power),$inp
mov \$64,%r11 # size optimization
mov \$9,%eax
jmp .Loop_gather_1024
.align 32
.Loop_gather_1024:
- vpand ($inp), %xmm8,%xmm0
- vpand ($inp,%r11), %xmm9,%xmm1
- vpand ($inp,%r11,2), %xmm10,%xmm2
- vpand 64($inp,%r11,2), %xmm11,%xmm3
+ vpand -64($inp), %xmm8,%xmm0
+ vpand ($inp), %xmm9,%xmm1
+ vpand 64($inp), %xmm10,%xmm2
+ vpand ($inp,%r11,2), %xmm11,%xmm3
vpor %xmm0,%xmm1,%xmm1
- vpand ($inp,%r11,4), %xmm12,%xmm4
+ vpand 64($inp,%r11,2), %xmm12,%xmm4
vpor %xmm2,%xmm3,%xmm3
- vpand 64($inp,%r11,4), %xmm13,%xmm5
+ vpand ($inp,%r11,4), %xmm13,%xmm5
vpor %xmm1,%xmm3,%xmm3
- vpand -128($inp,%r11,8), %xmm14,%xmm6
+ vpand 64($inp,%r11,4), %xmm14,%xmm6
vpor %xmm4,%xmm5,%xmm5
- vpand -64($inp,%r11,8), %xmm15,%xmm2
+ vpand -128($inp,%r11,8), %xmm15,%xmm2
lea ($inp,%r11,8),$inp
vpor %xmm3,%xmm5,%xmm5
vpor %xmm2,%xmm6,%xmm6
.rva .Lmul_1024_body,.Lmul_1024_epilogue
.LSEH_info_rsaz_1024_gather5:
.byte 0x01,0x33,0x16,0x00
- .byte 0x33,0xf8,0x09,0x00 #movaps 0x90(rsp),xmm15
- .byte 0x2e,0xe8,0x08,0x00 #movaps 0x80(rsp),xmm14
- .byte 0x29,0xd8,0x07,0x00 #movaps 0x70(rsp),xmm13
- .byte 0x24,0xc8,0x06,0x00 #movaps 0x60(rsp),xmm12
- .byte 0x1f,0xb8,0x05,0x00 #movaps 0x50(rsp),xmm11
- .byte 0x1a,0xa8,0x04,0x00 #movaps 0x40(rsp),xmm10
- .byte 0x15,0x98,0x03,0x00 #movaps 0x30(rsp),xmm9
- .byte 0x10,0x88,0x02,0x00 #movaps 0x20(rsp),xmm8
- .byte 0x0c,0x78,0x01,0x00 #movaps 0x10(rsp),xmm7
- .byte 0x08,0x68,0x00,0x00 #movaps 0x00(rsp),xmm6
+ .byte 0x36,0xf8,0x09,0x00 #vmovaps 0x90(rsp),xmm15
+ .byte 0x31,0xe8,0x08,0x00 #vmovaps 0x80(rsp),xmm14
+ .byte 0x2c,0xd8,0x07,0x00 #vmovaps 0x70(rsp),xmm13
+ .byte 0x27,0xc8,0x06,0x00 #vmovaps 0x60(rsp),xmm12
+ .byte 0x22,0xb8,0x05,0x00 #vmovaps 0x50(rsp),xmm11
+ .byte 0x1d,0xa8,0x04,0x00 #vmovaps 0x40(rsp),xmm10
+ .byte 0x18,0x98,0x03,0x00 #vmovaps 0x30(rsp),xmm9
+ .byte 0x13,0x88,0x02,0x00 #vmovaps 0x20(rsp),xmm8
+ .byte 0x0e,0x78,0x01,0x00 #vmovaps 0x10(rsp),xmm7
+ .byte 0x09,0x68,0x00,0x00 #vmovaps 0x00(rsp),xmm6
.byte 0x04,0x01,0x15,0x00 #sub rsp,0xa8
___
}
#!/usr/bin/env perl
-#******************************************************************************#
-#* Copyright(c) 2012, Intel Corp. *#
-#* Developers and authors: *#
-#* Shay Gueron (1, 2), and Vlad Krasnov (1) *#
-#* (1) Intel Architecture Group, Microprocessor and Chipset Development, *#
-#* Israel Development Center, Haifa, Israel *#
-#* (2) University of Haifa *#
-#******************************************************************************#
-#* This submission to OpenSSL is to be made available under the OpenSSL *#
-#* license, and only to the OpenSSL project, in order to allow integration *#
-#* into the publicly distributed code. ? *#
-#* The use of this code, or portions of this code, or concepts embedded in *#
-#* this code, or modification of this code and/or algorithm(s) in it, or the *#
-#* use of this code for any other purpose than stated above, requires special *#
-#* licensing. *#
-#******************************************************************************#
-#******************************************************************************#
-#* DISCLAIMER: *#
-#* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS AND THE COPYRIGHT OWNERS *#
-#* ``AS IS''. ANY EXPRESSED OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED *#
-#* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR *#
-#* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE CONTRIBUTORS OR THE COPYRIGHT*#
-#* OWNERS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, *#
-#* OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF *#
-#* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS *#
-#* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN *#
-#* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) *#
-#* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE *#
-#* POSSIBILITY OF SUCH DAMAGE. *#
-#******************************************************************************#
-#* Reference: *#
-#* [1] S. Gueron, "Efficient Software Implementations of Modular *#
-#* Exponentiation", http://eprint.iacr.org/2011/239 *#
-#* [2] S. Gueron, V. Krasnov. "Speeding up Big-Numbers Squaring". *#
-#* IEEE Proceedings of 9th International Conference on Information *#
-#* Technology: New Generations (ITNG 2012), 821-823 (2012). *#
-#* [3] S. Gueron, Efficient Software Implementations of Modular Exponentiation*#
-#* Journal of Cryptographic Engineering 2:31-43 (2012). *#
-#* [4] S. Gueron, V. Krasnov: "[PATCH] Efficient and side channel analysis *#
-#* resistant 512-bit and 1024-bit modular exponentiation for optimizing *#
-#* RSA1024 and RSA2048 on x86_64 platforms", *#
-#* http://rt.openssl.org/Ticket/Display.html?id=2582&user=guest&pass=guest*#
-################################################################################
+##############################################################################
+# #
+# Copyright (c) 2012, Intel Corporation #
+# #
+# All rights reserved. #
+# #
+# Redistribution and use in source and binary forms, with or without #
+# modification, are permitted provided that the following conditions are #
+# met: #
+# #
+# * Redistributions of source code must retain the above copyright #
+# notice, this list of conditions and the following disclaimer. #
+# #
+# * Redistributions in binary form must reproduce the above copyright #
+# notice, this list of conditions and the following disclaimer in the #
+# documentation and/or other materials provided with the #
+# distribution. #
+# #
+# * Neither the name of the Intel Corporation nor the names of its #
+# contributors may be used to endorse or promote products derived from #
+# this software without specific prior written permission. #
+# #
+# #
+# THIS SOFTWARE IS PROVIDED BY INTEL CORPORATION ""AS IS"" AND ANY #
+# EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE #
+# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR #
+# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL INTEL CORPORATION OR #
+# CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
+# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, #
+# PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR #
+# PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF #
+# LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
+# NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS #
+# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. #
+# #
+##############################################################################
+# Developers and authors: #
+# Shay Gueron (1, 2), and Vlad Krasnov (1) #
+# (1) Intel Architecture Group, Microprocessor and Chipset Development, #
+# Israel Development Center, Haifa, Israel #
+# (2) University of Haifa #
+##############################################################################
+# Reference: #
+# [1] S. Gueron, "Efficient Software Implementations of Modular #
+# Exponentiation", http://eprint.iacr.org/2011/239 #
+# [2] S. Gueron, V. Krasnov. "Speeding up Big-Numbers Squaring". #
+# IEEE Proceedings of 9th International Conference on Information #
+# Technology: New Generations (ITNG 2012), 821-823 (2012). #
+# [3] S. Gueron, Efficient Software Implementations of Modular Exponentiation#
+# Journal of Cryptographic Engineering 2:31-43 (2012). #
+# [4] S. Gueron, V. Krasnov: "[PATCH] Efficient and side channel analysis #
+# resistant 512-bit and 1024-bit modular exponentiation for optimizing #
+# RSA1024 and RSA2048 on x86_64 platforms", #
+# http://rt.openssl.org/Ticket/Display.html?id=2582&user=guest&pass=guest#
+##############################################################################
# While original submission covers 512- and 1024-bit exponentiation,
# this module is limited to 512-bit version only (and as such
#
# (*) rsax engine and fips numbers are presented for reference
# purposes;
-# (**) you might notice MULX code below, strangely enough gain is
-# marginal, which is why code remains disabled;
+# (**) MULX was attempted, but found to give only marginal improvement;
$flavour = shift;
$output = shift;
open OUT,"| $^X $xlate $flavour $output";
*STDOUT=*OUT;
+if (`$ENV{CC} -Wa,-v -c -o /dev/null -x assembler /dev/null 2>&1`
+ =~ /GNU assembler version ([2-9]\.[0-9]+)/) {
+ $addx = ($1>=2.23);
+}
+
+if (!$addx && $win64 && ($flavour =~ /nasm/ || $ENV{ASM} =~ /nasm/) &&
+ `nasm -v 2>&1` =~ /NASM version ([2-9]\.[0-9]+)/) {
+ $addx = ($1>=2.10);
+}
+
+if (!$addx && $win64 && ($flavour =~ /masm/ || $ENV{ASM} =~ /ml64/) &&
+ `ml64 2>&1` =~ /Version ([0-9]+)\./) {
+ $addx = ($1>=11);
+}
+
($out, $inp, $mod) = ("%rdi", "%rsi", "%rbp"); # common internal API
{
my ($out,$inp,$mod,$n0,$times) = ("%rdi","%rsi","%rdx","%rcx","%r8d");
$code.=<<___;
.text
+.extern OPENSSL_ia32cap_P
+
.globl rsaz_512_sqr
.type rsaz_512_sqr,\@function,5
.align 32
movq ($inp), %rdx
movq 8($inp), %rax
movq $n0, 128(%rsp)
+___
+$code.=<<___ if ($addx);
+ movl \$0x80100,%r11d
+ andl OPENSSL_ia32cap_P+8(%rip),%r11d
+ cmpl \$0x80100,%r11d # check for MULX and ADO/CX
+ je .Loop_sqrx
+___
+$code.=<<___;
jmp .Loop_sqr
.align 32
.Loop_sqr:
movl $times,128+8(%rsp)
-___
-if (1) {
-$code.=<<___;
#first iteration
movq %rdx, %rbx
mulq %rdx
movq %r13, 112(%rsp)
movq %r14, 120(%rsp)
+
+ movq (%rsp), %r8
+ movq 8(%rsp), %r9
+ movq 16(%rsp), %r10
+ movq 24(%rsp), %r11
+ movq 32(%rsp), %r12
+ movq 40(%rsp), %r13
+ movq 48(%rsp), %r14
+ movq 56(%rsp), %r15
+
+ call __rsaz_512_reduce
+
+ addq 64(%rsp), %r8
+ adcq 72(%rsp), %r9
+ adcq 80(%rsp), %r10
+ adcq 88(%rsp), %r11
+ adcq 96(%rsp), %r12
+ adcq 104(%rsp), %r13
+ adcq 112(%rsp), %r14
+ adcq 120(%rsp), %r15
+ sbbq %rcx, %rcx
+
+ call __rsaz_512_subtract
+
+ movq %r8, %rdx
+ movq %r9, %rax
+ movl 128+8(%rsp), $times
+ movq $out, $inp
+
+ decl $times
+ jnz .Loop_sqr
___
-} else {
+if ($addx) {
$code.=<<___;
+ jmp .Lsqr_tail
+
+.align 32
+.Loop_sqrx:
+ movl $times,128+8(%rsp)
movq $out, %xmm0 # off-load
+ movq %rbp, %xmm1 # off-load
#first iteration
mulx %rax, %r8, %r9
mulx 16($inp), %rcx, %r10
+ xor %rbp, %rbp # cf=0, of=0
mulx 24($inp), %rax, %r11
- add %rcx, %r9
+ adcx %rcx, %r9
mulx 32($inp), %rcx, %r12
- adc %rax, %r10
+ adcx %rax, %r10
mulx 40($inp), %rax, %r13
- adc %rcx, %r11
+ adcx %rcx, %r11
- mulx 48($inp), %rcx, %r14
- adc %rax, %r12
+ .byte 0xc4,0x62,0xf3,0xf6,0xb6,0x30,0x00,0x00,0x00 # mulx 48($inp), %rcx, %r14
+ adcx %rax, %r12
+ adcx %rcx, %r13
- mulx 56($inp), %rax, %r15
- adc %rcx, %r13
- mov %r9, %rcx
- adc %rax, %r14
- adc \$0, %r15
+ .byte 0xc4,0x62,0xfb,0xf6,0xbe,0x38,0x00,0x00,0x00 # mulx 56($inp), %rax, %r15
+ adcx %rax, %r14
+ adcx %rbp, %r15 # %rbp is 0
+ mov %r9, %rcx
shld \$1, %r8, %r9
shl \$1, %r8
+ xor %ebp, %ebp
mulx %rdx, %rax, %rdx
- add %rdx, %r8
- adc \$0, %r9
+ adcx %rdx, %r8
+ mov 8($inp), %rdx
+ adcx %rbp, %r9
mov %rax, (%rsp)
mov %r8, 8(%rsp)
#second iteration
- mov 8($inp), %rdx
mulx 16($inp), %rax, %rbx
+ adox %rax, %r10
+ adcx %rbx, %r11
- mulx 24($inp), $out, %r8
- add %rax, %r10
- adc %rbx, %r11
- adc \$0, %r8
+ .byte 0xc4,0x62,0xc3,0xf6,0x86,0x18,0x00,0x00,0x00 # mulx 24($inp), $out, %r8
+ adox $out, %r11
+ adcx %r8, %r12
mulx 32($inp), %rax, %rbx
- add $out, %r11
- adc %r8, %r12
- adc \$0, %rbx
+ adox %rax, %r12
+ adcx %rbx, %r13
mulx 40($inp), $out, %r8
- add %rax, %r12
- adc %rbx, %r13
- adc \$0, %r8
+ adox $out, %r13
+ adcx %r8, %r14
- mulx 48($inp), %rax, %rbx
- add $out, %r13
- adc %r8, %r14
- adc \$0, %rbx
+ .byte 0xc4,0xe2,0xfb,0xf6,0x9e,0x30,0x00,0x00,0x00 # mulx 48($inp), %rax, %rbx
+ adox %rax, %r14
+ adcx %rbx, %r15
- mulx 56($inp), $out, %r8
- add %rax, %r14
- adc %rbx, %r15
- mov %r11, %rbx
- adc \$0, %r8
- add $out, %r15
- adc \$0, %r8
+ .byte 0xc4,0x62,0xc3,0xf6,0x86,0x38,0x00,0x00,0x00 # mulx 56($inp), $out, %r8
+ adox $out, %r15
+ adcx %rbp, %r8
+ adox %rbp, %r8
+ mov %r11, %rbx
shld \$1, %r10, %r11
shld \$1, %rcx, %r10
+ xor %ebp,%ebp
mulx %rdx, %rax, %rcx
- add %rax, %r9
- adc %rcx, %r10
- adc \$0, %r11
+ mov 16($inp), %rdx
+ adcx %rax, %r9
+ adcx %rcx, %r10
+ adcx %rbp, %r11
mov %r9, 16(%rsp)
- mov %r10, 24(%rsp)
+ .byte 0x4c,0x89,0x94,0x24,0x18,0x00,0x00,0x00 # mov %r10, 24(%rsp)
#third iteration
- mov 16($inp), %rdx
- mulx 24($inp), $out, %r9
+ .byte 0xc4,0x62,0xc3,0xf6,0x8e,0x18,0x00,0x00,0x00 # mulx 24($inp), $out, %r9
+ adox $out, %r12
+ adcx %r9, %r13
mulx 32($inp), %rax, %rcx
- add $out, %r12
- adc %r9, %r13
- adc \$0, %rcx
+ adox %rax, %r13
+ adcx %rcx, %r14
mulx 40($inp), $out, %r9
- add %rax, %r13
- adc %rcx, %r14
- adc \$0, %r9
+ adox $out, %r14
+ adcx %r9, %r15
- mulx 48($inp), %rax, %rcx
- add $out, %r14
- adc %r9, %r15
- adc \$0, %rcx
+ .byte 0xc4,0xe2,0xfb,0xf6,0x8e,0x30,0x00,0x00,0x00 # mulx 48($inp), %rax, %rcx
+ adox %rax, %r15
+ adcx %rcx, %r8
- mulx 56($inp), $out, %r9
- add %rax, %r15
- adc %rcx, %r8
- mov %r13, %rcx
- adc \$0, %r9
- add $out, %r8
- adc \$0, %r9
+ .byte 0xc4,0x62,0xc3,0xf6,0x8e,0x38,0x00,0x00,0x00 # mulx 56($inp), $out, %r9
+ adox $out, %r8
+ adcx %rbp, %r9
+ adox %rbp, %r9
+ mov %r13, %rcx
shld \$1, %r12, %r13
shld \$1, %rbx, %r12
+ xor %ebp, %ebp
mulx %rdx, %rax, %rdx
- add %rax, %r11
- adc %rdx, %r12
- adc \$0, %r13
+ adcx %rax, %r11
+ adcx %rdx, %r12
+ mov 24($inp), %rdx
+ adcx %rbp, %r13
mov %r11, 32(%rsp)
- mov %r12, 40(%rsp)
+ .byte 0x4c,0x89,0xa4,0x24,0x28,0x00,0x00,0x00 # mov %r12, 40(%rsp)
#fourth iteration
- mov 24($inp), %rdx
- mulx 32($inp), %rax, %rbx
+ .byte 0xc4,0xe2,0xfb,0xf6,0x9e,0x20,0x00,0x00,0x00 # mulx 32($inp), %rax, %rbx
+ adox %rax, %r14
+ adcx %rbx, %r15
mulx 40($inp), $out, %r10
- add %rax, %r14
- adc %rbx, %r15
- adc \$0, %r10
+ adox $out, %r15
+ adcx %r10, %r8
mulx 48($inp), %rax, %rbx
- add $out, %r15
- adc %r10, %r8
- adc \$0, %rbx
+ adox %rax, %r8
+ adcx %rbx, %r9
mulx 56($inp), $out, %r10
- add %rax, %r8
- adc \$0, %rbx
- add $out, %r9
- adc \$0, %r10
- add %rbx, %r9
- mov %r15, %rbx
- adc \$0, %r10
+ adox $out, %r9
+ adcx %rbp, %r10
+ adox %rbp, %r10
+ .byte 0x66
+ mov %r15, %rbx
shld \$1, %r14, %r15
shld \$1, %rcx, %r14
+ xor %ebp, %ebp
mulx %rdx, %rax, %rdx
- add %rax, %r13
- adc %rdx, %r14
- adc \$0, %r15
+ adcx %rax, %r13
+ adcx %rdx, %r14
+ mov 32($inp), %rdx
+ adcx %rbp, %r15
mov %r13, 48(%rsp)
mov %r14, 56(%rsp)
#fifth iteration
- mov 32($inp), %rdx
- mulx 40($inp), $out, %r11
+ .byte 0xc4,0x62,0xc3,0xf6,0x9e,0x28,0x00,0x00,0x00 # mulx 40($inp), $out, %r11
+ adox $out, %r8
+ adcx %r11, %r9
mulx 48($inp), %rax, %rcx
- add $out, %r8
- adc %r11, %r9
- adc \$0, %rcx
+ adox %rax, %r9
+ adcx %rcx, %r10
mulx 56($inp), $out, %r11
- add %rax, %r9
- adc %rcx, %r10
- adc \$0, %r11
- add $out, %r10
- adc \$0, %r11
+ adox $out, %r10
+ adcx %rbp, %r11
+ adox %rbp, %r11
mov %r9, %rcx
shld \$1, %r8, %r9
shld \$1, %rbx, %r8
+ xor %ebp, %ebp
mulx %rdx, %rax, %rdx
- add %rax, %r15
- adc %rdx, %r8
- adc \$0, %r9
+ adcx %rax, %r15
+ adcx %rdx, %r8
+ mov 40($inp), %rdx
+ adcx %rbp, %r9
mov %r15, 64(%rsp)
mov %r8, 72(%rsp)
#sixth iteration
- mov 40($inp), %rdx
- mulx 48($inp), %rax, %rbx
+ .byte 0xc4,0xe2,0xfb,0xf6,0x9e,0x30,0x00,0x00,0x00 # mulx 48($inp), %rax, %rbx
+ adox %rax, %r10
+ adcx %rbx, %r11
- mulx 56($inp), $out, %r12
- add %rax, %r10
- adc %rbx, %r11
- adc \$0, %r12
- add $out, %r11
- adc \$0, %r12
+ .byte 0xc4,0x62,0xc3,0xf6,0xa6,0x38,0x00,0x00,0x00 # mulx 56($inp), $out, %r12
+ adox $out, %r11
+ adcx %rbp, %r12
+ adox %rbp, %r12
mov %r11, %rbx
shld \$1, %r10, %r11
shld \$1, %rcx, %r10
+ xor %ebp, %ebp
mulx %rdx, %rax, %rdx
- add %rax, %r9
- adc %rdx, %r10
- adc \$0, %r11
+ adcx %rax, %r9
+ adcx %rdx, %r10
+ mov 48($inp), %rdx
+ adcx %rbp, %r11
mov %r9, 80(%rsp)
mov %r10, 88(%rsp)
#seventh iteration
- mov 48($inp), %rdx
- mulx 56($inp), %rax, %r13
- add %rax, %r12
- adc \$0, %r13
+ .byte 0xc4,0x62,0xfb,0xf6,0xae,0x38,0x00,0x00,0x00 # mulx 56($inp), %rax, %r13
+ adox %rax, %r12
+ adox %rbp, %r13
xor %r14, %r14
shld \$1, %r13, %r14
shld \$1, %r12, %r13
shld \$1, %rbx, %r12
+ xor %ebp, %ebp
mulx %rdx, %rax, %rdx
- add %rax, %r11
- adc %rdx, %r12
- adc \$0, %r13
+ adcx %rax, %r11
+ adcx %rdx, %r12
+ mov 56($inp), %rdx
+ adcx %rbp, %r13
- mov %r11, 96(%rsp)
- mov %r12, 104(%rsp)
+ .byte 0x4c,0x89,0x9c,0x24,0x60,0x00,0x00,0x00 # mov %r11, 96(%rsp)
+ .byte 0x4c,0x89,0xa4,0x24,0x68,0x00,0x00,0x00 # mov %r12, 104(%rsp)
#eighth iteration
- mov 56($inp), %rdx
mulx %rdx, %rax, %rdx
- add %rax, %r13
- adc \$0, %rdx
-
+ adox %rax, %r13
+ adox %rbp, %rdx
+
+ .byte 0x66
add %rdx, %r14
movq %r13, 112(%rsp)
movq %r14, 120(%rsp)
movq %xmm0, $out
-___
-}
-$code.=<<___;
+ movq %xmm1, %rbp
+
+ movq 128(%rsp), %rdx # pull $n0
movq (%rsp), %r8
movq 8(%rsp), %r9
movq 16(%rsp), %r10
movq 48(%rsp), %r14
movq 56(%rsp), %r15
- call _rsaz_512_reduce
+ call __rsaz_512_reducex
addq 64(%rsp), %r8
adcq 72(%rsp), %r9
adcq 120(%rsp), %r15
sbbq %rcx, %rcx
- call _rsaz_512_subtract
+ call __rsaz_512_subtract
movq %r8, %rdx
movq %r9, %rax
movq $out, $inp
decl $times
- jnz .Loop_sqr
+ jnz .Loop_sqrx
+
+.Lsqr_tail:
+___
+}
+$code.=<<___;
leaq 128+24+48(%rsp), %rax
movq -48(%rax), %r15
movq $out, %xmm0 # off-load arguments
movq $mod, %xmm1
movq $n0, 128(%rsp)
-
+___
+$code.=<<___ if ($addx);
+ movl \$0x80100,%r11d
+ andl OPENSSL_ia32cap_P+8(%rip),%r11d
+ cmpl \$0x80100,%r11d # check for MULX and ADO/CX
+ je .Lmulx
+___
+$code.=<<___;
+ movq ($bp), %rbx # pass b[0]
movq $bp, %rbp # pass argument
call __rsaz_512_mul
movq 48(%rsp), %r14
movq 56(%rsp), %r15
- call _rsaz_512_reduce
+ call __rsaz_512_reduce
+___
+$code.=<<___ if ($addx);
+ jmp .Lmul_tail
+
+.align 32
+.Lmulx:
+ movq $bp, %rbp # pass argument
+ movq ($bp), %rdx # pass b[0]
+ call __rsaz_512_mulx
+
+ movq %xmm0, $out
+ movq %xmm1, %rbp
+ movq 128(%rsp), %rdx # pull $n0
+ movq (%rsp), %r8
+ movq 8(%rsp), %r9
+ movq 16(%rsp), %r10
+ movq 24(%rsp), %r11
+ movq 32(%rsp), %r12
+ movq 40(%rsp), %r13
+ movq 48(%rsp), %r14
+ movq 56(%rsp), %r15
+
+ call __rsaz_512_reducex
+.Lmul_tail:
+___
+$code.=<<___;
addq 64(%rsp), %r8
adcq 72(%rsp), %r9
adcq 80(%rsp), %r10
adcq 120(%rsp), %r15
sbbq %rcx, %rcx
- call _rsaz_512_subtract
+ call __rsaz_512_subtract
leaq 128+24+48(%rsp), %rax
movq -48(%rax), %r15
subq \$128+24, %rsp
.Lmul_gather4_body:
+___
+$code.=<<___ if ($addx);
+ movl \$0x80100,%r11d
+ andl OPENSSL_ia32cap_P+8(%rip),%r11d
+ cmpl \$0x80100,%r11d # check for MULX and ADO/CX
+ je .Lmulx_gather
+___
+$code.=<<___;
movl 64($bp,$pwr,4), %eax
movq $out, %xmm0 # off-load arguments
movl ($bp,$pwr,4), %ebx
movq 48(%rsp), %r14
movq 56(%rsp), %r15
- call _rsaz_512_reduce
+ call __rsaz_512_reduce
+___
+$code.=<<___ if ($addx);
+ jmp .Lmul_gather_tail
+
+.align 32
+.Lmulx_gather:
+ mov 64($bp,$pwr,4), %eax
+ movq $out, %xmm0 # off-load arguments
+ lea 128($bp,$pwr,4), %rbp
+ mov ($bp,$pwr,4), %edx
+ movq $mod, %xmm1
+ mov $n0, 128(%rsp)
+
+ shl \$32, %rax
+ or %rax, %rdx
+ mulx ($ap), %rbx, %r8 # 0 iteration
+ mov %rbx, (%rsp)
+ xor %edi, %edi # cf=0, of=0
+
+ mulx 8($ap), %rax, %r9
+ movd (%rbp), %xmm4
+
+ mulx 16($ap), %rbx, %r10
+ movd 64(%rbp), %xmm5
+ adcx %rax, %r8
+
+ mulx 24($ap), %rax, %r11
+ pslldq \$4, %xmm5
+ adcx %rbx, %r9
+
+ mulx 32($ap), %rbx, %r12
+ por %xmm5, %xmm4
+ adcx %rax, %r10
+
+ mulx 40($ap), %rax, %r13
+ adcx %rbx, %r11
+
+ mulx 48($ap), %rbx, %r14
+ lea 128(%rbp), %rbp
+ adcx %rax, %r12
+
+ mulx 56($ap), %rax, %r15
+ movq %xmm4, %rdx
+ adcx %rbx, %r13
+ adcx %rax, %r14
+ mov %r8, %rbx
+ adcx %rdi, %r15 # %rdi is 0
+
+ mov \$-7, %rcx
+ jmp .Loop_mulx_gather
+
+.align 32
+.Loop_mulx_gather:
+ mulx ($ap), %rax, %r8
+ adcx %rax, %rbx
+ adox %r9, %r8
+
+ mulx 8($ap), %rax, %r9
+ .byte 0x66,0x0f,0x6e,0xa5,0x00,0x00,0x00,0x00 # movd (%rbp), %xmm4
+ adcx %rax, %r8
+ adox %r10, %r9
+
+ mulx 16($ap), %rax, %r10
+ movd 64(%rbp), %xmm5
+ lea 128(%rbp), %rbp
+ adcx %rax, %r9
+ adox %r11, %r10
+
+ .byte 0xc4,0x62,0xfb,0xf6,0x9e,0x18,0x00,0x00,0x00 # mulx 24($ap), %rax, %r11
+ pslldq \$4, %xmm5
+ por %xmm5, %xmm4
+ adcx %rax, %r10
+ adox %r12, %r11
+
+ mulx 32($ap), %rax, %r12
+ adcx %rax, %r11
+ adox %r13, %r12
+
+ mulx 40($ap), %rax, %r13
+ adcx %rax, %r12
+ adox %r14, %r13
+
+ .byte 0xc4,0x62,0xfb,0xf6,0xb6,0x30,0x00,0x00,0x00 # mulx 48($ap), %rax, %r14
+ adcx %rax, %r13
+ adox %r15, %r14
+
+ mulx 56($ap), %rax, %r15
+ movq %xmm4, %rdx
+ mov %rbx, 64(%rsp,%rcx,8)
+ adcx %rax, %r14
+ adox %rdi, %r15
+ mov %r8, %rbx
+ adcx %rdi, %r15 # cf=0
+
+ inc %rcx # of=0
+ jnz .Loop_mulx_gather
+
+ mov %r8, 64(%rsp)
+ mov %r9, 64+8(%rsp)
+ mov %r10, 64+16(%rsp)
+ mov %r11, 64+24(%rsp)
+ mov %r12, 64+32(%rsp)
+ mov %r13, 64+40(%rsp)
+ mov %r14, 64+48(%rsp)
+ mov %r15, 64+56(%rsp)
+
+ movq %xmm0, $out
+ movq %xmm1, %rbp
+ mov 128(%rsp), %rdx # pull $n0
+ mov (%rsp), %r8
+ mov 8(%rsp), %r9
+ mov 16(%rsp), %r10
+ mov 24(%rsp), %r11
+ mov 32(%rsp), %r12
+ mov 40(%rsp), %r13
+ mov 48(%rsp), %r14
+ mov 56(%rsp), %r15
+
+ call __rsaz_512_reducex
+
+.Lmul_gather_tail:
+___
+$code.=<<___;
addq 64(%rsp), %r8
adcq 72(%rsp), %r9
adcq 80(%rsp), %r10
adcq 120(%rsp), %r15
sbbq %rcx, %rcx
- call _rsaz_512_subtract
+ call __rsaz_512_subtract
leaq 128+24+48(%rsp), %rax
movq -48(%rax), %r15
movq $n0, 128(%rsp)
movq $out, %rbp
+___
+$code.=<<___ if ($addx);
+ movl \$0x80100,%r11d
+ andl OPENSSL_ia32cap_P+8(%rip),%r11d
+ cmpl \$0x80100,%r11d # check for MULX and ADO/CX
+ je .Lmulx_scatter
+___
+$code.=<<___;
+ movq ($out),%rbx # pass b[0]
call __rsaz_512_mul
movq %xmm0, $out
movq 48(%rsp), %r14
movq 56(%rsp), %r15
- call _rsaz_512_reduce
+ call __rsaz_512_reduce
+___
+$code.=<<___ if ($addx);
+ jmp .Lmul_scatter_tail
+
+.align 32
+.Lmulx_scatter:
+ movq ($out), %rdx # pass b[0]
+ call __rsaz_512_mulx
+
+ movq %xmm0, $out
+ movq %xmm1, %rbp
+
+ movq 128(%rsp), %rdx # pull $n0
+ movq (%rsp), %r8
+ movq 8(%rsp), %r9
+ movq 16(%rsp), %r10
+ movq 24(%rsp), %r11
+ movq 32(%rsp), %r12
+ movq 40(%rsp), %r13
+ movq 48(%rsp), %r14
+ movq 56(%rsp), %r15
+
+ call __rsaz_512_reducex
+.Lmul_scatter_tail:
+___
+$code.=<<___;
addq 64(%rsp), %r8
adcq 72(%rsp), %r9
adcq 80(%rsp), %r10
movq %xmm2, $inp
sbbq %rcx, %rcx
- call _rsaz_512_subtract
+ call __rsaz_512_subtract
movl %r8d, 64*0($inp) # scatter
shrq \$32, %r8
subq \$128+24, %rsp
.Lmul_by_one_body:
+___
+$code.=<<___ if ($addx);
+ movl OPENSSL_ia32cap_P+8(%rip),%eax
+___
+$code.=<<___;
movq $mod, %rbp # reassign argument
movq $n0, 128(%rsp)
movdqa %xmm0, 64(%rsp)
movdqa %xmm0, 80(%rsp)
movdqa %xmm0, 96(%rsp)
-
- call _rsaz_512_reduce
-
+___
+$code.=<<___ if ($addx);
+ andl \$0x80100,%eax
+ cmpl \$0x80100,%eax # check for MULX and ADO/CX
+ je .Lby_one_callx
+___
+$code.=<<___;
+ call __rsaz_512_reduce
+___
+$code.=<<___ if ($addx);
+ jmp .Lby_one_tail
+.align 32
+.Lby_one_callx:
+ movq 128(%rsp), %rdx # pull $n0
+ call __rsaz_512_reducex
+.Lby_one_tail:
+___
+$code.=<<___;
movq %r8, ($out)
movq %r9, 8($out)
movq %r10, 16($out)
.size rsaz_512_mul_by_one,.-rsaz_512_mul_by_one
___
}
-{ # _rsaz_512_reduce
+{ # __rsaz_512_reduce
#
# input: %r8-%r15, %rbp - mod, 128(%rsp) - n0
# output: %r8-%r15
# clobbers: everything except %rbp and %rdi
$code.=<<___;
-.type _rsaz_512_reduce,\@abi-omnipotent
+.type __rsaz_512_reduce,\@abi-omnipotent
.align 32
-_rsaz_512_reduce:
-___
-if (1) {
-$code.=<<___;
+__rsaz_512_reduce:
movq %r8, %rbx
imulq 128+8(%rsp), %rbx
movq 0(%rbp), %rax
adcq \$0, %rdx
addq %r11, %r10
movq 128+8(%rsp), %rsi
+ #movq %rdx, %r11
+ #adcq \$0, %r11
+ adcq \$0, %rdx
movq %rdx, %r11
- adcq \$0, %r11
mulq %rbx
addq %rax, %r12
decl %ecx
jne .Lreduction_loop
+
+ ret
+.size __rsaz_512_reduce,.-__rsaz_512_reduce
___
-} else {
+}
+if ($addx) {
+ # __rsaz_512_reducex
+ #
+ # input: %r8-%r15, %rbp - mod, 128(%rsp) - n0
+ # output: %r8-%r15
+ # clobbers: everything except %rbp and %rdi
$code.=<<___;
- movq 128+8(%rsp), %rdx # pull $n0
+.type __rsaz_512_reducex,\@abi-omnipotent
+.align 32
+__rsaz_512_reducex:
+ #movq 128+8(%rsp), %rdx # pull $n0
imulq %r8, %rdx
+ xorq %rsi, %rsi # cf=0,of=0
movl \$8, %ecx
- jmp .Lreduction_loop
+ jmp .Lreduction_loopx
.align 32
-.Lreduction_loop:
- neg %r8
+.Lreduction_loopx:
+ mov %r8, %rbx
mulx 0(%rbp), %rax, %r8
- adc %r9, %r8
+ adcx %rbx, %rax
+ adox %r9, %r8
mulx 8(%rbp), %rax, %r9
- adc \$0, %r9
- add %rax, %r8
- adc %r10, %r9
-
- mulx 16(%rbp), %rax, %r10
- adc \$0, %r10
- mov 128+8(%rsp), %rbx # pull $n0
- imul %r8, %rbx
- add %rax, %r9
- adc %r11, %r10
-
- mulx 24(%rbp), %rax, %r11
- adc \$0, %r11
- add %rax, %r10
- adc %r12, %r11
-
- mulx 32(%rbp), %rax, %r12
- adc \$0, %r12
- add %rax, %r11
- adc %r13, %r12
+ adcx %rax, %r8
+ adox %r10, %r9
+
+ mulx 16(%rbp), %rbx, %r10
+ adcx %rbx, %r9
+ adox %r11, %r10
+
+ mulx 24(%rbp), %rbx, %r11
+ adcx %rbx, %r10
+ adox %r12, %r11
+
+ .byte 0xc4,0x62,0xe3,0xf6,0xa5,0x20,0x00,0x00,0x00 # mulx 32(%rbp), %rbx, %r12
+ mov %rdx, %rax
+ mov %r8, %rdx
+ adcx %rbx, %r11
+ adox %r13, %r12
+
+ mulx 128+8(%rsp), %rbx, %rdx
+ mov %rax, %rdx
mulx 40(%rbp), %rax, %r13
- adc \$0, %r13
- add %rax, %r12
- adc %r14, %r13
+ adcx %rax, %r12
+ adox %r14, %r13
- mulx 48(%rbp), %rax, %r14
- adc \$0, %r14
- add %rax, %r13
- adc %r15, %r14
+ .byte 0xc4,0x62,0xfb,0xf6,0xb5,0x30,0x00,0x00,0x00 # mulx 48(%rbp), %rax, %r14
+ adcx %rax, %r13
+ adox %r15, %r14
mulx 56(%rbp), %rax, %r15
mov %rbx, %rdx
- adc \$0, %r15
- add %rax, %r14
- adc \$0, %r15
+ adcx %rax, %r14
+ adox %rsi, %r15 # %rsi is 0
+ adcx %rsi, %r15 # cf=0
+
+ decl %ecx # of=0
+ jne .Lreduction_loopx
- dec %ecx
- jne .Lreduction_loop
-___
-}
-$code.=<<___;
ret
-.size _rsaz_512_reduce,.-_rsaz_512_reduce
+.size __rsaz_512_reducex,.-__rsaz_512_reducex
___
}
-{ # _rsaz_512_subtract
+{ # __rsaz_512_subtract
# input: %r8-%r15, %rdi - $out, %rbp - $mod, %rcx - mask
# output:
# clobbers: everything but %rdi, %rsi and %rbp
$code.=<<___;
-.type _rsaz_512_subtract,\@abi-omnipotent
+.type __rsaz_512_subtract,\@abi-omnipotent
.align 32
-_rsaz_512_subtract:
+__rsaz_512_subtract:
movq %r8, ($out)
movq %r9, 8($out)
movq %r10, 16($out)
movq %r15, 56($out)
ret
-.size _rsaz_512_subtract,.-_rsaz_512_subtract
+.size __rsaz_512_subtract,.-__rsaz_512_subtract
___
}
{ # __rsaz_512_mul
__rsaz_512_mul:
leaq 8(%rsp), %rdi
- movq ($bp), %rbx
movq ($ap), %rax
mulq %rbx
movq %rax, (%rdi)
.size __rsaz_512_mul,.-__rsaz_512_mul
___
}
+if ($addx) {
+ # __rsaz_512_mulx
+ #
+ # input: %rsi - ap, %rbp - bp
+ # ouput:
+ # clobbers: everything
+my ($ap,$bp,$zero) = ("%rsi","%rbp","%rdi");
+$code.=<<___;
+.type __rsaz_512_mulx,\@abi-omnipotent
+.align 32
+__rsaz_512_mulx:
+ mulx ($ap), %rbx, %r8 # initial %rdx preloaded by caller
+ mov \$-6, %rcx
+
+ mulx 8($ap), %rax, %r9
+ movq %rbx, 8(%rsp)
+
+ mulx 16($ap), %rbx, %r10
+ adc %rax, %r8
+
+ mulx 24($ap), %rax, %r11
+ adc %rbx, %r9
+
+ mulx 32($ap), %rbx, %r12
+ adc %rax, %r10
+
+ mulx 40($ap), %rax, %r13
+ adc %rbx, %r11
+
+ mulx 48($ap), %rbx, %r14
+ adc %rax, %r12
+
+ mulx 56($ap), %rax, %r15
+ mov 8($bp), %rdx
+ adc %rbx, %r13
+ adc %rax, %r14
+ adc \$0, %r15
+
+ xor $zero, $zero # cf=0,of=0
+ jmp .Loop_mulx
+
+.align 32
+.Loop_mulx:
+ movq %r8, %rbx
+ mulx ($ap), %rax, %r8
+ adcx %rax, %rbx
+ adox %r9, %r8
+
+ mulx 8($ap), %rax, %r9
+ adcx %rax, %r8
+ adox %r10, %r9
+
+ mulx 16($ap), %rax, %r10
+ adcx %rax, %r9
+ adox %r11, %r10
+
+ mulx 24($ap), %rax, %r11
+ adcx %rax, %r10
+ adox %r12, %r11
+
+ .byte 0x3e,0xc4,0x62,0xfb,0xf6,0xa6,0x20,0x00,0x00,0x00 # mulx 32($ap), %rax, %r12
+ adcx %rax, %r11
+ adox %r13, %r12
+
+ mulx 40($ap), %rax, %r13
+ adcx %rax, %r12
+ adox %r14, %r13
+
+ mulx 48($ap), %rax, %r14
+ adcx %rax, %r13
+ adox %r15, %r14
+
+ mulx 56($ap), %rax, %r15
+ movq 64($bp,%rcx,8), %rdx
+ movq %rbx, 8+64-8(%rsp,%rcx,8)
+ adcx %rax, %r14
+ adox $zero, %r15
+ adcx $zero, %r15 # cf=0
+
+ inc %rcx # of=0
+ jnz .Loop_mulx
+
+ movq %r8, %rbx
+ mulx ($ap), %rax, %r8
+ adcx %rax, %rbx
+ adox %r9, %r8
+
+ .byte 0xc4,0x62,0xfb,0xf6,0x8e,0x08,0x00,0x00,0x00 # mulx 8($ap), %rax, %r9
+ adcx %rax, %r8
+ adox %r10, %r9
+
+ .byte 0xc4,0x62,0xfb,0xf6,0x96,0x10,0x00,0x00,0x00 # mulx 16($ap), %rax, %r10
+ adcx %rax, %r9
+ adox %r11, %r10
+
+ mulx 24($ap), %rax, %r11
+ adcx %rax, %r10
+ adox %r12, %r11
+
+ mulx 32($ap), %rax, %r12
+ adcx %rax, %r11
+ adox %r13, %r12
+
+ mulx 40($ap), %rax, %r13
+ adcx %rax, %r12
+ adox %r14, %r13
+
+ .byte 0xc4,0x62,0xfb,0xf6,0xb6,0x30,0x00,0x00,0x00 # mulx 48($ap), %rax, %r14
+ adcx %rax, %r13
+ adox %r15, %r14
+
+ .byte 0xc4,0x62,0xfb,0xf6,0xbe,0x38,0x00,0x00,0x00 # mulx 56($ap), %rax, %r15
+ adcx %rax, %r14
+ adox $zero, %r15
+ adcx $zero, %r15
+
+ mov %rbx, 8+64-8(%rsp)
+ mov %r8, 8+64(%rsp)
+ mov %r9, 8+64+8(%rsp)
+ mov %r10, 8+64+16(%rsp)
+ mov %r11, 8+64+24(%rsp)
+ mov %r12, 8+64+32(%rsp)
+ mov %r13, 8+64+40(%rsp)
+ mov %r14, 8+64+48(%rsp)
+ mov %r15, 8+64+56(%rsp)
+
+ ret
+.size __rsaz_512_mulx,.-__rsaz_512_mulx
+___
+}
{
my ($out,$inp,$power)= $win64 ? ("%rcx","%rdx","%r8d") : ("%rdi","%rsi","%edx");
$code.=<<___;
-/******************************************************************************\r
-* Copyright(c) 2012, Intel Corp. \r
-* Developers and authors: \r
-* Shay Gueron (1, 2), and Vlad Krasnov (1) \r
-* (1) Intel Corporation, Israel Development Center, Haifa, Israel \r
-* (2) University of Haifa, Israel \r
-******************************************************************************\r
-* LICENSE: \r
-* This submission to OpenSSL is to be made available under the OpenSSL \r
-* license, and only to the OpenSSL project, in order to allow integration \r
-* into the publicly distributed code. \r
-* The use of this code, or portions of this code, or concepts embedded in\r
-* this code, or modification of this code and/or algorithm(s) in it, or the\r
-* use of this code for any other purpose than stated above, requires special\r
-* licensing. \r
-******************************************************************************\r
-* DISCLAIMER: \r
-* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS AND THE COPYRIGHT OWNERS \r
-* ``AS IS''. ANY EXPRESSED OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED \r
-* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR \r
-* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE CONTRIBUTORS OR THE COPYRIGHT\r
-* OWNERS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, \r
-* OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF \r
-* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS \r
-* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN \r
-* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) \r
-* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE \r
-* POSSIBILITY OF SUCH DAMAGE. \r
-******************************************************************************/\r
-\r
-#include "rsaz_exp.h"\r
-\r
-/*\r
- * See crypto/bn/asm/rsaz-avx2.pl for further details.\r
- */\r
-void rsaz_1024_norm2red_avx2(void *red,const void *norm);\r
-void rsaz_1024_mul_avx2(void *ret,const void *a,const void *b,const void *n,unsigned long k);\r
-void rsaz_1024_sqr_avx2(void *ret,const void *a,const void *n,unsigned long k,int cnt);\r
-void rsaz_1024_scatter5_avx2(void *tbl,const void *val,int i);\r
-void rsaz_1024_gather5_avx2(void *val,const void *tbl,int i);\r
-void rsaz_1024_red2norm_avx2(void *norm,const void *red);\r
-\r
-#if defined(__GNUC__)\r
-# define ALIGN64 __attribute__((aligned(64)))\r
-#elif defined(_MSC_VER)\r
-# define ALIGN64 __declspec(align(64))\r
-#elif defined(__SUNPRO_C)\r
-# define ALIGN64\r
-# pragma align 64(one,two80)\r
-#else\r
-# define ALIGN64 /* not fatal, might hurt performance a little */\r
-#endif\r
-\r
-ALIGN64 static const unsigned long one[40] =\r
- {1,0,0, 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0};\r
-ALIGN64 static const unsigned long two80[40] =\r
- {0,0,1<<22,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0};\r
-\r
-void RSAZ_1024_mod_exp_avx2(BN_ULONG result_norm[16],\r
- const BN_ULONG base_norm[16], const BN_ULONG exponent[16],\r
- const BN_ULONG m_norm[16], const BN_ULONG RR[16], BN_ULONG k0)\r
-{\r
- unsigned char storage[320*3+32*9*16+64]; /* 5.5KB */\r
- unsigned char *p_str = storage + (64-((size_t)storage%64));\r
- unsigned char *a_inv, *m, *result,\r
- *table_s = p_str+320*3,\r
- *R2 = table_s; /* borrow */\r
- int index;\r
- int wvalue;\r
-\r
- if ((((size_t)p_str&4095)+320)>>12) {\r
- result = p_str;\r
- a_inv = p_str + 320;\r
- m = p_str + 320*2; /* should not cross page */\r
- } else {\r
- m = p_str; /* should not cross page */\r
- result = p_str + 320;\r
- a_inv = p_str + 320*2;\r
- }\r
-\r
- rsaz_1024_norm2red_avx2(m, m_norm);\r
- rsaz_1024_norm2red_avx2(a_inv, base_norm);\r
- rsaz_1024_norm2red_avx2(R2, RR);\r
-\r
- rsaz_1024_mul_avx2(R2, R2, R2, m, k0);\r
- rsaz_1024_mul_avx2(R2, R2, two80, m, k0);\r
-\r
- /* table[0] = 1 */\r
- rsaz_1024_mul_avx2(result, R2, one, m, k0);\r
- /* table[1] = a_inv^1 */\r
- rsaz_1024_mul_avx2(a_inv, a_inv, R2, m, k0);\r
-\r
- rsaz_1024_scatter5_avx2(table_s,result,0);\r
- rsaz_1024_scatter5_avx2(table_s,a_inv,1);\r
-\r
- /* table[2] = a_inv^2 */\r
- rsaz_1024_sqr_avx2(result, a_inv, m, k0, 1);\r
- rsaz_1024_scatter5_avx2(table_s,result,2);\r
-#if 0\r
- /* this is almost 2x smaller and less than 1% slower */\r
- for (index=3; index<32; index++) {\r
- rsaz_1024_mul_avx2(result, result, a_inv, m, k0);\r
- rsaz_1024_scatter5_avx2(table_s,result,index);\r
- }\r
-#else\r
- /* table[4] = a_inv^4 */\r
- rsaz_1024_sqr_avx2(result, result, m, k0, 1);\r
- rsaz_1024_scatter5_avx2(table_s,result,4);\r
- /* table[8] = a_inv^8 */\r
- rsaz_1024_sqr_avx2(result, result, m, k0, 1);\r
- rsaz_1024_scatter5_avx2(table_s,result,8);\r
- /* table[16] = a_inv^16 */\r
- rsaz_1024_sqr_avx2(result, result, m, k0, 1);\r
- rsaz_1024_scatter5_avx2(table_s,result,16);\r
- /* table[17] = a_inv^17 */\r
- rsaz_1024_mul_avx2(result, result, a_inv, m, k0);\r
- rsaz_1024_scatter5_avx2(table_s,result,17);\r
-\r
- /* table[3] */\r
- rsaz_1024_gather5_avx2(result,table_s,2);\r
- rsaz_1024_mul_avx2(result,result,a_inv,m,k0);\r
- rsaz_1024_scatter5_avx2(table_s,result,3);\r
- /* table[6] */\r
- rsaz_1024_sqr_avx2(result, result, m, k0, 1);\r
- rsaz_1024_scatter5_avx2(table_s,result,6);\r
- /* table[12] */\r
- rsaz_1024_sqr_avx2(result, result, m, k0, 1);\r
- rsaz_1024_scatter5_avx2(table_s,result,12);\r
- /* table[24] */\r
- rsaz_1024_sqr_avx2(result, result, m, k0, 1);\r
- rsaz_1024_scatter5_avx2(table_s,result,24);\r
- /* table[25] */\r
- rsaz_1024_mul_avx2(result, result, a_inv, m, k0);\r
- rsaz_1024_scatter5_avx2(table_s,result,25);\r
-\r
- /* table[5] */\r
- rsaz_1024_gather5_avx2(result,table_s,4);\r
- rsaz_1024_mul_avx2(result,result,a_inv,m,k0);\r
- rsaz_1024_scatter5_avx2(table_s,result,5);\r
- /* table[10] */\r
- rsaz_1024_sqr_avx2(result, result, m, k0, 1);\r
- rsaz_1024_scatter5_avx2(table_s,result,10);\r
- /* table[20] */\r
- rsaz_1024_sqr_avx2(result, result, m, k0, 1);\r
- rsaz_1024_scatter5_avx2(table_s,result,20);\r
- /* table[21] */\r
- rsaz_1024_mul_avx2(result, result, a_inv, m, k0);\r
- rsaz_1024_scatter5_avx2(table_s,result,21);\r
-\r
- /* table[7] */\r
- rsaz_1024_gather5_avx2(result,table_s,6);\r
- rsaz_1024_mul_avx2(result,result,a_inv,m,k0);\r
- rsaz_1024_scatter5_avx2(table_s,result,7);\r
- /* table[14] */\r
- rsaz_1024_sqr_avx2(result, result, m, k0, 1);\r
- rsaz_1024_scatter5_avx2(table_s,result,14);\r
- /* table[28] */\r
- rsaz_1024_sqr_avx2(result, result, m, k0, 1);\r
- rsaz_1024_scatter5_avx2(table_s,result,28);\r
- /* table[29] */\r
- rsaz_1024_mul_avx2(result, result, a_inv, m, k0);\r
- rsaz_1024_scatter5_avx2(table_s,result,29);\r
-\r
- /* table[9] */\r
- rsaz_1024_gather5_avx2(result,table_s,8);\r
- rsaz_1024_mul_avx2(result,result,a_inv,m,k0);\r
- rsaz_1024_scatter5_avx2(table_s,result,9);\r
- /* table[18] */\r
- rsaz_1024_sqr_avx2(result, result, m, k0, 1);\r
- rsaz_1024_scatter5_avx2(table_s,result,18);\r
- /* table[19] */\r
- rsaz_1024_mul_avx2(result, result, a_inv, m, k0);\r
- rsaz_1024_scatter5_avx2(table_s,result,19);\r
-\r
- /* table[11] */\r
- rsaz_1024_gather5_avx2(result,table_s,10);\r
- rsaz_1024_mul_avx2(result,result,a_inv,m,k0);\r
- rsaz_1024_scatter5_avx2(table_s,result,11);\r
- /* table[22] */\r
- rsaz_1024_sqr_avx2(result, result, m, k0, 1);\r
- rsaz_1024_scatter5_avx2(table_s,result,22);\r
- /* table[23] */\r
- rsaz_1024_mul_avx2(result, result, a_inv, m, k0);\r
- rsaz_1024_scatter5_avx2(table_s,result,23);\r
-\r
- /* table[13] */\r
- rsaz_1024_gather5_avx2(result,table_s,12);\r
- rsaz_1024_mul_avx2(result,result,a_inv,m,k0);\r
- rsaz_1024_scatter5_avx2(table_s,result,13);\r
- /* table[26] */\r
- rsaz_1024_sqr_avx2(result, result, m, k0, 1);\r
- rsaz_1024_scatter5_avx2(table_s,result,26);\r
- /* table[27] */\r
- rsaz_1024_mul_avx2(result, result, a_inv, m, k0);\r
- rsaz_1024_scatter5_avx2(table_s,result,27);\r
-\r
- /* table[15] */\r
- rsaz_1024_gather5_avx2(result,table_s,14);\r
- rsaz_1024_mul_avx2(result,result,a_inv,m,k0);\r
- rsaz_1024_scatter5_avx2(table_s,result,15);\r
- /* table[30] */\r
- rsaz_1024_sqr_avx2(result, result, m, k0, 1);\r
- rsaz_1024_scatter5_avx2(table_s,result,30);\r
- /* table[31] */\r
- rsaz_1024_mul_avx2(result, result, a_inv, m, k0);\r
- rsaz_1024_scatter5_avx2(table_s,result,31);\r
-#endif\r
-\r
- /* load first window */\r
- p_str = (unsigned char*)exponent;\r
- wvalue = p_str[127] >> 3;\r
- rsaz_1024_gather5_avx2(result,table_s,wvalue);\r
-\r
- index = 1014;\r
-\r
- while(index > -1) { /* loop for the remaining 127 windows */\r
-\r
- rsaz_1024_sqr_avx2(result, result, m, k0, 5);\r
-\r
- wvalue = *((unsigned short*)&p_str[index/8]);\r
- wvalue = (wvalue>> (index%8)) & 31;\r
- index-=5;\r
-\r
- rsaz_1024_gather5_avx2(a_inv,table_s,wvalue); /* borrow a_inv */\r
- rsaz_1024_mul_avx2(result, result, a_inv, m, k0);\r
- }\r
-\r
- /* square four times */\r
- rsaz_1024_sqr_avx2(result, result, m, k0, 4);\r
-\r
- wvalue = p_str[0] & 15;\r
-\r
- rsaz_1024_gather5_avx2(a_inv,table_s,wvalue); /* borrow a_inv */\r
- rsaz_1024_mul_avx2(result, result, a_inv, m, k0);\r
-\r
- /* from Montgomery */\r
- rsaz_1024_mul_avx2(result, result, one, m, k0);\r
-\r
- rsaz_1024_red2norm_avx2(result_norm, result);\r
-\r
- OPENSSL_cleanse(storage,sizeof(storage));\r
-}\r
-\r
-/*\r
- * See crypto/bn/rsaz-x86_64.pl for further details.\r
- */\r
-void rsaz_512_mul(void *ret,const void *a,const void *b,const void *n,unsigned long k);\r
-void rsaz_512_mul_scatter4(void *ret,const void *a,const void *n,unsigned long k,const void *tbl,unsigned int power);\r
-void rsaz_512_mul_gather4(void *ret,const void *a,const void *tbl,const void *n,unsigned long k,unsigned int power);\r
-void rsaz_512_mul_by_one(void *ret,const void *a,const void *n,unsigned long k);\r
-void rsaz_512_sqr(void *ret,const void *a,const void *n,unsigned long k,int cnt);\r
-void rsaz_512_scatter4(void *tbl, const unsigned long *val, int power);\r
-void rsaz_512_gather4(unsigned long *val, const void *tbl, int power);\r
-\r
-void RSAZ_512_mod_exp(BN_ULONG result[8],\r
- const BN_ULONG base[8], const BN_ULONG exponent[8],\r
- const BN_ULONG m[8], BN_ULONG k0, const BN_ULONG RR[8])\r
-{\r
- unsigned char storage[16*8*8+64*2+64]; /* 1.2KB */\r
- unsigned char *table = storage + (64-((size_t)storage%64));\r
- unsigned long *a_inv = (unsigned long *)(table+16*8*8),\r
- *temp = (unsigned long *)(table+16*8*8+8*8);\r
- unsigned char *p_str = (unsigned char*)exponent;\r
- int index;\r
- unsigned int wvalue;\r
-\r
- /* table[0] = 1_inv */\r
- temp[0] = 0-m[0]; temp[1] = ~m[1];\r
- temp[2] = ~m[2]; temp[3] = ~m[3];\r
- temp[4] = ~m[4]; temp[5] = ~m[5];\r
- temp[6] = ~m[6]; temp[7] = ~m[7];\r
- rsaz_512_scatter4(table, temp, 0);\r
-\r
- /* table [1] = a_inv^1 */\r
- rsaz_512_mul(a_inv, base, RR, m, k0);\r
- rsaz_512_scatter4(table, a_inv, 1);\r
-\r
- /* table [2] = a_inv^2 */\r
- rsaz_512_sqr(temp, a_inv, m, k0, 1);\r
- rsaz_512_scatter4(table, temp, 2);\r
-\r
- for (index=3; index<16; index++)\r
- rsaz_512_mul_scatter4(temp, a_inv, m, k0, table, index);\r
-\r
- /* load first window */\r
- wvalue = p_str[63];\r
-\r
- rsaz_512_gather4(temp, table, wvalue>>4);\r
- rsaz_512_sqr(temp, temp, m, k0, 4);\r
- rsaz_512_mul_gather4(temp, temp, table, m, k0, wvalue&0xf);\r
-\r
- for (index=62; index>=0; index--) {\r
- wvalue = p_str[index];\r
-\r
- rsaz_512_sqr(temp, temp, m, k0, 4);\r
- rsaz_512_mul_gather4(temp, temp, table, m, k0, wvalue>>4);\r
-\r
- rsaz_512_sqr(temp, temp, m, k0, 4);\r
- rsaz_512_mul_gather4(temp, temp, table, m, k0, wvalue&0x0f);\r
- }\r
-\r
- /* from Montgomery */\r
- rsaz_512_mul_by_one(result, temp, m, k0);\r
-\r
- OPENSSL_cleanse(storage,sizeof(storage));\r
-}\r
+/*****************************************************************************
+* *
+* Copyright (c) 2012, Intel Corporation *
+* *
+* All rights reserved. *
+* *
+* Redistribution and use in source and binary forms, with or without *
+* modification, are permitted provided that the following conditions are *
+* met: *
+* *
+* * Redistributions of source code must retain the above copyright *
+* notice, this list of conditions and the following disclaimer. *
+* *
+* * Redistributions in binary form must reproduce the above copyright *
+* notice, this list of conditions and the following disclaimer in the *
+* documentation and/or other materials provided with the *
+* distribution. *
+* *
+* * Neither the name of the Intel Corporation nor the names of its *
+* contributors may be used to endorse or promote products derived from *
+* this software without specific prior written permission. *
+* *
+* *
+* THIS SOFTWARE IS PROVIDED BY INTEL CORPORATION ""AS IS"" AND ANY *
+* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE *
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR *
+* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL INTEL CORPORATION OR *
+* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, *
+* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, *
+* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR *
+* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF *
+* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING *
+* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS *
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *
+* *
+******************************************************************************
+* Developers and authors: *
+* Shay Gueron (1, 2), and Vlad Krasnov (1) *
+* (1) Intel Corporation, Israel Development Center, Haifa, Israel *
+* (2) University of Haifa, Israel *
+*****************************************************************************/
+
+#include "rsaz_exp.h"
+
+/*
+ * See crypto/bn/asm/rsaz-avx2.pl for further details.
+ */
+void rsaz_1024_norm2red_avx2(void *red,const void *norm);
+void rsaz_1024_mul_avx2(void *ret,const void *a,const void *b,const void *n,unsigned long k);
+void rsaz_1024_sqr_avx2(void *ret,const void *a,const void *n,unsigned long k,int cnt);
+void rsaz_1024_scatter5_avx2(void *tbl,const void *val,int i);
+void rsaz_1024_gather5_avx2(void *val,const void *tbl,int i);
+void rsaz_1024_red2norm_avx2(void *norm,const void *red);
+
+#if defined(__GNUC__)
+# define ALIGN64 __attribute__((aligned(64)))
+#elif defined(_MSC_VER)
+# define ALIGN64 __declspec(align(64))
+#elif defined(__SUNPRO_C)
+# define ALIGN64
+# pragma align 64(one,two80)
+#else
+# define ALIGN64 /* not fatal, might hurt performance a little */
+#endif
+
+ALIGN64 static const unsigned long one[40] =
+ {1,0,0, 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0};
+ALIGN64 static const unsigned long two80[40] =
+ {0,0,1<<22,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0};
+
+void RSAZ_1024_mod_exp_avx2(BN_ULONG result_norm[16],
+ const BN_ULONG base_norm[16], const BN_ULONG exponent[16],
+ const BN_ULONG m_norm[16], const BN_ULONG RR[16], BN_ULONG k0)
+{
+ unsigned char storage[320*3+32*9*16+64]; /* 5.5KB */
+ unsigned char *p_str = storage + (64-((size_t)storage%64));
+ unsigned char *a_inv, *m, *result,
+ *table_s = p_str+320*3,
+ *R2 = table_s; /* borrow */
+ int index;
+ int wvalue;
+
+ if ((((size_t)p_str&4095)+320)>>12) {
+ result = p_str;
+ a_inv = p_str + 320;
+ m = p_str + 320*2; /* should not cross page */
+ } else {
+ m = p_str; /* should not cross page */
+ result = p_str + 320;
+ a_inv = p_str + 320*2;
+ }
+
+ rsaz_1024_norm2red_avx2(m, m_norm);
+ rsaz_1024_norm2red_avx2(a_inv, base_norm);
+ rsaz_1024_norm2red_avx2(R2, RR);
+
+ rsaz_1024_mul_avx2(R2, R2, R2, m, k0);
+ rsaz_1024_mul_avx2(R2, R2, two80, m, k0);
+
+ /* table[0] = 1 */
+ rsaz_1024_mul_avx2(result, R2, one, m, k0);
+ /* table[1] = a_inv^1 */
+ rsaz_1024_mul_avx2(a_inv, a_inv, R2, m, k0);
+
+ rsaz_1024_scatter5_avx2(table_s,result,0);
+ rsaz_1024_scatter5_avx2(table_s,a_inv,1);
+
+ /* table[2] = a_inv^2 */
+ rsaz_1024_sqr_avx2(result, a_inv, m, k0, 1);
+ rsaz_1024_scatter5_avx2(table_s,result,2);
+#if 0
+ /* this is almost 2x smaller and less than 1% slower */
+ for (index=3; index<32; index++) {
+ rsaz_1024_mul_avx2(result, result, a_inv, m, k0);
+ rsaz_1024_scatter5_avx2(table_s,result,index);
+ }
+#else
+ /* table[4] = a_inv^4 */
+ rsaz_1024_sqr_avx2(result, result, m, k0, 1);
+ rsaz_1024_scatter5_avx2(table_s,result,4);
+ /* table[8] = a_inv^8 */
+ rsaz_1024_sqr_avx2(result, result, m, k0, 1);
+ rsaz_1024_scatter5_avx2(table_s,result,8);
+ /* table[16] = a_inv^16 */
+ rsaz_1024_sqr_avx2(result, result, m, k0, 1);
+ rsaz_1024_scatter5_avx2(table_s,result,16);
+ /* table[17] = a_inv^17 */
+ rsaz_1024_mul_avx2(result, result, a_inv, m, k0);
+ rsaz_1024_scatter5_avx2(table_s,result,17);
+
+ /* table[3] */
+ rsaz_1024_gather5_avx2(result,table_s,2);
+ rsaz_1024_mul_avx2(result,result,a_inv,m,k0);
+ rsaz_1024_scatter5_avx2(table_s,result,3);
+ /* table[6] */
+ rsaz_1024_sqr_avx2(result, result, m, k0, 1);
+ rsaz_1024_scatter5_avx2(table_s,result,6);
+ /* table[12] */
+ rsaz_1024_sqr_avx2(result, result, m, k0, 1);
+ rsaz_1024_scatter5_avx2(table_s,result,12);
+ /* table[24] */
+ rsaz_1024_sqr_avx2(result, result, m, k0, 1);
+ rsaz_1024_scatter5_avx2(table_s,result,24);
+ /* table[25] */
+ rsaz_1024_mul_avx2(result, result, a_inv, m, k0);
+ rsaz_1024_scatter5_avx2(table_s,result,25);
+
+ /* table[5] */
+ rsaz_1024_gather5_avx2(result,table_s,4);
+ rsaz_1024_mul_avx2(result,result,a_inv,m,k0);
+ rsaz_1024_scatter5_avx2(table_s,result,5);
+ /* table[10] */
+ rsaz_1024_sqr_avx2(result, result, m, k0, 1);
+ rsaz_1024_scatter5_avx2(table_s,result,10);
+ /* table[20] */
+ rsaz_1024_sqr_avx2(result, result, m, k0, 1);
+ rsaz_1024_scatter5_avx2(table_s,result,20);
+ /* table[21] */
+ rsaz_1024_mul_avx2(result, result, a_inv, m, k0);
+ rsaz_1024_scatter5_avx2(table_s,result,21);
+
+ /* table[7] */
+ rsaz_1024_gather5_avx2(result,table_s,6);
+ rsaz_1024_mul_avx2(result,result,a_inv,m,k0);
+ rsaz_1024_scatter5_avx2(table_s,result,7);
+ /* table[14] */
+ rsaz_1024_sqr_avx2(result, result, m, k0, 1);
+ rsaz_1024_scatter5_avx2(table_s,result,14);
+ /* table[28] */
+ rsaz_1024_sqr_avx2(result, result, m, k0, 1);
+ rsaz_1024_scatter5_avx2(table_s,result,28);
+ /* table[29] */
+ rsaz_1024_mul_avx2(result, result, a_inv, m, k0);
+ rsaz_1024_scatter5_avx2(table_s,result,29);
+
+ /* table[9] */
+ rsaz_1024_gather5_avx2(result,table_s,8);
+ rsaz_1024_mul_avx2(result,result,a_inv,m,k0);
+ rsaz_1024_scatter5_avx2(table_s,result,9);
+ /* table[18] */
+ rsaz_1024_sqr_avx2(result, result, m, k0, 1);
+ rsaz_1024_scatter5_avx2(table_s,result,18);
+ /* table[19] */
+ rsaz_1024_mul_avx2(result, result, a_inv, m, k0);
+ rsaz_1024_scatter5_avx2(table_s,result,19);
+
+ /* table[11] */
+ rsaz_1024_gather5_avx2(result,table_s,10);
+ rsaz_1024_mul_avx2(result,result,a_inv,m,k0);
+ rsaz_1024_scatter5_avx2(table_s,result,11);
+ /* table[22] */
+ rsaz_1024_sqr_avx2(result, result, m, k0, 1);
+ rsaz_1024_scatter5_avx2(table_s,result,22);
+ /* table[23] */
+ rsaz_1024_mul_avx2(result, result, a_inv, m, k0);
+ rsaz_1024_scatter5_avx2(table_s,result,23);
+
+ /* table[13] */
+ rsaz_1024_gather5_avx2(result,table_s,12);
+ rsaz_1024_mul_avx2(result,result,a_inv,m,k0);
+ rsaz_1024_scatter5_avx2(table_s,result,13);
+ /* table[26] */
+ rsaz_1024_sqr_avx2(result, result, m, k0, 1);
+ rsaz_1024_scatter5_avx2(table_s,result,26);
+ /* table[27] */
+ rsaz_1024_mul_avx2(result, result, a_inv, m, k0);
+ rsaz_1024_scatter5_avx2(table_s,result,27);
+
+ /* table[15] */
+ rsaz_1024_gather5_avx2(result,table_s,14);
+ rsaz_1024_mul_avx2(result,result,a_inv,m,k0);
+ rsaz_1024_scatter5_avx2(table_s,result,15);
+ /* table[30] */
+ rsaz_1024_sqr_avx2(result, result, m, k0, 1);
+ rsaz_1024_scatter5_avx2(table_s,result,30);
+ /* table[31] */
+ rsaz_1024_mul_avx2(result, result, a_inv, m, k0);
+ rsaz_1024_scatter5_avx2(table_s,result,31);
+#endif
+
+ /* load first window */
+ p_str = (unsigned char*)exponent;
+ wvalue = p_str[127] >> 3;
+ rsaz_1024_gather5_avx2(result,table_s,wvalue);
+
+ index = 1014;
+
+ while(index > -1) { /* loop for the remaining 127 windows */
+
+ rsaz_1024_sqr_avx2(result, result, m, k0, 5);
+
+ wvalue = *((unsigned short*)&p_str[index/8]);
+ wvalue = (wvalue>> (index%8)) & 31;
+ index-=5;
+
+ rsaz_1024_gather5_avx2(a_inv,table_s,wvalue); /* borrow a_inv */
+ rsaz_1024_mul_avx2(result, result, a_inv, m, k0);
+ }
+
+ /* square four times */
+ rsaz_1024_sqr_avx2(result, result, m, k0, 4);
+
+ wvalue = p_str[0] & 15;
+
+ rsaz_1024_gather5_avx2(a_inv,table_s,wvalue); /* borrow a_inv */
+ rsaz_1024_mul_avx2(result, result, a_inv, m, k0);
+
+ /* from Montgomery */
+ rsaz_1024_mul_avx2(result, result, one, m, k0);
+
+ rsaz_1024_red2norm_avx2(result_norm, result);
+
+ OPENSSL_cleanse(storage,sizeof(storage));
+}
+
+/*
+ * See crypto/bn/rsaz-x86_64.pl for further details.
+ */
+void rsaz_512_mul(void *ret,const void *a,const void *b,const void *n,unsigned long k);
+void rsaz_512_mul_scatter4(void *ret,const void *a,const void *n,unsigned long k,const void *tbl,unsigned int power);
+void rsaz_512_mul_gather4(void *ret,const void *a,const void *tbl,const void *n,unsigned long k,unsigned int power);
+void rsaz_512_mul_by_one(void *ret,const void *a,const void *n,unsigned long k);
+void rsaz_512_sqr(void *ret,const void *a,const void *n,unsigned long k,int cnt);
+void rsaz_512_scatter4(void *tbl, const unsigned long *val, int power);
+void rsaz_512_gather4(unsigned long *val, const void *tbl, int power);
+
+void RSAZ_512_mod_exp(BN_ULONG result[8],
+ const BN_ULONG base[8], const BN_ULONG exponent[8],
+ const BN_ULONG m[8], BN_ULONG k0, const BN_ULONG RR[8])
+{
+ unsigned char storage[16*8*8+64*2+64]; /* 1.2KB */
+ unsigned char *table = storage + (64-((size_t)storage%64));
+ unsigned long *a_inv = (unsigned long *)(table+16*8*8),
+ *temp = (unsigned long *)(table+16*8*8+8*8);
+ unsigned char *p_str = (unsigned char*)exponent;
+ int index;
+ unsigned int wvalue;
+
+ /* table[0] = 1_inv */
+ temp[0] = 0-m[0]; temp[1] = ~m[1];
+ temp[2] = ~m[2]; temp[3] = ~m[3];
+ temp[4] = ~m[4]; temp[5] = ~m[5];
+ temp[6] = ~m[6]; temp[7] = ~m[7];
+ rsaz_512_scatter4(table, temp, 0);
+
+ /* table [1] = a_inv^1 */
+ rsaz_512_mul(a_inv, base, RR, m, k0);
+ rsaz_512_scatter4(table, a_inv, 1);
+
+ /* table [2] = a_inv^2 */
+ rsaz_512_sqr(temp, a_inv, m, k0, 1);
+ rsaz_512_scatter4(table, temp, 2);
+
+ for (index=3; index<16; index++)
+ rsaz_512_mul_scatter4(temp, a_inv, m, k0, table, index);
+
+ /* load first window */
+ wvalue = p_str[63];
+
+ rsaz_512_gather4(temp, table, wvalue>>4);
+ rsaz_512_sqr(temp, temp, m, k0, 4);
+ rsaz_512_mul_gather4(temp, temp, table, m, k0, wvalue&0xf);
+
+ for (index=62; index>=0; index--) {
+ wvalue = p_str[index];
+
+ rsaz_512_sqr(temp, temp, m, k0, 4);
+ rsaz_512_mul_gather4(temp, temp, table, m, k0, wvalue>>4);
+
+ rsaz_512_sqr(temp, temp, m, k0, 4);
+ rsaz_512_mul_gather4(temp, temp, table, m, k0, wvalue&0x0f);
+ }
+
+ /* from Montgomery */
+ rsaz_512_mul_by_one(result, temp, m, k0);
+
+ OPENSSL_cleanse(storage,sizeof(storage));
+}
projects / openssl / commitdiff