The Mips FastISel back-end does not extend i1 values while lowering icmp.
Ensure that we bail into DAG ISel when handling this case.
Patch by Dragan Mladjenovic.
Differential Revision: https://reviews.llvm.org/D49290
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@337288
91177308-0d34-0410-b5e6-
96231b3b80d8
if (VReg == 0)
return 0;
MVT VMVT = TLI.getValueType(DL, V->getType(), true).getSimpleVT();
+
+ if (VMVT == MVT::i1)
+ return 0;
+
if ((VMVT == MVT::i8) || (VMVT == MVT::i16)) {
unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
if (!emitIntExt(VMVT, VReg, MVT::i32, TempReg, IsUnsigned))
--- /dev/null
+; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel=true -mcpu=mips32r2 \
+; RUN: < %s -verify-machineinstrs | FileCheck %s
+
+
+define zeroext i1 @foo(i8* nocapture readonly) {
+; CHECK-LABEL: foo
+; CHECK: lbu $[[REG0:[0-9]+]], 0($4)
+; CHECK-NEXT: xori $[[REG1:[0-9]+]], $[[REG0]], 1
+; CHECK-NEXT: andi $2, $[[REG1]], 1
+ %2 = load i8, i8* %0, align 1
+ %3 = trunc i8 %2 to i1
+ %4 = icmp ne i1 %3, true
+ ret i1 %4
+}
; CHECK-LABEL: sel_i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xor $1, $4, $zero
-; CHECK-NEXT: sltu $1, $zero, $1
; CHECK-NEXT: andi $1, $1, 1
; CHECK-NEXT: movn $6, $5, $1
; CHECK-NEXT: jr $ra
; CHECK-NEXT: move $2, $6
entry:
- %cond = icmp ne i1 %j, 0
+ %cond = xor i1 %j, false
%res = select i1 %cond, i1 %k, i1 %l
ret i1 %res
}