Merging r314897:

------------------------------------------------------------------------
r314897 | dylanmckay | 2017-10-04 23:36:07 +1300 (Wed, 04 Oct 2017) | 3 lines

[AVR] Factor out mayLoad in tablegen patterns

Patch by Gergo Erdi.
------------------------------------------------------------------------

git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_50@315835 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/AVR/AVRInstrInfo.td b/lib/Target/AVR/AVRInstrInfo.td
index 8c7b6f2439281fcb5793043410567a863b5ec1ba..7d1bfc8d85e0245952a8284849f52642ec409d32 100644 (file)
--- a/lib/Target/AVR/AVRInstrInfo.td
+++ b/lib/Target/AVR/AVRInstrInfo.td
@@ -1417,6 +1417,7 @@ def STDWPtrQRr : Pseudo<(outs),
 // Load program memory operations.
 let canFoldAsLoad = 1,
 isReMaterializable = 1,
+mayLoad = 1,
 hasSideEffects = 0 in
 {
   let Defs = [R0],
@@ -1437,8 +1438,7 @@ hasSideEffects = 0 in
                Requires<[HasLPMX]>;
 
   // Load program memory, while postincrementing the Z register.
-  let mayLoad = 1,
-  Defs = [R31R30] in
+  let Defs = [R31R30] in
   {
     def LPMRdZPi : FLPMX<0,
                          1,