[Hexagon] Check for presence before looking registers up in bit tracker

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297240 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/Hexagon/HexagonBitSimplify.cpp b/lib/Target/Hexagon/HexagonBitSimplify.cpp
index 28784f0aa31ef17969be9bd32eac0e4e4d58695a..5fef6083552b8d30bf2b76f94cbf36e42836e119 100644 (file)
--- a/lib/Target/Hexagon/HexagonBitSimplify.cpp
+++ b/lib/Target/Hexagon/HexagonBitSimplify.cpp
@@ -2216,6 +2216,8 @@ bool BitSimplification::genBitSplit(MachineInstr *MI,
   for (unsigned S = AVs.find_first(); S; S = AVs.find_next(S)) {
     // The number of leading zeros here should be the number of trailing
     // non-zeros in RC.
+    if (!BT.has(S))
+      continue;
     const BitTracker::RegisterCell &SC = BT.lookup(S);
     if (SC.width() != W || ctlz(SC) != W-Z)
       continue;
@@ -2421,6 +2423,8 @@ bool BitSimplification::simplifyExtractLow(MachineInstr *MI,
   bool Changed = false;
 
   for (unsigned R = AVs.find_first(); R != 0; R = AVs.find_next(R)) {
+    if (!BT.has(R))
+      continue;
     const BitTracker::RegisterCell &SC = BT.lookup(R);
     unsigned SW = SC.width();
 

diff --git a/test/CodeGen/Hexagon/bit-has.ll b/test/CodeGen/Hexagon/bit-has.ll
new file mode 100644 (file)
index 0000000..9022de3
--- /dev/null
+++ b/test/CodeGen/Hexagon/bit-has.ll
@@ -0,0 +1,64 @@
+; RUN: llc -march=hexagon < %s | FileCheck %s
+; REQUIRES: asserts
+
+; This used to crash. Check for some sane output.
+; CHECK: sath
+
+target triple = "hexagon"
+
+define void @fred() local_unnamed_addr #0 {
+b0:
+  %v1 = load i32, i32* undef, align 4
+  %v2 = tail call i32 @llvm.hexagon.A2.sath(i32 undef)
+  %v3 = and i32 %v1, 603979776
+  %v4 = trunc i32 %v3 to i30
+  switch i30 %v4, label %b22 [
+    i30 -536870912, label %b5
+    i30 -469762048, label %b6
+  ]
+
+b5:                                               ; preds = %b0
+  unreachable
+
+b6:                                               ; preds = %b0
+  %v7 = load i32, i32* undef, align 4
+  %v8 = sub nsw i32 65536, %v7
+  %v9 = load i32, i32* undef, align 4
+  %v10 = mul nsw i32 %v9, %v9
+  %v11 = zext i32 %v10 to i64
+  %v12 = mul nsw i32 %v2, %v8
+  %v13 = sext i32 %v12 to i64
+  %v14 = mul nsw i64 %v13, %v11
+  %v15 = trunc i64 %v14 to i32
+  %v16 = and i32 %v15, 2147483647
+  store i32 %v16, i32* undef, align 4
+  %v17 = lshr i64 %v14, 31
+  %v18 = trunc i64 %v17 to i32
+  store i32 %v18, i32* undef, align 4
+  br label %b19
+
+b19:                                              ; preds = %b6
+  br i1 undef, label %b20, label %b21
+
+b20:                                              ; preds = %b19
+  unreachable
+
+b21:                                              ; preds = %b19
+  br label %b23
+
+b22:                                              ; preds = %b0
+  unreachable
+
+b23:                                              ; preds = %b21
+  %v24 = load i32, i32* undef, align 4
+  %v25 = shl i32 %v24, 1
+  %v26 = and i32 %v25, 65534
+  %v27 = or i32 %v26, 0
+  store i32 %v27, i32* undef, align 4
+  ret void
+}
+
+declare i32 @llvm.hexagon.A2.sath(i32) #1
+
+attributes #0 = { nounwind "target-cpu"="hexagonv5" "target-features"="-hvx,-hvx-double,-long-calls" }
+attributes #1 = { nounwind readnone }