SwiftCC: Perform physical layout when computing coercion types

We need to take type alignment padding into account whe computing physical
layouts.

The layout must be compatible with the input layout, offsets are defined in
terms of offsets within a packed struct which are computed in terms of the alloc
size of a type.

Usingthe store size we would insert padding for the following type for example:

struct {

  int3 v;
  long long l;
} __attribute((packed))

On x86-64 int3 is padded to int4 alignment. The swiftcc type would be
<{ <3 x float>, [4 x i8], i64 }> which is not compatible with <{ <3 x float>,
i64 }>.

The latter has i64 at offset 16 and the former at offset 20.

rdar://32618125

git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@305956 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/CodeGen/SwiftCallingConv.cpp b/lib/CodeGen/SwiftCallingConv.cpp
index 0bfe30a32c8064e1dd6c81cdff8f8f0ccd0c76f5..fc8e36d2c599081c0afc5ae5f0e1fbce25ff29f0 100644 (file)
--- a/lib/CodeGen/SwiftCallingConv.cpp
+++ b/lib/CodeGen/SwiftCallingConv.cpp
@@ -57,6 +57,10 @@ static CharUnits getTypeStoreSize(CodeGenModule &CGM, llvm::Type *type) {
   return CharUnits::fromQuantity(CGM.getDataLayout().getTypeStoreSize(type));
 }
 
+static CharUnits getTypeAllocSize(CodeGenModule &CGM, llvm::Type *type) {
+  return CharUnits::fromQuantity(CGM.getDataLayout().getTypeAllocSize(type));
+}
+
 void SwiftAggLowering::addTypedData(QualType type, CharUnits begin) {
   // Deal with various aggregate types as special cases:
 
@@ -542,7 +546,9 @@ SwiftAggLowering::getCoerceAndExpandTypes() const {
       packed = true;
 
     elts.push_back(entry.Type);
-    lastEnd = entry.End;
+
+    lastEnd = entry.Begin + getTypeAllocSize(CGM, entry.Type);
+    assert(entry.End <= lastEnd);
   }
 
   // We don't need to adjust 'packed' to deal with possible tail padding

diff --git a/test/CodeGen/64bit-swiftcall.c b/test/CodeGen/64bit-swiftcall.c
index 06c31450155298ee41d20640b7bcf8e163d42d97..92ba37cd7fe63f69fc179faa13895bc3d0124305 100644 (file)
--- a/test/CodeGen/64bit-swiftcall.c
+++ b/test/CodeGen/64bit-swiftcall.c
@@ -1,4 +1,5 @@
 // RUN: %clang_cc1 -triple x86_64-apple-darwin10 -target-cpu core2 -emit-llvm -o - %s | FileCheck %s
+// RUN: %clang_cc1 -triple x86_64-apple-darwin10 -target-cpu core2 -emit-llvm -o - %s | FileCheck %s --check-prefix=X86-64
 // RUN: %clang_cc1 -triple arm64-apple-ios9 -target-cpu cyclone -emit-llvm -o - %s | FileCheck %s
 // RUN: %clang_cc1 -triple arm64-apple-ios9 -target-cpu cyclone -emit-llvm -o - %s | FileCheck %s --check-prefix=ARM64
 
@@ -1014,3 +1015,20 @@ typedef struct {
 TEST(struct_v1f3)
 // ARM64-LABEL: define swiftcc { <2 x float>, float } @return_struct_v1f3()
 // ARM64-LABEL: define swiftcc void @take_struct_v1f3(<2 x float>, float)
+
+typedef struct {
+  int3 vect;
+  unsigned long long val;
+} __attribute__((packed)) padded_alloc_size_vector;
+TEST(padded_alloc_size_vector)
+// X86-64-LABEL: take_padded_alloc_size_vector(<3 x i32>, i64)
+// X86-64-NOT: [4 x i8]
+// x86-64: ret void
+
+typedef union {
+  float f1;
+  float3 fv2;
+} union_hom_fp_partial2;
+TEST(union_hom_fp_partial2)
+// X86-64-LABEL: take_union_hom_fp_partial2(i64, float)
+// ARM64-LABEL: take_union_hom_fp_partial2(i64, float)