gn build: sort tablegen rules for X86 and AArch64

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360508 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/utils/gn/secondary/llvm/lib/Target/AArch64/MCTargetDesc/BUILD.gn b/utils/gn/secondary/llvm/lib/Target/AArch64/MCTargetDesc/BUILD.gn
index c505af6177d0d2acf5739679004137db57d20f98..65fa23c258160370bf1cd90fafa61b49dbf9ba49 100644 (file)
--- a/utils/gn/secondary/llvm/lib/Target/AArch64/MCTargetDesc/BUILD.gn
+++ b/utils/gn/secondary/llvm/lib/Target/AArch64/MCTargetDesc/BUILD.gn
@@ -1,41 +1,41 @@
 import("//llvm/utils/TableGen/tablegen.gni")
 
-tablegen("AArch64GenInstrInfo") {
+tablegen("AArch64GenAsmWriter") {
   visibility = [ ":tablegen" ]
-  args = [ "-gen-instr-info" ]
+  args = [ "-gen-asm-writer" ]
   td_file = "../AArch64.td"
 }
 
-tablegen("AArch64GenMCCodeEmitter") {
+tablegen("AArch64GenAsmWriter1") {
   visibility = [ ":tablegen" ]
-  args = [ "-gen-emitter" ]
+  args = [
+    "-gen-asm-writer",
+    "-asmwriternum=1",
+  ]
   td_file = "../AArch64.td"
 }
 
-tablegen("AArch64GenRegisterInfo") {
+tablegen("AArch64GenInstrInfo") {
   visibility = [ ":tablegen" ]
-  args = [ "-gen-register-info" ]
+  args = [ "-gen-instr-info" ]
   td_file = "../AArch64.td"
 }
 
-tablegen("AArch64GenSubtargetInfo") {
+tablegen("AArch64GenMCCodeEmitter") {
   visibility = [ ":tablegen" ]
-  args = [ "-gen-subtarget" ]
+  args = [ "-gen-emitter" ]
   td_file = "../AArch64.td"
 }
 
-tablegen("AArch64GenAsmWriter") {
+tablegen("AArch64GenRegisterInfo") {
   visibility = [ ":tablegen" ]
-  args = [ "-gen-asm-writer" ]
+  args = [ "-gen-register-info" ]
   td_file = "../AArch64.td"
 }
 
-tablegen("AArch64GenAsmWriter1") {
+tablegen("AArch64GenSubtargetInfo") {
   visibility = [ ":tablegen" ]
-  args = [
-    "-gen-asm-writer",
-    "-asmwriternum=1",
-  ]
+  args = [ "-gen-subtarget" ]
   td_file = "../AArch64.td"
 }
 

diff --git a/utils/gn/secondary/llvm/lib/Target/X86/MCTargetDesc/BUILD.gn b/utils/gn/secondary/llvm/lib/Target/X86/MCTargetDesc/BUILD.gn
index db7046acd1d7ec59752010391ab23b430832bc51..e493d867860dd1c2f225d638e3ce5d2c98b66491 100644 (file)
--- a/utils/gn/secondary/llvm/lib/Target/X86/MCTargetDesc/BUILD.gn
+++ b/utils/gn/secondary/llvm/lib/Target/X86/MCTargetDesc/BUILD.gn
@@ -1,35 +1,35 @@
 import("//llvm/utils/TableGen/tablegen.gni")
 
-tablegen("X86GenInstrInfo") {
+tablegen("X86GenAsmWriter") {
   visibility = [ ":tablegen" ]
-  args = [ "-gen-instr-info" ]
+  args = [ "-gen-asm-writer" ]
   td_file = "../X86.td"
 }
 
-tablegen("X86GenRegisterInfo") {
+tablegen("X86GenAsmWriter1") {
   visibility = [ ":tablegen" ]
-  args = [ "-gen-register-info" ]
+  args = [
+    "-gen-asm-writer",
+    "-asmwriternum=1",
+  ]
   td_file = "../X86.td"
 }
 
-tablegen("X86GenSubtargetInfo") {
+tablegen("X86GenInstrInfo") {
   visibility = [ ":tablegen" ]
-  args = [ "-gen-subtarget" ]
+  args = [ "-gen-instr-info" ]
   td_file = "../X86.td"
 }
 
-tablegen("X86GenAsmWriter") {
+tablegen("X86GenRegisterInfo") {
   visibility = [ ":tablegen" ]
-  args = [ "-gen-asm-writer" ]
+  args = [ "-gen-register-info" ]
   td_file = "../X86.td"
 }
 
-tablegen("X86GenAsmWriter1") {
+tablegen("X86GenSubtargetInfo") {
   visibility = [ ":tablegen" ]
-  args = [
-    "-gen-asm-writer",
-    "-asmwriternum=1",
-  ]
+  args = [ "-gen-subtarget" ]
   td_file = "../X86.td"
 }