[X86] Remove patterns that select unmasked vbroadcastf2x32/vbroadcasti2x32. Prefer...

There's no advantage to using these instructions when they aren't masked. This enables some additional execution domain switching without needing to update the table.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315674 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/X86/X86InstrAVX512.td b/lib/Target/X86/X86InstrAVX512.td
index 499440ea48fefca87fc8dffd05c8b1b511939700..bfb91702c3a44b1e26d1a1c4e2467d64a499d721 100644 (file)
--- a/lib/Target/X86/X86InstrAVX512.td
+++ b/lib/Target/X86/X86InstrAVX512.td
@@ -1110,17 +1110,29 @@ multiclass avx512_broadcast_scalar<bits<8> opc, string OpcodeStr,
 multiclass avx512_broadcast_rm_split<bits<8> opc, string OpcodeStr,
                                      X86VectorVTInfo MaskInfo,
                                      X86VectorVTInfo DestInfo,
-                                     X86VectorVTInfo SrcInfo> {
-  let ExeDomain = DestInfo.ExeDomain in {
-  defm r : AVX512_maskable<opc, MRMSrcReg, MaskInfo, (outs MaskInfo.RC:$dst),
+                                     X86VectorVTInfo SrcInfo,
+                                     SDPatternOperator UnmaskedOp = X86VBroadcast> {
+  let ExeDomain = DestInfo.ExeDomain, hasSideEffects = 0 in {
+  defm r : AVX512_maskable_split<opc, MRMSrcReg, MaskInfo,
+                   (outs MaskInfo.RC:$dst),
                    (ins SrcInfo.RC:$src), OpcodeStr, "$src", "$src",
+                   (MaskInfo.VT
+                    (bitconvert
+                     (DestInfo.VT
+                      (UnmaskedOp (SrcInfo.VT SrcInfo.RC:$src))))),
                    (MaskInfo.VT
                     (bitconvert
                      (DestInfo.VT
                       (X86VBroadcast (SrcInfo.VT SrcInfo.RC:$src)))))>,
                    T8PD, EVEX;
-  defm m : AVX512_maskable<opc, MRMSrcMem, MaskInfo, (outs MaskInfo.RC:$dst),
+  let mayLoad = 1 in
+  defm m : AVX512_maskable_split<opc, MRMSrcMem, MaskInfo,
+                   (outs MaskInfo.RC:$dst),
                    (ins SrcInfo.ScalarMemOp:$src), OpcodeStr, "$src", "$src",
+                   (MaskInfo.VT
+                    (bitconvert
+                     (DestInfo.VT (UnmaskedOp
+                                   (SrcInfo.ScalarLdFrag addr:$src))))),
                    (MaskInfo.VT
                     (bitconvert
                      (DestInfo.VT (X86VBroadcast
@@ -1130,7 +1142,7 @@ multiclass avx512_broadcast_rm_split<bits<8> opc, string OpcodeStr,
 
   def : Pat<(MaskInfo.VT
              (bitconvert
-              (DestInfo.VT (X86VBroadcast
+              (DestInfo.VT (UnmaskedOp
                             (SrcInfo.VT (scalar_to_vector
                                          (SrcInfo.ScalarLdFrag addr:$src))))))),
             (!cast<Instruction>(NAME#MaskInfo.ZSuffix#m) addr:$src)>;
@@ -1486,11 +1498,11 @@ multiclass avx512_common_broadcast_32x2<bits<8> opc, string OpcodeStr,
                          AVX512VLVectorVTInfo _Dst, AVX512VLVectorVTInfo _Src> {
   let Predicates = [HasDQI] in
     defm Z :    avx512_broadcast_rm_split<opc, OpcodeStr, _Dst.info512,
-                                          _Src.info512, _Src.info128>,
+                                          _Src.info512, _Src.info128, null_frag>,
                                           EVEX_V512;
   let Predicates = [HasDQI, HasVLX] in
     defm Z256 : avx512_broadcast_rm_split<opc, OpcodeStr, _Dst.info256,
-                                          _Src.info256, _Src.info128>,
+                                          _Src.info256, _Src.info128, null_frag>,
                                           EVEX_V256;
 }
 
@@ -1500,7 +1512,7 @@ multiclass avx512_common_broadcast_i32x2<bits<8> opc, string OpcodeStr,
 
   let Predicates = [HasDQI, HasVLX] in
     defm Z128 : avx512_broadcast_rm_split<opc, OpcodeStr, _Dst.info128,
-                                          _Src.info128, _Src.info128>,
+                                          _Src.info128, _Src.info128, null_frag>,
                                           EVEX_V128;
 }
 

diff --git a/test/CodeGen/X86/avx512-shuffles/broadcast-vector-fp.ll b/test/CodeGen/X86/avx512-shuffles/broadcast-vector-fp.ll
index f6229b1f8c6b93b93ad1601acaf1fdb0c414fe15..35f6b2a127b31b4e50a4a35785b1f7f679dadc33 100644 (file)
--- a/test/CodeGen/X86/avx512-shuffles/broadcast-vector-fp.ll
+++ b/test/CodeGen/X86/avx512-shuffles/broadcast-vector-fp.ll
@@ -108,7 +108,7 @@ define <8 x float> @test_masked_z_2xfloat_to_8xfloat_mask3(<8 x float> %vec) {
 define <16 x float> @test_2xfloat_to_16xfloat(<16 x float> %vec) {
 ; CHECK-LABEL: test_2xfloat_to_16xfloat:
 ; CHECK:       # BB#0:
-; CHECK-NEXT:    vbroadcastf32x2 {{.*#+}} zmm0 = xmm0[0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1]
+; CHECK-NEXT:    vbroadcastsd %xmm0, %zmm0
 ; CHECK-NEXT:    retq
   %res = shufflevector <16 x float> %vec, <16 x float> undef, <16 x i32> <i32 0, i32 1, i32 0, i32 1, i32 0, i32 1, i32 0, i32 1, i32 0, i32 1, i32 0, i32 1, i32 0, i32 1, i32 0, i32 1>
   ret <16 x float> %res
@@ -658,7 +658,7 @@ define <16 x float> @test_2xfloat_to_16xfloat_mem(<2 x float>* %vp) {
 ; CHECK-LABEL: test_2xfloat_to_16xfloat_mem:
 ; CHECK:       # BB#0:
 ; CHECK-NEXT:    vmovsd {{.*#+}} xmm0 = mem[0],zero
-; CHECK-NEXT:    vbroadcastf32x2 {{.*#+}} zmm0 = xmm0[0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1]
+; CHECK-NEXT:    vbroadcastsd %xmm0, %zmm0
 ; CHECK-NEXT:    retq
   %vec = load <2 x float>, <2 x float>* %vp
   %res = shufflevector <2 x float> %vec, <2 x float> undef, <16 x i32> <i32 0, i32 1, i32 0, i32 1, i32 0, i32 1, i32 0, i32 1, i32 0, i32 1, i32 0, i32 1, i32 0, i32 1, i32 0, i32 1>

diff --git a/test/CodeGen/X86/avx512-shuffles/broadcast-vector-int.ll b/test/CodeGen/X86/avx512-shuffles/broadcast-vector-int.ll
index 13cc877a8fd2a8e30574bd0e7119f273d155fc46..f1e693ba0a11b89e0cfa97ed21e127e2a0a61647 100644 (file)
--- a/test/CodeGen/X86/avx512-shuffles/broadcast-vector-int.ll
+++ b/test/CodeGen/X86/avx512-shuffles/broadcast-vector-int.ll
@@ -110,7 +110,7 @@ define <4 x i32> @test_masked_z_2xi32_to_4xi32_mask3(<4 x i32> %vec) {
 define <8 x i32> @test_2xi32_to_8xi32(<8 x i32> %vec) {
 ; CHECK-LABEL: test_2xi32_to_8xi32:
 ; CHECK:       # BB#0:
-; CHECK-NEXT:    vpbroadcastq %xmm0, %ymm0
+; CHECK-NEXT:    vbroadcastsd %xmm0, %ymm0
 ; CHECK-NEXT:    retq
   %res = shufflevector <8 x i32> %vec, <8 x i32> undef, <8 x i32> <i32 0, i32 1, i32 0, i32 1, i32 0, i32 1, i32 0, i32 1>
   ret <8 x i32> %res
@@ -214,7 +214,7 @@ define <8 x i32> @test_masked_z_2xi32_to_8xi32_mask3(<8 x i32> %vec) {
 define <16 x i32> @test_2xi32_to_16xi32(<16 x i32> %vec) {
 ; CHECK-LABEL: test_2xi32_to_16xi32:
 ; CHECK:       # BB#0:
-; CHECK-NEXT:    vbroadcasti32x2 {{.*#+}} zmm0 = xmm0[0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1]
+; CHECK-NEXT:    vbroadcastsd %xmm0, %zmm0
 ; CHECK-NEXT:    retq
   %res = shufflevector <16 x i32> %vec, <16 x i32> undef, <16 x i32> <i32 0, i32 1, i32 0, i32 1, i32 0, i32 1, i32 0, i32 1, i32 0, i32 1, i32 0, i32 1, i32 0, i32 1, i32 0, i32 1>
   ret <16 x i32> %res

diff --git a/test/CodeGen/X86/vector-shuffle-256-v8.ll b/test/CodeGen/X86/vector-shuffle-256-v8.ll
index b6c996e8f38cf7d6fbac203c0507748e9839974e..b95e7cf008aa270b79c5a29c109b4cf5edcdda83 100644 (file)
--- a/test/CodeGen/X86/vector-shuffle-256-v8.ll
+++ b/test/CodeGen/X86/vector-shuffle-256-v8.ll
@@ -1120,17 +1120,11 @@ define <8 x i32> @shuffle_v8i32_08080808(<8 x i32> %a, <8 x i32> %b) {
 ; AVX1-NEXT:    vinsertf128 $1, %xmm0, %ymm0, %ymm0
 ; AVX1-NEXT:    retq
 ;
-; AVX2-LABEL: shuffle_v8i32_08080808:
-; AVX2:       # BB#0:
-; AVX2-NEXT:    vunpcklps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
-; AVX2-NEXT:    vbroadcastsd %xmm0, %ymm0
-; AVX2-NEXT:    retq
-;
-; AVX512VL-LABEL: shuffle_v8i32_08080808:
-; AVX512VL:       # BB#0:
-; AVX512VL-NEXT:    vpunpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
-; AVX512VL-NEXT:    vpbroadcastq %xmm0, %ymm0
-; AVX512VL-NEXT:    retq
+; AVX2OR512VL-LABEL: shuffle_v8i32_08080808:
+; AVX2OR512VL:       # BB#0:
+; AVX2OR512VL-NEXT:    vunpcklps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
+; AVX2OR512VL-NEXT:    vbroadcastsd %xmm0, %ymm0
+; AVX2OR512VL-NEXT:    retq
   %shuffle = shufflevector <8 x i32> %a, <8 x i32> %b, <8 x i32> <i32 0, i32 8, i32 0, i32 8, i32 0, i32 8, i32 0, i32 8>
   ret <8 x i32> %shuffle
 }