[ARM] GlobalISel: Make tests less strict

These are intended as integration tests, so they shouldn't be too
specific about what they're checking.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315083 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/test/CodeGen/ARM/GlobalISel/arm-isel-divmod.ll b/test/CodeGen/ARM/GlobalISel/arm-isel-divmod.ll
index c2e8c5abca4e1a086517ce1b96ceef566eb44c4a..c645408d7961390a8736c7baf0d35440cc211c1c 100644 (file)
--- a/test/CodeGen/ARM/GlobalISel/arm-isel-divmod.ll
+++ b/test/CodeGen/ARM/GlobalISel/arm-isel-divmod.ll
@@ -1,4 +1,3 @@
-; We use V6 ops so we can easily check for the extensions (sxth vs bit tricks).
 ; RUN: llc -mtriple arm-gnueabi -mattr=+v6,+hwdiv-arm -global-isel %s -o - | FileCheck %s -check-prefixes=CHECK,HWDIV
 ; RUN: llc -mtriple arm-gnueabi -mattr=+v6,-hwdiv-arm -global-isel %s -o - | FileCheck %s -check-prefixes=CHECK,SOFT-AEABI
 ; RUN: llc -mtriple arm-gnu -mattr=+v6,+hwdiv-arm -global-isel %s -o - | FileCheck %s -check-prefixes=CHECK,HWDIV
@@ -6,7 +5,7 @@
 
 define arm_aapcscc i32 @test_sdiv_i32(i32 %a, i32 %b) {
 ; CHECK-LABEL: test_sdiv_i32:
-; HWDIV: sdiv r0, r0, r1
+; HWDIV: sdiv
 ; SOFT-AEABI: blx __aeabi_idiv
 ; SOFT-DEFAULT: blx __divsi3
   %r = sdiv i32 %a, %b
@@ -15,7 +14,7 @@ define arm_aapcscc i32 @test_sdiv_i32(i32 %a, i32 %b) {
 
 define arm_aapcscc i32 @test_udiv_i32(i32 %a, i32 %b) {
 ; CHECK-LABEL: test_udiv_i32:
-; HWDIV: udiv r0, r0, r1
+; HWDIV: udiv
 ; SOFT-AEABI: blx __aeabi_uidiv
 ; SOFT-DEFAULT: blx __udivsi3
   %r = udiv i32 %a, %b
@@ -24,9 +23,7 @@ define arm_aapcscc i32 @test_udiv_i32(i32 %a, i32 %b) {
 
 define arm_aapcscc i16 @test_sdiv_i16(i16 %a, i16 %b) {
 ; CHECK-LABEL: test_sdiv_i16:
-; CHECK-DAG: sxth r0, r0
-; CHECK-DAG: sxth r1, r1
-; HWDIV: sdiv r0, r0, r1
+; HWDIV: sdiv
 ; SOFT-AEABI: blx __aeabi_idiv
 ; SOFT-DEFAULT: blx __divsi3
   %r = sdiv i16 %a, %b
@@ -35,9 +32,7 @@ define arm_aapcscc i16 @test_sdiv_i16(i16 %a, i16 %b) {
 
 define arm_aapcscc i16 @test_udiv_i16(i16 %a, i16 %b) {
 ; CHECK-LABEL: test_udiv_i16:
-; CHECK-DAG: uxth r0, r0
-; CHECK-DAG: uxth r1, r1
-; HWDIV: udiv r0, r0, r1
+; HWDIV: udiv
 ; SOFT-AEABI: blx __aeabi_uidiv
 ; SOFT-DEFAULT: blx __udivsi3
   %r = udiv i16 %a, %b
@@ -46,9 +41,7 @@ define arm_aapcscc i16 @test_udiv_i16(i16 %a, i16 %b) {
 
 define arm_aapcscc i8 @test_sdiv_i8(i8 %a, i8 %b) {
 ; CHECK-LABEL: test_sdiv_i8:
-; CHECK-DAG: sxtb r0, r0
-; CHECK-DAG: sxtb r1, r1
-; HWDIV: sdiv r0, r0, r1
+; HWDIV: sdiv
 ; SOFT-AEABI: blx __aeabi_idiv
 ; SOFT-DEFAULT: blx __divsi3
   %r = sdiv i8 %a, %b
@@ -57,9 +50,7 @@ define arm_aapcscc i8 @test_sdiv_i8(i8 %a, i8 %b) {
 
 define arm_aapcscc i8 @test_udiv_i8(i8 %a, i8 %b) {
 ; CHECK-LABEL: test_udiv_i8:
-; CHECK-DAG: uxtb r0, r0
-; CHECK-DAG: uxtb r1, r1
-; HWDIV: udiv r0, r0, r1
+; HWDIV: udiv
 ; SOFT-AEABI: blx __aeabi_uidiv
 ; SOFT-DEFAULT: blx __udivsi3
   %r = udiv i8 %a, %b
@@ -68,9 +59,7 @@ define arm_aapcscc i8 @test_udiv_i8(i8 %a, i8 %b) {
 
 define arm_aapcscc i32 @test_srem_i32(i32 %x, i32 %y) {
 ; CHECK-LABEL: test_srem_i32:
-; HWDIV: sdiv [[Q:r[0-9]+]], r0, r1
-; HWDIV: mul [[P:r[0-9]+]], [[Q]], r1
-; HWDIV: sub r0, r0, [[P]]
+; HWDIV: sdiv
 ; SOFT-AEABI: blx __aeabi_idivmod
 ; SOFT-DEFAULT: blx __modsi3
   %r = srem i32 %x, %y
@@ -79,9 +68,7 @@ define arm_aapcscc i32 @test_srem_i32(i32 %x, i32 %y) {
 
 define arm_aapcscc i32 @test_urem_i32(i32 %x, i32 %y) {
 ; CHECK-LABEL: test_urem_i32:
-; HWDIV: udiv [[Q:r[0-9]+]], r0, r1
-; HWDIV: mul [[P:r[0-9]+]], [[Q]], r1
-; HWDIV: sub r0, r0, [[P]]
+; HWDIV: udiv
 ; SOFT-AEABI: blx __aeabi_uidivmod
 ; SOFT-DEFAULT: blx __umodsi3
   %r = urem i32 %x, %y
@@ -90,11 +77,7 @@ define arm_aapcscc i32 @test_urem_i32(i32 %x, i32 %y) {
 
 define arm_aapcscc i16 @test_srem_i16(i16 %x, i16 %y) {
 ; CHECK-LABEL: test_srem_i16:
-; CHECK-DAG: sxth r0, r0
-; CHECK-DAG: sxth r1, r1
-; HWDIV: sdiv [[Q:r[0-9]+]], r0, r1
-; HWDIV: mul [[P:r[0-9]+]], [[Q]], r1
-; HWDIV: sub r0, r0, [[P]]
+; HWDIV: sdiv
 ; SOFT-AEABI: blx __aeabi_idivmod
 ; SOFT-DEFAULT: blx __modsi3
   %r = srem i16 %x, %y
@@ -103,11 +86,7 @@ define arm_aapcscc i16 @test_srem_i16(i16 %x, i16 %y) {
 
 define arm_aapcscc i16 @test_urem_i16(i16 %x, i16 %y) {
 ; CHECK-LABEL: test_urem_i16:
-; CHECK-DAG: uxth r0, r0
-; CHECK-DAG: uxth r1, r1
-; HWDIV: udiv [[Q:r[0-9]+]], r0, r1
-; HWDIV: mul [[P:r[0-9]+]], [[Q]], r1
-; HWDIV: sub r0, r0, [[P]]
+; HWDIV: udiv
 ; SOFT-AEABI: blx __aeabi_uidivmod
 ; SOFT-DEFAULT: blx __umodsi3
   %r = urem i16 %x, %y
@@ -116,11 +95,7 @@ define arm_aapcscc i16 @test_urem_i16(i16 %x, i16 %y) {
 
 define arm_aapcscc i8 @test_srem_i8(i8 %x, i8 %y) {
 ; CHECK-LABEL: test_srem_i8:
-; CHECK-DAG: sxtb r0, r0
-; CHECK-DAG: sxtb r1, r1
-; HWDIV: sdiv [[Q:r[0-9]+]], r0, r1
-; HWDIV: mul [[P:r[0-9]+]], [[Q]], r1
-; HWDIV: sub r0, r0, [[P]]
+; HWDIV: sdiv
 ; SOFT-AEABI: blx __aeabi_idivmod
 ; SOFT-DEFAULT: blx __modsi3
   %r = srem i8 %x, %y
@@ -129,11 +104,7 @@ define arm_aapcscc i8 @test_srem_i8(i8 %x, i8 %y) {
 
 define arm_aapcscc i8 @test_urem_i8(i8 %x, i8 %y) {
 ; CHECK-LABEL: test_urem_i8:
-; CHECK-DAG: uxtb r0, r0
-; CHECK-DAG: uxtb r1, r1
-; HWDIV: udiv [[Q:r[0-9]+]], r0, r1
-; HWDIV: mul [[P:r[0-9]+]], [[Q]], r1
-; HWDIV: sub r0, r0, [[P]]
+; HWDIV: udiv
 ; SOFT-AEABI: blx __aeabi_uidivmod
 ; SOFT-DEFAULT: blx __umodsi3
   %r = urem i8 %x, %y

diff --git a/test/CodeGen/ARM/GlobalISel/arm-isel.ll b/test/CodeGen/ARM/GlobalISel/arm-isel.ll
index 419bcf71c106574d97f087ef8254cf4023ab14eb..9e3a711dea6d6a742f47436cac260073ea10b891 100644 (file)
--- a/test/CodeGen/ARM/GlobalISel/arm-isel.ll
+++ b/test/CodeGen/ARM/GlobalISel/arm-isel.ll
@@ -388,8 +388,6 @@ entry:
 
 define arm_aapcscc i32 @test_cmp_i16_slt(i16 %a, i16 %b) {
 ; CHECK-LABEL: test_cmp_i16_slt:
-; CHECK-DAG: sxth r0, r0
-; CHECK-DAG: sxth r1, r1
 ; CHECK-DAG: mov [[V:r[0-9]+]], #0
 ; CHECK: cmp r0, r1
 ; CHECK: movlt [[V]], #1