IteratorT begin() const { return begin_iterator; }
IteratorT end() const { return end_iterator; }
+ bool empty() const { return begin_iterator == end_iterator; }
};
/// Convenience function for iterating over sub-ranges.
// If the merge range is empty, then adding the edge didn't actually form any
// new cycles. We're done.
- if (empty(MergeRange)) {
+ if (MergeRange.empty()) {
// Now that the SCC structure is finalized, flip the kind to call.
SourceN->setEdgeKind(TargetN, Edge::Call);
return false; // No new cycle.
// If we're splitting the dwarf out now that we've got the entire
// CU then add the dwo id to it.
auto *SkCU = TheCU.getSkeleton();
- if (useSplitDwarf() && !empty(TheCU.getUnitDie().children())) {
+ if (useSplitDwarf() && !TheCU.getUnitDie().children().empty()) {
finishUnitAttributes(TheCU.getCUNode(), TheCU);
TheCU.addString(TheCU.getUnitDie(), dwarf::DW_AT_GNU_dwo_name,
Asm->TM.Options.MCOptions.SplitDwarfFile);
// is a bit pessimistic under LTO.
if (!AddrPool.isEmpty() &&
(getDwarfVersion() >= 5 ||
- (SkCU && !empty(TheCU.getUnitDie().children()))))
+ (SkCU && !TheCU.getUnitDie().children().empty())))
U.addAddrTableBase();
if (getDwarfVersion() >= 5) {
return true;
return !MI.mayLoadOrStore() && !MI.mayRaiseFPException() &&
- !MI.hasUnmodeledSideEffects() && empty(MI.implicit_operands());
+ !MI.hasUnmodeledSideEffects() && MI.implicit_operands().empty();
}
std::initializer_list<unsigned> Opcodes) {
unsigned Representative = *Opcodes.begin();
- assert(!empty(Opcodes) && Opcodes.begin() + 1 != Opcodes.end() &&
+ assert(!llvm::empty(Opcodes) && Opcodes.begin() + 1 != Opcodes.end() &&
"Initializer list must have at least two opcodes");
for (auto I = Opcodes.begin() + 1, E = Opcodes.end(); I != E; ++I)
"need new vreg for each breakdown");
// An empty range of new register means no repairing.
- assert(!empty(NewVRegs) && "We should not have to repair");
+ assert(!NewVRegs.empty() && "We should not have to repair");
MachineInstr *MI;
if (ValMapping.NumBreakDowns == 1) {
"This mapping is too complex for this function");
iterator_range<SmallVectorImpl<Register>::const_iterator> NewRegs =
OpdMapper.getVRegs(OpIdx);
- if (empty(NewRegs)) {
+ if (NewRegs.empty()) {
LLVM_DEBUG(dbgs() << " has not been repaired, nothing to be done\n");
continue;
}
bool MachineModuleInfoWrapperPass::doInitialization(Module &M) {
MMI.initialize();
MMI.TheModule = &M;
- MMI.DbgInfoAvailable = !empty(M.debug_compile_units());
+ MMI.DbgInfoAvailable = !M.debug_compile_units().empty();
return false;
}
ModuleAnalysisManager &) {
MachineModuleInfo MMI(TM);
MMI.TheModule = &M;
- MMI.DbgInfoAvailable = !empty(M.debug_compile_units());
+ MMI.DbgInfoAvailable = !M.debug_compile_units().empty();
return MMI;
}
}
void CtorDtorRunner::add(iterator_range<CtorDtorIterator> CtorDtors) {
- if (empty(CtorDtors))
+ if (CtorDtors.empty())
return;
MangleAndInterner Mangle(
}
static MDNode *stripDebugLocFromLoopID(MDNode *N) {
- assert(!empty(N->operands()) && "Missing self reference?");
+ assert(!N->operands().empty() && "Missing self reference?");
// if there is no debug location, we do not have to rewrite this MDNode.
if (std::none_of(N->op_begin() + 1, N->op_end(), [](const MDOperand &Op) {
if (DstTy != LLT::vector(2, 16))
break;
- assert(MI.getNumOperands() == 3 && empty(OpdMapper.getVRegs(0)));
+ assert(MI.getNumOperands() == 3 && OpdMapper.getVRegs(0).empty());
substituteSimpleCopyRegs(OpdMapper, 1);
substituteSimpleCopyRegs(OpdMapper, 2);
case AMDGPU::G_EXTRACT_VECTOR_ELT: {
SmallVector<Register, 2> DstRegs(OpdMapper.getVRegs(0));
- assert(empty(OpdMapper.getVRegs(1)) && empty(OpdMapper.getVRegs(2)));
+ assert(OpdMapper.getVRegs(1).empty() && OpdMapper.getVRegs(2).empty());
if (DstRegs.empty()) {
applyDefaultMapping(OpdMapper);
case AMDGPU::G_INSERT_VECTOR_ELT: {
SmallVector<Register, 2> InsRegs(OpdMapper.getVRegs(2));
- assert(empty(OpdMapper.getVRegs(0)));
- assert(empty(OpdMapper.getVRegs(1)));
- assert(empty(OpdMapper.getVRegs(3)));
+ assert(OpdMapper.getVRegs(0).empty());
+ assert(OpdMapper.getVRegs(1).empty());
+ assert(OpdMapper.getVRegs(3).empty());
if (InsRegs.empty()) {
applyDefaultMapping(OpdMapper);
case Intrinsic::amdgcn_readlane: {
substituteSimpleCopyRegs(OpdMapper, 2);
- assert(empty(OpdMapper.getVRegs(0)));
- assert(empty(OpdMapper.getVRegs(3)));
+ assert(OpdMapper.getVRegs(0).empty());
+ assert(OpdMapper.getVRegs(3).empty());
// Make sure the index is an SGPR. It doesn't make sense to run this in a
// waterfall loop, so assume it's a uniform value.
return;
}
case Intrinsic::amdgcn_writelane: {
- assert(empty(OpdMapper.getVRegs(0)));
- assert(empty(OpdMapper.getVRegs(2)));
- assert(empty(OpdMapper.getVRegs(3)));
+ assert(OpdMapper.getVRegs(0).empty());
+ assert(OpdMapper.getVRegs(2).empty());
+ assert(OpdMapper.getVRegs(3).empty());
substituteSimpleCopyRegs(OpdMapper, 4); // VGPR input val
constrainOpWithReadfirstlane(MI, MRI, 2); // Source value
case Intrinsic::amdgcn_ds_ordered_add:
case Intrinsic::amdgcn_ds_ordered_swap: {
// This is only allowed to execute with 1 lane, so readfirstlane is safe.
- assert(empty(OpdMapper.getVRegs(0)));
+ assert(OpdMapper.getVRegs(0).empty());
substituteSimpleCopyRegs(OpdMapper, 3);
constrainOpWithReadfirstlane(MI, MRI, 2); // M0
return;
LLVM_DEBUG(dbgs() << "********** Abstract Member Accesses **********\n");
// Bail out if no debug info.
- if (empty(M.debug_compile_units()))
+ if (M.debug_compile_units().empty())
return false;
return doTransformation(M);
AsmPrinter::doInitialization(M);
// Only emit BTF when debuginfo available.
- if (MAI->doesSupportDebugInformation() && !empty(M.debug_compile_units())) {
+ if (MAI->doesSupportDebugInformation() && !M.debug_compile_units().empty()) {
BTF = new BTFDebug(this);
Handlers.push_back(HandlerInfo(std::unique_ptr<BTFDebug>(BTF), "emit",
"Debug Info Emission", "BTF",
Register InUseReg = MI.getOperand(OpNo).getReg();
MI.getOperand(OpNo).ChangeToImmediate(Imm);
- if (empty(MI.implicit_operands()))
+ if (MI.implicit_operands().empty())
return;
// We need to make sure that the MI didn't have any implicit use
if (PSI->isFunctionEntryCold(F))
return {false, nullptr};
- if (empty(F->users()))
+ if (F->users().empty())
return {false, nullptr};
OptimizationRemarkEmitter ORE(F);
return false;
}
- assert(empty(Cloner.OrigFunc->users()) &&
+ assert(Cloner.OrigFunc->users().empty() &&
"F's users should all be replaced!");
std::vector<User *> Users(Cloner.ClonedFunc->user_begin(),
// have already been removed; TODO: generalize
BasicBlock *ExitBlock =
BI->getSuccessor(L->contains(BI->getSuccessor(0)) ? 1 : 0);
- if (!empty(ExitBlock->phis()))
+ if (!ExitBlock->phis().empty())
return true;
const SCEV *ExitCount = SE->getExitCount(L, ExitingBB);
return true;
});
// If we are left with no operands, it's dead.
- if (empty(Filtered)) {
+ if (Filtered.empty()) {
// If it has undef at this point, it means there are no-non-undef arguments,
// and thus, the value of the phi node must be undef.
if (HasUndef) {
if (isa<PredicateWithEdge>(ValInfo)) {
IRBuilder<> B(getBranchTerminator(ValInfo));
Function *IF = getCopyDeclaration(F.getParent(), Op->getType());
- if (empty(IF->users()))
+ if (IF->users().empty())
CreatedDeclarations.insert(IF);
CallInst *PIC =
B.CreateCall(IF, Op, Op->getName() + "." + Twine(Counter++));
"Should not have gotten here without it being an assume");
IRBuilder<> B(PAssume->AssumeInst);
Function *IF = getCopyDeclaration(F.getParent(), Op->getType());
- if (empty(IF->users()))
+ if (IF->users().empty())
CreatedDeclarations.insert(IF);
CallInst *PIC = B.CreateCall(IF, Op);
PredicateMap.insert({PIC, ValInfo});
// Figure out the corresponding result for each case value and phi node in the
// common destination, as well as the min and max case values.
- assert(!empty(SI->cases()));
+ assert(!SI->cases().empty());
SwitchInst::CaseIt CI = SI->case_begin();
ConstantInt *MinCaseVal = CI->getCaseValue();
ConstantInt *MaxCaseVal = CI->getCaseValue();