[RISCV] Extend test/CodeGen/RISCV/callee-saved-* to test getCalleePreservedRegs

Add a caller which exhausts regs then calls another function. This allows
getCalleePreservedRegs to be tested.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356122 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/test/CodeGen/RISCV/callee-saved-fpr32s.ll b/test/CodeGen/RISCV/callee-saved-fpr32s.ll
index 6ec18aaeb448fbaa1b0934f5e05a3c0a70cb582f..41bac2aa087a95a2cb9b0185750449fe26ea0875 100644 (file)
--- a/test/CodeGen/RISCV/callee-saved-fpr32s.ll
+++ b/test/CodeGen/RISCV/callee-saved-fpr32s.ll
@@ -1,4 +1,3 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs < %s \
 ; RUN:   | FileCheck %s -check-prefix=ILP32-LP64
 ; RUN: llc -mtriple=riscv64 -mattr=+f -verify-machineinstrs < %s \
@@ -8,8 +7,11 @@
 
 ; All floating point registers are temporaries for the ilp32 and lp64 ABIs.
 
-define void @foo() {
-; ILP32-LP64-LABEL: foo:
+; This function tests that RISCVRegisterInfo::getCalleeSavedRegs returns
+; something appropriate.
+
+define void @callee() {
+; ILP32-LP64-LABEL: callee:
 ; ILP32-LP64:       # %bb.0:
 ; ILP32-LP64-NEXT:    lui a0, %hi(var)
 ; ILP32-LP64-NEXT:    addi a1, a0, %lo(var)
@@ -82,3 +84,24 @@ define void @foo() {
   store volatile [32 x float] %val, [32 x float]* @var
   ret void
 }
+
+; This function tests that RISCVRegisterInfo::getCallPreservedMask returns
+; something appropriate.
+;
+; For the soft float ABIs, no floating point registers are preserved, and
+; codegen will use only ft0 in the body of caller.
+
+define void @caller() {
+; ILP32-LP64-LABEL: caller:
+; ILP32-LP64-NOT:     ft{{[1-9][0-9]*}}
+; ILP32-LP64-NOT:     fs{{[0-9]+}}
+; ILP32-LP64-NOT:     fa{{[0-9]+}}
+; ILP32-LP64:         ret
+; ILP32-LP64-NOT:     ft{{[1-9][0-9]*}}
+; ILP32-LP64-NOT:     fs{{[0-9]+}}
+; ILP32-LP64-NOT:     fa{{[0-9]+}}
+  %val = load [32 x float], [32 x float]* @var
+  call void @callee()
+  store volatile [32 x float] %val, [32 x float]* @var
+  ret void
+}

diff --git a/test/CodeGen/RISCV/callee-saved-fpr64s.ll b/test/CodeGen/RISCV/callee-saved-fpr64s.ll
index 17126bd42525eccc17fdfeb66c97d626dc71b16d..d8571baca5ddd545f9cf31cf8609701eea8b6a02 100644 (file)
--- a/test/CodeGen/RISCV/callee-saved-fpr64s.ll
+++ b/test/CodeGen/RISCV/callee-saved-fpr64s.ll
@@ -8,8 +8,11 @@
 
 ; All floating point registers are temporaries for the ilp32 and lp64 ABIs.
 
-define void @foo() {
-; ILP32-LP64-LABEL: foo:
+; This function tests that RISCVRegisterInfo::getCalleeSavedRegs returns
+; something appropriate.
+
+define void @callee() {
+; ILP32-LP64-LABEL: callee:
 ; ILP32-LP64:       # %bb.0:
 ; ILP32-LP64-NEXT:    lui a0, %hi(var)
 ; ILP32-LP64-NEXT:    addi a1, a0, %lo(var)
@@ -82,3 +85,24 @@ define void @foo() {
   store volatile [32 x double] %val, [32 x double]* @var
   ret void
 }
+
+; This function tests that RISCVRegisterInfo::getCallPreservedMask returns
+; something appropriate.
+;
+; For the soft float ABIs, no floating point registers are preserved, and
+; codegen will use only ft0 in the body of caller.
+
+define void @caller() {
+; ILP32-LP64-LABEL: caller:
+; ILP32-LP64-NOT:     ft{{[1-9][0-9]*}}
+; ILP32-LP64-NOT:     fs{{[0-9]+}}
+; ILP32-LP64-NOT:     fa{{[0-9]+}}
+; ILP32-LP64:         ret
+; ILP32-LP64-NOT:     ft{{[1-9][0-9]*}}
+; ILP32-LP64-NOT:     fs{{[0-9]+}}
+; ILP32-LP64-NOT:     fa{{[0-9]+}}
+  %val = load [32 x double], [32 x double]* @var
+  call void @callee()
+  store volatile [32 x double] %val, [32 x double]* @var
+  ret void
+}

diff --git a/test/CodeGen/RISCV/callee-saved-gprs.ll b/test/CodeGen/RISCV/callee-saved-gprs.ll
index e4c3fd5ebea1a427099a829ec21183562167202e..b10b5a6c77afc00ef6ad09957f389f7b1c9e0790 100644 (file)
--- a/test/CodeGen/RISCV/callee-saved-gprs.ll
+++ b/test/CodeGen/RISCV/callee-saved-gprs.ll
@@ -9,8 +9,11 @@
 
 @var = global [32 x i32] zeroinitializer
 
-define void @foo() {
-; RV32I-LABEL: foo:
+; This function tests that RISCVRegisterInfo::getCalleeSavedRegs returns
+; something appropriate.
+
+define void @callee() {
+; RV32I-LABEL: callee:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -80
 ; RV32I-NEXT:    sw s0, 76(sp)
@@ -28,7 +31,7 @@ define void @foo() {
 ; RV32I-NEXT:    lui a0, %hi(var)
 ; RV32I-NEXT:    addi a1, a0, %lo(var)
 ;
-; RV32I-WITH-FP-LABEL: foo:
+; RV32I-WITH-FP-LABEL: callee:
 ; RV32I-WITH-FP:       # %bb.0:
 ; RV32I-WITH-FP-NEXT:    addi sp, sp, -80
 ; RV32I-WITH-FP-NEXT:    sw ra, 76(sp)
@@ -48,7 +51,7 @@ define void @foo() {
 ; RV32I-WITH-FP-NEXT:    lui a0, %hi(var)
 ; RV32I-WITH-FP-NEXT:    addi a1, a0, %lo(var)
 ;
-; RV64I-LABEL: foo:
+; RV64I-LABEL: callee:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -144
 ; RV64I-NEXT:    sd s0, 136(sp)
@@ -66,7 +69,7 @@ define void @foo() {
 ; RV64I-NEXT:    lui a0, %hi(var)
 ; RV64I-NEXT:    addi a1, a0, %lo(var)
 ;
-; RV64I-WITH-FP-LABEL: foo:
+; RV64I-WITH-FP-LABEL: callee:
 ; RV64I-WITH-FP:       # %bb.0:
 ; RV64I-WITH-FP-NEXT:    addi sp, sp, -160
 ; RV64I-WITH-FP-NEXT:    sd ra, 152(sp)
@@ -89,3 +92,126 @@ define void @foo() {
   store volatile [32 x i32] %val, [32 x i32]* @var
   ret void
 }
+
+; This function tests that RISCVRegisterInfo::getCallPreservedMask returns
+; something appropriate.
+
+define void @caller() {
+; RV32I-LABEL: caller:
+; RV32I:         lui a0, %hi(var)
+; RV32I-NEXT:    addi s1, a0, %lo(var)
+; RV32I:         sw a0, 8(sp)
+; RV32I-NEXT:    lw s2, 84(s1)
+; RV32I-NEXT:    lw s3, 88(s1)
+; RV32I-NEXT:    lw s4, 92(s1)
+; RV32I-NEXT:    lw s5, 96(s1)
+; RV32I-NEXT:    lw s6, 100(s1)
+; RV32I-NEXT:    lw s7, 104(s1)
+; RV32I-NEXT:    lw s8, 108(s1)
+; RV32I-NEXT:    lw s9, 112(s1)
+; RV32I-NEXT:    lw s10, 116(s1)
+; RV32I-NEXT:    lw s11, 120(s1)
+; RV32I-NEXT:    lw s0, 124(s1)
+; RV32I-NEXT:    call callee
+; RV32I-NEXT:    sw s0, 124(s1)
+; RV32I-NEXT:    sw s11, 120(s1)
+; RV32I-NEXT:    sw s10, 116(s1)
+; RV32I-NEXT:    sw s9, 112(s1)
+; RV32I-NEXT:    sw s8, 108(s1)
+; RV32I-NEXT:    sw s7, 104(s1)
+; RV32I-NEXT:    sw s6, 100(s1)
+; RV32I-NEXT:    sw s5, 96(s1)
+; RV32I-NEXT:    sw s4, 92(s1)
+; RV32I-NEXT:    sw s3, 88(s1)
+; RV32I-NEXT:    sw s2, 84(s1)
+; RV32I-NEXT:    lw a0, 8(sp)
+;
+; RV32I-WITH-FP-LABEL: caller:
+; RV32I-WITH-FP:         addi s0, sp, 144
+; RV32I-WITH-FP-NEXT:    lui a0, %hi(var)
+; RV32I-WITH-FP-NEXT:    addi s1, a0, %lo(var)
+; RV32I-WITH-FP:         sw a0, -140(s0)
+; RV32I-WITH-FP-NEXT:    lw s5, 88(s1)
+; RV32I-WITH-FP-NEXT:    lw s6, 92(s1)
+; RV32I-WITH-FP-NEXT:    lw s7, 96(s1)
+; RV32I-WITH-FP-NEXT:    lw s8, 100(s1)
+; RV32I-WITH-FP-NEXT:    lw s9, 104(s1)
+; RV32I-WITH-FP-NEXT:    lw s10, 108(s1)
+; RV32I-WITH-FP-NEXT:    lw s11, 112(s1)
+; RV32I-WITH-FP-NEXT:    lw s2, 116(s1)
+; RV32I-WITH-FP-NEXT:    lw s3, 120(s1)
+; RV32I-WITH-FP-NEXT:    lw s4, 124(s1)
+; RV32I-WITH-FP-NEXT:    call callee
+; RV32I-WITH-FP-NEXT:    sw s4, 124(s1)
+; RV32I-WITH-FP-NEXT:    sw s3, 120(s1)
+; RV32I-WITH-FP-NEXT:    sw s2, 116(s1)
+; RV32I-WITH-FP-NEXT:    sw s11, 112(s1)
+; RV32I-WITH-FP-NEXT:    sw s10, 108(s1)
+; RV32I-WITH-FP-NEXT:    sw s9, 104(s1)
+; RV32I-WITH-FP-NEXT:    sw s8, 100(s1)
+; RV32I-WITH-FP-NEXT:    sw s7, 96(s1)
+; RV32I-WITH-FP-NEXT:    sw s6, 92(s1)
+; RV32I-WITH-FP-NEXT:    sw s5, 88(s1)
+; RV32I-WITH-FP-NEXT:    lw a0, -140(s0)
+;
+; RV64I-LABEL: caller:
+; RV64I:         lui a0, %hi(var)
+; RV64I-NEXT:    addi s1, a0, %lo(var)
+; RV64I:         sd a0, 0(sp)
+; RV64I-NEXT:    lw s2, 84(s1)
+; RV64I-NEXT:    lw s3, 88(s1)
+; RV64I-NEXT:    lw s4, 92(s1)
+; RV64I-NEXT:    lw s5, 96(s1)
+; RV64I-NEXT:    lw s6, 100(s1)
+; RV64I-NEXT:    lw s7, 104(s1)
+; RV64I-NEXT:    lw s8, 108(s1)
+; RV64I-NEXT:    lw s9, 112(s1)
+; RV64I-NEXT:    lw s10, 116(s1)
+; RV64I-NEXT:    lw s11, 120(s1)
+; RV64I-NEXT:    lw s0, 124(s1)
+; RV64I-NEXT:    call callee
+; RV64I-NEXT:    sw s0, 124(s1)
+; RV64I-NEXT:    sw s11, 120(s1)
+; RV64I-NEXT:    sw s10, 116(s1)
+; RV64I-NEXT:    sw s9, 112(s1)
+; RV64I-NEXT:    sw s8, 108(s1)
+; RV64I-NEXT:    sw s7, 104(s1)
+; RV64I-NEXT:    sw s6, 100(s1)
+; RV64I-NEXT:    sw s5, 96(s1)
+; RV64I-NEXT:    sw s4, 92(s1)
+; RV64I-NEXT:    sw s3, 88(s1)
+; RV64I-NEXT:    sw s2, 84(s1)
+; RV64I-NEXT:    ld a0, 0(sp)
+;
+; RV64I-WITH-FP-LABEL: caller:
+; RV64I-WITH-FP:         addi s0, sp, 288
+; RV64I-WITH-FP-NEXT:    lui a0, %hi(var)
+; RV64I-WITH-FP-NEXT:    addi s1, a0, %lo(var)
+; RV64I-WITH-FP:         sd a0, -280(s0)
+; RV64I-WITH-FP-NEXT:    lw s5, 88(s1)
+; RV64I-WITH-FP-NEXT:    lw s6, 92(s1)
+; RV64I-WITH-FP-NEXT:    lw s7, 96(s1)
+; RV64I-WITH-FP-NEXT:    lw s8, 100(s1)
+; RV64I-WITH-FP-NEXT:    lw s9, 104(s1)
+; RV64I-WITH-FP-NEXT:    lw s10, 108(s1)
+; RV64I-WITH-FP-NEXT:    lw s11, 112(s1)
+; RV64I-WITH-FP-NEXT:    lw s2, 116(s1)
+; RV64I-WITH-FP-NEXT:    lw s3, 120(s1)
+; RV64I-WITH-FP-NEXT:    lw s4, 124(s1)
+; RV64I-WITH-FP-NEXT:    call callee
+; RV64I-WITH-FP-NEXT:    sw s4, 124(s1)
+; RV64I-WITH-FP-NEXT:    sw s3, 120(s1)
+; RV64I-WITH-FP-NEXT:    sw s2, 116(s1)
+; RV64I-WITH-FP-NEXT:    sw s11, 112(s1)
+; RV64I-WITH-FP-NEXT:    sw s10, 108(s1)
+; RV64I-WITH-FP-NEXT:    sw s9, 104(s1)
+; RV64I-WITH-FP-NEXT:    sw s8, 100(s1)
+; RV64I-WITH-FP-NEXT:    sw s7, 96(s1)
+; RV64I-WITH-FP-NEXT:    sw s6, 92(s1)
+; RV64I-WITH-FP-NEXT:    sw s5, 88(s1)
+; RV64I-WITH-FP-NEXT:    ld a0, -280(s0)
+  %val = load [32 x i32], [32 x i32]* @var
+  call void @callee()
+  store volatile [32 x i32] %val, [32 x i32]* @var
+  ret void
+}