[X86] Add ANY_EXTEND to switch in ReplaceNodeResults, but just fall back to default...

ANY_EXTEND of v8i8 is marked Custom on AVX512 for handling extends
from v8i8. But the type legalization infrastructure will call
ReplaceNodeResults for v8i8 results. We should just defer it the
default handling instead of asserting in the default of the switch.

Fixes PR43509.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@373234 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp
index 089c7ebb19aecab0c3562ae4c28fd0f702af8b8e..18a998dba383c063c764d3ce1f41b1cc61ef88da 100644 (file)
--- a/lib/Target/X86/X86ISelLowering.cpp
+++ b/lib/Target/X86/X86ISelLowering.cpp
@@ -27887,6 +27887,12 @@ void X86TargetLowering::ReplaceNodeResults(SDNode *N,
     }
     return;
   }
+  case ISD::ANY_EXTEND:
+    // Right now, only MVT::v8i8 has Custom action for an illegal type.
+    // It's intended to custom handle the input type.
+    assert(N->getValueType(0) == MVT::v8i8 &&
+           "Do not know how to legalize this Node");
+    return;
   case ISD::SIGN_EXTEND:
   case ISD::ZERO_EXTEND: {
     EVT VT = N->getValueType(0);

diff --git a/test/CodeGen/X86/pr43509.ll b/test/CodeGen/X86/pr43509.ll
new file mode 100644 (file)
index 0000000..4243764
--- /dev/null
+++ b/test/CodeGen/X86/pr43509.ll
@@ -0,0 +1,25 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=skx | FileCheck %s
+
+define <8 x i8> @foo(<8 x float> %arg) {
+; CHECK-LABEL: foo:
+; CHECK:       # %bb.0: # %bb
+; CHECK-NEXT:    vcmpgtps {{.*}}(%rip){1to8}, %ymm0, %k0
+; CHECK-NEXT:    vpmovm2b %k0, %xmm1
+; CHECK-NEXT:    vxorps %xmm2, %xmm2, %xmm2
+; CHECK-NEXT:    vcmpltps %ymm2, %ymm0, %k1
+; CHECK-NEXT:    vmovdqu8 {{.*}}(%rip), %xmm0 {%k1} {z}
+; CHECK-NEXT:    vpand %xmm0, %xmm1, %xmm0
+; CHECK-NEXT:    vzeroupper
+; CHECK-NEXT:    retq
+bb:
+  %tmp = xor <8 x i8> zeroinitializer, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
+  %tmp1 = fcmp reassoc nsz contract ogt <8 x float> %arg, <float 8.000000e+00, float 8.000000e+00, float 8.000000e+00, float 8.000000e+00, float 8.000000e+00, float 8.000000e+00, float 8.000000e+00, float 8.000000e+00>
+  %tmp2 = zext <8 x i1> %tmp1 to <8 x i8>
+  %tmp3 = and <8 x i8> %tmp, %tmp2
+  %tmp4 = fcmp reassoc nsz contract ogt <8 x float> zeroinitializer, %arg
+  %tmp5 = or <8 x i1> zeroinitializer, %tmp4
+  %tmp6 = zext <8 x i1> %tmp5 to <8 x i8>
+  %tmp7 = and <8 x i8> %tmp3, %tmp6
+  ret <8 x i8> %tmp7
+}