Address r311914 review comments

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311917 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/test/TableGen/ConcatenatedSubregs.td b/test/TableGen/ConcatenatedSubregs.td
index dc2a298dd77ff94181879a9625796e2cee15d9bf..b67d6b02e54a7bc6a6aea1292658271754128e5b 100644 (file)
--- a/test/TableGen/ConcatenatedSubregs.td
+++ b/test/TableGen/ConcatenatedSubregs.td
@@ -13,6 +13,12 @@ class MyClass<int size, list<ValueType> types, dag registers>
   let Size = size;
 }
 
+// Register Example:
+// D0_D1 -- D0 (sub0) -- S0 (ssub0)
+//       \            \- S1 (ssub1)
+//        \ D1 (sub1) -- S2 (ssub2)
+//                    \- S3 (ssub3)
+
 def sub0 : SubRegIndex<32>;
 def sub1 : SubRegIndex<32, 32>;
 def sub2 : SubRegIndex<32, 64>;

diff --git a/utils/TableGen/CodeGenRegisters.cpp b/utils/TableGen/CodeGenRegisters.cpp
index 5ff1608afc99c52102be3e50b3daaf8e32939b2c..425351ccf04f24053843a4aab250c76da0beace5 100644 (file)
--- a/utils/TableGen/CodeGenRegisters.cpp
+++ b/utils/TableGen/CodeGenRegisters.cpp
@@ -122,12 +122,11 @@ LaneBitmask CodeGenSubRegIndex::computeLaneMask() const {
 
 void CodeGenSubRegIndex::setConcatenationOf(
     ArrayRef<CodeGenSubRegIndex*> Parts) {
-  if (ConcatenationOf.empty()) {
+  if (ConcatenationOf.empty())
     ConcatenationOf.assign(Parts.begin(), Parts.end());
-  } else {
+  else
     assert(std::equal(Parts.begin(), Parts.end(),
                       ConcatenationOf.begin()) && "parts consistent");
-  }
 }
 
 void CodeGenSubRegIndex::computeConcatTransitiveClosure() {
@@ -492,16 +491,15 @@ void CodeGenRegister::computeSecondarySubRegs(CodeGenRegBank &RegBank) {
       SmallVector<CodeGenSubRegIndex*, 8> Parts;
       // We know that the first component is (SubRegIdx,SubReg). However we
       // may still need to split it into smaller subregister parts.
-      assert(Cand->ExplicitSubRegs[0] == SubReg);
-      assert(getSubRegIndex(SubReg) == SubRegIdx);
+      assert(Cand->ExplicitSubRegs[0] == SubReg && "LeadingSuperRegs correct");
+      assert(getSubRegIndex(SubReg) == SubRegIdx && "LeadingSuperRegs correct");
       for (CodeGenRegister *SubReg : Cand->ExplicitSubRegs) {
         if (CodeGenSubRegIndex *SubRegIdx = getSubRegIndex(SubReg)) {
           if (SubRegIdx->ConcatenationOf.empty()) {
             Parts.push_back(SubRegIdx);
-          } else {
+          } else
             for (CodeGenSubRegIndex *SubIdx : SubRegIdx->ConcatenationOf)
               Parts.push_back(SubIdx);
-          }
         } else {
           // Sub-register doesn't exist.
           Parts.clear();