[AArch64][RegisterBankInfo] Bump the cost of vector loads.

This does not change anything yet, because we do not offer any
alternative mapping.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@284088 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/AArch64/AArch64RegisterBankInfo.cpp b/lib/Target/AArch64/AArch64RegisterBankInfo.cpp
index 69ba5023f939e39183cbf41ba9c24cdc629892bf..298e697df909c848b63d8fe506cec65925b1ce3f 100644 (file)
--- a/lib/Target/AArch64/AArch64RegisterBankInfo.cpp
+++ b/lib/Target/AArch64/AArch64RegisterBankInfo.cpp
@@ -431,6 +431,16 @@ AArch64RegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
                    *AArch64::PartMappings[OpRegBankIdx[1]].RegBank, OpSize[0]);
     break;
   }
+  case TargetOpcode::G_LOAD: {
+    // Loading in vector unit is slightly more expensive.
+    // This is actually only true for the LD1R and co instructions,
+    // but anyway for the fast mode this number does not matter and
+    // for the greedy mode the cost of the cross bank copy will
+    // offset this number.
+    // FIXME: Should be derived from the scheduling model.
+    if (OpRegBankIdx[0] >= AArch64::FirstFPR)
+      Cost = 2;
+  }
   }
 
   // Finally construct the computed mapping.