Revert of 357063 [AMDGPU][MC] Corrected handling of tied src for atomic return MUBUF...

Reason: the change was mistakenly committed before review

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357066 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp b/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
index 5bf597a0cbb8c196608644640223624ea9ba7c36..086a7d79fe174153ffc97d2eddfb41e046753741 100644 (file)
--- a/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
+++ b/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
@@ -4911,19 +4911,13 @@ void AMDGPUAsmParser::cvtMubufImpl(MCInst &Inst,
   bool HasLdsModifier = false;
   OptionalImmIndexMap OptionalIdx;
   assert(IsAtomicReturn ? IsAtomic : true);
-  unsigned FirstOperandIdx = 1;
 
-  for (unsigned i = FirstOperandIdx, e = Operands.size(); i != e; ++i) {
+  for (unsigned i = 1, e = Operands.size(); i != e; ++i) {
     AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[i]);
 
     // Add the register arguments
     if (Op.isReg()) {
       Op.addRegOperands(Inst, 1);
-      // Insert a tied src for atomic return dst.
-      // This cannot be postponed as subsequent calls to
-      // addImmOperands rely on correct number of MC operands.
-      if (IsAtomicReturn && i == FirstOperandIdx)
-        Op.addRegOperands(Inst, 1);
       continue;
     }
 
@@ -4961,6 +4955,12 @@ void AMDGPUAsmParser::cvtMubufImpl(MCInst &Inst,
     }
   }
 
+  // Copy $vdata_in operand and insert as $vdata for MUBUF_Atomic RTN insns.
+  if (IsAtomicReturn) {
+    MCInst::iterator I = Inst.begin(); // $vdata_in is always at the beginning.
+    Inst.insert(I, *I);
+  }
+
   addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyOffset);
   if (!IsAtomic) { // glc is hard-coded.
     addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyGLC);

diff --git a/test/MC/AMDGPU/mubuf.s b/test/MC/AMDGPU/mubuf.s
index aa2681ac661d1123d1a1029f07de352d16a91a5f..dffd0656144f09787b8cb3db2d4fbe0f6682e94e 100644 (file)
--- a/test/MC/AMDGPU/mubuf.s
+++ b/test/MC/AMDGPU/mubuf.s
@@ -711,14 +711,6 @@ buffer_atomic_inc v1, v[2:3], s[8:11], 56 idxen offen offset:4 glc slc
 // SICI: buffer_atomic_inc v1, v[2:3], s[8:11], 56 idxen offen offset:4 glc slc ; encoding: [0x04,0x70,0xf0,0xe0,0x02,0x01,0x42,0xb8]
 // VI:   buffer_atomic_inc v1, v[2:3], s[8:11], 56 idxen offen offset:4 glc slc ; encoding: [0x04,0x70,0x2e,0xe1,0x02,0x01,0x02,0xb8]
 
-buffer_atomic_add v5, off, s[8:11], 0.5 offset:4095 glc
-// SICI: buffer_atomic_add v5, off, s[8:11], 0.5 offset:4095 glc ; encoding: [0xff,0x4f,0xc8,0xe0,0x00,0x05,0x02,0xf0]
-// VI:   buffer_atomic_add v5, off, s[8:11], 0.5 offset:4095 glc ; encoding: [0xff,0x4f,0x08,0xe1,0x00,0x05,0x02,0xf0]
-
-buffer_atomic_add v5, off, s[8:11], 0.15915494 offset:4095 glc
-// NOSICI: error: invalid operand for instruction
-// VI:   buffer_atomic_add v5, off, s[8:11], 0.15915494 offset:4095 glc ; encoding: [0xff,0x4f,0x08,0xe1,0x00,0x05,0x02,0xf8]
-
 //===----------------------------------------------------------------------===//
 // Lds support
 //===----------------------------------------------------------------------===//