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AMDGPU/GlobalISel: Don't use g_implicit_def in a few tests
authorMatt Arsenault <Matthew.Arsenault@amd.com>
Thu, 7 Feb 2019 18:33:22 +0000 (18:33 +0000)
committerMatt Arsenault <Matthew.Arsenault@amd.com>
Thu, 7 Feb 2019 18:33:22 +0000 (18:33 +0000)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@353443 91177308-0d34-0410-b5e6-96231b3b80d8

test/CodeGen/AMDGPU/GlobalISel/legalize-anyext.mir patch | blob | history
test/CodeGen/AMDGPU/GlobalISel/legalize-sext.mir patch | blob | history
test/CodeGen/AMDGPU/GlobalISel/legalize-zext.mir patch | blob | history

diff --git a/test/CodeGen/AMDGPU/GlobalISel/legalize-anyext.mir b/test/CodeGen/AMDGPU/GlobalISel/legalize-anyext.mir
index 3d19f9b06bdf4c6283abfcb944ccc3baefa99143..a7b202a3b0a6f027a53627cd7f607e0d7215a6fc 100644 (file)
--- a/test/CodeGen/AMDGPU/GlobalISel/legalize-anyext.mir
+++ b/test/CodeGen/AMDGPU/GlobalISel/legalize-anyext.mir
@@ -4,7 +4,7 @@
 ---
 name: test_anyext_s32_to_s64
 body: |
-  bb.0.entry:
+  bb.0:
     liveins: $vgpr0
 
     ; CHECK-LABEL: name: test_anyext_s32_to_s64
@@ -19,7 +19,7 @@ body: |
 ---
 name: test_anyext_s16_to_s64
 body: |
-  bb.0.entry:
+  bb.0:
     liveins: $vgpr0
 
     ; CHECK-LABEL: name: test_anyext_s16_to_s64
@@ -35,7 +35,7 @@ body: |
 ---
 name: test_anyext_s16_to_s32
 body: |
-  bb.0.entry:
+  bb.0:
     liveins: $vgpr0
 
     ; CHECK-LABEL: name: test_anyext_s16_to_s32
@@ -51,7 +51,7 @@ body: |
 ---
 name: test_anyext_s1_to_s32
 body: |
-  bb.0.entry:
+  bb.0:
 
     ; CHECK-LABEL: name: test_anyext_s1_to_s32
     ; CHECK: [[C:%[0-9]+]]:_(s1) = G_CONSTANT i1 false
@@ -65,7 +65,7 @@ body: |
 ---
 name: test_anyext_s1_to_s64
 body: |
-  bb.0.entry:
+  bb.0:
 
     ; CHECK-LABEL: name: test_anyext_s1_to_s64
     ; CHECK: [[C:%[0-9]+]]:_(s1) = G_CONSTANT i1 false
@@ -79,7 +79,7 @@ body: |
 ---
 name: test_anyext_v2s16_to_v2s32
 body: |
-  bb.0.entry:
+  bb.0:
     liveins: $vgpr0
 
     ; CHECK-LABEL: name: test_anyext_v2s16_to_v2s32
@@ -97,21 +97,28 @@ body: |
 ---
 name: test_anyext_v3s16_to_v3s32
 body: |
-  bb.0.entry:
-    liveins: $vgpr0
+  bb.0:
+    liveins: $vgpr0_vgpr1
 
     ; CHECK-LABEL: name: test_anyext_v3s16_to_v3s32
-    ; CHECK: [[DEF:%[0-9]+]]:_(<3 x s32>) = G_IMPLICIT_DEF
-    ; CHECK: $vgpr0_vgpr1_vgpr2 = COPY [[DEF]](<3 x s32>)
-    %0:_(<3 x s16>) = G_IMPLICIT_DEF
-    %1:_(<3 x s32>) = G_ANYEXT %0
-    $vgpr0_vgpr1_vgpr2 = COPY %1
+    ; CHECK: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $vgpr0_vgpr1
+    ; CHECK: [[EXTRACT:%[0-9]+]]:_(<3 x s16>) = G_EXTRACT [[COPY]](<4 x s16>), 0
+    ; CHECK: [[UV:%[0-9]+]]:_(s16), [[UV1:%[0-9]+]]:_(s16), [[UV2:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[EXTRACT]](<3 x s16>)
+    ; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[UV]](s16)
+    ; CHECK: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[UV1]](s16)
+    ; CHECK: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[UV2]](s16)
+    ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[ANYEXT]](s32), [[ANYEXT1]](s32), [[ANYEXT2]](s32)
+    ; CHECK: $vgpr0_vgpr1_vgpr2 = COPY [[BUILD_VECTOR]](<3 x s32>)
+    %0:_(<4 x s16>) = COPY $vgpr0_vgpr1
+    %1:_(<3 x s16>) = G_EXTRACT %0, 0
+    %2:_(<3 x s32>) = G_ANYEXT %1
+    $vgpr0_vgpr1_vgpr2 = COPY %2
 ...
 
 ---
 name: test_anyext_v4s16_to_v4s32
 body: |
-  bb.0.entry:
+  bb.0:
     liveins: $vgpr0
 
     ; CHECK-LABEL: name: test_anyext_v4s16_to_v4s32
@@ -125,7 +132,7 @@ body: |
 ---
 name: test_anyext_v2s32_to_v2s64
 body: |
-  bb.0.entry:
+  bb.0:
     liveins: $vgpr0_vgpr1
 
     ; CHECK-LABEL: name: test_anyext_v2s32_to_v2s64
@@ -143,7 +150,7 @@ body: |
 ---
 name: test_anyext_v3s32_to_v3s64
 body: |
-  bb.0.entry:
+  bb.0:
     liveins: $vgpr0_vgpr1_vgpr2
 
     ; CHECK-LABEL: name: test_anyext_v3s32_to_v3s64
@@ -163,7 +170,7 @@ body: |
 ---
 name: test_anyext_v4s32_to_v4s64
 body: |
-  bb.0.entry:
+  bb.0:
     liveins: $vgpr0_vgpr1_vgpr2_vgpr3
 
     ; CHECK-LABEL: name: test_anyext_v4s32_to_v4s64
diff --git a/test/CodeGen/AMDGPU/GlobalISel/legalize-sext.mir b/test/CodeGen/AMDGPU/GlobalISel/legalize-sext.mir
index 258872df6ee0df1a1ad01b19b0342419b6c2bcfa..20dc8713888993baec213fb5bfacc9b1b413e903 100644 (file)
--- a/test/CodeGen/AMDGPU/GlobalISel/legalize-sext.mir
+++ b/test/CodeGen/AMDGPU/GlobalISel/legalize-sext.mir
@@ -78,7 +78,7 @@ body: |
 ---
 name: test_sext_v2s16_to_v2s32
 body: |
-  bb.0.entry:
+  bb.0:
     liveins: $vgpr0
 
     ; CHECK-LABEL: name: test_sext_v2s16_to_v2s32
@@ -96,38 +96,40 @@ body: |
 ---
 name: test_sext_v3s16_to_v3s32
 body: |
-  bb.0.entry:
-    liveins: $vgpr0
+  bb.0:
+    liveins: $vgpr0_vgpr1
 
     ; CHECK-LABEL: name: test_sext_v3s16_to_v3s32
-    ; CHECK: [[DEF:%[0-9]+]]:_(<3 x s16>) = G_IMPLICIT_DEF
-    ; CHECK: [[UV:%[0-9]+]]:_(s16), [[UV1:%[0-9]+]]:_(s16), [[UV2:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[DEF]](<3 x s16>)
+    ; CHECK: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $vgpr0_vgpr1
+    ; CHECK: [[EXTRACT:%[0-9]+]]:_(<3 x s16>) = G_EXTRACT [[COPY]](<4 x s16>), 0
+    ; CHECK: [[UV:%[0-9]+]]:_(s16), [[UV1:%[0-9]+]]:_(s16), [[UV2:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[EXTRACT]](<3 x s16>)
     ; CHECK: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[UV]](s16)
     ; CHECK: [[SEXT1:%[0-9]+]]:_(s32) = G_SEXT [[UV1]](s16)
     ; CHECK: [[SEXT2:%[0-9]+]]:_(s32) = G_SEXT [[UV2]](s16)
     ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[SEXT]](s32), [[SEXT1]](s32), [[SEXT2]](s32)
     ; CHECK: $vgpr0_vgpr1_vgpr2 = COPY [[BUILD_VECTOR]](<3 x s32>)
-    %0:_(<3 x s16>) = G_IMPLICIT_DEF
-    %1:_(<3 x s32>) = G_SEXT %0
-    $vgpr0_vgpr1_vgpr2 = COPY %1
+    %0:_(<4 x s16>) = COPY $vgpr0_vgpr1
+    %1:_(<3 x s16>) = G_EXTRACT %0, 0
+    %2:_(<3 x s32>) = G_SEXT %1
+    $vgpr0_vgpr1_vgpr2 = COPY %2
 ...
 
 ---
 name: test_sext_v4s16_to_v4s32
 body: |
-  bb.0.entry:
-    liveins: $vgpr0
+  bb.0:
+    liveins: $vgpr0_vgpr1
 
     ; CHECK-LABEL: name: test_sext_v4s16_to_v4s32
-    ; CHECK: [[DEF:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF
-    ; CHECK: [[UV:%[0-9]+]]:_(s16), [[UV1:%[0-9]+]]:_(s16), [[UV2:%[0-9]+]]:_(s16), [[UV3:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[DEF]](<4 x s16>)
+    ; CHECK: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $vgpr0_vgpr1
+    ; CHECK: [[UV:%[0-9]+]]:_(s16), [[UV1:%[0-9]+]]:_(s16), [[UV2:%[0-9]+]]:_(s16), [[UV3:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[COPY]](<4 x s16>)
     ; CHECK: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[UV]](s16)
     ; CHECK: [[SEXT1:%[0-9]+]]:_(s32) = G_SEXT [[UV1]](s16)
     ; CHECK: [[SEXT2:%[0-9]+]]:_(s32) = G_SEXT [[UV2]](s16)
     ; CHECK: [[SEXT3:%[0-9]+]]:_(s32) = G_SEXT [[UV3]](s16)
     ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[SEXT]](s32), [[SEXT1]](s32), [[SEXT2]](s32), [[SEXT3]](s32)
     ; CHECK: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<4 x s32>)
-    %0:_(<4 x s16>) = G_IMPLICIT_DEF
+    %0:_(<4 x s16>) = COPY $vgpr0_vgpr1
     %1:_(<4 x s32>) = G_SEXT %0
     $vgpr0_vgpr1_vgpr2_vgpr3 = COPY %1
 ...
@@ -135,7 +137,7 @@ body: |
 ---
 name: test_sext_v2s32_to_v2s64
 body: |
-  bb.0.entry:
+  bb.0:
     liveins: $vgpr0_vgpr1
 
     ; CHECK-LABEL: name: test_sext_v2s32_to_v2s64
@@ -153,7 +155,7 @@ body: |
 ---
 name: test_sext_v3s32_to_v3s64
 body: |
-  bb.0.entry:
+  bb.0:
     liveins: $vgpr0_vgpr1_vgpr2
 
     ; CHECK-LABEL: name: test_sext_v3s32_to_v3s64
@@ -173,7 +175,7 @@ body: |
 ---
 name: test_sext_v4s32_to_v4s64
 body: |
-  bb.0.entry:
+  bb.0:
     liveins: $vgpr0_vgpr1_vgpr2_vgpr3
 
     ; CHECK-LABEL: name: test_sext_v4s32_to_v4s64
diff --git a/test/CodeGen/AMDGPU/GlobalISel/legalize-zext.mir b/test/CodeGen/AMDGPU/GlobalISel/legalize-zext.mir
index c6f1df1b6725e4a6bda070acd499c0b9596652aa..f4f2bf3eaab4af0d09746b10434343390cb12026 100644 (file)
--- a/test/CodeGen/AMDGPU/GlobalISel/legalize-zext.mir
+++ b/test/CodeGen/AMDGPU/GlobalISel/legalize-zext.mir
@@ -4,7 +4,7 @@
 ---
 name: test_zext_s32_to_s64
 body: |
-  bb.0.entry:
+  bb.0:
     liveins: $vgpr0
 
     ; CHECK-LABEL: name: test_zext_s32_to_s64
@@ -19,7 +19,7 @@ body: |
 ---
 name: test_zext_s16_to_s64
 body: |
-  bb.0.entry:
+  bb.0:
     liveins: $vgpr0
 
     ; CHECK-LABEL: name: test_zext_s16_to_s64
@@ -37,7 +37,7 @@ body: |
 ---
 name: test_zext_s16_to_s32
 body: |
-  bb.0.entry:
+  bb.0:
     liveins: $vgpr0
 
     ; CHECK-LABEL: name: test_zext_s16_to_s32
@@ -55,7 +55,7 @@ body: |
 ---
 name: test_zext_i1_to_s32
 body: |
-  bb.0.entry:
+  bb.0:
 
     ; CHECK-LABEL: name: test_zext_i1_to_s32
     ; CHECK: [[C:%[0-9]+]]:_(s1) = G_CONSTANT i1 false
@@ -69,7 +69,7 @@ body: |
 ---
 name: test_zext_i1_to_i64
 body: |
-  bb.0.entry:
+  bb.0:
 
     ; CHECK-LABEL: name: test_zext_i1_to_i64
     ; CHECK: [[C:%[0-9]+]]:_(s1) = G_CONSTANT i1 false
@@ -83,7 +83,7 @@ body: |
 ---
 name: test_zext_v2s16_to_v2s32
 body: |
-  bb.0.entry:
+  bb.0:
     liveins: $vgpr0
 
     ; CHECK-LABEL: name: test_zext_v2s16_to_v2s32
@@ -101,38 +101,40 @@ body: |
 ---
 name: test_zext_v3s16_to_v3s32
 body: |
-  bb.0.entry:
-    liveins: $vgpr0
+  bb.0:
+    liveins: $vgpr0_vgpr1
 
     ; CHECK-LABEL: name: test_zext_v3s16_to_v3s32
-    ; CHECK: [[DEF:%[0-9]+]]:_(<3 x s16>) = G_IMPLICIT_DEF
-    ; CHECK: [[UV:%[0-9]+]]:_(s16), [[UV1:%[0-9]+]]:_(s16), [[UV2:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[DEF]](<3 x s16>)
+    ; CHECK: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $vgpr0_vgpr1
+    ; CHECK: [[EXTRACT:%[0-9]+]]:_(<3 x s16>) = G_EXTRACT [[COPY]](<4 x s16>), 0
+    ; CHECK: [[UV:%[0-9]+]]:_(s16), [[UV1:%[0-9]+]]:_(s16), [[UV2:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[EXTRACT]](<3 x s16>)
     ; CHECK: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[UV]](s16)
     ; CHECK: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[UV1]](s16)
     ; CHECK: [[ZEXT2:%[0-9]+]]:_(s32) = G_ZEXT [[UV2]](s16)
     ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[ZEXT]](s32), [[ZEXT1]](s32), [[ZEXT2]](s32)
     ; CHECK: $vgpr0_vgpr1_vgpr2 = COPY [[BUILD_VECTOR]](<3 x s32>)
-    %0:_(<3 x s16>) = G_IMPLICIT_DEF
-    %1:_(<3 x s32>) = G_ZEXT %0
-    $vgpr0_vgpr1_vgpr2 = COPY %1
+    %0:_(<4 x s16>) = COPY $vgpr0_vgpr1
+    %1:_(<3 x s16>) = G_EXTRACT %0, 0
+    %2:_(<3 x s32>) = G_ZEXT %1
+    $vgpr0_vgpr1_vgpr2 = COPY %2
 ...
 
 ---
 name: test_zext_v4s16_to_v4s32
 body: |
-  bb.0.entry:
-    liveins: $vgpr0
+  bb.0:
+    liveins: $vgpr0_vgpr1
 
     ; CHECK-LABEL: name: test_zext_v4s16_to_v4s32
-    ; CHECK: [[DEF:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF
-    ; CHECK: [[UV:%[0-9]+]]:_(s16), [[UV1:%[0-9]+]]:_(s16), [[UV2:%[0-9]+]]:_(s16), [[UV3:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[DEF]](<4 x s16>)
+    ; CHECK: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $vgpr0_vgpr1
+    ; CHECK: [[UV:%[0-9]+]]:_(s16), [[UV1:%[0-9]+]]:_(s16), [[UV2:%[0-9]+]]:_(s16), [[UV3:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[COPY]](<4 x s16>)
     ; CHECK: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[UV]](s16)
     ; CHECK: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[UV1]](s16)
     ; CHECK: [[ZEXT2:%[0-9]+]]:_(s32) = G_ZEXT [[UV2]](s16)
     ; CHECK: [[ZEXT3:%[0-9]+]]:_(s32) = G_ZEXT [[UV3]](s16)
     ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[ZEXT]](s32), [[ZEXT1]](s32), [[ZEXT2]](s32), [[ZEXT3]](s32)
     ; CHECK: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<4 x s32>)
-    %0:_(<4 x s16>) = G_IMPLICIT_DEF
+    %0:_(<4 x s16>) = COPY $vgpr0_vgpr1
     %1:_(<4 x s32>) = G_ZEXT %0
     $vgpr0_vgpr1_vgpr2_vgpr3 = COPY %1
 ...
@@ -140,7 +142,7 @@ body: |
 ---
 name: test_zext_v2s32_to_v2s64
 body: |
-  bb.0.entry:
+  bb.0:
     liveins: $vgpr0_vgpr1
 
     ; CHECK-LABEL: name: test_zext_v2s32_to_v2s64
@@ -158,7 +160,7 @@ body: |
 ---
 name: test_zext_v3s32_to_v3s64
 body: |
-  bb.0.entry:
+  bb.0:
     liveins: $vgpr0_vgpr1_vgpr2
 
     ; CHECK-LABEL: name: test_zext_v3s32_to_v3s64
@@ -178,7 +180,7 @@ body: |
 ---
 name: test_zext_v4s32_to_v4s64
 body: |
-  bb.0.entry:
+  bb.0:
     liveins: $vgpr0_vgpr1_vgpr2_vgpr3
 
     ; CHECK-LABEL: name: test_zext_v4s32_to_v4s64
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