AArch64/PEI: Do not add reserved regs to liveins

We do not track liveness for reserved registers. It is unnecessary to
add them to block livein lists.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@304059 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/CodeGen/PrologEpilogInserter.cpp b/lib/CodeGen/PrologEpilogInserter.cpp
index a483ec764652b854382d7bf4a1f858ae21b33f66..a9813e534c5fa660d203b0adb1df9ca76658d093 100644 (file)
--- a/lib/CodeGen/PrologEpilogInserter.cpp
+++ b/lib/CodeGen/PrologEpilogInserter.cpp
@@ -450,12 +450,13 @@ static void updateLiveness(MachineFunction &MF) {
 
   const std::vector<CalleeSavedInfo> &CSI = MFI.getCalleeSavedInfo();
 
+  MachineRegisterInfo &MRI = MF.getRegInfo();
   for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
     for (MachineBasicBlock *MBB : Visited) {
       MCPhysReg Reg = CSI[i].getReg();
       // Add the callee-saved register as live-in.
       // It's killed at the spill.
-      if (!MBB->isLiveIn(Reg))
+      if (!MRI.isReserved(Reg) && !MBB->isLiveIn(Reg))
         MBB->addLiveIn(Reg);
     }
   }

diff --git a/lib/Target/AArch64/AArch64FrameLowering.cpp b/lib/Target/AArch64/AArch64FrameLowering.cpp
index 681024918a3ed24c6998ef4c3172a34afa35a401..0b92249580c820fcf91740f4393bdad50323abf7 100644 (file)
--- a/lib/Target/AArch64/AArch64FrameLowering.cpp
+++ b/lib/Target/AArch64/AArch64FrameLowering.cpp
@@ -991,6 +991,7 @@ bool AArch64FrameLowering::spillCalleeSavedRegisters(
   SmallVector<RegPairInfo, 8> RegPairs;
 
   computeCalleeSaveRegisterPairs(MF, CSI, TRI, RegPairs);
+  const MachineRegisterInfo &MRI = MF.getRegInfo();
 
   for (auto RPII = RegPairs.rbegin(), RPIE = RegPairs.rend(); RPII != RPIE;
        ++RPII) {
@@ -1022,9 +1023,11 @@ bool AArch64FrameLowering::spillCalleeSavedRegisters(
           dbgs() << ")\n");
 
     MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(StrOpc));
-    MBB.addLiveIn(Reg1);
+    if (!MRI.isReserved(Reg1))
+      MBB.addLiveIn(Reg1);
     if (RPI.isPaired()) {
-      MBB.addLiveIn(Reg2);
+      if (!MRI.isReserved(Reg2))
+        MBB.addLiveIn(Reg2);
       MIB.addReg(Reg2, getPrologueDeath(MF, Reg2));
       MIB.addMemOperand(MF.getMachineMemOperand(
           MachinePointerInfo::getFixedStack(MF, RPI.FrameIdx + 1),

diff --git a/test/CodeGen/AArch64/live-interval-analysis.mir b/test/CodeGen/AArch64/live-interval-analysis.mir
index d44300973566cba1f6cacde2e00be4889f11aed0..93dfcf507fff39353aa3947f7e452b66f477d564 100644 (file)
--- a/test/CodeGen/AArch64/live-interval-analysis.mir
+++ b/test/CodeGen/AArch64/live-interval-analysis.mir
@@ -6,7 +6,7 @@
 ---
 # CHECK-LABEL: ********** INTERVALS **********
 # W29 is reserved, so we should only see dead defs
-# CHECK-DAG: W29 [0B,0d:{{[0-9]+}})[32r,32d:{{[0-9]+}})[64r,64d:{{[0-9]+}})
+# CHECK-DAG: W29 [32r,32d:{{[0-9]+}})[64r,64d:{{[0-9]+}})
 # For normal registers like x28 we should see the full intervals
 # CHECK-DAG: W28 [0B,16r:{{[0-9]+}})[32r,48r:{{[0-9]+}})[48r,48d:{{[0-9]+}})
 # CHECK: # End machine code for function reserved_reg_liveness.
@@ -14,7 +14,7 @@ name: reserved_reg_liveness
 tracksRegLiveness: true
 body: |
   bb.0:
-    liveins: %x28_fp
+    liveins: %x28
     %6 : xseqpairsclass = COPY %x28_fp
     %x28_fp = COPY %6
     %x28 = COPY %x28