Merging r309323:

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r309323 | ab | 2017-07-27 14:27:25 -0700 (Thu, 27 Jul 2017) | 12 lines

[AArch64] Fix legality info passed to demanded bits for TBI opt.

The (seldom-used) TBI-aware optimization had a typo lying dormant since
it was first introduced, in r252573:  when asking for demanded bits, it
told TLI that it was running after legalize, where the opposite was
true.

This is an important piece of information, that the demanded bits
analysis uses to make assumptions about the node.  r301019 added such an
assumption, which was broken by the TBI combine.

Instead, pass the correct flags to TLO.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_50@309586 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/AArch64/AArch64ISelLowering.cpp b/lib/Target/AArch64/AArch64ISelLowering.cpp
index 8c30c4410c097364dc7f2a9d3e9d9c6d72fe4037..9d879886d39dd93b188fa8720be7ac8d95fe1b19 100644 (file)
--- a/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -9586,8 +9586,8 @@ static bool performTBISimplification(SDValue Addr,
                                      SelectionDAG &DAG) {
   APInt DemandedMask = APInt::getLowBitsSet(64, 56);
   KnownBits Known;
-  TargetLowering::TargetLoweringOpt TLO(DAG, DCI.isBeforeLegalize(),
-                                        DCI.isBeforeLegalizeOps());
+  TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
+                                        !DCI.isBeforeLegalizeOps());
   const TargetLowering &TLI = DAG.getTargetLoweringInfo();
   if (TLI.SimplifyDemandedBits(Addr, DemandedMask, Known, TLO)) {
     DCI.CommitTargetLoweringOpt(TLO);

diff --git a/test/CodeGen/AArch64/tbi.ll b/test/CodeGen/AArch64/tbi.ll
index ab2d31b7cacc0ece1bb9b6f08200cb755dbae360..153bd4e6438d8d3c2153f388404e6ccf932780ce 100644 (file)
--- a/test/CodeGen/AArch64/tbi.ll
+++ b/test/CodeGen/AArch64/tbi.ll
@@ -100,3 +100,14 @@ define i32 @ld_and32_narrower(i64 %p) {
   %load = load i32, i32* %cast
   ret i32 %load
 }
+
+; BOTH-LABEL:ld_and8:
+; BOTH: and x
+define i32 @ld_and8(i64 %base, i8 %off) {
+  %off_masked = and i8 %off, 63
+  %off_64 = zext i8 %off_masked to i64
+  %p = add i64 %base, %off_64
+  %cast = inttoptr i64 %p to i32*
+  %load = load i32, i32* %cast
+  ret i32 %load
+}