/* Returns offset of tsrm_ls_cache slot from Thread Control Block address */
TSRM_API size_t tsrm_get_ls_cache_tcb_offset(void)
{/*{{{*/
-#if defined(__x86_64__) && defined(__GNUC__)
+#if defined(__APPLE__) && defined(__x86_64__)
+ // TODO: Implement support for fast JIT ZTS code ???
+ return 0;
+#elif defined(__x86_64__) && defined(__GNUC__)
size_t ret;
asm ("movq _tsrm_ls_cache@gottpoff(%%rip),%0"
echo 'int i;' > conftest.$ac_ext
if AC_TRY_EVAL(ac_compile); then
case `/usr/bin/file conftest.o` in
+ *"Mach-O 64-bit"*)
+ DASM_FLAGS="-D X64APPLE=1 -D X64=1"
+ ;;
*64-bit*)
DASM_FLAGS="-D X64=1"
;;
| mov reg, aword [0x2c]
| mov reg, aword [reg + tsrm_tls_index]
| mov reg, aword [reg + tsrm_tls_offset]
+| .elif X64APPLE
+| gs
+|| if (tsrm_ls_cache_tcb_offset) {
+| mov reg, aword [tsrm_ls_cache_tcb_offset]
+|| } else {
+| mov reg, aword [tsrm_tls_index]
+| mov reg, aword [reg + tsrm_tls_offset]
+|| }
| .elif X64
| fs
|| if (tsrm_ls_cache_tcb_offset) {
return FAILURE;
}
} while(0);
+# elif defined(__APPLE__) && defined(__x86_64__)
+ tsrm_ls_cache_tcb_offset = tsrm_get_ls_cache_tcb_offset();
+ if (tsrm_ls_cache_tcb_offset == 0) {
+ size_t *ti;
+ __asm__(
+ "leaq __tsrm_ls_cache(%%rip),%0"
+ : "=r" (ti));
+ tsrm_tls_offset = ti[2];
+ tsrm_tls_index = ti[1] * 8;
+ }
# elif defined(__GNUC__) && defined(__x86_64__)
tsrm_ls_cache_tcb_offset = tsrm_get_ls_cache_tcb_offset();
if (tsrm_ls_cache_tcb_offset == 0) {