Remove Windows line endings in some tests to prepare for a future commit. NFC

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268882 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/test/CodeGen/X86/avx512ifmavl-intrinsics.ll b/test/CodeGen/X86/avx512ifmavl-intrinsics.ll
index 3ed8c3104ee67bbc6d989558f022a1d830df88d8..2a8c6b36558a77cf7b5a8c98dcb2ed3d26af1390 100644 (file)
--- a/test/CodeGen/X86/avx512ifmavl-intrinsics.ll
+++ b/test/CodeGen/X86/avx512ifmavl-intrinsics.ll
@@ -1,209 +1,209 @@
-; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=knl -mattr=+avx512vl -mattr=+avx512ifma | FileCheck %s\r
-\r
-declare <2 x i64> @llvm.x86.avx512.mask.vpmadd52h.uq.128(<2 x i64>, <2 x i64>, <2 x i64>, i8)\r
-\r
-define <2 x i64>@test_int_x86_avx512_mask_vpmadd52h_uq_128(<2 x i64> %x0, <2 x i64> %x1, <2 x i64> %x2, i8 %x3) {\r
-; CHECK-LABEL: test_int_x86_avx512_mask_vpmadd52h_uq_128:\r
-; CHECK: kmovw %edi, %k1\r
-; CHECK: vmovaps %zmm0, %zmm3\r
-; CHECK: vpmadd52huq %xmm2, %xmm1, %xmm3 {%k1}\r
-; CHECK: vmovaps %zmm0, %zmm4\r
-; CHECK: vpmadd52huq %xmm2, %xmm1, %xmm4\r
-; CHECK: vxorps %xmm2, %xmm2, %xmm2\r
-; CHECK: vpmadd52huq %xmm2, %xmm1, %xmm0 {%k1}\r
-; CHECK: vpmadd52huq %xmm2, %xmm1, %xmm2 {%k1} {z}\r
-; CHECK: vpaddq %xmm0, %xmm3, %xmm0\r
-; CHECK: vpaddq %xmm2, %xmm4, %xmm1\r
-; CHECK: vpaddq %xmm0, %xmm1, %xmm0\r
-\r
-  %res = call <2 x i64> @llvm.x86.avx512.mask.vpmadd52h.uq.128(<2 x i64> %x0, <2 x i64> %x1, <2 x i64> %x2, i8 %x3)\r
-  %res1 = call <2 x i64> @llvm.x86.avx512.mask.vpmadd52h.uq.128(<2 x i64> %x0, <2 x i64> %x1, <2 x i64> zeroinitializer, i8 %x3)\r
-  %res2 = call <2 x i64> @llvm.x86.avx512.mask.vpmadd52h.uq.128(<2 x i64> zeroinitializer, <2 x i64> %x1, <2 x i64> zeroinitializer, i8 %x3)\r
-  %res3 = call <2 x i64> @llvm.x86.avx512.mask.vpmadd52h.uq.128(<2 x i64> %x0, <2 x i64> %x1, <2 x i64> %x2, i8 -1)\r
-  %res4 = add <2 x i64> %res, %res1\r
-  %res5 = add <2 x i64> %res3, %res2\r
-  %res6 = add <2 x i64> %res5, %res4\r
-  ret <2 x i64> %res6\r
-}\r
-\r
-declare <4 x i64> @llvm.x86.avx512.mask.vpmadd52h.uq.256(<4 x i64>, <4 x i64>, <4 x i64>, i8)\r
-\r
-define <4 x i64>@test_int_x86_avx512_mask_vpmadd52h_uq_256(<4 x i64> %x0, <4 x i64> %x1, <4 x i64> %x2, i8 %x3) {\r
-; CHECK-LABEL: test_int_x86_avx512_mask_vpmadd52h_uq_256:\r
-; CHECK: kmovw %edi, %k1\r
-; CHECK: vmovaps %zmm0, %zmm3\r
-; CHECK: vpmadd52huq %ymm2, %ymm1, %ymm3 {%k1}\r
-; CHECK: vmovaps %zmm0, %zmm4\r
-; CHECK: vpmadd52huq %ymm2, %ymm1, %ymm4\r
-; CHECK: vxorps %ymm2, %ymm2, %ymm2\r
-; CHECK: vpmadd52huq %ymm2, %ymm1, %ymm0 {%k1}\r
-; CHECK: vpmadd52huq %ymm2, %ymm1, %ymm2 {%k1} {z}\r
-; CHECK: vpaddq %ymm0, %ymm3, %ymm0\r
-; CHECK: vpaddq %ymm2, %ymm4, %ymm1\r
-; CHECK: vpaddq %ymm0, %ymm1, %ymm0\r
-\r
-  %res = call <4 x i64> @llvm.x86.avx512.mask.vpmadd52h.uq.256(<4 x i64> %x0, <4 x i64> %x1, <4 x i64> %x2, i8 %x3)\r
-  %res1 = call <4 x i64> @llvm.x86.avx512.mask.vpmadd52h.uq.256(<4 x i64> %x0, <4 x i64> %x1, <4 x i64> zeroinitializer, i8 %x3)\r
-  %res2 = call <4 x i64> @llvm.x86.avx512.mask.vpmadd52h.uq.256(<4 x i64> zeroinitializer, <4 x i64> %x1, <4 x i64> zeroinitializer, i8 %x3)\r
-  %res3 = call <4 x i64> @llvm.x86.avx512.mask.vpmadd52h.uq.256(<4 x i64> %x0, <4 x i64> %x1, <4 x i64> %x2, i8 -1)\r
-  %res4 = add <4 x i64> %res, %res1\r
-  %res5 = add <4 x i64> %res3, %res2\r
-  %res6 = add <4 x i64> %res5, %res4\r
-  ret <4 x i64> %res6\r
-}\r
-\r
-declare <2 x i64> @llvm.x86.avx512.maskz.vpmadd52h.uq.128(<2 x i64>, <2 x i64>, <2 x i64>, i8)\r
-\r
-define <2 x i64>@test_int_x86_avx512_maskz_vpmadd52h_uq_128(<2 x i64> %x0, <2 x i64> %x1, <2 x i64> %x2, i8 %x3) {\r
-; CHECK-LABEL: test_int_x86_avx512_maskz_vpmadd52h_uq_128:\r
-; CHECK: kmovw %edi, %k1\r
-; CHECK: vmovaps %zmm0, %zmm3\r
-; CHECK: vpmadd52huq %xmm2, %xmm1, %xmm3 {%k1} {z}\r
-; CHECK: vmovaps %zmm0, %zmm4\r
-; CHECK: vpmadd52huq %xmm2, %xmm1, %xmm4\r
-; CHECK: vxorps %xmm2, %xmm2, %xmm2\r
-; CHECK: vpmadd52huq %xmm2, %xmm1, %xmm0 {%k1} {z}\r
-; CHECK: vpmadd52huq %xmm2, %xmm1, %xmm2 {%k1} {z}\r
-; CHECK: vpaddq %xmm0, %xmm3, %xmm0\r
-; CHECK: vpaddq %xmm2, %xmm4, %xmm1\r
-; CHECK: vpaddq %xmm0, %xmm1, %xmm0\r
-\r
-  %res = call <2 x i64> @llvm.x86.avx512.maskz.vpmadd52h.uq.128(<2 x i64> %x0, <2 x i64> %x1, <2 x i64> %x2, i8 %x3)\r
-  %res1 = call <2 x i64> @llvm.x86.avx512.maskz.vpmadd52h.uq.128(<2 x i64> %x0, <2 x i64> %x1, <2 x i64> zeroinitializer, i8 %x3)\r
-  %res2 = call <2 x i64> @llvm.x86.avx512.maskz.vpmadd52h.uq.128(<2 x i64> zeroinitializer, <2 x i64> %x1, <2 x i64> zeroinitializer, i8 %x3)\r
-  %res3 = call <2 x i64> @llvm.x86.avx512.maskz.vpmadd52h.uq.128(<2 x i64> %x0, <2 x i64> %x1, <2 x i64> %x2, i8 -1)\r
-  %res4 = add <2 x i64> %res, %res1\r
-  %res5 = add <2 x i64> %res3, %res2\r
-  %res6 = add <2 x i64> %res5, %res4\r
-  ret <2 x i64> %res6\r
-}\r
-\r
-declare <4 x i64> @llvm.x86.avx512.maskz.vpmadd52h.uq.256(<4 x i64>, <4 x i64>, <4 x i64>, i8)\r
-\r
-define <4 x i64>@test_int_x86_avx512_maskz_vpmadd52h_uq_256(<4 x i64> %x0, <4 x i64> %x1, <4 x i64> %x2, i8 %x3) {\r
-; CHECK-LABEL: test_int_x86_avx512_maskz_vpmadd52h_uq_256:\r
-; CHECK: kmovw %edi, %k1\r
-; CHECK: vmovaps %zmm0, %zmm3\r
-; CHECK: vpmadd52huq %ymm2, %ymm1, %ymm3 {%k1} {z}\r
-; CHECK: vmovaps %zmm0, %zmm4\r
-; CHECK: vpmadd52huq %ymm2, %ymm1, %ymm4\r
-; CHECK: vxorps %ymm2, %ymm2, %ymm2\r
-; CHECK: vpmadd52huq %ymm2, %ymm1, %ymm0 {%k1} {z}\r
-; CHECK: vpmadd52huq %ymm2, %ymm1, %ymm2 {%k1} {z}\r
-; CHECK: vpaddq %ymm0, %ymm3, %ymm0\r
-; CHECK: vpaddq %ymm2, %ymm4, %ymm1\r
-; CHECK: vpaddq %ymm0, %ymm1, %ymm0\r
-\r
-  %res = call <4 x i64> @llvm.x86.avx512.maskz.vpmadd52h.uq.256(<4 x i64> %x0, <4 x i64> %x1, <4 x i64> %x2, i8 %x3)\r
-  %res1 = call <4 x i64> @llvm.x86.avx512.maskz.vpmadd52h.uq.256(<4 x i64> %x0, <4 x i64> %x1, <4 x i64> zeroinitializer, i8 %x3)\r
-  %res2 = call <4 x i64> @llvm.x86.avx512.maskz.vpmadd52h.uq.256(<4 x i64> zeroinitializer, <4 x i64> %x1, <4 x i64> zeroinitializer, i8 %x3)\r
-  %res3 = call <4 x i64> @llvm.x86.avx512.maskz.vpmadd52h.uq.256(<4 x i64> %x0, <4 x i64> %x1, <4 x i64> %x2, i8 -1)\r
-  %res4 = add <4 x i64> %res, %res1\r
-  %res5 = add <4 x i64> %res3, %res2\r
-  %res6 = add <4 x i64> %res5, %res4\r
-  ret <4 x i64> %res6\r
-}\r
-\r
-declare <2 x i64> @llvm.x86.avx512.mask.vpmadd52l.uq.128(<2 x i64>, <2 x i64>, <2 x i64>, i8)\r
-\r
-define <2 x i64>@test_int_x86_avx512_mask_vpmadd52l_uq_128(<2 x i64> %x0, <2 x i64> %x1, <2 x i64> %x2, i8 %x3) {\r
-; CHECK-LABEL: test_int_x86_avx512_mask_vpmadd52l_uq_128:\r
-; CHECK: kmovw %edi, %k1\r
-; CHECK: vmovaps %zmm0, %zmm3\r
-; CHECK: vpmadd52luq %xmm2, %xmm1, %xmm3 {%k1}\r
-; CHECK: vmovaps %zmm0, %zmm4\r
-; CHECK: vpmadd52luq %xmm2, %xmm1, %xmm4\r
-; CHECK: vxorps %xmm2, %xmm2, %xmm2\r
-; CHECK: vpmadd52luq %xmm2, %xmm1, %xmm0 {%k1}\r
-; CHECK: vpmadd52luq %xmm2, %xmm1, %xmm2 {%k1} {z}\r
-; CHECK: vpaddq %xmm0, %xmm3, %xmm0\r
-; CHECK: vpaddq %xmm2, %xmm4, %xmm1\r
-; CHECK: vpaddq %xmm0, %xmm1, %xmm0\r
-\r
-  %res = call <2 x i64> @llvm.x86.avx512.mask.vpmadd52l.uq.128(<2 x i64> %x0, <2 x i64> %x1, <2 x i64> %x2, i8 %x3)\r
-  %res1 = call <2 x i64> @llvm.x86.avx512.mask.vpmadd52l.uq.128(<2 x i64> %x0, <2 x i64> %x1, <2 x i64> zeroinitializer, i8 %x3)\r
-  %res2 = call <2 x i64> @llvm.x86.avx512.mask.vpmadd52l.uq.128(<2 x i64> zeroinitializer, <2 x i64> %x1, <2 x i64> zeroinitializer, i8 %x3)\r
-  %res3 = call <2 x i64> @llvm.x86.avx512.mask.vpmadd52l.uq.128(<2 x i64> %x0, <2 x i64> %x1, <2 x i64> %x2, i8 -1)\r
-  %res4 = add <2 x i64> %res, %res1\r
-  %res5 = add <2 x i64> %res3, %res2\r
-  %res6 = add <2 x i64> %res5, %res4\r
-  ret <2 x i64> %res6\r
-}\r
-\r
-declare <4 x i64> @llvm.x86.avx512.mask.vpmadd52l.uq.256(<4 x i64>, <4 x i64>, <4 x i64>, i8)\r
-\r
-define <4 x i64>@test_int_x86_avx512_mask_vpmadd52l_uq_256(<4 x i64> %x0, <4 x i64> %x1, <4 x i64> %x2, i8 %x3) {\r
-; CHECK-LABEL: test_int_x86_avx512_mask_vpmadd52l_uq_256:\r
-; CHECK: kmovw %edi, %k1\r
-; CHECK: vmovaps %zmm0, %zmm3\r
-; CHECK: vpmadd52luq %ymm2, %ymm1, %ymm3 {%k1}\r
-; CHECK: vmovaps %zmm0, %zmm4\r
-; CHECK: vpmadd52luq %ymm2, %ymm1, %ymm4\r
-; CHECK: vxorps %ymm2, %ymm2, %ymm2\r
-; CHECK: vpmadd52luq %ymm2, %ymm1, %ymm0 {%k1}\r
-; CHECK: vpmadd52luq %ymm2, %ymm1, %ymm2 {%k1} {z}\r
-; CHECK: vpaddq %ymm0, %ymm3, %ymm0\r
-; CHECK: vpaddq %ymm2, %ymm4, %ymm1\r
-; CHECK: vpaddq %ymm0, %ymm1, %ymm0\r
-\r
-  %res = call <4 x i64> @llvm.x86.avx512.mask.vpmadd52l.uq.256(<4 x i64> %x0, <4 x i64> %x1, <4 x i64> %x2, i8 %x3)\r
-  %res1 = call <4 x i64> @llvm.x86.avx512.mask.vpmadd52l.uq.256(<4 x i64> %x0, <4 x i64> %x1, <4 x i64> zeroinitializer, i8 %x3)\r
-  %res2 = call <4 x i64> @llvm.x86.avx512.mask.vpmadd52l.uq.256(<4 x i64> zeroinitializer, <4 x i64> %x1, <4 x i64> zeroinitializer, i8 %x3)\r
-  %res3 = call <4 x i64> @llvm.x86.avx512.mask.vpmadd52l.uq.256(<4 x i64> %x0, <4 x i64> %x1, <4 x i64> %x2, i8 -1)\r
-  %res4 = add <4 x i64> %res, %res1\r
-  %res5 = add <4 x i64> %res3, %res2\r
-  %res6 = add <4 x i64> %res5, %res4\r
-  ret <4 x i64> %res6\r
-}\r
-\r
-declare <2 x i64> @llvm.x86.avx512.maskz.vpmadd52l.uq.128(<2 x i64>, <2 x i64>, <2 x i64>, i8)\r
-\r
-define <2 x i64>@test_int_x86_avx512_maskz_vpmadd52l_uq_128(<2 x i64> %x0, <2 x i64> %x1, <2 x i64> %x2, i8 %x3) {\r
-; CHECK-LABEL: test_int_x86_avx512_maskz_vpmadd52l_uq_128:\r
-; CHECK: kmovw %edi, %k1\r
-; CHECK: vmovaps %zmm0, %zmm3\r
-; CHECK: vpmadd52luq %xmm2, %xmm1, %xmm3 {%k1} {z}\r
-; CHECK: vmovaps %zmm0, %zmm4\r
-; CHECK: vpmadd52luq %xmm2, %xmm1, %xmm4\r
-; CHECK: vxorps %xmm2, %xmm2, %xmm2\r
-; CHECK: vpmadd52luq %xmm2, %xmm1, %xmm0 {%k1} {z}\r
-; CHECK: vpmadd52luq %xmm2, %xmm1, %xmm2 {%k1} {z}\r
-; CHECK: vpaddq %xmm0, %xmm3, %xmm0\r
-; CHECK: vpaddq %xmm2, %xmm4, %xmm1\r
-; CHECK: vpaddq %xmm0, %xmm1, %xmm0\r
-\r
-  %res = call <2 x i64> @llvm.x86.avx512.maskz.vpmadd52l.uq.128(<2 x i64> %x0, <2 x i64> %x1, <2 x i64> %x2, i8 %x3)\r
-  %res1 = call <2 x i64> @llvm.x86.avx512.maskz.vpmadd52l.uq.128(<2 x i64> %x0, <2 x i64> %x1, <2 x i64> zeroinitializer, i8 %x3)\r
-  %res2 = call <2 x i64> @llvm.x86.avx512.maskz.vpmadd52l.uq.128(<2 x i64> zeroinitializer, <2 x i64> %x1, <2 x i64> zeroinitializer, i8 %x3)\r
-  %res3 = call <2 x i64> @llvm.x86.avx512.maskz.vpmadd52l.uq.128(<2 x i64> %x0, <2 x i64> %x1, <2 x i64> %x2, i8 -1)\r
-  %res4 = add <2 x i64> %res, %res1\r
-  %res5 = add <2 x i64> %res3, %res2\r
-  %res6 = add <2 x i64> %res5, %res4\r
-  ret <2 x i64> %res6\r
-}\r
-\r
-declare <4 x i64> @llvm.x86.avx512.maskz.vpmadd52l.uq.256(<4 x i64>, <4 x i64>, <4 x i64>, i8)\r
-\r
-define <4 x i64>@test_int_x86_avx512_maskz_vpmadd52l_uq_256(<4 x i64> %x0, <4 x i64> %x1, <4 x i64> %x2, i8 %x3) {\r
-; CHECK-LABEL: test_int_x86_avx512_maskz_vpmadd52l_uq_256:\r
-; CHECK: kmovw %edi, %k1\r
-; CHECK: vmovaps %zmm0, %zmm3\r
-; CHECK: vpmadd52luq %ymm2, %ymm1, %ymm3 {%k1} {z}\r
-; CHECK: vmovaps %zmm0, %zmm4\r
-; CHECK: vpmadd52luq %ymm2, %ymm1, %ymm4\r
-; CHECK: vxorps %ymm2, %ymm2, %ymm2\r
-; CHECK: vpmadd52luq %ymm2, %ymm1, %ymm0 {%k1} {z}\r
-; CHECK: vpmadd52luq %ymm2, %ymm1, %ymm2 {%k1} {z}\r
-; CHECK: vpaddq %ymm0, %ymm3, %ymm0\r
-; CHECK: vpaddq %ymm2, %ymm4, %ymm1\r
-; CHECK: vpaddq %ymm0, %ymm1, %ymm0\r
-\r
-  %res = call <4 x i64> @llvm.x86.avx512.maskz.vpmadd52l.uq.256(<4 x i64> %x0, <4 x i64> %x1, <4 x i64> %x2, i8 %x3)\r
-  %res1 = call <4 x i64> @llvm.x86.avx512.maskz.vpmadd52l.uq.256(<4 x i64> %x0, <4 x i64> %x1, <4 x i64> zeroinitializer, i8 %x3)\r
-  %res2 = call <4 x i64> @llvm.x86.avx512.maskz.vpmadd52l.uq.256(<4 x i64> zeroinitializer, <4 x i64> %x1, <4 x i64> zeroinitializer, i8 %x3)\r
-  %res3 = call <4 x i64> @llvm.x86.avx512.maskz.vpmadd52l.uq.256(<4 x i64> %x0, <4 x i64> %x1, <4 x i64> %x2, i8 -1)\r
-  %res4 = add <4 x i64> %res, %res1\r
-  %res5 = add <4 x i64> %res3, %res2\r
-  %res6 = add <4 x i64> %res5, %res4\r
-  ret <4 x i64> %res6\r
-}\r
+; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=knl -mattr=+avx512vl -mattr=+avx512ifma | FileCheck %s
+
+declare <2 x i64> @llvm.x86.avx512.mask.vpmadd52h.uq.128(<2 x i64>, <2 x i64>, <2 x i64>, i8)
+
+define <2 x i64>@test_int_x86_avx512_mask_vpmadd52h_uq_128(<2 x i64> %x0, <2 x i64> %x1, <2 x i64> %x2, i8 %x3) {
+; CHECK-LABEL: test_int_x86_avx512_mask_vpmadd52h_uq_128:
+; CHECK: kmovw %edi, %k1
+; CHECK: vmovaps %zmm0, %zmm3
+; CHECK: vpmadd52huq %xmm2, %xmm1, %xmm3 {%k1}
+; CHECK: vmovaps %zmm0, %zmm4
+; CHECK: vpmadd52huq %xmm2, %xmm1, %xmm4
+; CHECK: vxorps %xmm2, %xmm2, %xmm2
+; CHECK: vpmadd52huq %xmm2, %xmm1, %xmm0 {%k1}
+; CHECK: vpmadd52huq %xmm2, %xmm1, %xmm2 {%k1} {z}
+; CHECK: vpaddq %xmm0, %xmm3, %xmm0
+; CHECK: vpaddq %xmm2, %xmm4, %xmm1
+; CHECK: vpaddq %xmm0, %xmm1, %xmm0
+
+  %res = call <2 x i64> @llvm.x86.avx512.mask.vpmadd52h.uq.128(<2 x i64> %x0, <2 x i64> %x1, <2 x i64> %x2, i8 %x3)
+  %res1 = call <2 x i64> @llvm.x86.avx512.mask.vpmadd52h.uq.128(<2 x i64> %x0, <2 x i64> %x1, <2 x i64> zeroinitializer, i8 %x3)
+  %res2 = call <2 x i64> @llvm.x86.avx512.mask.vpmadd52h.uq.128(<2 x i64> zeroinitializer, <2 x i64> %x1, <2 x i64> zeroinitializer, i8 %x3)
+  %res3 = call <2 x i64> @llvm.x86.avx512.mask.vpmadd52h.uq.128(<2 x i64> %x0, <2 x i64> %x1, <2 x i64> %x2, i8 -1)
+  %res4 = add <2 x i64> %res, %res1
+  %res5 = add <2 x i64> %res3, %res2
+  %res6 = add <2 x i64> %res5, %res4
+  ret <2 x i64> %res6
+}
+
+declare <4 x i64> @llvm.x86.avx512.mask.vpmadd52h.uq.256(<4 x i64>, <4 x i64>, <4 x i64>, i8)
+
+define <4 x i64>@test_int_x86_avx512_mask_vpmadd52h_uq_256(<4 x i64> %x0, <4 x i64> %x1, <4 x i64> %x2, i8 %x3) {
+; CHECK-LABEL: test_int_x86_avx512_mask_vpmadd52h_uq_256:
+; CHECK: kmovw %edi, %k1
+; CHECK: vmovaps %zmm0, %zmm3
+; CHECK: vpmadd52huq %ymm2, %ymm1, %ymm3 {%k1}
+; CHECK: vmovaps %zmm0, %zmm4
+; CHECK: vpmadd52huq %ymm2, %ymm1, %ymm4
+; CHECK: vxorps %ymm2, %ymm2, %ymm2
+; CHECK: vpmadd52huq %ymm2, %ymm1, %ymm0 {%k1}
+; CHECK: vpmadd52huq %ymm2, %ymm1, %ymm2 {%k1} {z}
+; CHECK: vpaddq %ymm0, %ymm3, %ymm0
+; CHECK: vpaddq %ymm2, %ymm4, %ymm1
+; CHECK: vpaddq %ymm0, %ymm1, %ymm0
+
+  %res = call <4 x i64> @llvm.x86.avx512.mask.vpmadd52h.uq.256(<4 x i64> %x0, <4 x i64> %x1, <4 x i64> %x2, i8 %x3)
+  %res1 = call <4 x i64> @llvm.x86.avx512.mask.vpmadd52h.uq.256(<4 x i64> %x0, <4 x i64> %x1, <4 x i64> zeroinitializer, i8 %x3)
+  %res2 = call <4 x i64> @llvm.x86.avx512.mask.vpmadd52h.uq.256(<4 x i64> zeroinitializer, <4 x i64> %x1, <4 x i64> zeroinitializer, i8 %x3)
+  %res3 = call <4 x i64> @llvm.x86.avx512.mask.vpmadd52h.uq.256(<4 x i64> %x0, <4 x i64> %x1, <4 x i64> %x2, i8 -1)
+  %res4 = add <4 x i64> %res, %res1
+  %res5 = add <4 x i64> %res3, %res2
+  %res6 = add <4 x i64> %res5, %res4
+  ret <4 x i64> %res6
+}
+
+declare <2 x i64> @llvm.x86.avx512.maskz.vpmadd52h.uq.128(<2 x i64>, <2 x i64>, <2 x i64>, i8)
+
+define <2 x i64>@test_int_x86_avx512_maskz_vpmadd52h_uq_128(<2 x i64> %x0, <2 x i64> %x1, <2 x i64> %x2, i8 %x3) {
+; CHECK-LABEL: test_int_x86_avx512_maskz_vpmadd52h_uq_128:
+; CHECK: kmovw %edi, %k1
+; CHECK: vmovaps %zmm0, %zmm3
+; CHECK: vpmadd52huq %xmm2, %xmm1, %xmm3 {%k1} {z}
+; CHECK: vmovaps %zmm0, %zmm4
+; CHECK: vpmadd52huq %xmm2, %xmm1, %xmm4
+; CHECK: vxorps %xmm2, %xmm2, %xmm2
+; CHECK: vpmadd52huq %xmm2, %xmm1, %xmm0 {%k1} {z}
+; CHECK: vpmadd52huq %xmm2, %xmm1, %xmm2 {%k1} {z}
+; CHECK: vpaddq %xmm0, %xmm3, %xmm0
+; CHECK: vpaddq %xmm2, %xmm4, %xmm1
+; CHECK: vpaddq %xmm0, %xmm1, %xmm0
+
+  %res = call <2 x i64> @llvm.x86.avx512.maskz.vpmadd52h.uq.128(<2 x i64> %x0, <2 x i64> %x1, <2 x i64> %x2, i8 %x3)
+  %res1 = call <2 x i64> @llvm.x86.avx512.maskz.vpmadd52h.uq.128(<2 x i64> %x0, <2 x i64> %x1, <2 x i64> zeroinitializer, i8 %x3)
+  %res2 = call <2 x i64> @llvm.x86.avx512.maskz.vpmadd52h.uq.128(<2 x i64> zeroinitializer, <2 x i64> %x1, <2 x i64> zeroinitializer, i8 %x3)
+  %res3 = call <2 x i64> @llvm.x86.avx512.maskz.vpmadd52h.uq.128(<2 x i64> %x0, <2 x i64> %x1, <2 x i64> %x2, i8 -1)
+  %res4 = add <2 x i64> %res, %res1
+  %res5 = add <2 x i64> %res3, %res2
+  %res6 = add <2 x i64> %res5, %res4
+  ret <2 x i64> %res6
+}
+
+declare <4 x i64> @llvm.x86.avx512.maskz.vpmadd52h.uq.256(<4 x i64>, <4 x i64>, <4 x i64>, i8)
+
+define <4 x i64>@test_int_x86_avx512_maskz_vpmadd52h_uq_256(<4 x i64> %x0, <4 x i64> %x1, <4 x i64> %x2, i8 %x3) {
+; CHECK-LABEL: test_int_x86_avx512_maskz_vpmadd52h_uq_256:
+; CHECK: kmovw %edi, %k1
+; CHECK: vmovaps %zmm0, %zmm3
+; CHECK: vpmadd52huq %ymm2, %ymm1, %ymm3 {%k1} {z}
+; CHECK: vmovaps %zmm0, %zmm4
+; CHECK: vpmadd52huq %ymm2, %ymm1, %ymm4
+; CHECK: vxorps %ymm2, %ymm2, %ymm2
+; CHECK: vpmadd52huq %ymm2, %ymm1, %ymm0 {%k1} {z}
+; CHECK: vpmadd52huq %ymm2, %ymm1, %ymm2 {%k1} {z}
+; CHECK: vpaddq %ymm0, %ymm3, %ymm0
+; CHECK: vpaddq %ymm2, %ymm4, %ymm1
+; CHECK: vpaddq %ymm0, %ymm1, %ymm0
+
+  %res = call <4 x i64> @llvm.x86.avx512.maskz.vpmadd52h.uq.256(<4 x i64> %x0, <4 x i64> %x1, <4 x i64> %x2, i8 %x3)
+  %res1 = call <4 x i64> @llvm.x86.avx512.maskz.vpmadd52h.uq.256(<4 x i64> %x0, <4 x i64> %x1, <4 x i64> zeroinitializer, i8 %x3)
+  %res2 = call <4 x i64> @llvm.x86.avx512.maskz.vpmadd52h.uq.256(<4 x i64> zeroinitializer, <4 x i64> %x1, <4 x i64> zeroinitializer, i8 %x3)
+  %res3 = call <4 x i64> @llvm.x86.avx512.maskz.vpmadd52h.uq.256(<4 x i64> %x0, <4 x i64> %x1, <4 x i64> %x2, i8 -1)
+  %res4 = add <4 x i64> %res, %res1
+  %res5 = add <4 x i64> %res3, %res2
+  %res6 = add <4 x i64> %res5, %res4
+  ret <4 x i64> %res6
+}
+
+declare <2 x i64> @llvm.x86.avx512.mask.vpmadd52l.uq.128(<2 x i64>, <2 x i64>, <2 x i64>, i8)
+
+define <2 x i64>@test_int_x86_avx512_mask_vpmadd52l_uq_128(<2 x i64> %x0, <2 x i64> %x1, <2 x i64> %x2, i8 %x3) {
+; CHECK-LABEL: test_int_x86_avx512_mask_vpmadd52l_uq_128:
+; CHECK: kmovw %edi, %k1
+; CHECK: vmovaps %zmm0, %zmm3
+; CHECK: vpmadd52luq %xmm2, %xmm1, %xmm3 {%k1}
+; CHECK: vmovaps %zmm0, %zmm4
+; CHECK: vpmadd52luq %xmm2, %xmm1, %xmm4
+; CHECK: vxorps %xmm2, %xmm2, %xmm2
+; CHECK: vpmadd52luq %xmm2, %xmm1, %xmm0 {%k1}
+; CHECK: vpmadd52luq %xmm2, %xmm1, %xmm2 {%k1} {z}
+; CHECK: vpaddq %xmm0, %xmm3, %xmm0
+; CHECK: vpaddq %xmm2, %xmm4, %xmm1
+; CHECK: vpaddq %xmm0, %xmm1, %xmm0
+
+  %res = call <2 x i64> @llvm.x86.avx512.mask.vpmadd52l.uq.128(<2 x i64> %x0, <2 x i64> %x1, <2 x i64> %x2, i8 %x3)
+  %res1 = call <2 x i64> @llvm.x86.avx512.mask.vpmadd52l.uq.128(<2 x i64> %x0, <2 x i64> %x1, <2 x i64> zeroinitializer, i8 %x3)
+  %res2 = call <2 x i64> @llvm.x86.avx512.mask.vpmadd52l.uq.128(<2 x i64> zeroinitializer, <2 x i64> %x1, <2 x i64> zeroinitializer, i8 %x3)
+  %res3 = call <2 x i64> @llvm.x86.avx512.mask.vpmadd52l.uq.128(<2 x i64> %x0, <2 x i64> %x1, <2 x i64> %x2, i8 -1)
+  %res4 = add <2 x i64> %res, %res1
+  %res5 = add <2 x i64> %res3, %res2
+  %res6 = add <2 x i64> %res5, %res4
+  ret <2 x i64> %res6
+}
+
+declare <4 x i64> @llvm.x86.avx512.mask.vpmadd52l.uq.256(<4 x i64>, <4 x i64>, <4 x i64>, i8)
+
+define <4 x i64>@test_int_x86_avx512_mask_vpmadd52l_uq_256(<4 x i64> %x0, <4 x i64> %x1, <4 x i64> %x2, i8 %x3) {
+; CHECK-LABEL: test_int_x86_avx512_mask_vpmadd52l_uq_256:
+; CHECK: kmovw %edi, %k1
+; CHECK: vmovaps %zmm0, %zmm3
+; CHECK: vpmadd52luq %ymm2, %ymm1, %ymm3 {%k1}
+; CHECK: vmovaps %zmm0, %zmm4
+; CHECK: vpmadd52luq %ymm2, %ymm1, %ymm4
+; CHECK: vxorps %ymm2, %ymm2, %ymm2
+; CHECK: vpmadd52luq %ymm2, %ymm1, %ymm0 {%k1}
+; CHECK: vpmadd52luq %ymm2, %ymm1, %ymm2 {%k1} {z}
+; CHECK: vpaddq %ymm0, %ymm3, %ymm0
+; CHECK: vpaddq %ymm2, %ymm4, %ymm1
+; CHECK: vpaddq %ymm0, %ymm1, %ymm0
+
+  %res = call <4 x i64> @llvm.x86.avx512.mask.vpmadd52l.uq.256(<4 x i64> %x0, <4 x i64> %x1, <4 x i64> %x2, i8 %x3)
+  %res1 = call <4 x i64> @llvm.x86.avx512.mask.vpmadd52l.uq.256(<4 x i64> %x0, <4 x i64> %x1, <4 x i64> zeroinitializer, i8 %x3)
+  %res2 = call <4 x i64> @llvm.x86.avx512.mask.vpmadd52l.uq.256(<4 x i64> zeroinitializer, <4 x i64> %x1, <4 x i64> zeroinitializer, i8 %x3)
+  %res3 = call <4 x i64> @llvm.x86.avx512.mask.vpmadd52l.uq.256(<4 x i64> %x0, <4 x i64> %x1, <4 x i64> %x2, i8 -1)
+  %res4 = add <4 x i64> %res, %res1
+  %res5 = add <4 x i64> %res3, %res2
+  %res6 = add <4 x i64> %res5, %res4
+  ret <4 x i64> %res6
+}
+
+declare <2 x i64> @llvm.x86.avx512.maskz.vpmadd52l.uq.128(<2 x i64>, <2 x i64>, <2 x i64>, i8)
+
+define <2 x i64>@test_int_x86_avx512_maskz_vpmadd52l_uq_128(<2 x i64> %x0, <2 x i64> %x1, <2 x i64> %x2, i8 %x3) {
+; CHECK-LABEL: test_int_x86_avx512_maskz_vpmadd52l_uq_128:
+; CHECK: kmovw %edi, %k1
+; CHECK: vmovaps %zmm0, %zmm3
+; CHECK: vpmadd52luq %xmm2, %xmm1, %xmm3 {%k1} {z}
+; CHECK: vmovaps %zmm0, %zmm4
+; CHECK: vpmadd52luq %xmm2, %xmm1, %xmm4
+; CHECK: vxorps %xmm2, %xmm2, %xmm2
+; CHECK: vpmadd52luq %xmm2, %xmm1, %xmm0 {%k1} {z}
+; CHECK: vpmadd52luq %xmm2, %xmm1, %xmm2 {%k1} {z}
+; CHECK: vpaddq %xmm0, %xmm3, %xmm0
+; CHECK: vpaddq %xmm2, %xmm4, %xmm1
+; CHECK: vpaddq %xmm0, %xmm1, %xmm0
+
+  %res = call <2 x i64> @llvm.x86.avx512.maskz.vpmadd52l.uq.128(<2 x i64> %x0, <2 x i64> %x1, <2 x i64> %x2, i8 %x3)
+  %res1 = call <2 x i64> @llvm.x86.avx512.maskz.vpmadd52l.uq.128(<2 x i64> %x0, <2 x i64> %x1, <2 x i64> zeroinitializer, i8 %x3)
+  %res2 = call <2 x i64> @llvm.x86.avx512.maskz.vpmadd52l.uq.128(<2 x i64> zeroinitializer, <2 x i64> %x1, <2 x i64> zeroinitializer, i8 %x3)
+  %res3 = call <2 x i64> @llvm.x86.avx512.maskz.vpmadd52l.uq.128(<2 x i64> %x0, <2 x i64> %x1, <2 x i64> %x2, i8 -1)
+  %res4 = add <2 x i64> %res, %res1
+  %res5 = add <2 x i64> %res3, %res2
+  %res6 = add <2 x i64> %res5, %res4
+  ret <2 x i64> %res6
+}
+
+declare <4 x i64> @llvm.x86.avx512.maskz.vpmadd52l.uq.256(<4 x i64>, <4 x i64>, <4 x i64>, i8)
+
+define <4 x i64>@test_int_x86_avx512_maskz_vpmadd52l_uq_256(<4 x i64> %x0, <4 x i64> %x1, <4 x i64> %x2, i8 %x3) {
+; CHECK-LABEL: test_int_x86_avx512_maskz_vpmadd52l_uq_256:
+; CHECK: kmovw %edi, %k1
+; CHECK: vmovaps %zmm0, %zmm3
+; CHECK: vpmadd52luq %ymm2, %ymm1, %ymm3 {%k1} {z}
+; CHECK: vmovaps %zmm0, %zmm4
+; CHECK: vpmadd52luq %ymm2, %ymm1, %ymm4
+; CHECK: vxorps %ymm2, %ymm2, %ymm2
+; CHECK: vpmadd52luq %ymm2, %ymm1, %ymm0 {%k1} {z}
+; CHECK: vpmadd52luq %ymm2, %ymm1, %ymm2 {%k1} {z}
+; CHECK: vpaddq %ymm0, %ymm3, %ymm0
+; CHECK: vpaddq %ymm2, %ymm4, %ymm1
+; CHECK: vpaddq %ymm0, %ymm1, %ymm0
+
+  %res = call <4 x i64> @llvm.x86.avx512.maskz.vpmadd52l.uq.256(<4 x i64> %x0, <4 x i64> %x1, <4 x i64> %x2, i8 %x3)
+  %res1 = call <4 x i64> @llvm.x86.avx512.maskz.vpmadd52l.uq.256(<4 x i64> %x0, <4 x i64> %x1, <4 x i64> zeroinitializer, i8 %x3)
+  %res2 = call <4 x i64> @llvm.x86.avx512.maskz.vpmadd52l.uq.256(<4 x i64> zeroinitializer, <4 x i64> %x1, <4 x i64> zeroinitializer, i8 %x3)
+  %res3 = call <4 x i64> @llvm.x86.avx512.maskz.vpmadd52l.uq.256(<4 x i64> %x0, <4 x i64> %x1, <4 x i64> %x2, i8 -1)
+  %res4 = add <4 x i64> %res, %res1
+  %res5 = add <4 x i64> %res3, %res2
+  %res6 = add <4 x i64> %res5, %res4
+  ret <4 x i64> %res6
+}

diff --git a/test/CodeGen/X86/avx512vbmivl-intrinsics.ll b/test/CodeGen/X86/avx512vbmivl-intrinsics.ll
index 690d1604ba065aaa960b80d2250ca8675aaa7c0e..d28478a6cca32949d90bd27eb033bbc4572dbe12 100644 (file)
--- a/test/CodeGen/X86/avx512vbmivl-intrinsics.ll
+++ b/test/CodeGen/X86/avx512vbmivl-intrinsics.ll
@@ -1,45 +1,45 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py\r
-; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=skx -mattr=+avx512vl -mattr=+avx512vbmi --show-mc-encoding| FileCheck %s\r
-declare <16 x i8> @llvm.x86.avx512.mask.permvar.qi.128(<16 x i8>, <16 x i8>, <16 x i8>, i16)\r
-\r
-define <16 x i8>@test_int_x86_avx512_mask_permvar_qi_128(<16 x i8> %x0, <16 x i8> %x1, <16 x i8> %x2, i16 %x3) {\r
-; CHECK-LABEL: test_int_x86_avx512_mask_permvar_qi_128:\r
-; CHECK:       ## BB#0:\r
-; CHECK-NEXT:    kmovw %edi, %k1 \r
-; CHECK-NEXT:    vpermb %xmm1, %xmm0, %xmm2 {%k1} \r
-; CHECK-NEXT:    vpermb %xmm1, %xmm0, %xmm3 {%k1} {z} \r
-; CHECK-NEXT:    vpermb %xmm1, %xmm0, %xmm0 \r
-; CHECK-NEXT:    vpaddb %xmm3, %xmm2, %xmm1 \r
-; CHECK-NEXT:    vpaddb %xmm0, %xmm1, %xmm0 \r
-; CHECK-NEXT:    retq \r
-  %res = call <16 x i8> @llvm.x86.avx512.mask.permvar.qi.128(<16 x i8> %x0, <16 x i8> %x1, <16 x i8> %x2, i16 %x3)\r
-  %res1 = call <16 x i8> @llvm.x86.avx512.mask.permvar.qi.128(<16 x i8> %x0, <16 x i8> %x1, <16 x i8> zeroinitializer, i16 %x3)\r
-  %res2 = call <16 x i8> @llvm.x86.avx512.mask.permvar.qi.128(<16 x i8> %x0, <16 x i8> %x1, <16 x i8> %x2, i16 -1)\r
-  %res3 = add <16 x i8> %res, %res1\r
-  %res4 = add <16 x i8> %res3, %res2\r
-  ret <16 x i8> %res4\r
-}\r
-\r
-declare <32 x i8> @llvm.x86.avx512.mask.permvar.qi.256(<32 x i8>, <32 x i8>, <32 x i8>, i32)\r
-\r
-define <32 x i8>@test_int_x86_avx512_mask_permvar_qi_256(<32 x i8> %x0, <32 x i8> %x1, <32 x i8> %x2, i32 %x3) {\r
-; CHECK-LABEL: test_int_x86_avx512_mask_permvar_qi_256:\r
-; CHECK:       ## BB#0:\r
-; CHECK-NEXT:    kmovd %edi, %k1 \r
-; CHECK-NEXT:    vpermb %ymm1, %ymm0, %ymm2 {%k1} \r
-; CHECK-NEXT:    vpermb %ymm1, %ymm0, %ymm3 {%k1} {z} \r
-; CHECK-NEXT:    vpermb %ymm1, %ymm0, %ymm0 \r
-; CHECK-NEXT:    vpaddb %ymm3, %ymm2, %ymm1 \r
-; CHECK-NEXT:    vpaddb %ymm0, %ymm1, %ymm0 \r
-; CHECK-NEXT:    retq \r
-  %res = call <32 x i8> @llvm.x86.avx512.mask.permvar.qi.256(<32 x i8> %x0, <32 x i8> %x1, <32 x i8> %x2, i32 %x3)\r
-  %res1 = call <32 x i8> @llvm.x86.avx512.mask.permvar.qi.256(<32 x i8> %x0, <32 x i8> %x1, <32 x i8> zeroinitializer, i32 %x3)\r
-  %res2 = call <32 x i8> @llvm.x86.avx512.mask.permvar.qi.256(<32 x i8> %x0, <32 x i8> %x1, <32 x i8> %x2, i32 -1)\r
-  %res3 = add <32 x i8> %res, %res1\r
-  %res4 = add <32 x i8> %res3, %res2\r
-  ret <32 x i8> %res4\r
-}\r
-\r
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=skx -mattr=+avx512vl -mattr=+avx512vbmi --show-mc-encoding| FileCheck %s
+declare <16 x i8> @llvm.x86.avx512.mask.permvar.qi.128(<16 x i8>, <16 x i8>, <16 x i8>, i16)
+
+define <16 x i8>@test_int_x86_avx512_mask_permvar_qi_128(<16 x i8> %x0, <16 x i8> %x1, <16 x i8> %x2, i16 %x3) {
+; CHECK-LABEL: test_int_x86_avx512_mask_permvar_qi_128:
+; CHECK:       ## BB#0:
+; CHECK-NEXT:    kmovw %edi, %k1 
+; CHECK-NEXT:    vpermb %xmm1, %xmm0, %xmm2 {%k1} 
+; CHECK-NEXT:    vpermb %xmm1, %xmm0, %xmm3 {%k1} {z} 
+; CHECK-NEXT:    vpermb %xmm1, %xmm0, %xmm0 
+; CHECK-NEXT:    vpaddb %xmm3, %xmm2, %xmm1 
+; CHECK-NEXT:    vpaddb %xmm0, %xmm1, %xmm0 
+; CHECK-NEXT:    retq 
+  %res = call <16 x i8> @llvm.x86.avx512.mask.permvar.qi.128(<16 x i8> %x0, <16 x i8> %x1, <16 x i8> %x2, i16 %x3)
+  %res1 = call <16 x i8> @llvm.x86.avx512.mask.permvar.qi.128(<16 x i8> %x0, <16 x i8> %x1, <16 x i8> zeroinitializer, i16 %x3)
+  %res2 = call <16 x i8> @llvm.x86.avx512.mask.permvar.qi.128(<16 x i8> %x0, <16 x i8> %x1, <16 x i8> %x2, i16 -1)
+  %res3 = add <16 x i8> %res, %res1
+  %res4 = add <16 x i8> %res3, %res2
+  ret <16 x i8> %res4
+}
+
+declare <32 x i8> @llvm.x86.avx512.mask.permvar.qi.256(<32 x i8>, <32 x i8>, <32 x i8>, i32)
+
+define <32 x i8>@test_int_x86_avx512_mask_permvar_qi_256(<32 x i8> %x0, <32 x i8> %x1, <32 x i8> %x2, i32 %x3) {
+; CHECK-LABEL: test_int_x86_avx512_mask_permvar_qi_256:
+; CHECK:       ## BB#0:
+; CHECK-NEXT:    kmovd %edi, %k1 
+; CHECK-NEXT:    vpermb %ymm1, %ymm0, %ymm2 {%k1} 
+; CHECK-NEXT:    vpermb %ymm1, %ymm0, %ymm3 {%k1} {z} 
+; CHECK-NEXT:    vpermb %ymm1, %ymm0, %ymm0 
+; CHECK-NEXT:    vpaddb %ymm3, %ymm2, %ymm1 
+; CHECK-NEXT:    vpaddb %ymm0, %ymm1, %ymm0 
+; CHECK-NEXT:    retq 
+  %res = call <32 x i8> @llvm.x86.avx512.mask.permvar.qi.256(<32 x i8> %x0, <32 x i8> %x1, <32 x i8> %x2, i32 %x3)
+  %res1 = call <32 x i8> @llvm.x86.avx512.mask.permvar.qi.256(<32 x i8> %x0, <32 x i8> %x1, <32 x i8> zeroinitializer, i32 %x3)
+  %res2 = call <32 x i8> @llvm.x86.avx512.mask.permvar.qi.256(<32 x i8> %x0, <32 x i8> %x1, <32 x i8> %x2, i32 -1)
+  %res3 = add <32 x i8> %res, %res1
+  %res4 = add <32 x i8> %res3, %res2
+  ret <32 x i8> %res4
+}
+
 declare <16 x i8> @llvm.x86.avx512.mask.pmultishift.qb.128(<16 x i8>, <16 x i8>, <16 x i8>, i16)
 
 define <16 x i8>@test_int_x86_avx512_mask_pmultishift_qb_128(<16 x i8> %x0, <16 x i8> %x1, <16 x i8> %x2, i16 %x3) {