uint32_t entry_addr);
static void update_flash_config(const esp_image_header_t* pfhdr);
static void uart_console_configure(void);
+static void wdt_reset_check(void);
void IRAM_ATTR call_start_cpu0()
{
rtc_clk_init(clk_cfg);
uart_console_configure();
+ wdt_reset_check();
ESP_LOGI(TAG, "ESP-IDF %s 2nd stage bootloader", IDF_VER);
#if defined(CONFIG_SECURE_BOOT_ENABLED) || defined(CONFIG_FLASH_ENCRYPTION_ENABLED)
esp_err_t err;
#endif // CONFIG_CONSOLE_UART_NONE
}
+
+static void wdt_reset_info_enable(void)
+{
+ REG_SET_BIT(DPORT_PRO_CPU_RECORD_CTRL_REG, DPORT_PRO_CPU_PDEBUG_ENABLE | DPORT_PRO_CPU_RECORD_ENABLE);
+ REG_CLR_BIT(DPORT_PRO_CPU_RECORD_CTRL_REG, DPORT_PRO_CPU_RECORD_ENABLE);
+ REG_SET_BIT(DPORT_APP_CPU_RECORD_CTRL_REG, DPORT_APP_CPU_PDEBUG_ENABLE | DPORT_APP_CPU_RECORD_ENABLE);
+ REG_CLR_BIT(DPORT_APP_CPU_RECORD_CTRL_REG, DPORT_APP_CPU_RECORD_ENABLE);
+}
+
+static void wdt_reset_info_dump(int cpu)
+{
+ uint32_t inst = 0, pid = 0, stat = 0, data = 0, pc = 0,
+ lsstat = 0, lsaddr = 0, lsdata = 0, dstat = 0;
+ char *cpu_name = cpu ? "APP" : "PRO";
+
+ if (cpu == 0) {
+ stat = REG_READ(DPORT_PRO_CPU_RECORD_STATUS_REG);
+ pid = REG_READ(DPORT_PRO_CPU_RECORD_PID_REG);
+ inst = REG_READ(DPORT_PRO_CPU_RECORD_PDEBUGINST_REG);
+ dstat = REG_READ(DPORT_PRO_CPU_RECORD_PDEBUGSTATUS_REG);
+ data = REG_READ(DPORT_PRO_CPU_RECORD_PDEBUGDATA_REG);
+ pc = REG_READ(DPORT_PRO_CPU_RECORD_PDEBUGPC_REG);
+ lsstat = REG_READ(DPORT_PRO_CPU_RECORD_PDEBUGLS0STAT_REG);
+ lsaddr = REG_READ(DPORT_PRO_CPU_RECORD_PDEBUGLS0ADDR_REG);
+ lsdata = REG_READ(DPORT_PRO_CPU_RECORD_PDEBUGLS0DATA_REG);
+
+ } else {
+ stat = REG_READ(DPORT_APP_CPU_RECORD_STATUS_REG);
+ pid = REG_READ(DPORT_APP_CPU_RECORD_PID_REG);
+ inst = REG_READ(DPORT_APP_CPU_RECORD_PDEBUGINST_REG);
+ dstat = REG_READ(DPORT_APP_CPU_RECORD_PDEBUGSTATUS_REG);
+ data = REG_READ(DPORT_APP_CPU_RECORD_PDEBUGDATA_REG);
+ pc = REG_READ(DPORT_APP_CPU_RECORD_PDEBUGPC_REG);
+ lsstat = REG_READ(DPORT_APP_CPU_RECORD_PDEBUGLS0STAT_REG);
+ lsaddr = REG_READ(DPORT_APP_CPU_RECORD_PDEBUGLS0ADDR_REG);
+ lsdata = REG_READ(DPORT_APP_CPU_RECORD_PDEBUGLS0DATA_REG);
+ }
+ if (DPORT_RECORD_PDEBUGINST_SZ(inst) == 0 &&
+ DPORT_RECORD_PDEBUGSTATUS_BBCAUSE(dstat) == DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_WAITI) {
+ ESP_LOGW(TAG, "WDT reset info: %s CPU PC=0x%x (waiti mode)", cpu_name, pc);
+ } else {
+ ESP_LOGW(TAG, "WDT reset info: %s CPU PC=0x%x", cpu_name, pc);
+ }
+ ESP_LOGD(TAG, "WDT reset info: %s CPU STATUS 0x%08x", cpu_name, stat);
+ ESP_LOGD(TAG, "WDT reset info: %s CPU PID 0x%08x", cpu_name, pid);
+ ESP_LOGD(TAG, "WDT reset info: %s CPU PDEBUGINST 0x%08x", cpu_name, inst);
+ ESP_LOGD(TAG, "WDT reset info: %s CPU PDEBUGSTATUS 0x%08x", cpu_name, dstat);
+ ESP_LOGD(TAG, "WDT reset info: %s CPU PDEBUGDATA 0x%08x", cpu_name, data);
+ ESP_LOGD(TAG, "WDT reset info: %s CPU PDEBUGPC 0x%08x", cpu_name, pc);
+ ESP_LOGD(TAG, "WDT reset info: %s CPU PDEBUGLS0STAT 0x%08x", cpu_name, lsstat);
+ ESP_LOGD(TAG, "WDT reset info: %s CPU PDEBUGLS0ADDR 0x%08x", cpu_name, lsaddr);
+ ESP_LOGD(TAG, "WDT reset info: %s CPU PDEBUGLS0DATA 0x%08x", cpu_name, lsdata);
+}
+
+static void wdt_reset_check(void)
+{
+ int wdt_rst = 0;
+ RESET_REASON rst_reas[2];
+
+ rst_reas[0] = rtc_get_reset_reason(0);
+ rst_reas[1] = rtc_get_reset_reason(1);
+ if (rst_reas[0] == RTCWDT_SYS_RESET || rst_reas[0] == TG0WDT_SYS_RESET || rst_reas[0] == TG1WDT_SYS_RESET ||
+ rst_reas[0] == TGWDT_CPU_RESET || rst_reas[0] == RTCWDT_CPU_RESET) {
+ ESP_LOGW(TAG, "PRO CPU has been reset by WDT.");
+ wdt_rst = 1;
+ }
+ if (rst_reas[1] == RTCWDT_SYS_RESET || rst_reas[1] == TG0WDT_SYS_RESET || rst_reas[1] == TG1WDT_SYS_RESET ||
+ rst_reas[1] == TGWDT_CPU_RESET || rst_reas[1] == RTCWDT_CPU_RESET) {
+ ESP_LOGW(TAG, "APP CPU has been reset by WDT.");
+ wdt_rst = 1;
+ }
+ if (wdt_rst) {
+ // if reset by WDT dump info from trace port
+ wdt_reset_info_dump(0);
+ wdt_reset_info_dump(1);
+ }
+ wdt_reset_info_enable();
+}
#define DPORT_RECORD_PRO_PDEBUGINST_M ((DPORT_RECORD_PRO_PDEBUGINST_V)<<(DPORT_RECORD_PRO_PDEBUGINST_S))
#define DPORT_RECORD_PRO_PDEBUGINST_V 0xFFFFFFFF
#define DPORT_RECORD_PRO_PDEBUGINST_S 0
+/* register layout:
+ * SIZE [7..0] : Instructions normally complete in the W stage. The size of the instruction in the W is given
+ * by this field in number of bytes. If it is 8’b0 in a given cycle the W stage has no completing
+ * instruction. This is also known as a bubble cycle. Also see DPORT_PRO_CPU_RECORD_PDEBUGSTATUS_REG.
+ * ISRC [14..12] : Instruction source.
+** LOOP [23..20] : Loopback status.
+** CINTLEVEL [27..24]: CINTLEVEL.
+*/
+#define DPORT_RECORD_PDEBUGINST_SZ_M ((DPORT_RECORD_PDEBUGINST_SZ_V)<<(DPORT_RECORD_PDEBUGINST_SZ_S))
+#define DPORT_RECORD_PDEBUGINST_SZ_V 0xFF
+#define DPORT_RECORD_PDEBUGINST_SZ_S 0
+#define DPORT_RECORD_PDEBUGINST_SZ(_r_) (((_r_)>>DPORT_RECORD_PDEBUGINST_SZ_S) & DPORT_RECORD_PDEBUGINST_SZ_V)
+#define DPORT_RECORD_PDEBUGINST_ISRC_M ((DPORT_RECORD_PDEBUGINST_ISRC_V)<<(DPORT_RECORD_PDEBUGINST_ISRC_S))
+#define DPORT_RECORD_PDEBUGINST_ISRC_V 0x07
+#define DPORT_RECORD_PDEBUGINST_ISRC_S 12
+#define DPORT_RECORD_PDEBUGINST_ISRC(_r_) (((_r_)>>DPORT_RECORD_PDEBUGINST_ISRC_S) & DPORT_RECORD_PDEBUGINST_ISRC_V)
+// #define DPORT_RECORD_PDEBUGINST_LOOP_M ((DPORT_RECORD_PDEBUGINST_LOOP_V)<<(DPORT_RECORD_PDEBUGINST_LOOP_S))
+// #define DPORT_RECORD_PDEBUGINST_LOOP_V 0x0F
+// #define DPORT_RECORD_PDEBUGINST_LOOP_S 20
+// #define DPORT_RECORD_PDEBUGINST_LOOP(_r_) (((_r_)>>DPORT_RECORD_PDEBUGINST_LOOP_S) & DPORT_RECORD_PDEBUGINST_LOOP_V)
+#define DPORT_RECORD_PDEBUGINST_LOOP_REP (BIT(20)) /* loopback will occur */
+#define DPORT_RECORD_PDEBUGINST_LOOP (BIT(21)) /* last inst of loop */
+#define DPORT_RECORD_PDEBUGINST_CINTL_M ((DPORT_RECORD_PDEBUGINST_CINTL_V)<<(DPORT_RECORD_PDEBUGINST_CINTL_S))
+#define DPORT_RECORD_PDEBUGINST_CINTL_V 0x0F
+#define DPORT_RECORD_PDEBUGINST_CINTL_S 24
+#define DPORT_RECORD_PDEBUGINST_CINTL(_r_) (((_r_)>>DPORT_RECORD_PDEBUGINST_CINTL_S) & DPORT_RECORD_PDEBUGINST_CINTL_V)
#define DPORT_PRO_CPU_RECORD_PDEBUGSTATUS_REG (DR_REG_DPORT_BASE + 0x450)
/* DPORT_RECORD_PRO_PDEBUGSTATUS : RO ;bitpos:[7:0] ;default: 8'b0 ; */
#define DPORT_RECORD_PRO_PDEBUGSTATUS_M ((DPORT_RECORD_PRO_PDEBUGSTATUS_V)<<(DPORT_RECORD_PRO_PDEBUGSTATUS_S))
#define DPORT_RECORD_PRO_PDEBUGSTATUS_V 0xFF
#define DPORT_RECORD_PRO_PDEBUGSTATUS_S 0
+/* register layout:
+ * BBCAUSE [5..0]: Indicates cause for bubble cycle. See below for posible values. When DPORT_RECORD_PDEBUGINST_SZ == 0
+ * INSNTYPE[5..0]: Indicates type of instruction retiring in the W stage. See below for posible values. When DPORT_RECORD_PDEBUGINST_SZ > 0
+*/
+#define DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_M ((DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_V)<<(DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_S))
+#define DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_V 0x3F
+#define DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_S 0
+#define DPORT_RECORD_PDEBUGSTATUS_BBCAUSE(_r_) (((_r_)>>DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_S) & DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_V)
+#define DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_PSO 0x00 /* Power shut off */
+#define DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_DEP 0x02 /* Register dependency or resource conflict. See DPORT_XXX_CPU_RECORD_PDEBUGDATA_REG for extra info. */
+#define DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_CTL 0x04 /* Control transfer bubble */
+#define DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_ICM 0x08 /* I-cache miss (incl uncached miss) */
+#define DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_DCM 0x0C /* D-cache miss (excl uncached miss) */
+#define DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_EXC0 0x10 /* Exception or interrupt (W stage). See DPORT_XXX_CPU_RECORD_PDEBUGDATA_REG for extra info.
+ The virtual address of the instruction that was killed appears on DPORT_PRO_CPU_RECORD_PDEBUGPC_REG[31:0] */
+#define DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_EXC1 0x11 /* Exception or interrupt (W+1 stage). See DPORT_XXX_CPU_RECORD_PDEBUGDATA_REG for extra info. */
+#define DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_RPL 0x14 /* Instruction replay (other). DPORT_XXX_CPU_RECORD_PDEBUGDATA_REG has the PC of the replaying instruction. */
+#define DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_ITLB 0x18 /* HW ITLB refill. The refill address and data are available on
+ DPORT_PRO_CPU_RECORD_PDEBUGLS0ADDR_REG and DPORT_PRO_CPU_RECORD_PDEBUGLS0DATA_REG. */
+#define DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_ITLBM 0x1A /* ITLB miss */
+#define DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_DTLB 0x1C /* HW DTLB refill. The refill address and data are available on
+ DPORT_PRO_CPU_RECORD_PDEBUGLS0ADDR_REG and DPORT_PRO_CPU_RECORD_PDEBUGLS0DATA_REG. */
+#define DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_DTLBM 0x1E /* DTLB miss */
+#define DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_STALL 0x20 /* Stall . The cause of the global stall is further classified in the DPORT_XXX_CPU_RECORD_PDEBUGDATA_REG. */
+#define DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_HWMEC 0x24 /* HW-corrected memory error */
+#define DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_WAITI 0x28 /* WAITI mode */
+#define DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_OTHER 0x3C /* all other bubbles */
+#define DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_M ((DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_V)<<(DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_S))
+#define DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_V 0x3F
+#define DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_S 0
+#define DPORT_RECORD_PDEBUGSTATUS_INSNTYPE(_r_) (((_r_)>>DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_S) & DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_V)
+#define DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_JX 0x00 /* JX */
+#define DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_CALLX 0x04 /* CALLX */
+#define DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_CRET 0x08 /* All call returns */
+#define DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_ERET 0x0C /* All exception returns */
+#define DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_B 0x10 /* Branch taken or loop not taken */
+#define DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_J 0x14 /* J */
+#define DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_CALL 0x18 /* CALL */
+#define DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_BN 0x1C /* Branch not taken */
+#define DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_LOOP 0x20 /* Loop instruction (taken) */
+#define DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_S32C1I 0x24 /* S32C1I. The address and load data (before the conditional store) are available on the LS signals*/
+#define DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_WXSR2LB 0x28 /* WSR/XSR to LBEGIN */
+#define DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_WSR2MMID 0x2C /* WSR to MMID */
+#define DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_RWXSR 0x30 /* RSR or WSR (except MMID and LBEGIN) or XSR (except LBEGIN) */
+#define DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_RWER 0x34 /* RER or WER */
+#define DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_DEF 0x3C /* Default */
#define DPORT_PRO_CPU_RECORD_PDEBUGDATA_REG (DR_REG_DPORT_BASE + 0x454)
/* DPORT_RECORD_PRO_PDEBUGDATA : RO ;bitpos:[31:0] ;default: 32'b0 ; */
#define DPORT_RECORD_PRO_PDEBUGDATA_M ((DPORT_RECORD_PRO_PDEBUGDATA_V)<<(DPORT_RECORD_PRO_PDEBUGDATA_S))
#define DPORT_RECORD_PRO_PDEBUGDATA_V 0xFFFFFFFF
#define DPORT_RECORD_PRO_PDEBUGDATA_S 0
+/* register layout when bubble cycke cause is DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_DEP:
+ *
+ * HALT [17]: HALT instruction (TX only)
+ * MEMW [16]: MEMW, EXTW or EXCW instruction dependency
+ * REG [12]: register dependencies or resource (e.g.TIE ports) conflicts
+ * STR [11]: store release (instruction) dependency
+ * LSU [8] : various LSU dependencies (MHT access, prefetch, cache access insts, s32c1i, etc)
+ * OTHER[0] : all other hold dependencies resulting from data or resource dependencies
+*/
+#define DPORT_RECORD_PDEBUGDATA_DEP_HALT (BIT(17))
+#define DPORT_RECORD_PDEBUGDATA_DEP_MEMW (BIT(16))
+#define DPORT_RECORD_PDEBUGDATA_DEP_REG (BIT(12))
+#define DPORT_RECORD_PDEBUGDATA_DEP_STR (BIT(11))
+#define DPORT_RECORD_PDEBUGDATA_DEP_LSU (BIT(8))
+#define DPORT_RECORD_PDEBUGDATA_DEP_OTHER (BIT(0))
+/* register layout when bubble cycke cause is DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_EXCn:
+ *
+ * EXCCAUSE[21..16]: Processor exception cause
+ * EXCVEC [4..0] : Encoded Exception Vector
+*/
+#define DPORT_RECORD_PDEBUGDATA_EXCCAUSE_M ((DPORT_RECORD_PDEBUGDATA_EXCCAUSE_V)<<(DPORT_RECORD_PDEBUGDATA_EXCCAUSE_S))
+#define DPORT_RECORD_PDEBUGDATA_EXCCAUSE_V 0x3F
+#define DPORT_RECORD_PDEBUGDATA_EXCCAUSE_S 16
+#define DPORT_RECORD_PDEBUGDATA_EXCCAUSE(_r_) (((_r_)>>DPORT_RECORD_PDEBUGDATA_EXCCAUSE_S) & DPORT_RECORD_PDEBUGDATA_EXCCAUSE_V)
+#define DPORT_RECORD_PDEBUGDATA_EXCVEC_M ((DPORT_RECORD_PDEBUGDATA_EXCCAUSE_V)<<(DPORT_RECORD_PDEBUGDATA_EXCCAUSE_S))
+#define DPORT_RECORD_PDEBUGDATA_EXCVEC_V 0x1F
+#define DPORT_RECORD_PDEBUGDATA_EXCVEC_S 0
+#define DPORT_RECORD_PDEBUGDATA_EXCVEC(_r_) (((_r_)>>DPORT_RECORD_PDEBUGDATA_EXCCAUSE_S) & DPORT_RECORD_PDEBUGDATA_EXCCAUSE_V)
+#define DPORT_RECORD_PDEBUGDATA_EXCVEC_NONE 0x00 /* no vector */
+#define DPORT_RECORD_PDEBUGDATA_EXCVEC_RST 0x01 /* Reset */
+#define DPORT_RECORD_PDEBUGDATA_EXCVEC_DBG 0x02 /* Debug (repl corresp level “n”) */
+#define DPORT_RECORD_PDEBUGDATA_EXCVEC_NMI 0x03 /* NMI (repl corresp level “n”) */
+#define DPORT_RECORD_PDEBUGDATA_EXCVEC_USR 0x04 /* User */
+#define DPORT_RECORD_PDEBUGDATA_EXCVEC_KRNL 0x05 /* Kernel */
+#define DPORT_RECORD_PDEBUGDATA_EXCVEC_DBL 0x06 /* Double */
+#define DPORT_RECORD_PDEBUGDATA_EXCVEC_EMEM 0x07 /* Memory Error */
+#define DPORT_RECORD_PDEBUGDATA_EXCVEC_OVF4 0x0A /* Window Overflow 4 */
+#define DPORT_RECORD_PDEBUGDATA_EXCVEC_UNF4 0x0B /* Window Underflow 4 */
+#define DPORT_RECORD_PDEBUGDATA_EXCVEC_OVF8 0x0C /* Window Overflow 8 */
+#define DPORT_RECORD_PDEBUGDATA_EXCVEC_UNF8 0x0D /* Window Underflow 8 */
+#define DPORT_RECORD_PDEBUGDATA_EXCVEC_OVF12 0x0E /* Window Overflow 12 */
+#define DPORT_RECORD_PDEBUGDATA_EXCVEC_UNF12 0x0F /* Window Underflow 12 */
+#define DPORT_RECORD_PDEBUGDATA_EXCVEC_INT2 0x10 /* Int Level 2 (n/a if debug/NMI) */
+#define DPORT_RECORD_PDEBUGDATA_EXCVEC_INT3 0x11 /* Int Level 3 (n/a if debug/NMI) */
+#define DPORT_RECORD_PDEBUGDATA_EXCVEC_INT4 0x12 /* Int Level 4 (n/a if debug/NMI) */
+#define DPORT_RECORD_PDEBUGDATA_EXCVEC_INT5 0x13 /* Int Level 5 (n/a if debug/NMI) */
+#define DPORT_RECORD_PDEBUGDATA_EXCVEC_INT6 0x14 /* Int Level 6 (n/a if debug/NMI) */
+/* register layout when bubble cycke cause is DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_STALL:
+ *
+ * ITERDIV[19] : Iterative divide stall.
+ * ITERMUL[18] : Iterative multiply stall.
+ * BANKCONFL[16]: Bank-conflict stall.
+ * BPLOAD[15] : Bypass load stall.
+ * LSPROC[14] : Load/store miss-processing stall.
+ * L32R[13] : FastL32R stall.
+ * BPIFETCH[12] : Bypass I fetch stall.
+ * RUNSTALL[10] : RunStall.
+ * TIE[9] : TIE port stall.
+ * IPIF[8] : Instruction RAM inbound-PIF stall.
+ * IRAMBUSY[7] : Instruction RAM/ROM busy stall.
+ * ICM[6] : I-cache-miss stall.
+ * LSU[4] : The LSU will stall the pipeline under various local memory access conflict situations.
+ * DCM[3] : D-cache-miss stall.
+ * BUFFCONFL[2] : Store buffer conflict stall.
+ * BUFF[1] : Store buffer full stall.
+*/
+#define DPORT_RECORD_PDEBUGDATA_STALL_ITERDIV (BIT(19))
+#define DPORT_RECORD_PDEBUGDATA_STALL_ITERMUL (BIT(18))
+#define DPORT_RECORD_PDEBUGDATA_STALL_BANKCONFL (BIT(16))
+#define DPORT_RECORD_PDEBUGDATA_STALL_BPLOAD (BIT(15))
+#define DPORT_RECORD_PDEBUGDATA_STALL_LSPROC (BIT(14))
+#define DPORT_RECORD_PDEBUGDATA_STALL_L32R (BIT(13))
+#define DPORT_RECORD_PDEBUGDATA_STALL_BPIFETCH (BIT(12))
+#define DPORT_RECORD_PDEBUGDATA_STALL_RUN (BIT(10))
+#define DPORT_RECORD_PDEBUGDATA_STALL_TIE (BIT(9))
+#define DPORT_RECORD_PDEBUGDATA_STALL_IPIF (BIT(8))
+#define DPORT_RECORD_PDEBUGDATA_STALL_IRAMBUSY (BIT(7))
+#define DPORT_RECORD_PDEBUGDATA_STALL_ICM (BIT(6))
+#define DPORT_RECORD_PDEBUGDATA_STALL_LSU (BIT(4))
+#define DPORT_RECORD_PDEBUGDATA_STALL_DCM (BIT(3))
+#define DPORT_RECORD_PDEBUGDATA_STALL_BUFFCONFL (BIT(2))
+#define DPORT_RECORD_PDEBUGDATA_STALL_BUFF (BIT(1))
+/* register layout for DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_RWXSR:
+ *
+ * XSR[10] : XSR Instruction
+ * WSR[9] : WSR Instruction
+ * RSR[8] : RSR Instruction
+ * SR[7..0] : Special Register Number
+*/
+#define DPORT_RECORD_PDEBUGDATA_INSNTYPE_XSR (BIT(10))
+#define DPORT_RECORD_PDEBUGDATA_INSNTYPE_WSR (BIT(9))
+#define DPORT_RECORD_PDEBUGDATA_INSNTYPE_RSR (BIT(8))
+#define DPORT_RECORD_PDEBUGDATA_INSNTYPE_SR_M ((DPORT_RECORD_PDEBUGDATA_INSNTYPE_SR_V)<<(DPORT_RECORD_PDEBUGDATA_INSNTYPE_SR_S))
+#define DPORT_RECORD_PDEBUGDATA_INSNTYPE_SR_V 0xFF
+#define DPORT_RECORD_PDEBUGDATA_INSNTYPE_SR_S 0
+#define DPORT_RECORD_PDEBUGDATA_INSNTYPE_SR(_r_) (((_r_)>>DPORT_RECORD_PDEBUGDATA_INSNTYPE_SR_S) & DPORT_RECORD_PDEBUGDATA_INSNTYPE_SR_V)
+/* register layout for DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_RWER:
+ *
+ * ER[13..2]: ER Address
+ * WER[1] : WER Instruction
+ * RER[0] : RER Instruction
+*/
+#define DPORT_RECORD_PDEBUGDATA_INSNTYPE_ER_M ((DPORT_RECORD_PDEBUGDATA_INSNTYPE_ER_V)<<(DPORT_RECORD_PDEBUGDATA_INSNTYPE_ER_S))
+#define DPORT_RECORD_PDEBUGDATA_INSNTYPE_ER_V 0xFFF
+#define DPORT_RECORD_PDEBUGDATA_INSNTYPE_ER_S 2
+#define DPORT_RECORD_PDEBUGDATA_INSNTYPE_ER(_r_) (((_r_)>>DPORT_RECORD_PDEBUGDATA_INSNTYPE_ER_S) & DPORT_RECORD_PDEBUGDATA_INSNTYPE_ER_V)
+#define DPORT_RECORD_PDEBUGDATA_INSNTYPE_WER (BIT(1))
+#define DPORT_RECORD_PDEBUGDATA_INSNTYPE_RER (BIT(0))
+
#define DPORT_PRO_CPU_RECORD_PDEBUGPC_REG (DR_REG_DPORT_BASE + 0x458)
/* DPORT_RECORD_PRO_PDEBUGPC : RO ;bitpos:[31:0] ;default: 32'b0 ; */
#define DPORT_RECORD_PRO_PDEBUGLS0STAT_M ((DPORT_RECORD_PRO_PDEBUGLS0STAT_V)<<(DPORT_RECORD_PRO_PDEBUGLS0STAT_S))
#define DPORT_RECORD_PRO_PDEBUGLS0STAT_V 0xFFFFFFFF
#define DPORT_RECORD_PRO_PDEBUGLS0STAT_S 0
+/* register layout:
+ * TYPE [3..0] : Type of instruction in LS.
+ * SZ [7..4] : Operand size.
+ * DTLBM [8] : Data TLB miss.
+ * DCM [9] : D-cache miss.
+ * DCH [10] : D-cache hit.
+ * UC [12] : Uncached.
+ * WB [13] : Writeback.
+ * COH [16] : Coherency.
+ * STCOH [18..17]: Coherent state.
+ * TGT [23..20] : Local target.
+*/
+#define DPORT_RECORD_PDEBUGLS0STAT_TYPE_M ((DPORT_RECORD_PDEBUGLS0STAT_TYPE_V)<<(DPORT_RECORD_PDEBUGLS0STAT_TYPE_S))
+#define DPORT_RECORD_PDEBUGLS0STAT_TYPE_V 0x0F
+#define DPORT_RECORD_PDEBUGLS0STAT_TYPE_S 0
+#define DPORT_RECORD_PDEBUGLS0STAT_TYPE(_r_) (((_r_)>>DPORT_RECORD_PDEBUGLS0STAT_TYPE_S) & DPORT_RECORD_PDEBUGLS0STAT_TYPE_V)
+#define DPORT_RECORD_PDEBUGLS0STAT_TYPE_NONE 0x00 /* neither */
+#define DPORT_RECORD_PDEBUGLS0STAT_TYPE_ITLBR 0x01 /* hw itlb refill */
+#define DPORT_RECORD_PDEBUGLS0STAT_TYPE_DTLBR 0x02 /* hw dtlb refill */
+#define DPORT_RECORD_PDEBUGLS0STAT_TYPE_LD 0x05 /* load */
+#define DPORT_RECORD_PDEBUGLS0STAT_TYPE_STR 0x06 /* store */
+#define DPORT_RECORD_PDEBUGLS0STAT_TYPE_L32R 0x08 /* l32r */
+#define DPORT_RECORD_PDEBUGLS0STAT_TYPE_S32CLI1 0x0A /* s32ci1 */
+#define DPORT_RECORD_PDEBUGLS0STAT_TYPE_CTI 0x0C /* cache test inst */
+#define DPORT_RECORD_PDEBUGLS0STAT_TYPE_RWXSR 0x0E /* rsr/wsr/xsr */
+#define DPORT_RECORD_PDEBUGLS0STAT_TYPE_RWER 0x0F /* rer/wer */
+#define DPORT_RECORD_PDEBUGLS0STAT_SZ_M ((DPORT_RECORD_PDEBUGLS0STAT_SZ_V)<<(DPORT_RECORD_PDEBUGLS0STAT_SZ_S))
+#define DPORT_RECORD_PDEBUGLS0STAT_SZ_V 0x0F
+#define DPORT_RECORD_PDEBUGLS0STAT_SZ_S 4
+#define DPORT_RECORD_PDEBUGLS0STAT_SZ(_r_) (((_r_)>>DPORT_RECORD_PDEBUGLS0STAT_SZ_S) & DPORT_RECORD_PDEBUGLS0STAT_SZ_V)
+#define DPORT_RECORD_PDEBUGLS0STAT_SZB(_r_) ((8<<DPORT_RECORD_PDEBUGLS0STAT_SZ(_r_))/8) // in bytes
+#define DPORT_RECORD_PDEBUGLS0STAT_DTLBM (BIT(8))
+#define DPORT_RECORD_PDEBUGLS0STAT_DCM (BIT(9))
+#define DPORT_RECORD_PDEBUGLS0STAT_DCH (BIT(10))
+#define DPORT_RECORD_PDEBUGLS0STAT_UC (BIT(12))
+#define DPORT_RECORD_PDEBUGLS0STAT_WB (BIT(13))
+#define DPORT_RECORD_PDEBUGLS0STAT_COH (BIT(16))
+#define DPORT_RECORD_PDEBUGLS0STAT_STCOH_M ((DPORT_RECORD_PDEBUGLS0STAT_STCOH_V)<<(DPORT_RECORD_PDEBUGLS0STAT_STCOH_S))
+#define DPORT_RECORD_PDEBUGLS0STAT_STCOH_V 0x03
+#define DPORT_RECORD_PDEBUGLS0STAT_STCOH_S 17
+#define DPORT_RECORD_PDEBUGLS0STAT_STCOH(_r_) (((_r_)>>DPORT_RECORD_PDEBUGLS0STAT_STCOH_S) & DPORT_RECORD_PDEBUGLS0STAT_STCOH_V)
+#define DPORT_RECORD_PDEBUGLS0STAT_STCOH_NONE 0x0 /* neither shared nor exclusive nor modified */
+#define DPORT_RECORD_PDEBUGLS0STAT_STCOH_SHARED 0x1 /* shared */
+#define DPORT_RECORD_PDEBUGLS0STAT_STCOH_EXCL 0x2 /* exclusive */
+#define DPORT_RECORD_PDEBUGLS0STAT_STCOH_MOD 0x3 /* modified */
+#define DPORT_RECORD_PDEBUGLS0STAT_TGT_M ((DPORT_RECORD_PDEBUGLS0STAT_TGT_V)<<(DPORT_RECORD_PDEBUGLS0STAT_TGT_S))
+#define DPORT_RECORD_PDEBUGLS0STAT_TGT_V 0x0F
+#define DPORT_RECORD_PDEBUGLS0STAT_TGT_S 20
+#define DPORT_RECORD_PDEBUGLS0STAT_TGT(_r_) (((_r_)>>DPORT_RECORD_PDEBUGLS0STAT_TGT_S) & DPORT_RECORD_PDEBUGLS0STAT_TGT_V)
+#define DPORT_RECORD_PDEBUGLS0STAT_TGT_EXT 0x0 /* not to local memory */
+#define DPORT_RECORD_PDEBUGLS0STAT_TGT_IRAM0 0x2 /* 001x: InstRAM (0/1) */
+#define DPORT_RECORD_PDEBUGLS0STAT_TGT_IRAM1 0x3 /* 001x: InstRAM (0/1) */
+#define DPORT_RECORD_PDEBUGLS0STAT_TGT_IROM0 0x4 /* 010x: InstROM (0/1) */
+#define DPORT_RECORD_PDEBUGLS0STAT_TGT_IROM1 0x5 /* 010x: InstROM (0/1) */
+#define DPORT_RECORD_PDEBUGLS0STAT_TGT_DRAM0 0x0A /* 101x: DataRAM (0/1) */
+#define DPORT_RECORD_PDEBUGLS0STAT_TGT_DRAM1 0x0B /* 101x: DataRAM (0/1) */
+#define DPORT_RECORD_PDEBUGLS0STAT_TGT_DROM0 0xE /* 111x: DataROM (0/1) */
+#define DPORT_RECORD_PDEBUGLS0STAT_TGT_DROM1 0xF /* 111x: DataROM (0/1) */
+// #define DPORT_RECORD_PDEBUGLS0STAT_TGT_IRAM(_t_) (((_t_)&0xE)=0x2) /* 001x: InstRAM (0/1) */
+// #define DPORT_RECORD_PDEBUGLS0STAT_TGT_IROM(_t_) (((_t_)&0xE)=0x4) /* 010x: InstROM (0/1) */
+// #define DPORT_RECORD_PDEBUGLS0STAT_TGT_DRAM(_t_) (((_t_)&0xE)=0x2) /* 101x: DataRAM (0/1) */
+// #define DPORT_RECORD_PDEBUGLS0STAT_TGT_DROM(_t_) (((_t_)&0xE)=0x2) /* 111x: DataROM (0/1) */
#define DPORT_PRO_CPU_RECORD_PDEBUGLS0ADDR_REG (DR_REG_DPORT_BASE + 0x460)
/* DPORT_RECORD_PRO_PDEBUGLS0ADDR : RO ;bitpos:[31:0] ;default: 32'b0 ; */
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