[MIPS GlobalISel] Select G_UMULH

Legalize G_UMULO and select G_UMULH for MIPS32.

Differential Revision: https://reviews.llvm.org/D58714

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@355177 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/Mips/MipsInstructionSelector.cpp b/lib/Target/Mips/MipsInstructionSelector.cpp
index c97fac9d21b6b5e4d80345fe30d5dd985e5f152e..92a62b5186b69ae15245494ecc859c4e4eb0ef8f 100644 (file)
--- a/lib/Target/Mips/MipsInstructionSelector.cpp
+++ b/lib/Target/Mips/MipsInstructionSelector.cpp
@@ -139,6 +139,26 @@ bool MipsInstructionSelector::select(MachineInstr &I,
   using namespace TargetOpcode;
 
   switch (I.getOpcode()) {
+  case G_UMULH: {
+    unsigned PseudoMULTuReg = MRI.createVirtualRegister(&Mips::ACC64RegClass);
+    MachineInstr *PseudoMULTu, *PseudoMove;
+
+    PseudoMULTu = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::PseudoMULTu))
+                      .addDef(PseudoMULTuReg)
+                      .add(I.getOperand(1))
+                      .add(I.getOperand(2));
+    if (!constrainSelectedInstRegOperands(*PseudoMULTu, TII, TRI, RBI))
+      return false;
+
+    PseudoMove = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::PseudoMFHI))
+                     .addDef(I.getOperand(0).getReg())
+                     .addUse(PseudoMULTuReg);
+    if (!constrainSelectedInstRegOperands(*PseudoMove, TII, TRI, RBI))
+      return false;
+
+    I.eraseFromParent();
+    return true;
+  }
   case G_GEP: {
     MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::ADDu))
              .add(I.getOperand(0))

diff --git a/lib/Target/Mips/MipsLegalizerInfo.cpp b/lib/Target/Mips/MipsLegalizerInfo.cpp
index dd87d01777e3e4e78a64e4527ec6fa5bb130f12d..1da43b0b6dfb3d4f06b7b0ec226503022acb17af 100644 (file)
--- a/lib/Target/Mips/MipsLegalizerInfo.cpp
+++ b/lib/Target/Mips/MipsLegalizerInfo.cpp
@@ -32,9 +32,12 @@ MipsLegalizerInfo::MipsLegalizerInfo(const MipsSubtarget &ST) {
       .legalFor({s32})
       .minScalar(0, s32);
 
-  getActionDefinitionsBuilder({G_UADDO, G_UADDE, G_USUBO, G_USUBE})
+  getActionDefinitionsBuilder({G_UADDO, G_UADDE, G_USUBO, G_USUBE, G_UMULO})
       .lowerFor({{s32, s1}});
 
+  getActionDefinitionsBuilder(G_UMULH)
+      .legalFor({s32});
+
   getActionDefinitionsBuilder({G_LOAD, G_STORE})
       .legalForTypesWithMemDesc({{s32, p0, 8, 8},
                                  {s32, p0, 16, 8},

diff --git a/lib/Target/Mips/MipsRegisterBankInfo.cpp b/lib/Target/Mips/MipsRegisterBankInfo.cpp
index c463ca11ea5309a3791236db5e9acf33f89259ba..214dd106869eefa59e21957cc504e0f4c42758b7 100644 (file)
--- a/lib/Target/Mips/MipsRegisterBankInfo.cpp
+++ b/lib/Target/Mips/MipsRegisterBankInfo.cpp
@@ -86,6 +86,7 @@ MipsRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
   case G_ADD:
   case G_SUB:
   case G_MUL:
+  case G_UMULH:
   case G_LOAD:
   case G_STORE:
   case G_ZEXTLOAD:

diff --git a/test/CodeGen/Mips/GlobalISel/instruction-select/mul.mir b/test/CodeGen/Mips/GlobalISel/instruction-select/mul.mir
index 507c33520a80ba8526853ff97ba3324e1dd1f54c..0b173e1c7414cc382e127143271b14efcb78f58d 100644 (file)
--- a/test/CodeGen/Mips/GlobalISel/instruction-select/mul.mir
+++ b/test/CodeGen/Mips/GlobalISel/instruction-select/mul.mir
@@ -3,6 +3,7 @@
 --- |
 
   define void @mul_i32(i32 %x, i32 %y) {entry: ret void}
+  define void @umul_with_overflow(i32 %lhs, i32 %rhs, i1* %pcarry_flag) { ret void }
 
 ...
 ---
@@ -29,3 +30,42 @@ body:             |
     RetRA implicit $v0
 
 ...
+---
+name:            umul_with_overflow
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+body:             |
+  bb.1 (%ir-block.0):
+    liveins: $a0, $a1, $a2
+
+    ; MIPS32-LABEL: name: umul_with_overflow
+    ; MIPS32: liveins: $a0, $a1, $a2
+    ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
+    ; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
+    ; MIPS32: [[COPY2:%[0-9]+]]:gpr32 = COPY $a2
+    ; MIPS32: [[PseudoMULTu:%[0-9]+]]:acc64 = PseudoMULTu [[COPY]], [[COPY1]]
+    ; MIPS32: [[PseudoMFHI:%[0-9]+]]:gpr32 = PseudoMFHI [[PseudoMULTu]]
+    ; MIPS32: [[LUi:%[0-9]+]]:gpr32 = LUi 0
+    ; MIPS32: [[ORi:%[0-9]+]]:gpr32 = ORi [[LUi]], 0
+    ; MIPS32: [[XOR:%[0-9]+]]:gpr32 = XOR [[PseudoMFHI]], [[ORi]]
+    ; MIPS32: [[SLTu:%[0-9]+]]:gpr32 = SLTu $zero, [[XOR]]
+    ; MIPS32: [[LUi1:%[0-9]+]]:gpr32 = LUi 0
+    ; MIPS32: [[ORi1:%[0-9]+]]:gpr32 = ORi [[LUi1]], 1
+    ; MIPS32: [[AND:%[0-9]+]]:gpr32 = AND [[SLTu]], [[ORi1]]
+    ; MIPS32: SB [[AND]], [[COPY2]], 0 :: (store 1 into %ir.pcarry_flag)
+    ; MIPS32: RetRA
+    %0:gprb(s32) = COPY $a0
+    %1:gprb(s32) = COPY $a1
+    %2:gprb(p0) = COPY $a2
+    %6:gprb(s32) = G_UMULH %0, %1
+    %7:gprb(s32) = G_CONSTANT i32 0
+    %8:gprb(s32) = G_ICMP intpred(ne), %6(s32), %7
+    %9:gprb(s32) = G_CONSTANT i32 1
+    %10:gprb(s32) = COPY %8(s32)
+    %5:gprb(s32) = G_AND %10, %9
+    G_STORE %5(s32), %2(p0) :: (store 1 into %ir.pcarry_flag)
+    RetRA
+
+...

diff --git a/test/CodeGen/Mips/GlobalISel/legalizer/mul.mir b/test/CodeGen/Mips/GlobalISel/legalizer/mul.mir
index 481f8fce71268903dcf7dc3ebe49e8d5be38fd17..24b8341f8ecb6a4c6343a2bdf13ca342dc2cba52 100644 (file)
--- a/test/CodeGen/Mips/GlobalISel/legalizer/mul.mir
+++ b/test/CodeGen/Mips/GlobalISel/legalizer/mul.mir
@@ -9,6 +9,7 @@
   define void @mul_i16_sext() {entry: ret void}
   define void @mul_i16_zext() {entry: ret void}
   define void @mul_i16_aext() {entry: ret void}
+  define void @umul_with_overflow(i32 %lhs, i32 %rhs, i1* %pcarry_flag) { ret void }
 
 ...
 ---
@@ -211,3 +212,32 @@ body:             |
     RetRA implicit $v0
 
 ...
+---
+name:            umul_with_overflow
+alignment:       2
+tracksRegLiveness: true
+body:             |
+  bb.1 (%ir-block.0):
+    liveins: $a0, $a1, $a2
+
+    ; MIPS32-LABEL: name: umul_with_overflow
+    ; MIPS32: liveins: $a0, $a1, $a2
+    ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
+    ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
+    ; MIPS32: [[COPY2:%[0-9]+]]:_(p0) = COPY $a2
+    ; MIPS32: [[UMULH:%[0-9]+]]:_(s32) = G_UMULH [[COPY]], [[COPY1]]
+    ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+    ; MIPS32: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[UMULH]](s32), [[C]]
+    ; MIPS32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+    ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[ICMP]](s32)
+    ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
+    ; MIPS32: G_STORE [[AND]](s32), [[COPY2]](p0) :: (store 1 into %ir.pcarry_flag)
+    ; MIPS32: RetRA
+    %0:_(s32) = COPY $a0
+    %1:_(s32) = COPY $a1
+    %2:_(p0) = COPY $a2
+    %3:_(s32), %4:_(s1) = G_UMULO %0, %1
+    G_STORE %4(s1), %2(p0) :: (store 1 into %ir.pcarry_flag)
+    RetRA
+
+...

diff --git a/test/CodeGen/Mips/GlobalISel/llvm-ir/mul.ll b/test/CodeGen/Mips/GlobalISel/llvm-ir/mul.ll
index 11e5426ad771ae136e7fda3059fa0afec4c4e2db..8475d78f6e520f84e07a910163a4dc63f6085659 100644 (file)
--- a/test/CodeGen/Mips/GlobalISel/llvm-ir/mul.ll
+++ b/test/CodeGen/Mips/GlobalISel/llvm-ir/mul.ll
@@ -86,3 +86,25 @@ entry:
   %mul = mul i16 %b, %a
   ret i16 %mul
 }
+
+declare { i32, i1 } @llvm.umul.with.overflow.i32(i32, i32)
+define void @umul_with_overflow(i32 %lhs, i32 %rhs, i1* %pcarry_flag) {
+; MIPS32-LABEL: umul_with_overflow:
+; MIPS32:       # %bb.0:
+; MIPS32-NEXT:    multu $4, $5
+; MIPS32-NEXT:    mfhi $4
+; MIPS32-NEXT:    lui $5, 0
+; MIPS32-NEXT:    ori $5, $5, 0
+; MIPS32-NEXT:    xor $4, $4, $5
+; MIPS32-NEXT:    sltu $4, $zero, $4
+; MIPS32-NEXT:    lui $5, 0
+; MIPS32-NEXT:    ori $5, $5, 1
+; MIPS32-NEXT:    and $4, $4, $5
+; MIPS32-NEXT:    sb $4, 0($6)
+; MIPS32-NEXT:    jr $ra
+; MIPS32-NEXT:    nop
+  %res = call { i32, i1 } @llvm.umul.with.overflow.i32(i32 %lhs, i32 %rhs)
+  %carry_flag = extractvalue { i32, i1 } %res, 1
+  store i1 %carry_flag, i1* %pcarry_flag
+  ret void
+}

diff --git a/test/CodeGen/Mips/GlobalISel/regbankselect/mul.mir b/test/CodeGen/Mips/GlobalISel/regbankselect/mul.mir
index 18ed66020dd94444451e37f0d7b665734d843880..f02bdd6711425b8cea3ca98c220565955b81aaa3 100644 (file)
--- a/test/CodeGen/Mips/GlobalISel/regbankselect/mul.mir
+++ b/test/CodeGen/Mips/GlobalISel/regbankselect/mul.mir
@@ -3,6 +3,7 @@
 --- |
 
   define void @mul_i32(i32 %x, i32 %y) {entry: ret void}
+  define void @umul_with_overflow(i32 %lhs, i32 %rhs, i1* %pcarry_flag) { ret void }
 
 ...
 ---
@@ -28,3 +29,38 @@ body:             |
     RetRA implicit $v0
 
 ...
+---
+name:            umul_with_overflow
+alignment:       2
+legalized:       true
+tracksRegLiveness: true
+body:             |
+  bb.1 (%ir-block.0):
+    liveins: $a0, $a1, $a2
+
+    ; MIPS32-LABEL: name: umul_with_overflow
+    ; MIPS32: liveins: $a0, $a1, $a2
+    ; MIPS32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $a0
+    ; MIPS32: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $a1
+    ; MIPS32: [[COPY2:%[0-9]+]]:gprb(p0) = COPY $a2
+    ; MIPS32: [[UMULH:%[0-9]+]]:gprb(s32) = G_UMULH [[COPY]], [[COPY1]]
+    ; MIPS32: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 0
+    ; MIPS32: [[ICMP:%[0-9]+]]:gprb(s32) = G_ICMP intpred(ne), [[UMULH]](s32), [[C]]
+    ; MIPS32: [[C1:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 1
+    ; MIPS32: [[COPY3:%[0-9]+]]:gprb(s32) = COPY [[ICMP]](s32)
+    ; MIPS32: [[AND:%[0-9]+]]:gprb(s32) = G_AND [[COPY3]], [[C1]]
+    ; MIPS32: G_STORE [[AND]](s32), [[COPY2]](p0) :: (store 1 into %ir.pcarry_flag)
+    ; MIPS32: RetRA
+    %0:_(s32) = COPY $a0
+    %1:_(s32) = COPY $a1
+    %2:_(p0) = COPY $a2
+    %6:_(s32) = G_UMULH %0, %1
+    %7:_(s32) = G_CONSTANT i32 0
+    %8:_(s32) = G_ICMP intpred(ne), %6(s32), %7
+    %9:_(s32) = G_CONSTANT i32 1
+    %10:_(s32) = COPY %8(s32)
+    %5:_(s32) = G_AND %10, %9
+    G_STORE %5(s32), %2(p0) :: (store 1 into %ir.pcarry_flag)
+    RetRA
+
+...