[mips] Duplicate the reciprocal instruction definitions for FP32

Add instruction definitions for FP32 mode for recip.d and rsqrt.d.

Previously these instructions were only defined when targeting the
full 64-bit FPU model but were not guarded properly.

Reviewers: nitesh.jain, atanasyan

Differential Revision: https://reviews.llvm.org/D38400

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315318 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/Mips/MicroMipsInstrFPU.td b/lib/Target/Mips/MicroMipsInstrFPU.td
index 2fbe930c37bca80d6190fa10240e76c12c0df3f0..29ef471788a0dcc9c2e4a9466c54c73c53427d91 100644 (file)
--- a/lib/Target/Mips/MicroMipsInstrFPU.td
+++ b/lib/Target/Mips/MicroMipsInstrFPU.td
@@ -169,16 +169,28 @@ let AdditionalPredicates = [InMicroMips] in {
     def RECIP_S_MM : MMRel, ABSS_FT<"recip.s", FGR32Opnd, FGR32Opnd,
                                     II_RECIP_S>,
                      ROUND_W_FM_MM<0b0, 0b01001000>;
-    def RECIP_D_MM : MMRel, ABSS_FT<"recip.d", AFGR64Opnd, AFGR64Opnd,
-                                    II_RECIP_D>,
-                     ROUND_W_FM_MM<0b1, 0b01001000>;
+    def RECIP_D32_MM : MMRel, ABSS_FT<"recip.d", AFGR64Opnd, AFGR64Opnd,
+                                      II_RECIP_D>,
+                     ROUND_W_FM_MM<0b1, 0b01001000>, FGR_32 {
+      let BaseOpcode = "RECIP_D32";
+    }
+    let DecoderNamespace = "MicroMipsFP64" in
+      def RECIP_D64_MM : MMRel, ABSS_FT<"recip.d", FGR64Opnd, FGR64Opnd,
+                                        II_RECIP_D>,
+                       ROUND_W_FM_MM<0b1, 0b01001000>, FGR_64;
     def RSQRT_S_MM : MMRel, ABSS_FT<"rsqrt.s", FGR32Opnd, FGR32Opnd,
                                     II_RECIP_S>,
                      ROUND_W_FM_MM<0b0, 0b00001000>;
-    def RSQRT_D_MM : MMRel, ABSS_FT<"rsqrt.d", AFGR64Opnd, AFGR64Opnd,
+    def RSQRT_D32_MM : MMRel, ABSS_FT<"rsqrt.d", AFGR64Opnd, AFGR64Opnd,
                                     II_RECIP_D>,
-                     ROUND_W_FM_MM<0b1, 0b00001000>;
-  }
+                     ROUND_W_FM_MM<0b1, 0b00001000>, FGR_32 {
+      let BaseOpcode = "RSQRT_D32";
+    }
+    let DecoderNamespace = "MicroMipsFP64" in
+      def RSQRT_D64_MM : MMRel, ABSS_FT<"rsqrt.d", FGR64Opnd, FGR64Opnd,
+                                        II_RECIP_D>,
+                         ROUND_W_FM_MM<0b1, 0b00001000>, FGR_64;
+   }
   let DecoderNamespace = "MicroMips",  DecoderMethod = "DecodeFMemMMR2" in {
     def LDC1_MM : MMRel, LW_FT<"ldc1", AFGR64Opnd, mem_mm_16, II_LDC1, load>,
                   LW_FM_MM<0x2f>, FGR_32 {

diff --git a/lib/Target/Mips/MipsInstrFPU.td b/lib/Target/Mips/MipsInstrFPU.td
index c2338f2d901192dea319093fff081fcc6bb8a77f..75e1b2be2a43dd0fc18a3b62313698a543cb1e7d 100644 (file)
--- a/lib/Target/Mips/MipsInstrFPU.td
+++ b/lib/Target/Mips/MipsInstrFPU.td
@@ -369,12 +369,24 @@ defm CVT_W   : ROUND_M<"cvt.w.d", II_CVT>, ABSS_FM<0x24, 17>;
 let AdditionalPredicates = [NotInMicroMips] in {
   def RECIP_S : MMRel, ABSS_FT<"recip.s", FGR32Opnd, FGR32Opnd, II_RECIP_S>,
                 ABSS_FM<0b010101, 0x10>, INSN_MIPS4_32R2;
-  def RECIP_D : MMRel, ABSS_FT<"recip.d", FGR64Opnd, FGR64Opnd, II_RECIP_D>,
-                ABSS_FM<0b010101, 0x11>, INSN_MIPS4_32R2;
+  def RECIP_D32 : MMRel, ABSS_FT<"recip.d", AFGR64Opnd, AFGR64Opnd, II_RECIP_D>,
+                  ABSS_FM<0b010101, 0x11>, INSN_MIPS4_32R2, FGR_32 {
+    let BaseOpcode = "RECIP_D32";
+  }
+  let DecoderNamespace = "MipsFP64" in
+    def RECIP_D64 : MMRel, ABSS_FT<"recip.d", FGR64Opnd, FGR64Opnd,
+                                   II_RECIP_D>, ABSS_FM<0b010101, 0x11>,
+                    INSN_MIPS4_32R2, FGR_64;
   def RSQRT_S : MMRel, ABSS_FT<"rsqrt.s", FGR32Opnd, FGR32Opnd, II_RSQRT_S>,
                 ABSS_FM<0b010110, 0x10>, INSN_MIPS4_32R2;
-  def RSQRT_D : MMRel, ABSS_FT<"rsqrt.d", FGR64Opnd, FGR64Opnd, II_RSQRT_D>,
-                ABSS_FM<0b010110, 0x11>, INSN_MIPS4_32R2;
+  def RSQRT_D32 : MMRel, ABSS_FT<"rsqrt.d", AFGR64Opnd, AFGR64Opnd, II_RSQRT_D>,
+                  ABSS_FM<0b010110, 0x11>, INSN_MIPS4_32R2, FGR_32 {
+    let BaseOpcode = "RSQRT_D32";
+  }
+  let DecoderNamespace = "MipsFP64" in
+    def RSQRT_D64 : MMRel, ABSS_FT<"rsqrt.d", FGR64Opnd, FGR64Opnd,
+                                   II_RSQRT_D>, ABSS_FM<0b010110, 0x11>,
+                    INSN_MIPS4_32R2, FGR_64;
 }
 let DecoderNamespace = "MipsFP64" in {
   let AdditionalPredicates = [NotInMicroMips] in {

diff --git a/test/MC/Mips/mips32r2/valid.s b/test/MC/Mips/mips32r2/valid.s
index 3cd6a09fdd8cd949defb66663cc42bc066c970b3..badac0ac7e2244ff55627b9be7bd54977cc783c4 100644 (file)
--- a/test/MC/Mips/mips32r2/valid.s
+++ b/test/MC/Mips/mips32r2/valid.s
@@ -197,7 +197,7 @@ a:
                                        # CHECK-NEXT: .set  mips32r2
                                        # CHECK-NEXT: rdhwr $sp, $11
                                        # CHECK-NEXT: .set  pop          # encoding: [0x7c,0x1d,0x58,0x3b]
-        recip.d   $f19,$f6             # CHECK: recip.d $f19, $f6       # encoding: [0x46,0x20,0x34,0xd5]
+        recip.d   $f14,$f6             # CHECK: recip.d $f14, $f6       # encoding: [0x46,0x20,0x33,0x95]
         recip.s   $f3,$f30             # CHECK: recip.s $f3, $f30       # encoding: [0x46,0x00,0xf0,0xd5]
         rotr      $1,15                # CHECK: rotr $1, $1, 15         # encoding: [0x00,0x21,0x0b,0xc2]
         rotr      $1,$14,15            # CHECK: rotr $1, $14, 15        # encoding: [0x00,0x2e,0x0b,0xc2]

diff --git a/test/MC/Mips/mips32r3/valid.s b/test/MC/Mips/mips32r3/valid.s
index b69a78776a45f53d5cfb70c0f1be09f3091dbfbf..c8009351e4754bd15cbec586b60f8c04165aaac3 100644 (file)
--- a/test/MC/Mips/mips32r3/valid.s
+++ b/test/MC/Mips/mips32r3/valid.s
@@ -197,7 +197,7 @@ a:
                                        # CHECK-NEXT: .set  mips32r2
                                        # CHECK-NEXT: rdhwr $sp, $11
                                        # CHECK-NEXT: .set  pop          # encoding: [0x7c,0x1d,0x58,0x3b]
-        recip.d   $f19,$f6             # CHECK: recip.d $f19, $f6       # encoding: [0x46,0x20,0x34,0xd5]
+        recip.d   $f14,$f6             # CHECK: recip.d $f14, $f6       # encoding: [0x46,0x20,0x33,0x95]
         recip.s   $f3,$f30             # CHECK: recip.s $f3, $f30       # encoding: [0x46,0x00,0xf0,0xd5]
         rotr      $1,15                # CHECK: rotr $1, $1, 15         # encoding: [0x00,0x21,0x0b,0xc2]
         rotr      $1,$14,15            # CHECK: rotr $1, $14, 15        # encoding: [0x00,0x2e,0x0b,0xc2]

diff --git a/test/MC/Mips/mips32r5/valid.s b/test/MC/Mips/mips32r5/valid.s
index 5ac82e7fe985ea2c6da610caf4adf3c03d639783..de56e3e37b275d7f3b06e5e99d0bc146bf3a1d53 100644 (file)
--- a/test/MC/Mips/mips32r5/valid.s
+++ b/test/MC/Mips/mips32r5/valid.s
@@ -198,7 +198,7 @@ a:
                                        # CHECK-NEXT: .set  mips32r2
                                        # CHECK-NEXT: rdhwr $sp, $11
                                        # CHECK-NEXT: .set  pop          # encoding: [0x7c,0x1d,0x58,0x3b]
-        recip.d   $f19,$f6             # CHECK: recip.d $f19, $f6       # encoding: [0x46,0x20,0x34,0xd5]
+        recip.d   $f14,$f6             # CHECK: recip.d $f14, $f6       # encoding: [0x46,0x20,0x33,0x95]
         recip.s   $f3,$f30             # CHECK: recip.s $f3, $f30       # encoding: [0x46,0x00,0xf0,0xd5]
         rotr      $1,15                # CHECK: rotr $1, $1, 15         # encoding: [0x00,0x21,0x0b,0xc2]
         rotr      $1,$14,15            # CHECK: rotr $1, $14, 15        # encoding: [0x00,0x2e,0x0b,0xc2]