Clean up predefined macros for AArch64 to follow ACLE 2.0.

git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@195068 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Basic/Targets.cpp b/lib/Basic/Targets.cpp
index 8d147072747da32d493a0a188cff3f506b68235d..2578681c4659aac4bc7d457dbf760001eb204ffc 100644 (file)
--- a/lib/Basic/Targets.cpp
+++ b/lib/Basic/Targets.cpp
@@ -3401,6 +3401,7 @@ class AArch64TargetInfo : public TargetInfo {
   };
 
   unsigned FPU;
+  unsigned Crypto;
   static const Builtin::Info BuiltinInfo[];
 
 public:
@@ -3430,22 +3431,20 @@ public:
     Builder.defineMacro("__AARCH64EL__");
 
     // ACLE predefines. Many can only have one possible value on v8 AArch64.
-
-    // FIXME: these were written based on an unreleased version of a 32-bit ACLE
-    // which was intended to be compatible with a 64-bit implementation. They
-    // will need updating when a real 64-bit ACLE exists. Particularly pressing
-    // instances are: __ARM_ARCH_ISA_ARM, __ARM_ARCH_ISA_THUMB, __ARM_PCS.
-    Builder.defineMacro("__ARM_ACLE",         "101");
+    Builder.defineMacro("__ARM_ACLE",         "200");
     Builder.defineMacro("__ARM_ARCH",         "8");
     Builder.defineMacro("__ARM_ARCH_PROFILE", "'A'");
 
+    Builder.defineMacro("__ARM_64BIT_STATE");
+    Builder.defineMacro("__ARM_PCS_AAPCS64");
+    Builder.defineMacro("__ARM_ARCH_ISA_A64");
+
     Builder.defineMacro("__ARM_FEATURE_UNALIGNED");
     Builder.defineMacro("__ARM_FEATURE_CLZ");
     Builder.defineMacro("__ARM_FEATURE_FMA");
+    Builder.defineMacro("__ARM_FEATURE_DIV");
 
-    // FIXME: ACLE 1.1 reserves bit 4. Will almost certainly come to mean
-    // 128-bit LDXP present, at which point this becomes 0x1f.
-    Builder.defineMacro("__ARM_FEATURE_LDREX", "0xf");
+    Builder.defineMacro("__ARM_ALIGN_MAX_STACK_PWR", "4");
 
     // 0xe implies support for half, single and double precision operations.
     Builder.defineMacro("__ARM_FP", "0xe");
@@ -3470,10 +3469,13 @@ public:
       Builder.defineMacro("__AARCH_BIG_ENDIAN");
 
     if (FPU == NeonMode) {
-      Builder.defineMacro("__AARCH_FEATURE_ADVSIMD");
-
+      Builder.defineMacro("__ARM_NEON");
       // 64-bit NEON supports half, single and double precision operations.
-      Builder.defineMacro("__AARCH_ADVSIMD_FP", "0xe");
+      Builder.defineMacro("__ARM_NEON_FP", "7");
+    }
+
+    if (Crypto) {
+      Builder.defineMacro("__ARM_FEATURE_CRYPTO");
     }
   }
   virtual void getTargetBuiltins(const Builtin::Info *&Records,
@@ -3495,9 +3497,12 @@ public:
   virtual bool handleTargetFeatures(std::vector<std::string> &Features,
                                     DiagnosticsEngine &Diags) {
     FPU = FPUMode;
+    Crypto = 0;
     for (unsigned i = 0, e = Features.size(); i != e; ++i) {
       if (Features[i] == "+neon")
         FPU = NeonMode;
+      if (Features[i] == "+crypto")
+        Crypto = 1;
     }
     return true;
   }

diff --git a/test/Preprocessor/aarch64-target-features.c b/test/Preprocessor/aarch64-target-features.c
index 25bdb71bc3c656e399a811d9094dd384c7452d95..9978f91e2605d08980ff095e165d2217aa65e22e 100644 (file)
--- a/test/Preprocessor/aarch64-target-features.c
+++ b/test/Preprocessor/aarch64-target-features.c
@@ -1,28 +1,33 @@
 // RUN: %clang -target aarch64-none-linux-gnu -x c -E -dM %s -o - | FileCheck %s
-// CHECK: __AARCH64EL__
-// CHECK-NOT: __AARCH_ADVSIMD_FP
-// CHECK-NOT: __AARCH_FEATURE_ADVSIMD
-// CHECK: __ARM_ACLE 101
+
+// CHECK: __AARCH64EL__ 1
+// CHECK: __ARM_64BIT_STATE 1
+// CHECK: __ARM_ACLE 200
+// CHECK: __ARM_ALIGN_MAX_STACK_PWR 4
 // CHECK: __ARM_ARCH 8
+// CHECK: __ARM_ARCH_ISA_A64 1
 // CHECK: __ARM_ARCH_PROFILE 'A'
 // CHECK-NOT: __ARM_FEATURE_BIG_ENDIAN
 // CHECK: __ARM_FEATURE_CLZ 1
+// CHECK-NOT: __ARM_FEATURE_CRYPTO 1
+// CHECK: __ARM_FEATURE_DIV 1
 // CHECK: __ARM_FEATURE_FMA 1
-// CHECK: __ARM_FEATURE_LDREX 0xf
 // CHECK: __ARM_FEATURE_UNALIGNED 1
 // CHECK: __ARM_FP 0xe
-// CHECK-NOT: __ARM_FP_FAST
 // CHECK: __ARM_FP16_FORMAT_IEEE 1
+// CHECK-NOT: __ARM_FP_FAST 1
 // CHECK: __ARM_FP_FENV_ROUNDING 1
-// CHECK-NOT: __ARM_NEON_FP
-// CHECK-NOT: __ARM_NEON
-// CHECK: __ARM_SIZEOF_MINIMAL_ENUM 4
-// CHECK: __ARM_SIZEOF_WCHAR_T 4
-// CHECK: __aarch64__
+// CHECK-NOT: __ARM_NEON 1
+// CHECK-NOT: __ARM_NEON_FP 7
+// CHECK: __ARM_PCS_AAPCS64 1
+// CHECK-NOT: __ARM_SIZEOF_MINIMAL_ENUM 1
+// CHECK-NOT: __ARM_SIZEOF_WCHAR_T 2
 
+// RUN: %clang -target aarch64-none-linux-gnu -mfpu=crypto-neon-fp-armv8 -x c -E -dM %s -o - | FileCheck --check-prefix=CHECK-CRYPTO %s
+// CHECK-CRYPTO: __ARM_FEATURE_CRYPTO 1
 
 // RUN: %clang -target aarch64-none-linux-gnu -ffast-math -x c -E -dM %s -o - | FileCheck --check-prefix=CHECK-FASTMATH %s
-// CHECK-FASTMATH: __ARM_FP_FAST
+// CHECK-FASTMATH: __ARM_FP_FAST 1
 
 // RUN: %clang -target aarch64-none-linux-gnu -fshort-wchar -x c -E -dM %s -o - | FileCheck --check-prefix=CHECK-SHORTWCHAR %s
 // CHECK-SHORTWCHAR: __ARM_SIZEOF_WCHAR_T 2
@@ -31,5 +36,5 @@
 // CHECK-SHORTENUMS: __ARM_SIZEOF_MINIMAL_ENUM 1
 
 // RUN: %clang -target aarch64-none-linux-gnu -mfpu=neon -x c -E -dM %s -o - | FileCheck --check-prefix=CHECK-NEON %s
-// CHECK-NEON: __AARCH_ADVSIMD_FP
-// CHECK-NEON: __AARCH_FEATURE_ADVSIMD
+// CHECK-NEON: __ARM_NEON 1
+// CHECK-NEON: __ARM_NEON_FP 7

diff --git a/utils/TableGen/NeonEmitter.cpp b/utils/TableGen/NeonEmitter.cpp
index 874a661c5d54d979ff31c0bebab54de15a438d89..86cd429b173addc2c7e413b6d164a2a4eba21933 100644 (file)
--- a/utils/TableGen/NeonEmitter.cpp
+++ b/utils/TableGen/NeonEmitter.cpp
@@ -2405,7 +2405,7 @@ void NeonEmitter::run(raw_ostream &OS) {
   OS << "#ifndef __ARM_NEON_H\n";
   OS << "#define __ARM_NEON_H\n\n";
 
-  OS << "#if !defined(__ARM_NEON__) && !defined(__AARCH_FEATURE_ADVSIMD)\n";
+  OS << "#if !defined(__ARM_NEON__) && !defined(__ARM_NEON)\n";
   OS << "#error \"NEON support not enabled\"\n";
   OS << "#endif\n\n";