Revert "[AVX-512] EVEX2VEX, don't reject intrinsic instructions when both have a...

This reverts r297596.

There were other issues that were making this not work that have been fixed now. Reverting this results in a more accurate table.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297602 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/test/CodeGen/X86/evex-to-vex-compress.mir b/test/CodeGen/X86/evex-to-vex-compress.mir
index 8b28ea1d03f97e5ce654a9c12b5b17a7fc5b1104..138cd540cceef05f226759fe559184853f410b99 100755 (executable)
--- a/test/CodeGen/X86/evex-to-vex-compress.mir
+++ b/test/CodeGen/X86/evex-to-vex-compress.mir
@@ -2172,7 +2172,7 @@ body: |
   %rdi = VCVTSS2SI64Zrr                        %xmm0                                                   
   ; CHECK: %edi = VCVTSS2SIrr                  %xmm0
   %edi = VCVTSS2SIZrr                          %xmm0                                                   
-  ; CHECK: %rdi = Int_VCVTTSD2SI64rm           %rdi, %xmm0, 1, _, 0
+  ; CHECK: %rdi = VCVTTSD2SI64rm               %rdi, %xmm0, 1, _, 0
   %rdi = VCVTTSD2SI64Zrm                       %rdi, %xmm0, 1, _, 0                                    
   ; CHECK: %rdi = Int_VCVTTSD2SI64rm           %rdi, %xmm0, 1, _, 0
   %rdi = VCVTTSD2SI64Zrm_Int                   %rdi, %xmm0, 1, _, 0                                    
@@ -2180,7 +2180,7 @@ body: |
   %rdi = VCVTTSD2SI64Zrr                       %xmm0                                                   
   ; CHECK: %rdi = Int_VCVTTSD2SI64rr           %xmm0
   %rdi = VCVTTSD2SI64Zrr_Int                   %xmm0                                                   
-  ; CHECK: %edi = Int_VCVTTSD2SIrm             %rdi, %xmm0, 1, _, 0
+  ; CHECK: %edi = VCVTTSD2SIrm                 %rdi, %xmm0, 1, _, 0
   %edi = VCVTTSD2SIZrm                         %rdi, %xmm0, 1, _, 0                                    
   ; CHECK: %edi = Int_VCVTTSD2SIrm             %rdi, %xmm0, 1, _, 0
   %edi = VCVTTSD2SIZrm_Int                     %rdi, %xmm0, 1, _, 0                                    
@@ -2188,7 +2188,7 @@ body: |
   %edi = VCVTTSD2SIZrr                         %xmm0                                                   
   ; CHECK: %edi = Int_VCVTTSD2SIrr             %xmm0
   %edi = VCVTTSD2SIZrr_Int                     %xmm0                                                   
-  ; CHECK: %rdi = Int_VCVTTSS2SI64rm           %rdi, %xmm0, 1, _, 0
+  ; CHECK: %rdi = VCVTTSS2SI64rm               %rdi, %xmm0, 1, _, 0
   %rdi = VCVTTSS2SI64Zrm                       %rdi, %xmm0, 1, _, 0                                    
   ; CHECK: %rdi = Int_VCVTTSS2SI64rm           %rdi, %xmm0, 1, _, 0
   %rdi = VCVTTSS2SI64Zrm_Int                   %rdi, %xmm0, 1, _, 0                                    
@@ -2196,7 +2196,7 @@ body: |
   %rdi = VCVTTSS2SI64Zrr                       %xmm0                                                   
   ; CHECK: %rdi = Int_VCVTTSS2SI64rr           %xmm0
   %rdi = VCVTTSS2SI64Zrr_Int                   %xmm0                                                   
-  ; CHECK: %edi = Int_VCVTTSS2SIrm             %rdi, %xmm0, 1, _, 0
+  ; CHECK: %edi = VCVTTSS2SIrm                 %rdi, %xmm0, 1, _, 0
   %edi = VCVTTSS2SIZrm                         %rdi, %xmm0, 1, _, 0                                    
   ; CHECK: %edi = Int_VCVTTSS2SIrm             %rdi, %xmm0, 1, _, 0
   %edi = VCVTTSS2SIZrm_Int                     %rdi, %xmm0, 1, _, 0                                    

diff --git a/utils/TableGen/X86EVEX2VEXTablesEmitter.cpp b/utils/TableGen/X86EVEX2VEXTablesEmitter.cpp
index 142a969d340ba8c0ac606f01f2fcc478abc22ddb..1fe9cd6864fb1a39d2f3919ecd6152f907c3e13f 100644 (file)
--- a/utils/TableGen/X86EVEX2VEXTablesEmitter.cpp
+++ b/utils/TableGen/X86EVEX2VEXTablesEmitter.cpp
@@ -72,8 +72,7 @@ private:
       "VPSRAQ",
       "VDBPSADBW",
       "VRNDSCALE",
-      "VSCALEFPS",
-      "VSCALEFSS",
+      "VSCALEFPS"
   };
 
   bool inExceptionList(const CodeGenInstruction *Inst) {
@@ -243,7 +242,7 @@ public:
         if (getRegOperandSize(OpRec1) != getRegOperandSize(OpRec2))
           return false;
       } else if (isMemoryOperand(OpRec1) && isMemoryOperand(OpRec2)) {
-        continue;
+        return false;
       } else if (isImmediateOperand(OpRec1) && isImmediateOperand(OpRec2)) {
         if (OpRec1->getValueAsDef("Type") != OpRec2->getValueAsDef("Type"))
           return false;