[RISCV] Fix failure to parse parenthesized immediates

Since the parser attempts to parse an operand as a register with
parentheses before parsing it as an immediate, immediates in
parentheses should not be parsed by parseRegister. However in the case
where the immediate does not start with an identifier, the LParen is not
unlexed and so the RParen causes an unexpected token error.

This patch adds the missing UnLex, and modifies the existing UnLex to
not use a buffered token, as it should always be unlexing an LParen.

Differential Revision: https://reviews.llvm.org/D57319

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363782 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp b/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
index bac43187ca770be866eca6ef9e66843f8454fe0e..083d4b77ccccfd1fc03b739be16609c97dc7c036 100644 (file)
--- a/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
+++ b/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
@@ -997,19 +997,24 @@ OperandMatchResultTy RISCVAsmParser::parseRegister(OperandVector &Operands,
                                                    bool AllowParens) {
   SMLoc FirstS = getLoc();
   bool HadParens = false;
-  AsmToken Buf[2];
+  AsmToken LParen;
 
-  // If this a parenthesised register name is allowed, parse it atomically
+  // If this is an LParen and a parenthesised register name is allowed, parse it
+  // atomically.
   if (AllowParens && getLexer().is(AsmToken::LParen)) {
+    AsmToken Buf[2];
     size_t ReadCount = getLexer().peekTokens(Buf);
     if (ReadCount == 2 && Buf[1].getKind() == AsmToken::RParen) {
       HadParens = true;
+      LParen = getParser().getTok();
       getParser().Lex(); // Eat '('
     }
   }
 
   switch (getLexer().getKind()) {
   default:
+    if (HadParens)
+      getLexer().UnLex(LParen);
     return MatchOperand_NoMatch;
   case AsmToken::Identifier:
     StringRef Name = getLexer().getTok().getIdentifier();
@@ -1018,7 +1023,7 @@ OperandMatchResultTy RISCVAsmParser::parseRegister(OperandVector &Operands,
 
     if (RegNo == 0) {
       if (HadParens)
-        getLexer().UnLex(Buf[0]);
+        getLexer().UnLex(LParen);
       return MatchOperand_NoMatch;
     }
     if (HadParens)

diff --git a/test/MC/RISCV/rv32i-valid.s b/test/MC/RISCV/rv32i-valid.s
index 01b46b58dd62116f438be7478fc4ba6d6122f2bd..7b711a32231515308c3b58c94ca53f368f04c7d7 100644 (file)
--- a/test/MC/RISCV/rv32i-valid.s
+++ b/test/MC/RISCV/rv32i-valid.s
@@ -84,6 +84,12 @@ jal a0, a0
 # CHECK-ASM-AND-OBJ: jal a0, 30
 # CHECK-ASM: encoding: [0x6f,0x05,0xe0,0x01]
 jal a0, CONST
+# CHECK-ASM-AND-OBJ: jal s0, 0
+# CHECK-ASM: encoding: [0x6f,0x04,0x00,0x00]
+jal s0, (0)
+# CHECK-ASM-AND-OBJ: jal s0, 156
+# CHECK-ASM: encoding: [0x6f,0x04,0xc0,0x09]
+jal s0, (0xff-99)
 
 # CHECK-ASM-AND-OBJ: jalr a0, a1, -2048
 # CHECK-ASM: encoding: [0x67,0x85,0x05,0x80]
@@ -154,6 +160,12 @@ lhu t3, %pcrel_lo(foo)(t3)
 # CHECK-ASM-AND-OBJ: lb t0, 30(t1)
 # CHECK-ASM: encoding: [0x83,0x02,0xe3,0x01]
 lb t0, CONST(t1)
+# CHECK-ASM-AND-OBJ: lb s0, 0(s1)
+# CHECK-ASM: encoding: [0x03,0x84,0x04,0x00]
+lb s0, (0)(s1)
+# CHECK-ASM-AND-OBJ: lb s0, 156(s1)
+# CHECK-ASM: encoding: [0x03,0x84,0xc4,0x09]
+lb s0, (0xff-99)(s1)
 
 # CHECK-ASM-AND-OBJ: sb a0, 2047(a2)
 # CHECK-ASM: encoding: [0xa3,0x0f,0xa6,0x7e]
@@ -170,6 +182,12 @@ sw ra, 999(zero)
 # CHECK-ASM-AND-OBJ: sw a0, 30(t0)
 # CHECK-ASM: encoding: [0x23,0xaf,0xa2,0x00]
 sw a0, CONST(t0)
+# CHECK-ASM-AND-OBJ: sw s0, 0(s1)
+# CHECK-ASM: encoding: [0x23,0xa0,0x84,0x00]
+sw s0, (0)(s1)
+# CHECK-ASM-AND-OBJ: sw s0, 156(s1)
+# CHECK-ASM: encoding: [0x23,0xae,0x84,0x08]
+sw s0, (0xff-99)(s1)
 
 # CHECK-ASM-AND-OBJ: addi ra, sp, 2
 # CHECK-ASM: encoding: [0x93,0x00,0x21,0x00]
@@ -182,6 +200,12 @@ addi ra, sp, %lo(foo)
 # CHECK-ASM-AND-OBJ: addi ra, sp, 30
 # CHECK-ASM: encoding: [0x93,0x00,0xe1,0x01]
 addi ra, sp, CONST
+# CHECK-ASM-AND-OBJ: addi ra, sp, 0
+# CHECK-ASM: encoding: [0x93,0x00,0x01,0x00]
+addi ra, sp, (0)
+# CHECK-ASM-AND-OBJ: addi ra, sp, 156
+# CHECK-ASM: encoding: [0x93,0x00,0xc1,0x09]
+addi ra, sp, (0xff-99)
 # CHECK-ASM-AND-OBJ: slti a0, a2, -20
 # CHECK-ASM: encoding: [0x13,0x25,0xc6,0xfe]
 slti a0, a2, -20