[Hexagon] Report error instead of crashing on wrong inline-asm constraints

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316236 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/Hexagon/HexagonISelLowering.cpp b/lib/Target/Hexagon/HexagonISelLowering.cpp
index 5a1b21a2aaf302ecafb28c303b5f350ae7513928..bece022eabf7f1ea6f5e2178f540878d730670fd 100644 (file)
--- a/lib/Target/Hexagon/HexagonISelLowering.cpp
+++ b/lib/Target/Hexagon/HexagonISelLowering.cpp
@@ -2979,46 +2979,47 @@ HexagonTargetLowering::getRegForInlineAsmConstraint(
     case 'r':   // R0-R31
       switch (VT.SimpleTy) {
       default:
-        llvm_unreachable("getRegForInlineAsmConstraint Unhandled data type");
+        return {0u, nullptr};
       case MVT::i1:
       case MVT::i8:
       case MVT::i16:
       case MVT::i32:
       case MVT::f32:
-        return std::make_pair(0U, &Hexagon::IntRegsRegClass);
+        return {0u, &Hexagon::IntRegsRegClass};
       case MVT::i64:
       case MVT::f64:
-        return std::make_pair(0U, &Hexagon::DoubleRegsRegClass);
+        return {0u, &Hexagon::DoubleRegsRegClass};
       }
       break;
     case 'a': // M0-M1
-      return std::make_pair(0U, &Hexagon::ModRegsRegClass);
+      if (VT != MVT::i32)
+        return {0u, nullptr};
+      return {0u, &Hexagon::ModRegsRegClass};
     case 'q': // q0-q3
       switch (VT.getSizeInBits()) {
       default:
-        llvm_unreachable("getRegForInlineAsmConstraint Unhandled vector size");
+        return {0u, nullptr};
       case 512:
-        return std::make_pair(0U, &Hexagon::HvxQRRegClass);
       case 1024:
-        return std::make_pair(0U, &Hexagon::HvxQRRegClass);
+        return {0u, &Hexagon::HvxQRRegClass};
       }
       break;
     case 'v': // V0-V31
       switch (VT.getSizeInBits()) {
       default:
-        llvm_unreachable("getRegForInlineAsmConstraint Unhandled vector size");
+        return {0u, nullptr};
       case 512:
-        return std::make_pair(0U, &Hexagon::HvxVRRegClass);
+        return {0u, &Hexagon::HvxVRRegClass};
       case 1024:
         if (Subtarget.hasV60TOps() && Subtarget.useHVX128BOps())
-          return std::make_pair(0U, &Hexagon::HvxVRRegClass);
-        return std::make_pair(0U, &Hexagon::HvxWRRegClass);
+          return {0u, &Hexagon::HvxVRRegClass};
+        return {0u, &Hexagon::HvxWRRegClass};
       case 2048:
-        return std::make_pair(0U, &Hexagon::HvxWRRegClass);
+        return {0u, &Hexagon::HvxWRRegClass};
       }
       break;
     default:
-      llvm_unreachable("Unknown asm register class");
+      return {0u, nullptr};
     }
   }
 

diff --git a/test/CodeGen/Hexagon/inline-asm-bad-constraint.ll b/test/CodeGen/Hexagon/inline-asm-bad-constraint.ll
new file mode 100644 (file)
index 0000000..2c4e3f4
--- /dev/null
+++ b/test/CodeGen/Hexagon/inline-asm-bad-constraint.ll
@@ -0,0 +1,16 @@
+; RUN: not llc -march=hexagon < %s 2>&1 | FileCheck %s
+
+; CHECK: error: couldn't allocate output register for constraint 'r'
+
+target datalayout = "e-m:e-p:32:32:32-a:0-n16:32-i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048"
+target triple = "hexagon"
+
+define void @fred() #0 {
+entry:
+  %a0 = alloca <16 x i32>, align 64
+  %0 = call <16 x i32> asm sideeffect "$0 = vmem(r0)", "=r"()
+  store <16 x i32> %0, <16 x i32>* %a0, align 64
+  ret void
+}
+
+attributes #0 = { noinline nounwind }