[ARM] Fix formatting issue in ARMISelLowering.cpp

Fix a formatting error in ARMISelLowering.cpp::Expand64BitShift. My test
commit after receiving write access.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364560 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/ARM/ARMISelLowering.cpp b/lib/Target/ARM/ARMISelLowering.cpp
index 7ff0846e1a0e55ac989f530a2dcc4222c0f410f2..9785339ee7b52aa53379e9a3a3444ac91e38094f 100644 (file)
--- a/lib/Target/ARM/ARMISelLowering.cpp
+++ b/lib/Target/ARM/ARMISelLowering.cpp
@@ -5565,7 +5565,8 @@ static SDValue Expand64BitShift(SDNode *N, SelectionDAG &DAG,
     return SDValue();
 
   // If we are in thumb mode, we don't have RRX.
-  if (ST->isThumb1Only()) return SDValue();
+  if (ST->isThumb1Only())
+    return SDValue();
 
   // Okay, we have a 64-bit SRA or SRL of 1.  Lower this to an RRX expr.
   SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(0),